UPD442012LGY-C10X-MKH [ETC]
x16 SRAM ; X16 SRAM
| 型号： | UPD442012LGY-C10X-MKH |
| 厂家： | 
ETC |
| 描述： | x16 SRAM
|
| 文件： | 总24页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
PD442012L-X
µ
2M-BIT CMOS STATIC RAM
128K-WORD BY 16-BIT
EXTENDED TEMPERATURE OPERATION
Description
The µPD442012L-X is a high speed, low power, 2,097,152 bits (131,072 words by 16 bits) CMOS static RAM.
The µPD442012L-X has two chip enable pins (/CE1, CE2) to extend the capacity.
The µPD442012L-X is packed in 48-pin plastic TSOP (I).
Features
• 131,072 words by 16 bits organization
• Fast access time: 70, 85, 100, 120, 150, 200 ns (MAX.)
• Byte data control: /LB (I/O1 - I/O8), /UB (I/O9 - I/O16)
• Low voltage operation
(B version: VCC = 2.7 to 3.6 V, C version: VCC = 2.2 to 3.6 V, D version: VCC = 1.8 to 3.6 V)
• Low VCC data retention
★
(B version: 2.0 V (MIN.), C version: 1.5 V (MIN.), D version: 1.5 V (MIN.))
• Operating ambient temperature: TA = –25 to +85 °C
• Output Enable input for easy application
• Two Chip Enable inputs: /CE1, CE2
Part number
Access time Operating supply Operating ambient
Supply current
ns (MAX.)
voltage
V
temperature
°C
At operating
mA (MAX.)
At standby
At data retention
µA (MAX.)
µA (MAX.)
µPD442012L-BxxX
µPD442012L-CxxX
70, 85
2.7 to 3.6
2.2 to 3.6
1.8 to 3.6
−25 to +85
35
4
4
100, 120
µPD442012L-DxxX Note 150, 200
Note Under development
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14274EJ3V0DS00 (3rd edition)
Date Published November 1999 NS CP (K)
Printed in Japan
The mark ★ shows major revised points.
1999
©
µPD442012L-X
Ordering Information
Operating
Operating
Access time
ns (MAX.)
Part number
Package
supply voltage temperature
Remark
V
°C
µPD442012LGY-B70X-MJH
µPD442012LGY-B70X-MKH
µPD442012LGY-B85X-MJH
µPD442012LGY-B85X-MKH
µPD442012LGY-C10X-MJH
µPD442012LGY-C10X-MKH
µPD442012LGY-C12X-MJH
µPD442012LGY-C12X-MKH
µPD442012LGY-D15X-MJH Note
µPD442012LGY-D15X-MKH Note
µPD442012LGY-D20X-MJH Note
µPD442012LGY-D20X-MKH Note
48-pin Plastic TSOP (I)
70
2.7 to 3.6
−25 to +85
B version
(12×18) (Normal bent)
48-pin Plastic TSOP (I)
(12×18) (Reverse bent)
48-pin Plastic TSOP (I)
85
(12×18) (Normal bent)
48-pin Plastic TSOP (I)
(12×18) (Reverse bent)
48-pin Plastic TSOP (I)
100
120
150
200
2.2 to 3.6
C version
(12×18) (Normal bent)
48-pin Plastic TSOP (I)
(12×18) (Reverse bent)
48-pin Plastic TSOP (I)
(12×18) (Normal bent)
48-pin Plastic TSOP (I)
(12×18) (Reverse bent)
48-pin Plastic TSOP (I)
1.8 to 3.6
D version
(12×18) (Normal bent)
48-pin Plastic TSOP (I)
(12×18) (Reverse bent)
48-pin Plastic TSOP (I)
(12×18) (Normal bent)
48-pin Plastic TSOP (I)
(12×18) (Reverse bent)
Note Under development
2
Data Sheet M14274EJ3V0DS00
µPD442012L-X
Pin Configurations (Marking Side)
/xxx indicates active low signal.
48-pin Plastic TSOP (I) (12×18) (Normal bent)
[ µPD442012LGY-BxxX-MJH ]
[ µPD442012LGY-CxxX-MJH ]
[ µPD442012LGY-DxxX-MJH ]
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
NC
GND
I/O16
I/O8
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
A8
NC
NC
/WE
CE2
IC
/UB
/LB
NC
NC
A7
A6
A5
A4
A3
A2
A1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VCC
★
I/O12
I/O4
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
/OE
GND
/CE1
A0
A0 - A16
: Address inputs
I/O1 - I/O16 : Data inputs / outputs
/CE1, CE2 : Chip Enable 1, 2
/WE
: Write Enable
: Output Enable
: Byte data select
: Power supply
: Ground
/OE
/LB, /UB
VCC
GND
NC
ICNote
: No Connection
: Internal Connection
Note Leave this pin unconnected or connect to GND.
Remark Refer to Package Drawings for the 1-pin marking.
3
Data Sheet M14274EJ3V0DS00
µPD442012L-X
48-pin Plastic TSOP (I) (12×18) (Reverse bent)
[ µPD442012LGY-BxxX-MKH ]
[ µPD442012LGY-CxxX-MKH ]
[ µPD442012LGY-DxxX-MKH ]
A16
NC
GND
I/O16
I/O8
I/O15
I/O7
I/O14
I/O6
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
/WE
CE2
IC
/UB
/LB
NC
NC
A7
A6
A5
A4
A3
A2
A1
I/O13
I/O5
V
CC
★
I/O12
I/O4
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
/OE
GND
/CE1
A0
A0 - A16
: Address inputs
I/O1 - I/O16 : Data inputs / outputs
/CE1, CE2 : Chip Enable 1, 2
/WE
: Write Enable
: Output Enable
: Byte data select
: Power supply
: Ground
/OE
/LB, /UB
VCC
GND
NC
ICNote
: No Connection
: Internal Connection
Note Leave this pin unconnected or connect to GND.
Remark Refer to Package Drawings for the 1-pin marking.
4
Data Sheet M14274EJ3V0DS00
µPD442012L-X
Block Diagram
V
CC
GND
A0
Address
buffer
Row
decoder
Memory cell array
2,097,152 bits
A16
I/O1 - I/O8
Sense / Switch
Input data
Output data
controller
controller
Column decoder
I/O9 - I/O16
Address buffer
/CE1
CE2
/LB
/UB
/WE
/OE
5
Data Sheet M14274EJ3V0DS00
µPD442012L-X
Truth Table
/CE1
CE2
/OE
/WE
/LB
/UB
Mode
I/O
Supply current
I/O1 - I/O8
I/O9 - I/O16
H
×
L
×
L
×
×
H
L
×
×
×
×
×
L
×
×
×
L
Not selected
High impedance
High impedance
ISB
H
H
H
Output disable
Word read
High impedance
DOUT
High impedance
DOUT
ICCA
L
H
L
Lower byte read
Upper byte read
Word write
DOUT
High impedance
DOUT
H
L
High impedance
DIN
×
L
L
DIN
L
H
L
Lower byte write
Upper byte write
Not selected
DIN
High impedance
DIN
H
H
High impedance
High impedance
×
×
×
×
H
High impedance
ISBNote
Note /CE1, CE2 = VIH or VIL
Remark × : Don’t care
6
Data Sheet M14274EJ3V0DS00
µPD442012L-X
Electrical Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
VCC
VT
Condition
Rating
Unit
V
–0.5Note to +4.0
Input / Output voltage
Operating ambient temperature
Storage temperature
–0.5Note to VCC+0.4 (4.0 V MAX.)
V
TA
–25 to +85
°C
°C
Tstg
–55 to +125
Note –3.0 V (MIN.) (Pulse width : 30 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
µPD442012L-BxxX µPD442012L-CxxX µPD442012L-DxxX Unit
MIN.
2.7
MAX.
3.6
MIN.
2.2
MAX.
3.6
MIN.
1.8
MAX.
3.6
Supply voltage
VCC
VIH
V
V
High level input voltage
Low level input voltage
2.7 V ≤ VCC ≤ 3.6 V
2.2 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.2 V
2.4
VCC+0.4
–
2.4
VCC+0.4
VCC+0.3
–
2.4
VCC+0.4
VCC+0.3
VCC+0.2
+0.2
–
2.0
2.0
–
–
–
1.6
VIL
TA
–0.3 Note
+0.5
+85
–0.3 Note
+0.3
–0.3 Note
V
Operating ambient
temperature
–25
–25
+85
–25
+85
°C
Note –1.5 V (MIN.) (Pulse width: 30 ns)
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Symbol
CIN
Test condition
MIN.
TYP.
MAX.
8
Unit
pF
VIN = 0 V
VI/O = 0 V
Input / Output capacitance
CI/O
10
pF
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These parameters are periodically sampled and not 100% tested.
7
Data Sheet M14274EJ3V0DS00
µPD442012L-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
Test condition
VCC ≥ 2.7 V
VCC ≥ 2.2 V
VCC ≥ 1.8 V
Unit
µPD442012L-BxxX µPD442012L-CxxX µPD442012L-DxxX
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX.
Input leakage
current
ILI
VIN = 0 V to VCC
–1.0
+1.0 –1.0
+1.0 –1.0
+1.0 µA
I/O leakage
current
ILO
VI/O = 0 V to VCC, /CE1 = VIH or
CE2 = VIL or /WE = VIL or /OE = VIH
/CE1 = VIL, CE2 = VIH,
–1.0
+1.0 –1.0
+1.0 –1.0
+1.0 µA
Operating
supply current
ICCA1
–
–
–
–
–
–
–
35
–
–
–
–
–
–
–
–
35
20
–
–
–
–
–
–
–
–
35 mA
Minimum cycle time,
II/O = 0 mA
VCC ≤ 2.7 V
VCC ≤ 2.2 V
20
15
10
8
–
ICCA2
/CE1 = VIL, CE2 = VIH,
II/O = 0 mA
10
–
10
8
VCC ≤ 2.7 V
VCC ≤ 2.2 V
–
–
6
ICCA3
/CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V,
8
8
8
Cycle = 1 MHz, II/O = 0 mA,
VIL ≤ 0.2 V,
VCC ≤ 2.7 V
VCC ≤ 2.2 V
–
–
–
–
–
–
6
–
–
–
6
VIH ≥ VCC – 0.2 V
5
Standby
ISB
ISB1
ISB2
ISB3
VOH
VOL
/CE1 = VIH or CE2 = VIL or
–
0.6
–
–
0.6
0.6
–
–
0.6 mA
0.6
supply current
/LB = /UB = VIH,
VCC ≤ 2.7 V
–
–
–
/CE1, CE2 = VIH or VIL VCC ≤ 2.2 V
/CE1 ≥ VCC − 0.2 V,
–
–
–
–
0.6
0.3
–
4
0.3
4
0.3
4
µA
CE2 ≥ VCC − 0.2 V
VCC ≤ 2.7 V
VCC ≤ 2.2 V
–
0.25 3.5
0.25 3.5
–
–
–
–
4
0.2
0.3
3
4
CE2 ≤ 0.2 V
0.3
–
4
0.3
VCC ≤ 2.7 V
VCC ≤ 2.2 V
–
0.25 3.5
0.25 3.5
–
–
–
–
4
0.2
0.3
3
4
/LB = /UB ≥ VCC − 0.2 V,
/CE1 ≤ 0.2 V,
0.3
–
4
0.3
VCC ≤ 2.7 V
VCC ≤ 2.2 V
–
0.25 3.5
0.25 3.5
CE2 ≥ VCC − 0.2 V
IOH = –0.5 mA
–
–
–
–
0.2
3
High level
2.4
–
2.4
1.8
–
2.4
1.8
1.5
V
V
output voltage
VCC ≤ 2.7 V
VCC ≤ 2.2 V
–
Low level
IOL = 1.0 mA
0.4
0.4
0.4
output voltage
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These DC characteristics are in common regardless of package types and access time.
8
Data Sheet M14274EJ3V0DS00
µPD442012L-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[ µPD442012L-B70X, µPD442012L-B85X ]
Input Waveform (Rise and Fall Time ≤ 5 ns)
2.4 V
1.5 V
Test points
1.5 V
0.5 V
Output Waveform
1.5 V
Test points
1.5 V
Output Load
1TTL + 50 pF
[ µPD442012L-C10X, µPD442012L-C12X ]
Input Waveform (Rise and Fall Time ≤ 5 ns)
2.0 V
1.1 V
0.3 V
Test points
1.1 V
Output Waveform
1.1 V
Test points
1.1 V
Output Load
1TTL + 30 pF
[ µPD442012L-D15X, µPD442012L-D20X ]
Input Waveform (Rise and Fall Time ≤ 5 ns)
1.6 V
0.9 V
0.2 V
Test points
0.9 V
Output Waveform
0.9 V
Test Points
0.9 V
Output Load
1TTL + 30 pF
9
Data Sheet M14274EJ3V0DS00
µPD442012L-X
Read Cycle
Parameter
Symbol
VCC ≥ 2.7 V
VCC ≥ 2.2 V
VCC ≥ 1.8 V
Unit Condition
µPD442012L µPD442012L µPD442012L µPD442012L µPD442012L µPD442012L
-B70X -B85X -C10X -C12X -D15X -D20X
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Read cycle time
tRC
tAA
70
85
100
120
150
200
ns
ns
ns
ns
ns
ns
ns
Address access time
/CE1 access time
CE2 access time
70
70
70
35
70
85
85
85
40
85
100
100
100
50
120
120
120
60
150
150
150
70
200
200
200
100
200
Note 1
tCO1
tCO2
tOE
tBA
/OE to output valid
/LB, /UB to output valid
100
120
150
Output hold from
address change
tOH
10
10
10
5
10
10
10
5
10
10
10
5
10
10
10
5
10
10
10
5
10
10
10
5
/CE1 to output
tLZ1
tLZ2
tOLZ
tBLZ
tHZ1
tHZ2
tOHZ
tBHZ
ns
ns
ns
ns
ns
ns
ns
ns
Note 2
in low impedance
CE2 to output
in low impedance
/OE to output
in low impedance
/LB, /UB to output
in low impedance
10
10
10
10
10
10
/CE1 to output
25
25
25
25
30
30
30
30
35
35
35
35
40
40
40
40
50
50
50
50
70
70
70
70
in high impedance
CE2 to output
in high impedance
/OE to output
in high impedance
/LB, /UB to output
in high impedance
Notes 1. The output load is 1TTL + 50 pF (µ
2. The output load is 1TTL + 5 pF.
-BxxX) or 1TTL + 30 pF (µ -CxxX, -DxxX).
PD442012L
PD442012L
Remark These AC characteristics are in common regardless of package types.
10
Data Sheet M14274EJ3V0DS00
µPD442012L-X
Read Cycle Timing Chart
t
RC
Address (Input)
/CE1 (Input)
t
AA
t
OH
t
CO1
CO2
t
t
HZ1
t
t
LZ1
CE2 (Input)
/OE (Input)
t
HZ2
LZ2
t
OE
t
OHZ
t
OLZ
/LB, /UB (Input)
I/O (Output)
t
BA
t
BHZ
t
BLZ
High impedance
Data out
Remark In read cycle, /WE should be fixed to high level.
11
Data Sheet M14274EJ3V0DS00
µPD442012L-X
Write Cycle
Parameter
Symbol
VCC ≥ 2.7 V
VCC ≥ 2.2 V
VCC ≥ 1.8 V
Unit Condition
µPD442012L µPD442012L µPD442012L µPD442012L µPD442012L µPD442012L
-B70X -B85X -C10X -C12X -D15X -D20X
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Write cycle time
tWC
tCW1
tCW2
tBW
tAW
tAS
70
55
55
55
55
0
85
70
70
70
70
0
100
80
80
80
80
0
120
100
100
100
100
0
150
120
120
120
120
0
200
160
160
160
160
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/CE1 to end of write
CE2 to end of write
/LB, /UB to end of write
Address valid to end of write
Address setup time
Write pulse width
tWP
tWR
tDW
tDH
50
0
55
0
60
0
85
0
100
0
140
0
Write recovery time
Data valid to end of write
Data hold time
30
0
35
0
40
0
60
0
80
100
0
0
/WE to output
tWHZ
25
30
35
40
50
70
Note
in high impedance
Output active
tOW
5
5
5
5
5
5
ns
from end of write
Note The output load is 1TTL + 5 pF.
Remark These AC characteristics are in common regardless of package types.
12
Data Sheet M14274EJ3V0DS00
µPD442012L-X
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
Address (Input)
t
CW1
CW2
/CE1 (Input)
CE2 (Input)
t
t
AW
t
AS
t
WP
t
WR
/WE (Input)
t
BW
/LB, /UB (Input)
t
OW
t
WHZ
t
DW
t
DH
High
High
I/O (Input / Output)
Indefinite data out
Data in
Indefinite data out
impe-
dance
impe-
dance
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are
opposite in phase with output signals.
Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a
high level CE2.
2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2
changes to high level at the same time or after the change of /WE to low level, the I/O pins will
remain high impedance state.
3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
13
Data Sheet M14274EJ3V0DS00
µPD442012L-X
Write Cycle Timing Chart 2 (/CE1 Controlled)
t
WC
Address (Input)
t
AS
t
CW1
/CE1 (Input)
CE2 (Input)
t
CW2
t
AW
t
WP
t
WR
/WE (Input)
t
BW
/LB, /UB (Input)
I/O (Input)
t
DW
t
DH
High impedance
High
Data in
impedance
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are
opposite in phase with output signals.
Remark Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high level
CE2.
14
Data Sheet M14274EJ3V0DS00
µPD442012L-X
Write Cycle Timing Chart 3 (CE2 Controlled)
t
WC
Address (Input)
/CE1 (Input)
t
CW1
t
AS
t
CW2
CE2 (Input)
t
AW
t
WP
t
WR
/WE (Input)
t
BW
/LB, /UB (Input)
t
DW
t
DH
High impedance
High
Data in
I/O (Input)
impedance
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are
opposite in phase with output signals.
Remark Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high level
CE2.
15
Data Sheet M14274EJ3V0DS00
µPD442012L-X
Write Cycle Timing Chart 4 (/LB, /UB Controlled)
t
WC
Address (Input)
t
t
CW1
CW2
/CE1 (Input)
CE2 (Input)
t
AW
t
WP
t
WR
/WE (Input)
t
AS
t
BW
/LB, /UB (Input)
I/O (Input)
t
DW
t
DH
High impedance
High
Data in
impedance
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are
opposite in phase with output signals.
Remark Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high level
CE2.
16
Data Sheet M14274EJ3V0DS00
µPD442012L-X
Low VCC Data Retention Characteristics (TA = –25 to +85 °C)
Parameter
Symbol
Test Condition
VCC ≥ 2.7 V
VCC ≥ 2.2 V
VCC ≥ 1.8 V
Unit
µPD442012L
-B××X
µPD442012L
-C××X
µPD442012L
-D××X
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX.
Data retention
supply voltage
VCCDR1
/CE1 ≥ VCC − 0.2 V,
2.0
3.6 1.5
3.6 1.5
3.6
V
CE2 ≥ VCC − 0.2 V
VCCDR2
VCCDR3
CE2 ≤ 0.2 V
2.0
2.0
3.6 1.5
3.6 1.5
3.6 1.5
3.6 1.5
3.6
3.6
/LB = /UB ≥ VCC − 0.2 V,
/CE1 ≤ 0.2 V, CE2 ≥ VCC − 0.2 V
Data retention
supply current
ICCDR1
VCC = 3.0 V, /CE1 ≥ VCC − 0.2 V,
CE2 ≥ VCC − 0.2 V or CE2 ≤ 0.2 V
0.3
4
0.3
4
0.3
4
µA
0.3
0.3
4
4
0.3
0.3
4
4
0.3
0.3
4
4
ICCDR2
ICCDR3
VCC = 3.0 V, CE2 ≤ 0.2 V
VCC = 3.0 V, /LB = /UB ≥ VCC − 0.2 V,
/CE1 ≤ 0.2 V, CE2 ≥ VCC − 0.2 V
Chip deselection
to data retention
mode
tCDR
0
0
0
ns
ns
Operation
tR
tRCNote
tRCNote
tRCNote
recovery time
Note tRC : Read cycle time
17
Data Sheet M14274EJ3V0DS00
µPD442012L-X
Data Retention Timing Chart
(1) /CE1 Controlled
t
CDR
Data retention mode
t
R
3.0 V
V
CC (MIN.)Note
V
CC
/CE1
V
IH (MIN.)
VCCDR (MIN.)
/CE1 ≥ VCC – 0.2 V
V
IL (MAX.)
GND
Note B version : 2.7 V, C version : 2.2 V, D version : 1.8 V
Remark On the data retention mode by controlling /CE1, the input level of CE2 must be ≥ VCC − 0.2 V or
≤ 0.2 V. The other pins (Address, I/O, /WE, /OE, /LB, /UB) can be in high impedance state.
(2) CE2 Controlled
t
CDR
Data retention mode
t
R
3.0 V
V
CC (MIN.)Note
V
CC
V
IH (MIN.)
V
CCDR (MIN.)
CE2
V
IL (MAX.)
GND
CE2 ≤ 0.2 V
Note B version : 2.7 V, C version : 2.2 V, D version : 1.8 V
Remark The other pins (/CE1, Address, I/O, /WE, /OE, /LB, /UB) can be in high impedance state.
18
Data Sheet M14274EJ3V0DS00
µPD442012L-X
(3) /LB, /UB Controlled
t
CDR
Data retention mode
t
R
3.0 V
V
CC (MIN.)Note
V
CC
/LB, /UB
V
IH (MIN.)
V
CCDR (MIN.)
/LB, /UB ≥ VCC – 0.2 V
V
IL (MAX.)
GND
Note B version : 2.7 V, C version : 2.2 V, D version : 1.8 V
Remark On the data retention mode by controlling /LB and /UB, the input level of /CE1 and CE2 must be ≥ VCC −
0.2 V or ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state.
19
Data Sheet M14274EJ3V0DS00
µPD442012L-X
Package Drawings
★
48-PIN PLASTIC TSOP(I) (12x18)
detail of lead end
1
48
F
G
R
Q
L
24
25
S
E
P
I
A
J
C
S
B
M
M
D
N
S
K
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
E
F
G
I
12.0±0.1
0.45 MAX.
0.5 (T.P.)
0.22±0.05
0.1±0.05
1.2 MAX.
1.0±0.05
16.4±0.1
0.8±0.2
0.145±0.05
0.5
2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
J
K
L
M
N
P
0.10
0.10
18.0±0.2
+5°
3°
Q
−3°
R
S
0.25
0.60±0.15
S48GY-50-MJH1-1
20
Data Sheet M14274EJ3V0DS00
µPD442012L-X
★
48-PIN PLASTIC TSOP(I) (12x18)
detail of lead end
1
48
E
S
L
Q
R
G
24
25
F
K
N
S
M
A
D
M
B
S
C
I
J
P
NOTES
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
C
D
E
F
G
I
12.0±0.1
0.45 MAX.
0.5 (T.P.)
0.22±0.05
0.1±0.05
1.2 MAX.
1.0±0.05
16.4±0.1
0.8±0.2
0.145±0.05
0.5
2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
J
K
L
M
N
P
0.10
0.10
18.0±0.2
+5°
3°
Q
−3°
R
S
0.25
0.60±0.15
S48GY-50-MKH1-1
21
Data Sheet M14274EJ3V0DS00
µPD442012L-X
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the µPD442012L-X.
Types of Surface Mount Device
µPD442012LGY-BxxX-MJH: 48-pin Plastic TSOP (I) (12×18) (Normal bent)
µPD442012LGY-BxxX-MKH: 48-pin Plastic TSOP (I) (12×18) (Reverse bent)
µPD442012LGY-CxxX-MJH: 48-pin Plastic TSOP (I) (12×18) (Normal bent)
µPD442012LGY-CxxX-MKH: 48-pin Plastic TSOP (I) (12×18) (Reverse bent)
µPD442012LGY-DxxX-MJH: 48-pin Plastic TSOP (I) (12×18) (Normal bent)
µPD442012LGY-DxxX-MKH: 48-pin Plastic TSOP (I) (12×18) (Reverse bent)
22
Data Sheet M14274EJ3V0DS00
µPD442012L-X
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
23
Data Sheet M14274EJ3V0DS00
µPD442012L-X
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
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