UPD444008LG5-A12-7JF [ETC]
x8 SRAM ; X8 SRAM\n
| 型号： | UPD444008LG5-A12-7JF |
| 厂家： | 
ETC |
| 描述： | x8 SRAM
|
| 文件： | 总16页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD444008L
4M-BIT CMOS FAST SRAM
512K-WORD BY 8-BIT
Description
The µPD444008L is a high speed, low power, 4,194,304 bits (524,288 words by 8 bits) CMOS static RAM.
Operating supply voltage is 3.3 V ± 0.3 V.
The µPD444008L is packaged in 36-pin plastic SOJ and 44-pin plastic TSOP (II).
Features
• 524,288 words by 8 bits organization
• Fast access time : 8, 10, 12, ns (MAX.)
• Output Enable input for easy application
• Single +3.3 V power supply
Ordering Information
Part number
Package
Access time
Supply current mA (MAX.)
ns (MAX.)
At operating
185
At standby
µPD444008LLE-A8
36-pin plastic SOJ
(10.16 mm (400))
8
5
µPD444008LLE-A10
10
12
8
165
µPD444008LLE-A12
155
µPD444008LG5-A8-7JF Note
µPD444008LG5-A10-7JF Note
µPD444008LG5-A12-7JF Note
44-pin plastic TSOP (II)
(10.16 mm (400))
(Normal bent)
185
•
•
•
10
12
165
155
•
Note Under development
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14429EJ3V0DS00 (3rd edition)
Date Published January 2001 NS CP(K)
Printed in Japan
The mark • shows major revised points.
1999
©
µ
PD444008L
Pin Configurations (Marking Side)
/××× indicates active low signal.
36-pin plastic SOJ (10.16 mm (400))
[ µPD444008LLE ]
A0
A1
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
2
A18
A17
A16
A15
/OE
I/O8
I/O7
GND
A2
3
A3
4
A4
5
/CS
I/O1
I/O2
6
7
8
V
CC
9
GND
I/O3
I/O4
/WE
A5
10
11
12
13
14
15
16
17
18
VCC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
A6
A7
A8
A9
A0 - A18
: Address Inputs
I/O1 - I/O8 : Data Inputs / Outputs
/CS
/WE
/OE
: Chip Select
: Write Enable
: Output Enable
: Power supply
: Ground
CC
V
GND
NC
: No connection
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M14429EJ3V0DS
2
µ
PD444008L
44-pin plastic TSOP (II) (10.16 mm (400)) (Normal bent)
[ µPD444008LG5-×××-7JF ]
NC
NC
A0
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
2
NC
3
NC
A1
4
A18
A17
A16
A15
/OE
I/O8
I/O7
GND
A2
5
A3
6
A4
7
/CS
I/O1
I/O2
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
V
CC
GND
I/O3
I/O4
/WE
A5
VCC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
A6
A7
A8
A9
NC
NC
NC
NC
A0 - A18
: Address Inputs
I/O1 - I/O8 : Data Inputs / Outputs
/CS
/WE
/OE
: Chip Select
: Write Enable
: Output Enable
: Power supply
: Ground
CC
V
GND
NC
: No connection
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M14429EJ3V0DS
3
µ
PD444008L
Block Diagram
A0
|
A18
Memory cell array
4,194,304 bits
I/O1
|
I/O8
Input data
controller
Sense amplifier /
Switching circuit
Output data
controller
Column decoder
Address buffer
/CS
/OE
/WE
V
CC
GND
Truth Table
/CS
H
/OE
×
/WE
×
Mode
Not selected
Read
I/O
High impedance
DOUT
Supply current
ISB
ICC
L
L
H
L
×
L
Write
DIN
L
H
H
Output disable
High impedance
Remark × : Don’t care
Data Sheet M14429EJ3V0DS
4
µ
PD444008L
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
VCC
VT
Condition
Rating
Unit
V
–0.5 Note to +4.0
–0.5 Note to +4.0
0 to 70
•
•
Supply voltage
Input / Output voltage
Operating ambient temperature
Storage temperature
V
TA
°C
°C
Tstg
–55 to +125
Note –2.0 V (MIN.) (pulse width : 2 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply voltage
Symbol
VCC
VIH
Condition
MIN.
3.0
TYP.
3.3
MAX.
3.6
Unit
V
High level input voltage
2.0
VCC+0.3
+0.8
V
Low level input voltage
VIL
–0.3 Note
0
V
Operating ambient temperature
TA
70
°C
Note –2.0 V (MIN.) (pulse width : 2 ns)
Data Sheet M14429EJ3V0DS
5
µ
PD444008L
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Input leakage current
Output leakage current
Symbol
ILI
Test condition
VIN = 0 V to VCC
MIN.
–2
TYP.
MAX.
+2
Unit
µA
ILO
VI/O = 0 V to VCC,
–2
+2
µA
/CS = VIH or /OE = VIH or /WE = VIL
Operating supply current
Standby supply current
ICC
/CS = VIL,
Cycle time : 8 ns
185
165
155
40
mA
mA
II/O = 0 mA,
Cycle time : 10 ns
Cycle time : 12 ns
Minimum cycle time
ISB
/CS = VIH, VIN = VIH or VIL
/CS ≥ VCC – 0.2 V,
ISB1
5
VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V
IOH = –4.0 mA
High level output voltage
Low level output voltage
VOH
VOL
2.4
V
V
IOL = +8.0 mA
0.4
IN
Remarks 1. V : Input voltage
I/O
V
: Input / Output voltage
2. These DC characteristics are in common regardless of package types.
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter Symbol
Input capacitance CIN
CI/O
Test condition
MIN.
TYP.
MAX.
Unit
pF
VIN = 0 V
VI/O = 0 V
6
8
Input / Output capacitance
pF
IN
Remarks 1. V : Input voltage
I/O
V
: Input / Output voltage
2. These parameters are periodically sampled and not 100% tested.
Data Sheet M14429EJ3V0DS
6
µ
PD444008L
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
Input Waveform (Rise and Fall Time ≤ 3 ns)
3.0 V
1.5 V
Test Points
1.5 V
GND
Output Waveform
1.5 V
Test Points
1.5 V
Output Load
AC characteristics directed with the note should be measured with the output load shown in Figure 1 or
Figure 2.
Figure 1
Figure 2
AA ACS OE OH
CLZ OLZ CHZ OHZ WHZ OW
(t , t , t , t
)
(t , t , t , t , t
, t
)
V
TT = +1.5 V
+3.3 V
50 Ω
317 Ω
ZO = 50 Ω
I/O (Output)
I/O (Output)
351 Ω
30 pF
5 pF
C
L
C
L
L
Remark C includes capacitances of the probe and jig, and stray capacitances.
Data Sheet M14429EJ3V0DS
7
µ
PD444008L
Read Cycle
Parameter
Symbol
µPD444008L-A8 µPD444008L-A10 µPD444008L-A12 Unit Notes
MIN.
8
MAX.
MIN.
10
MAX.
MIN.
12
MAX.
Read cycle time
tRC
tAA
tACS
tOE
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
8
8
4
10
10
5
12
12
6
1
/CS access time
/OE access time
Output hold from address change
/CS to output in low impedance
/OE to output in low impedance
/CS to output in high impedance
/OE to output hold in high impedance
tOH
3
3
0
3
3
0
3
3
0
tCLZ
tOLZ
tCHZ
tOHZ
2, 3
4
4
5
5
6
6
Notes 1. See the output load shown in Figure 1.
2. Transition is measured at ± 200 mV from steady-state voltage with the output load shown in Figure 2.
3. These parameters are periodically sampled and not 100% tested.
Remark These AC characteristics are in common regardless of package types.
Read Cycle Timing Chart 1 (Address Access)
t
RC
Address (Input)
I/O (Output)
t
AA
t
OH
Previous data out
Data out
Remarks 1. In read cycle, /WE should be fixed to high level.
IL
2. /CS = /OE = V
Data Sheet M14429EJ3V0DS
8
µ
PD444008L
Read Cycle Timing Chart 2 (/CS Access)
tRC
Address (Input)
t
AA
ACS
t
/CS (Input)
t
CLZ
t
CHZ
/OE (Input)
tOHZ
t
OE
t
OLZ
High impedance
High impedance
I/O (Output)
Data out
Caution Address valid prior to or coincident with /CS low level input.
Remark In read cycle, /WE should be fixed to high level.
Data Sheet M14429EJ3V0DS
9
µ
PD444008L
Write Cycle
Parameter
Symbol
µPD444008L-A8 µPD444008L-A10 µPD444008L-A12 Unit Notes
MIN.
MAX.
MIN.
10
7
MAX.
MIN.
12
8
MAX.
Write cycle time
tWC
tCW
tAW
tWP
tDW
tDH
8
6
6
6
4
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/CS to end of write
Address valid to end of write
Write pulse width
7
8
7
8
Data valid to end of write
Data hold time
5
6
0
0
Address setup time
tAS
0
0
Write recovery time
tWR
tWHZ
tOW
0
0
/WE to output in high impedance
Output active from end of write
4
5
6
1, 2
3
3
3
Notes 1. Transition is measured at ± 200 mV from steady-state voltage with the output load shown in Figure 2.
2. These parameters are periodically sampled and not 100% tested.
Remark These AC characteristics are in common regardless of package types.
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
Address (Input)
/CS (Input)
t
CW
t
AW
t
AS
t
WP
t
WR
/WE (Input)
t
OW
t
WHZ
t
DW
t
DH
High
High
I/O (Input / Output)
Indefinite data out
Data in
Indefinite data out
impe-
dance
impe-
dance
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. Do not input data to the I/O pins while they are in the output state.
•
Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE.
2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read
operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance.
Data Sheet M14429EJ3V0DS
10
µ
PD444008L
Write Cycle Timing Chart 2 (/CS Controlled)
t
WC
Address (Input)
t
AS
t
CW
/CS (Input)
/WE (Input)
t
t
AW
WP
t
WR
t
DW
t
DH
High impedance
High impedance
Data in
I/O (Input)
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. Do not input data to the I/O pins while they are in the output state.
•
Remark Write operation is done during the overlap time of a low level /CS and a low level /WE.
Data Sheet M14429EJ3V0DS
11
µ
PD444008L
Package Drawings
36-PIN PLASTIC SOJ (10.16 mm (400))
B
36
19
C
D
1
18
G
H
J
E
F
U
T
S
P
Q
S
M
M
N
K
I
NOTE
ITEM MILLIMETERS
B
C
D
E
F
G
H
I
23.6±0.20
10.16±0.1
11.18±0.2
1.005±0.1
0.74
Each lead centerline is located within 0.12 mm
of its true position (T.P.) at maximum material
condition.
3.5±0.2
2.545±0.2
0.8 MIN.
2.6
J
K
1.27 (T.P.)
+0.08
0.42
M
−0.07
N
P
Q
T
0.12
9.4±0.20
0.1
R 0.85
+0.08
0.22
U
−0.07
P36LE-400A-2
Data Sheet M14429EJ3V0DS
12
µ
PD444008L
44-PIN PLASTIC TSOP (II) (10.16 mm (400))
44
23
detail of lead end
F
P
E
1
22
A
H
I
G
J
S
C
N
S
L
M
D
M
K
B
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
A
B
C
18.63 MAX.
0.93 MAX.
0.8 (T.P.)
+0.08
0.32
D
−0.07
E
F
G
H
I
0.1±0.05
1.2 MAX.
0.97
11.76±0.2
10.16±0.1
0.8±0.2
J
+0.025
0.145
K
−0.015
L
M
N
0.5±0.1
0.13
0.10
+7°
3°
P
−3°
S44G5-80-7JF5-1
Data Sheet M14429EJ3V0DS
13
µ
PD444008L
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the µPD444008L.
Types of Surface Mount Device
µPD444008LLE
: 36-pin plastic SOJ (10.16 mm (400))
µPD444008LG5-7JF : 44-pin plastic TSOP (II) (10.16 mm (400)) (Normal bent)
Data Sheet M14429EJ3V0DS
14
µ
PD444008L
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet M14429EJ3V0DS
15
µ
PD444008L
•
The information in this document is current as of January, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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redundancy, fire-containment, and anti-failure features.
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"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
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support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
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to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
相关型号：
UPD444008LLE-A8-A
Standard SRAM, 512KX8, 8ns, CMOS, PDSO36, 0.400 INCH, LEAD FREE, PLASTIC, SOJ-36
NEC
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