UPD780031AGK-XXX-9ET [ETC]
Microcontroller ; 微控制器\n
| 型号： | UPD780031AGK-XXX-9ET |
| 厂家： | 
ETC |
| 描述： | Microcontroller
|
| 文件： | 总70页 (文件大小：567K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD780031A, 780032A, 780033A, and 780034A are members of the µPD780034A Subseries of the 78K/0
Series. Only selected functions of the existing µPD78054 Subseries are provided, and the serial interface is enhanced.
The µPD780031AY, 780032AY, 780033AY, and 780034AY are the µPD780034A Subseries with multimaster
supporting I2C bus interface, which makes them suitable for AV equipment.
Flash memory versions, the µPD78F0034A and 78F0034AY, that can operate in the same power supply voltage
range as the mask ROM version, and various development tools, are supported.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µPD780024A, 780034A, 780024AY, 780034AY
Subseries User’s Manual:
U14046E
U12326E
78K/0 Series User’s Manual Instructions:
FEATURES
Internal ROM and RAM
Item Program Memory
(Internal ROM)
Data Memory
Package
Part Number
(Internal High-Speed RAM)
µPD780031A, 780031AY
µPD780032A, 780032AY
µPD780033A, 780033AY
µPD780034A, 780034AY
8 KB
16 KB
24 KB
32 KB
512 bytes
• 64-pin plastic SDIP (19.05 mm (750))
• 64-pin plastic QFP (14 × 14)
• 64-pin plastic TQFP (12 × 12)
1024 bytes
External memory expansion space: 64 KB
Minimum instruction execution time: 0.24 µs (@ fX = 8.38 MHz operation)
I/O ports: 51 (5 V-tolerant N-ch open-drain: 4)
10-bit resolution A/D converter: 8 channels (AVDD = 1.8 to 5.5 V)
Serial interfaces: 3 channels
•
•
µPD780031A, 780032A, 780033A, 780034A: UART mode, 3-wire serial I/O mode (2 channels)
µPD780031AY, 780032AY, 780033AY, 780034AY: UART mode, 3-wire serial I/O mode, I2C bus mode
Timer: 5 channels
Power supply voltage: VDD = 1.8 to 5.5 V
APPLICATIONS
Telephones, household electrical appliances, pagers, AV equipment, car audios, office automation equipment, etc.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14044EJ3V0DS00 (3rd edition)
Date Published December 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
1999, 2000
©
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
ORDERING INFORMATION
Part Number
Package
µPD780031ACW-×××
64-pin plastic SDIP (19.05 mm (750))
64-pin plastic QFP (14 × 14)
64-pin plastic TQFP (12 × 12)
64-pin plastic SDIP (19.05 mm (750))
64-pin plastic QFP (14 × 14)
64-pin plastic TQFP (12 × 12)
64-pin plastic SDIP (19.05 mm (750))
64-pin plastic QFP (14 × 14)
64-pin plastic TQFP (12 × 12)
64-pin plastic SDIP (19.05 mm (750))
64-pin plastic QFP (14 × 14)
64-pin plastic TQFP (12 × 12)
64-pin plastic SDIP (19.05 mm (750))
64-pin plastic QFP (14 × 14)
64-pin plastic TQFP (12 × 12)
64-pin plastic SDIP (19.05 mm (750))
64-pin plastic QFP (14 × 14)
64-pin plastic TQFP (12 × 12)
64-pin plastic SDIP (19.05 mm (750))
64-pin plastic QFP (14 × 14)
64-pin plastic TQFP (12 × 12)
64-pin plastic SDIP (19.05 mm (750))
64-pin plastic QFP (14 × 14)
µPD780031AGC-×××-AB8
µPD780031AGK-×××-9ET
µPD780032ACW-×××
µPD780032AGC-×××-AB8
µPD780032AGK-×××-9ET
µPD780033ACW-×××
µPD780033AGC-×××-AB8
µPD780033AGK-×××-9ET
µPD780034ACW-×××
µPD780034AGC-×××-AB8
µPD780034AGK-×××-9ET
µPD780031AYCW-×××
µPD780031AYGC-×××-AB8
µPD780031AYGK-×××-9ET
µPD780032AYCW-×××
µPD780032AYGC-×××-AB8
µPD780032AYGK-×××-9ET
µPD780033AYCW-×××
µPD780033AYGC-×××-AB8
µPD780033AYGK-×××-9ET
µPD780034AYCW-×××
µPD780034AYGC-×××-AB8
µPD780034AYGK-×××-9ET
64-pin plastic TQFP (12 × 12)
Remark ××× indicates ROM code suffix.
2
Data Sheet U14044EJ3V0DS
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
78K/0 SERIES LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production
Products under development
Y subseries products are compatible with I2C bus.
Control
µ
EMI-noise reduced version of the PD78078
PD78075B
PD78078
µ
µ
µ
100-pin
100-pin
100-pin
100-pin
80-pin
µ
PD78054 with added timer and enhanced external interface
µ
µ
PD78078Y
PD78070A
PD78070AY
µ
ROM-less version of the PD78078
µ
µ
PD78078Y with enhanced serial I/O and limited function
PD780018AY
PD780058Y
µ
PD78054 with enhanced serial I/O
PD780058
µ
µ
PD78058F
PD78054
EMI-noise reduced version of the
µPD78054
µ
PD78058FY
PD78054Y
µ
80-pin
µ
µPD78018F with added UART and D/A converter and enhanced I/O
80-pin
µ
PD780065
µ
µ
RAM capacity of the PD780024A increased
80-pin
µ
µ
µ
PD780034A with added timer and enhanced serial I/O
PD780024A with enhanced A/D converter
PD78018F with enhanced serial I/O
PD780078Y
PD780034AY
PD780024AY
µ
µ
µ
µ
µ
µ
µ
µ
64-pin
64-pin
64-pin
64-pin
PD780078
PD780034A
PD780024A
PD78014H
PD78018F
PD78083
µ
EMI-noise reduced version of the
µPD78018F
Basic subseries for control
PD78018FY
64-pin
µ
On-chip UART, capable of operating at low voltage (1.8 V)
On-chip inverter controller and UART. EMI-noise reduced.
42-/44-pin
Inverter control
PD780988
64-pin
µ
VFD drive
µ
PD78044F with enhanced I/O and VFD C/D. Display output total: 53
For panel control. On-chip VFD and C/D. Display output total: 53
PD78044F with added N-ch open-drain I/O. Display output total: 34
Basic subseries for VFD drive. Display output total: 34
100-pin
80-pin
80-pin
80-pin
PD780208
PD780232
PD78044H
PD78044F
µ
µ
µ
µ
78K/0
Series
µ
LCD drive
µ
µ
µ
PD780308 with enhanced display function and timer. Segment signal output: 40 pins max.
PD780308 with enhanced display function and timer. Segment signal output: 32 pins max.
PD780308 with enhanced display function and timer. Segment signal output: 24 pins max.
120-pin
120-pin
120-pin
100-pin
100-pin
100-pin
PD780338
PD780328
PD780318
µ
µ
µ
PD780308Y
PD78064Y
µ
µ
PD78064 with enhanced SIO, and increased ROM, RAM capacity
EMI-noise reduced version of the PD78064
PD780308
µ
µ
µ
µ
PD78064B
PD78064
Basic subseries for LCD drive, on-chip UART
µ
Bus interface supported
100-pin
80-pin
µ
µ
PD780948
PD78098B
On-chip D-CAN controller
µ
PD78054 with added IEBusTM controller. EMI-noise reduced.
80-pin
80-pin
PD780701Y
PD780833Y
µ
µ
On-chip D-CAN/IEBus controller
On-chip controller compliant with J1850 (Class 2)
Meter control
PD780958
For industrial meter control
100-pin
80-pin
µ
On-chip automobile meter controller/driver
PD780852
µ
For automobile meter driver. On-chip D-CAN controller
80-pin
PD780824
µ
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.
Data Sheet U14044EJ3V0DS
3
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
The major functional differences among the subseries are shown below.
•
Non Y subseries
VDD
Function
Subseries Name
ROM
Capacity
Timer
8-Bit 10-Bit 8-Bit
A/D A/D D/A
Serial Interface
I/O
External
MIN.
Value Expansion
8-Bit 16-Bit Watch WDT
Control µPD78075B 32 K to 40 K 4 ch 1 ch 1 ch 1 ch 8 ch
µPD78078 48 K to 60 K
–
2 ch 3 ch (UART: 1 ch)
88 1.8 V
√
µPD78070A
–
61 2.7 V
µPD780058 24 K to 60 K 2 ch
µPD78058F 48 K to 60 K
µPD78054 16 K to 60 K
µPD780065 40 K to 48 K
µPD780078 48 K to 60 K
µPD780034A 8 K to 32 K
µPD780024A
3 ch (Time-division UART: 1 ch) 68 1.8 V
3 ch (UART: 1ch)
69 2.7 V
2.0 V
–
4 ch (UART: 1 ch)
3 ch (UART: 2 ch)
3 ch (UART: 1 ch,
time-division 3-wire: 1 ch)
2 ch
60 2.7 V
52 1.8 V
51
2 ch
1 ch
–
8 ch
–
8 ch
µPD78014H
53
µPD78018F 8 K to 60 K
µPD78083 8 K to 16 K
–
–
–
1 ch (UART: 1 ch)
3 ch (UART: 2 ch)
33
–
Inverter µPD780988 16 K to 60 K 3 ch Note
1 ch
–
8 ch
–
–
–
47 4.0 V
√
control
VFD
drive
µPD780208 32 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch
2 ch
74 2.7 V
40 4.5 V
68 2.7 V
–
µPD780232 16 K to 24 K 3 ch
–
–
4 ch
8 ch
µPD78044H 32 K to 48 K 2 ch 1 ch 1 ch
µPD78044F 16 K to 40 K
1 ch
2 ch
LCD
drive
µPD780338 48 K to 60 K 3 ch 2 ch 1 ch 1 ch
µPD780328
–
10 ch 1 ch 2 ch (UART: 1 ch)
54 1.8 V
–
62
70
µPD780318
µPD780308 48 K to 60 K 2 ch 1 ch
µPD78064B 32 K
8 ch
–
–
–
3 ch (Time-division UART: 1 ch) 57 2.0 V
2 ch (UART: 1 ch)
µPD78064 16 K to 32 K
Bus
interface
µPD780948 60 K
2 ch 2 ch 1 ch 1 ch 8 ch
1 ch
–
3 ch (UART: 1 ch)
2 ch (UART: 1 ch)
79 4.0 V
√
supported µPD78098B 40 K to 60 K
2 ch
–
69 2.7 V
69 2.2 V
–
–
Meter
control
µPD780958 48 K to 60 K 4 ch 2 ch
–
1 ch
–
–
–
Dash
board
µPD780852 32 K to 40 K 3 ch 1 ch 1 ch 1 ch 5 ch
–
3 ch (UART: 1 ch)
2 ch (UART: 1 ch)
56 4.0 V
59
–
control µPD780824 32 K to 60 K
Note 16-bit timer: 2 channels
10-bit timer: 1 channel
4
Data Sheet U14044EJ3V0DS
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
•
Y subseries
VDD
MIN.
Value
Function
ROM
Capacity
Timer
8-Bit 10-Bit 8-Bit
Serial Interface
I/O
External
Expansion
Subseries Name
Control µPD78078Y
µPD78070AY
8-Bit 16-Bit Watch WDT
48 K to 60 K 4 ch 1 ch 1 ch 1 ch 8 ch
–
–
2 ch 3 ch (UART: 1 ch,
88 1.8 V
61 2.7 V
88
√
2
I C: 1 ch)
2
µPD780018AY 48 K to 60 K
–
3 ch (I C: 1 ch)
µPD780058Y 24 K to 60 K 2 ch
2 ch 3 ch (Time division 68 1.8 V
2
UART: 1 ch, I C: 1 ch)
µPD78058FY 48 K to 60 K
3 ch (UART: 1 ch,
69 2.7 V
2.0 V
2
I C: 1 ch)
µPD78054Y
16 K to 60 K
µPD780078Y 48 K to 60 K
2 ch
1 ch
–
8 ch
–
4 ch (UART: 2 ch,
52 1.8 V
2
I C: 1 ch)
µPD780034AY 8 K to 32 K
µPD780024AY
3 ch (UART: 1 ch,
51
2
I C: 1 ch)
8 ch
–
–
2
µPD78018FY 8 K to 60 K
2 ch (I C: 1 ch)
53
LCD
drive
µPD780308Y 48 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch
–
–
3 ch (Time division 57 2.0 V
–
–
2
UART: 1 ch, I C: 1 ch)
µPD78064Y
16 K to 32 K
2 ch (UART: 1 ch,
2
I C: 1 ch)
For bus µPD780701Y 60 K
3 ch 2 ch 1 ch 1 ch 16 ch
–
4 ch (UART: 1 ch,
67 3.5 V
65 4.5 V
2
interface
I C: 1 ch)
µPD780833Y
Remark The functions of non Y subseries and Y subseries products are the same, except for the serial interface.
Data Sheet U14044EJ3V0DS
5
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
OVERVIEW OF FUNCTIONS
Part Number
µPD780031A
µPD780032A
µPD780033A
µPD780034A
Item
µPD780031AY
µPD780032AY
µPD780033AY
µPD780034AY
Internal
memory
ROM
8 KB
16 KB
24 KB
1024 bytes
32 KB
High-speed RAM
512 bytes
64 KB
Memory space
General-purpose registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution
time
On-chip minimum instruction execution time cycle variable function
When main system 0.24 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs (@ 8.38 MHz operation)
clock selected
When subsystem
clock selected
122 µs (@ 32.768 kHz operation)
Instruction set
I/O ports
• 16-bit operation
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulation (set, reset, test, Boolean operation)
• BCD adjust, etc.
Total:
51
• CMOS input:
8
• CMOS I/O:
39
4
• 5 V-tolerant N-ch open-drain I/O :
A/D converter
• 10-bit resolution × 8 channels
• Low-voltage operation available: AVDD = 1.8 to 5.5 V
Serial interfaces
• µPD780031A, 780032A, 780033A, 780034A
UART mode:
1 channel
3-wire serial I/O mode:
2 channels
• µPD780031AY, 780032AY, 780033AY, 780034AY
UART mode:
1 channel
3-wire serial I/O mode:
1 channel
I2C bus mode (multimaster supporing): 1 channel
Timers
• 16-bit timer/event counter:
• 8-bit timer/event counter:
• Watch timer:
1 channel
2 channels
1 channel
1 channel
• Watchdog timer:
Timer outputs
Clock output
3 (8-bit PWM output capable: 2)
• 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz
(@ 8.38 MHz operation with main system clock )
• 32.768 kHz (@ 32.768 kHz operation with subsystem clock)
Buzzer output
1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (@ 8.38 MHz operation with main system clock)
Vectored
interrupt
sources
Maskable
Internal: 13, external: 5
Internal: 1
Non-maskable
Software
1
Power supply voltage
Operating ambient temperature
Package
VDD = 1.8 to 5.5 V
TA = –40 to +85°C
• 64-pin plastic SDIP (19.05 mm (750))
• 64-pin plastic QFP (14 × 14)
• 64-pin plastic TQFP (12 × 12)
6
Data Sheet U14044EJ3V0DS
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ................................................................................................8
2. BLOCK DIAGRAM ............................................................................................................................11
3. PIN FUNCTIONS ...............................................................................................................................12
3.1 Port Pins .................................................................................................................................................... 12
3.2 Non-Port Pins............................................................................................................................................ 13
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins..................................................... 15
4. MEMORY SPACE ..............................................................................................................................17
5. PERIPHERAL HARDWARE FUNCTION FEATURES ...................................................................18
5.1 Ports ........................................................................................................................................................... 18
5.2 Clock Generator........................................................................................................................................ 19
5.3 Timer/Counter ........................................................................................................................................... 20
5.4 Clock Output/Buzzer Output Controller ................................................................................................ 23
5.5 A/D Converter ........................................................................................................................................... 24
5.6 Serial Interface.......................................................................................................................................... 25
6. INTERRUPT FUNCTIONS ................................................................................................................28
7. EXTERNAL DEVICE EXPANSION FUNCTION ............................................................................31
8. STANDBY FUNCTION ......................................................................................................................31
9. RESET FUNCTION ...........................................................................................................................32
10. MASK OPTION..................................................................................................................................32
11. INSTRUCTION SET ..........................................................................................................................33
12. ELECTRICAL SPECIFICATIONS.....................................................................................................35
13. PACKAGE DRAWINGS.....................................................................................................................57
14. RECOMMENDED SOLDERING CONDITIONS..............................................................................60
APPENDIX A. DEVELOPMENT TOOLS ...............................................................................................62
APPENDIX B. RELATED DOCUMENTS ..............................................................................................65
Data Sheet U14044EJ3V0DS
7
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
1. PIN CONFIGURATION (TOP VIEW)
•
64-pin plastic SDIP (19.05 mm (750))
µPD780031ACW-×××, 780032ACW-×××, 780033ACW-×××, 780034ACW-×××,
µPD780031AYCW-×××, 780032AYCW-×××, 780033AYCW-×××, 780034AYCW-×××
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
P50/A8
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P67/ASTB
P66/WAIT
2
3
P65/WR
4
P64/RD
5
P75/BUZ
6
P74/PCL
7
P73/TI51/TO51
P72/TI50/TO50
P71/TI01
8
9
P51/A9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P70/TI00/TO0
P03/INTP3/ADTRG
P02/INTP2
P01/INTP1
P00/INTP0
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
V
SS1
X1
VSS0
X2
VDD0
IC
P30
XT1
P31
XT2
P32/SDA0Note 1
P33/SCL0Note 1
P34/SI31Note 2
P35/SO31Note 2
P36/SCK31Note 2
P20/SI30
RESET
AVDD
AVREF
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
P14/ANI4
P15/ANI5
P16/ANI6
P17/ANI7
AVSS
P21/SO30
P22/SCK30
P23/RxD0
P24/TxD0
P25/ASCK0
VDD1
Notes 1. SDA0 and SCL0 are incorporated only in the µPD780034AY Subseries.
2. SI31, SO31, and SCK31 are incorporated only in the µPD780034A Subseries.
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.
2. Connect the AVSS pin to VSS0.
Remark WhentheµPD780031A,780032A,780033A,780034A,780031AY,780032AY,780033AY,and 780034AY
are used in applications where the noise generated inside the microcontroller needs to be reduced, the
implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually
and connecting VSS0 and VSS1 to different ground lines, is recommended.
8
Data Sheet U14044EJ3V0DS
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
•
•
64-pin plastic QFP (14 × 14)
µPD780031AGC-×××-AB8, 780032AGC-×××-AB8, 780033AGC-×××-AB8, 780034AGC-×××-AB8,
µPD780031AYGC-×××-AB8, 780032AYGC-×××-AB8, 780033AYGC-×××-AB8, 780034AYGC-×××-AB8
64-pin plastic TQFP (12 × 12)
µPD780031AGK-×××-9ET, 780032AGK-×××-9ET, 780033AGK-×××-9ET, 780034AGK-×××-9ET,
µPD780031AYGK-×××-9ET, 780032AYGK-×××-9ET, 780033AYGK-×××-9ET, 780034AYGK-×××-9ET
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P50/A8
P51/A9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P71/TI01
2
P70/TI00/TO0
P03/INTP3/ADTRG
P02/INTP2
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
3
4
5
P01/INTP1
6
P00/INTP0
7
VSS1
8
X1
VSS0
9
X2
VDD0
10
11
12
13
14
15
16
IC
P30
P31
XT1
XT2
P32/SDA0Note 1
P33/SCL0Note 1
P34/SI31Note 2
P35/SO31Note 2
RESET
AVDD
AVREF
P10/ANI0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Data Sheet U14044EJ3V0DS
9
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
Notes 1. SDA0 and SCL0 are incorporated only in the µPD780034AY Subseries.
2. SI31, SO31, and SCK31 are incorporated only in the µPD780034A Subseries.
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.
2. Connect the AVSS pin to VSS0.
Remark WhentheµPD780031A,780032A,780033A,780034A,780031AY,780032AY,780033AY,and780034AY
are used in applications where the noise generated inside the microcontroller needs to be reduced, the
implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually
and connecting VSS0 and VSS1 to different ground lines, is recommended.
A8 to A15:
AD0 to AD7:
ADTRG:
Address Bus
Address/Data Bus
AD Trigger Input
Analog Input
P70 to P75:
PCL:
Port 7
Programmable Clock
Read Strobe
Reset
RD:
ANI0 to ANI7:
ASCK0:
RESET:
RxD0:
Asynchronous Serial Clock
Address Strobe
Analog Power Supply
Analog Reference Voltage
Analog Ground
Buzzer Clock
Internally Connected
External Interrupt Input
Port 0
Receive Data
ASTB:
SCK30, SCK31, SCL0: Serial Clock
AVDD:
SDA0:
Serial Data
AVREF:
SI30, SI31:
SO30, SO31:
TI00, TI01, TI50, TI51:
TO0, TO50, TO51:
TxD0:
Serial Input
AVSS:
Serial Output
Timer Input
BUZ:
IC:
Timer Output
Transmit Data
Power Supply
Ground
INTP0 to INTP3:
P00 to P03:
P10 to P17:
P20 to P25:
P30 to P36:
P40 to P47:
P50 to P57:
P64 to P67:
VDD0, VDD1:
VSS0, VSS1:
WAIT:
Port 1
Port 2
Wait
Port 3
WR:
Write Strobe
Port 4
X1, X2:
Crystal (Main System Clock)
Crystal (Subsystem Clock)
Port 5
XT1, XT2:
Port 6
10
Data Sheet U14044EJ3V0DS
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
2. BLOCK DIAGRAM
TI00/TO0/P70
TI01/P71
Port 0
Port 1
P00 to P03
P10 to P17
P20 to P25
P30 to P36
P40 to P47
P50 to P57
16-bit timer/
event counter
8-bit timer/
event counter 50
TI50/TO50/P72
TI51/TO51/P73
8-bit timer/
event counter 51
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Watchdog timer
Watch timer
78K/0
CPU core
ROM
SI30/P20
SO30/P21
SCK30/P22
Serial
interface 30
P64 to P67
P70 to P75
SI31/P34
SO31/P35
SCK31/P36
Serial
interface 31Note 1
RAM
RxD0/P23
TxD0/P24
ASCK0/P25
AD0/P40 to
AD7/P47
UART0
A8/P50 to
A15/P57
SDA0/P32
SCL0/P33
External
access
I2C busNote 2
RD/P64
WR/P65
WAIT/P66
ASTB/P67
ANI0/P10 to
ANI7/P17
AVDD
AVSS
A/D converter
AVREF
RESET
X1
X2
XT1
XT2
System
control
INTP0/P00 to
INTP3/P03
Interrupt control
Buzzer output
BUZ/P75
PCL/P74
Clock output
control
V
DD0
V
DD1
V
SS0
VSS1 IC
Notes 1. Incorporated only in the µPD780034A Subseries.
2. Incorporated only in the µPD780034AY Subseries.
Remark The internal ROM and RAM capacities vary depending on the product.
Data Sheet U14044EJ3V0DS
11
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
Pin Name
I/O
Function
After
Alternate
Function
Reset
P00
P01
P02
P03
I/O
Port 0
Input
INTP0
4-bit I/O port
INTP1
Input/output can be specified in 1-bit units.
INTP2
An on-chip pull-up resistor can be specified by means of software.
INTP3/ADTRG
ANI0 to ANI7
P10 to P17 Input Port 1
8-bit input-only port
Input
Input
P20
I/O
Port 2
SI30
6-bit I/O port
P21
SO30
SCK30
RxD0
TxD0
ASCK0
—
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
P22
P23
P24
P25
P30
I/O
Port 3
N-ch open-drain I/O port
Input
7-bit I/O port
An on-chip pull-up resistor can be
specified by the mask option.
LEDs can be driven directly.
P31
Input/output can be specified in
1-bit units.
P32
SDA0Note 1
SCL0Note 1
SI31Note 2
P33
P34
An on-chip pull-up resistor can be
specified by means of software.
P35
SO31Note 2
SCK31Note 2
AD0 to AD7
P36
P40 to P47
I/O
I/O
I/O
Port 4
Input
Input
Input
8-bit I/O port
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
The interrupt request flag (KRIF) is set to 1 by falling edge detection.
P50 to P57
Port 5
A8 to A15
8-bit I/O port
LEDs can be driven directly.
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
P64
P65
P66
P67
Port 6
RD
4-bit I/O port
WR
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
WAIT
ASTB
Notes 1. SDA0 and SCL0 are incorporated only in the µPD780034AY Subseries.
2. SI31, SO31, and SCK31 are incorporated only in the µPD780034A Subseries.
12
Data Sheet U14044EJ3V0DS
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
3.1 Port Pins (2/2)
Pin Name
I/O
Function
After
Alternate
Function
Reset
P70
P71
P72
P73
P74
P75
I/O
Port 7
Input
TI00/TO0
TI01
6-bit I/O port
Input/output can be specified in 1-bit units.
TI50/TO50
TI51/TO51
PCL
An on-chip pull-up resistor can be specified by means of software.
BUZ
3.2 Non-Port Pins (1/2)
Pin Name
I/O
Function
After
Alternate
Function
Reset
INTP0
Input External interrupt request input for which the valid edge (rising edge,
falling edge, or both rising and falling edges) can be specified
Input
P00
INTP1
P01
INTP2
P02
INTP3
P03/ADTRG
P20
SI30
Input Serial interface serial data input
Output Serial interface serial data output
Input
SI31Note 1
SO30
P34
Input
Input
P21
SO31Note 1
SDA0Note 2
SCK30
SCK31Note 1
SCL0Note 2
RxD0
P35
I/O
I/O
Serial interface serial data input/output
Serial interface serial clock input/output
P32
Input
P22
P36
P33
Input Serial data input for asynchronous serial interface
Output Serial data output for asynchronous serial interface
Input Serial clock input for asynchronous serial interface
Input
Input
P23
TxD0
P24
ASCK0
P25
Notes 1. SI31, SO31, and SCK31 are incorporated only in the µPD780034A Subseries.
2. SDA0 and SCL0 are incorporated only in the µPD780034AY Subseries.
Data Sheet U14044EJ3V0DS
13
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
3.2 Non-Port Pins (2/2)
Pin Name
I/O
Function
After
Alternate
Function
Reset
TI00
Input External count clock input to 16-bit timer/event counter 0
Capture trigger input to capture register 01 (CR01) of 16-bit timer/event
counter 0
Input
P70/TO0
TI01
Capture trigger input to capture register 00 (CR00) of 16-bit timer/event
counter 0
P71
TI50
External count clock input to 8-bit timer/event counter 50
External count clock input to 8-bit timer/event counter 51
Output 16-bit timer/event counter 0 output
P72/TO50
P73/TO51
P70/TI00
P72/TI50
P73/TI51
P74
TI51
TO0
Input
Input
TO50
TO51
PCL
8-bit timer/event counter 50 output (also used for 8-bit PWM output)
8-bit timer/event counter 51 output (also used for 8-bit PWM output)
Output Clock output (for trimming of main system clock and subsystem clock)
Output Buzzer output
Input
Input
Input
Input
Input
BUZ
P75
AD0 to AD7
A8 to A15
RD
I/O
Lower address/data bus for expanding memory externally
P40 to P47
P50 to P57
P64
Output Higher address bus for expanding memory externally
Output Strobe signal output for reading from external memory
Strobe signal output for writing to external memory
WR
P65
WAIT
ASTB
Input Wait insertion at external memory access
Input
Input
P66
Output Strobe output that externally latches address information output to
ports 4 and 5 to access external memory
P67
ANI0 to ANI7 Input A/D converter analog input
Input
Input
—
P10 to P17
ADTRG
AVREF
AVDD
AVSS
RESET
X1
Input A/D converter trigger signal input
P03/INTP3
Input A/D converter reference voltage input
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
A/D converter analog power supply. Set potential to that of VDD0 or VDD1
A/D converter ground potential. Set potential to that of VSS0 or VSS1
—
—
Input System reset input
—
Input Connecting crystal resonator for main system clock oscillation
—
X2
—
—
XT1
Input Connecting crystal resonator for subsystem clock oscillation
—
XT2
—
—
VDD0
VSS0
—
—
—
—
—
Positive power supply for ports
—
Ground potential of ports
—
VDD1
VSS1
Positive power supply (except ports)
Ground potential (except ports)
—
—
IC
Internally connected. Connect directly to VSS0 or VSS1.
—
14
Data Sheet U14044EJ3V0DS
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the input/output circuit configuration of each type, see Figure 3-1.
Table 3-1. Types of Pin I/O Circuits
Pin Name
Input/Output
Circuit Type
I/O
Recommended Connection of Unused Pins
P00/INTP0
8-C
Input
Input: Independently connect to VSS0 via a resistor.
Output: Leave open.
P01/INTP1
P02/INTP2
P03/INTP3/ADTRG
P10/ANI0 to P17/ANI7
P20/SI30
25
Input
I/O
Connect to VDD0 or VSS0.
Input: Independently connect to VDD0 or VSS0 via a
resistor.
8-C
5-H
8-C
P21/SO30
P22/SCK30
P23/RxD0
Output: Leave open.
P24/TxD0
5-H
8-C
P25/ASCK0
P30, P31
13-Q
13-S
I/O
Input: Independently connect to VDD0 via a resistor.
Output: Leave open.
P32, P33
(µPD780034A Subseries only)
P32/SDA0
13-R
(µPD780034AY Subseries only)
P33/SCL0
(µPD780034AY Subseries only)
P34/SI31Note
8-C
5-H
8-C
5-H
Input: Independently connect to VDD0 or VSS0 via a
P35/SO31Note
resistor.
P36/SCK31Note
Output: Leave open.
P40/AD0 to P47/AD7
I/O
Input: Independently connect to VDD0 via a resistor.
Output: Leave open.
P50/A8 to P57/A15
P64/RD
I/O
I/O
Input: Independently connect to VDD0 or VSS0 via a
resistor.
P65/WR
P66/WAIT
P67/ASTB
P70/TI00/TO0
P71/TI01
P72/TI50/TO50
P73/TI51/TO51
P74/PCL
P75/BUZ
RESET
Output: Leave open.
8-C
5-H
2
Input
—
Connect to VDD0.
XT1
16
XT2
—
Leave open.
AVDD
—
Connect to VDD0 or VDD1.
Connect to VSS0 or VSS1.
AVREF
AVSS
IC
Connect directly to VSS0 or VSS1.
Note SI31, SO31, and SCK31 are incorporated only in the µPD780034A Subseries.
Data Sheet U14044EJ3V0DS
15
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
Figure 3-1. Pin I/O Circuits
TYPE 2
TYPE 13-R
IN/OUT
Data
Output disable
N-ch
IN
V
SS0
Schmitt-triggered input with hysteresis characteristics
TYPE 13-S
TYPE 5-H
V
DD0
V
DD0
Mask
option
IN/OUT
Pullup
enable
P-ch
Data
Output disable
N-ch
VDD0
Data
P-ch
V
SS0
IN/OUT
Output
disable
N-ch
VSS0
Input
enable
TYPE 8-C
TYPE 16
VDD0
Feedback
cut-off
Pullup
enable
P-ch
P-ch
VDD0
Data
P-ch
IN/OUT
Output
disable
N-ch
VSS0
XT1
XT2
TYPE 25
TYPE 13-Q
VDD0
Mask
option
IN/OUT
P-ch
N-ch
Comparator
Data
Output disable
+
N-ch
–
VSS0
V
SS0
IN
VREF (threshold voltage)
Input
enable
Input
enable
16
Data Sheet U14044EJ3V0DS
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
4. MEMORY SPACE
Figure 4-1 shows the memory map of the µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY,
780033AY, and 780034AY.
Figure 4-1. Memory Map
FFFFH
Special function registers (SFRs)
256 × 8 bits
FF00H
FEFFH
General-purpose
registers
32 × 8 bits
FEE0H
FEDFH
Internal high-speed
RAMNote
mmmmH
mmmmH – 1
nnnnH
Data memory
space
Reserved
Program area
1000H
0FFFH
CALLF entry area
F800H
F7FFH
0800H
07FFH
Program area
CALLT table area
Vector table area
External memory
Internal ROMNote
0080H
007FH
Program memory
space
nnnnH + 1
nnnnH
0040H
003FH
0000H
0000H
Note The internal ROM and internal high-speed RAM capacities vary depending on the product (see the following
table).
Part Number
Last Address of Internal ROM
nnnnH
Start Address of Internal High-Speed RAM
mmmmH
µPD780031A, 780031AY
µPD780032A, 780032AY
µPD780033A, 780033AY
µPD780034A, 780034AY
1FFFH
3FFFH
5FFFH
7FFFH
FD00H
FB00H
Data Sheet U14044EJ3V0DS
17
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
5. PERIPHERAL HARDWARE FUNCTION FEATURES
5.1 Ports
The following 3 types of I/O ports are available.
•
•
•
CMOS input (Port 1):
8
CMOS I/O (Ports 0, 2, 4 to 7, P34 to P36): 39
N-ch open-drain I/O (P30 to P33):
Total:
4
51
Table 5-1. Port Functions
Name
Pin Name
Function
Port 0
P00 to P03
I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
Port 1
Port 2
P10 to P17
P20 to P25
Input-only port.
I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
Port 3
P30 to P33
N-ch open-drain I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by mask option.
LEDs can be driven directly.
P34 to P36
P40 to P47
I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
Port 4
Port 5
I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
The interrupt request flag (KRIF) is set to 1 by falling edge detection.
P50 to P57
I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
LEDs can be driven directly.
Port 6
Port 7
P64 to P67
P70 to P75
I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
18
Data Sheet U14044EJ3V0DS
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
5.2 Clock Generator
A system clock generator is incorporated.
The minimum instruction execution time can be changed.
•
•
0.24 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs (@ 8.38 MHz operation with main system clock)
122 µs (@ 32.768 kHz operation with subsystem clock)
Figure 5-1. Clock Generator Block Diagram
XT1
XT2
Subsystem
clock
oscillator
f
XT
Watch timer, clock
output function
Prescaler
1
2
X1
X2
Main system
clock
oscillator
f
XT
Clock to peripheral
hardware
Prescaler
2
f
X
f
2
X
f
X
f
X
23
f
X
24
22
Standby
controller
Wait
controller
STOP
CPU clock
Selector
(fCPU
)
Data Sheet U14044EJ3V0DS
19
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
5.3 Timer/Counter
Five timer/counter channels are incorporated.
•
•
•
•
16-bit timer/event counter: 1 channel
8-bit timer/event counter: 2 channels
Watch timer:
1 channel
1 channel
Watchdog timer:
Table 5-2. Operations of Timer/Event Counter
16-Bit Timer/
8-Bit Timer/
Watch Timer
Watchdog Timer
Event Counter 0
Event Counters 50, 51
Operation mode
Interval timer
1 channel
1 channel
2 channels
2 channels
1 channelNote 1
—
1 channelNote 2
—
External event counter
Function
Timer output
1
2
—
2
—
—
—
—
—
2
—
—
—
—
—
1
PPG output
1
PWM output
—
Pulse width measurement
Square wave output
Interrupt source
2 inputs
—
2
1
2
2
Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.
2. The watchdog timer has the watchdog timer and interval timer functions. However, use the watchdog timer
by selecting either the watchdog timer function or the interval timer function.
Figure 5-2. Block Diagram of 16-Bit Timer/Event Counter 0
Internal bus
INTTM00
Noise
elimi-
nator
16-bit capture/compare
register 00 (CR00)
TI01/P71
Match
f
X
f
f
X
/22
/26
16-bit timer counter 0
(TM0)
X
Clear
Output
controller
TO0/TI00/P70
Match
Noise
elimi-
nator
f
/23
X
Noise
elimi-
nator
16-bit capture/compare
register 01 (CR01)
TI00/TO0/P70
INTTM01
Internal bus
20
Data Sheet U14044EJ3V0DS
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
Figure 5-3. Block Diagram of 8-Bit Timer/Event Counter 50
Internal bus
8-bit compare
register 50 (CR50)
Selector
INTTM50
TI50/TO50/P72
Match
fX
f
f
f
f
X
X
X
X
/22
/24
/26
/28
S
INV
Q
8-bit timer
OVF
TO50/TI50/P72
counter 50 (TM50)
R
f
X
/210
Clear
S
R
Level
inversion
3
Selector
TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50
TCL502 TCL501 TCL500
8-bit timer mode control
register 50 (TMC50)
Timer clock select
register 50 (TCL50)
Internal bus
Figure 5-4. Block Diagram of 8-Bit Timer/Event Counter 51
Internal bus
8-bit compare
register 51
(CR51)
Selector
INTTM51
TI51/TO51/P73
/2
Match
f
X
f
f
f
f
X
X
X
X
/23
S
Q
/25
/27
/29
INV
OVF
8-bit timer
TO51/TI51/P73
counter 51 (TM51)
R
f
X
/211
Clear
S
R
Level
inversion
3
Selector
TCE51 TMC516 TMC514 LVS51 LVR51 TMC511 TOE51
TCL512 TCL511 TCL510
8-bit timer mode control
register 51 (TMC51)
Timer clock select
register 51 (TCL51)
Internal bus
Data Sheet U14044EJ3V0DS
21
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
Figure 5-5. Watch Timer Block Diagram
Clear
f
/27
X
5-bit counter
INTWT
INTWTI
9-bit prescaler
fW
fW
f
W
fW
fW
f
W
f
W
29
Clear
24 25 26 27 28
fXT
WTM7 WTM6 WTM5 WTM4 WTM1 WTM0
Watch timer operation
mode register (WTM)
Internal bus
Figure 5-6. Watchdog Timer Block Diagram
fX
Clock
input
controller
Divided
clock
selector
INTWDT
RESET
fX
/28
Divider
Output
controller
RUN
Division mode
selector
3
WDT mode signal
OSTS2 OSTS1 OSTS0
WDCS2 WDCS1 WDCS0
RUN WDTM4WDTM3
Oscillation
Watchdog timer
clock select
register (WDCS)
Watchdog timer
mode register
(WDTM)
stabilization time
select register
(OSTS)
Internal bus
22
Data Sheet U14044EJ3V0DS
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
5.4 Clock Output/Buzzer Output Controller
A clock output/buzzer output controller (CKU) is incorporated.
Clocks with the following frequencies can be output as clock output.
•
•
65.5 kHz/131 kHz/262 kHz/524 kHz/1.05 MHz/2.10 MHz/4.19 MHz/8.38 MHz (@ 8.38 MHz operation with main
system clock)
32.768 kHz (@ 32.768 kHz operation with subsystem clock)
Clocks with the following frequencies can be output as buzzer output.
•
1.02 kHz/2.05 kHz/4.10 kHz/8.19 kHz (@ 8.38 MHz operation with main system clock)
Figure 5-7. Block Diagram of Clock Output/Buzzer Output Controller CKU
Prescaler
8
f
X
/210 to f /213
X
4
f
X
BUZ/P75
PCL/P74
BCS0, BCS1
BZOE
f
X
to f
X
/27
Clock
controller
f
XT
CLOE
BZOE BCS1 BCS0 CLOE CCS3 CCS2 CCS1 CCS0
Clock output select register (CKS)
Internal bus
Data Sheet U14044EJ3V0DS
23
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
5.5 A/D Converter
An A/D converter consisting of eight 10-bit resolution channels is incorporated.
The following two A/D conversion operation startup methods are available.
•
•
Hardware start
Software start
Figure 5-8. A/D Converter Block Diagram
Series resistor string
AVDD
Sample & hold circuit
Voltage comparator
ANI0/P10
ANI1/P11
ANI2/P12
ANI3/P13
ANI4/P14
ANI5/P15
ANI6/P16
ANI7/P17
AVREF
Tap
selector
Selector
Succesive approximation
register (SAR)
AVSS
Edge
detector
INTAD
ADTRG/INTP3/P03
Controller
A/D conversion
result register 0 (ADCR0)
Edge
detector
INTP3
Internal bus
Data Sheet U14044EJ3V0DS
24
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
5.6 Serial Interface
Three serial interface channels are incorporated.
•
•
µPD780034A Subseries
Serial interface UART0: 1 channel
Serial interface 30, 31:
2 channels
µPD780034AY Subseries
Serial interface UART0: 1 channel
Serial interface 30:
Serial interface IIC0:
1 channel
1 channel
(1) Serial interface UART0
Serial interface UART0 has two modes: asynchronous serial interface (UART) mode and infrared data transfer
mode.
•
Asynchronous serial interface (UART) mode
This mode enables full-duplex operation wherein one byte of data starting from the start bit is transmitted
and received.
The on-chip UART-dedicated baud-rate generator enables communication using a wide range of selectable
baud rates. In addition, a baud rate can be also defined by dividing the clock input to the ASCK0 pin.
The UART-dedicated baud-rate generator can also be used to generate a MIDI-standard baud rate (31.25
kbps).
•
Infrared data transfer mode
This mode enables pulse output and pulse reception in data format.
This mode can be used for office equipment applications such as personal computers.
Figure 5-9. Block Diagram of Serial Interface UART0
Internal bus
Asynchronous serial
interface mode register 0
(ASIM 0)
Receive
buffer
RXB0
RX0
TXE0 RXE0 PS01 PS00 CL0 SL0 ISRM0 IRDAM0
register 0
Asynchronous serial
interface status register 0
(ASIS 0)
Transmit
Receive
shift
register 0
TXS0
shift
RxD0/P23
TxD0/P24
PE0 FE0 OVE0
register 0
Receive
controller
(parity
Transmit
controller
(parity
INTSER0
INTST0
INTSR0
check)
addition)
ASCK0/P25
/2 to f
/27
Baud rate
generator
fX
X
Data Sheet U14044EJ3V0DS
25
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
(2) Serial interface 3nNote
Serial interface 3n has one mode: 3-wire serial I/O mode.
•
3-wire serial I/O mode (fixed as MSB first)
This is an 8-bit data transfer mode using three lines: a serial clock line (SCK3n), serial output line (SO3n),
and serial input line (SI3n).
Since simultaneous transmit and receive operations are enabled in the 3-wire serial I/O mode, the
processing time for data transfer is reduced.
The first bit in 8-bit data in the serial transfer is fixed as MSB.
The 3-wire serial I/O mode is useful for connection to peripheral I/O devices, and display controllers, etc.,
that include a clocked serial interface.
Figure 5-10. Block Diagram of Serial Interface 3n
Internal bus
8
Serial I/O shift register
3n (SIO3n)
SI3n
SO3n
Serial clock
counter
Interrupt request
signal generator
SCK3n
INTCSI3n
fX
fX
fX
/23
/24
/25
Serial clock
controller
Selector
Remark µPD780034A Subseries:
n = 0, 1
µPD780034AY Subseries: n = 0
Data Sheet U14044EJ3V0DS
26
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
(3) Serial interface IIC0 (µPD780034AY Subseries only)
The serial interface IIC0 has the I2C (Inter IC) bus mode (multimaster supported).
•
I2C bus mode (multimaster supported)
This is an 8-bit data transfer mode using two lines: a serial clock line (SCL0) and serial data bus line (SDA0).
This mode complies with the I2C bus format, and can output “start condition”, “data”, and “stop condition”
during transmission via the serial data bus. This data is automatically detected by hardware during
reception.
Since the SCL0 and SDA0 are open-drain outputs in IIC0, pull-up resistors for the serial clock line and the
serial data bus line are required.
Figure 5-11. Block Diagram of Serial Interface IIC0
Internal bus
IIC status register 0
(IICS0)
MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
IIC control register 0
(IICC0)
Slave address
register 0 (SVA0)
IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
SDA0/P32
Matched
signal
CLEAR
SET
Noise
eliminator
SO0 latch
IIC shift register 0
(IIC0)
D
CL00
Acknowledge
detector
Data hold
time corrector
N-ch open-
drain output
Wake-up controller
Acknowledge
detector
Start condition
detector
Stop condition
detector
SCL0/P33
Interrupt request
signal generator
Noise
eliminator
INTIIC0
Serial clock counter
Serial clock controller
Serial clock wait
controller
N-ch open-drain
output
fX
Prescaler
IIC transfer clock select
register 0 (IICCL0)
CLD0 DAD0 SMC0 DFC0
Internal bus
CL00
Data Sheet U14044EJ3V0DS
27
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
6. INTERRUPT FUNCTIONS
A total of 20 interrupt sources are provided, divided into the following three types.
•
•
•
Non-maskable: 1
Maskable:
Software:
18
1
Table 6-1. Interrupt Source List
Interrupt Source
Vector
Table
Basic
Interrupt
Type
Default
Internal/
External
Configuration
Note 1
Priority
Note 2
Name
Trigger
Address
Type
Non-
—
0
INTWDT
Watchdog timer overflow
Internal
0004H
(A)
(B)
(C)
maskable
(with watchdog timer mode 1 selected)
Maskable
INTWDT
Watchdog timer overflow
(with interval timer mode selected)
1
2
3
4
5
INTP0
INTP1
INTP2
INTP3
INTSER0
Pin input edge detection
External 0006H
0008H
000AH
000CH
Serial interface UART0 reception error
generation
Internal
000EH
(B)
6
7
8
9
INTSR0
End of serial interface UART0 reception
End of serial interface UART0 transmission
End of serial interface SIO3 (SIO30) transfer
0010H
0012H
0014H
0016H
INTST0
INTCSI30
INTCSI31
End of serial interface SIO3 (SIO31) transfer
[Only for µPD780034A Subseries]
10
INTIIC0
End of serial interface IIC0 transfer
0018H
[Only for µPD780034AY Subseries]
11
12
INTWTI
Reference time interval signal from watch timer
001AH
001CH
INTTM00
Match between TM0 and CR00
(when CR00 is specified as compare register)
Detection of TI01 valid edge
(when CR00 is specified as capture register)
13
INTTM01
Match between TM0 and CR01
001EH
(when CR01 is specified as compare register)
Detection of TI00 valid edge
(when CR01 is specified as capture register)
14
15
16
17
18
—
INTTM50
INTTM51
INTAD0
INTWT
INTKR
Match between TM50 and CR50
Match between TM51 and CR51
End of A/D conversion
0020H
0022H
0024H
0026H
Watch timer overflow
Port 4 falling edge detection
BRK instruction execution
External 0028H
003EH
(D)
(E)
Software
BRK
—
Notes 1. The default priority is the priority order when several maskable interrupt requests are generated at the
same time. 0 is the highest, and 18 is the lowest.
2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1.
Remark Two watchdog timer interrupt sources (INTWDT): a non-maskable interrupt and a mask interrupt
(internal), are available, either of which can be selected.
Data Sheet U14044EJ3V0DS
28
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
Figure 6-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal non-maskable interrupt
Internal bus
Vector table
Priority
controller
Interrupt
request
address
generator
Standby release
signal
(B) Internal maskable interrupt
Internal bus
PR
ISP
MK
IE
Vector table
address
Priority
controller
Interrupt
request
IF
generator
Standby release
signal
(C) External maskable interrupt (INTP0 to INTP3)
Internal bus
MK
External interrupt
edge enable register
(EGP, EGN)
PR
ISP
IE
Vector table
address
Priority
controller
Interrupt
request
Edge
detector
IF
generator
Standby release
signal
Data Sheet U14044EJ3V0DS
29
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
Figure 6-1. Basic Configuration of Interrupt Function (2/2)
(D) External maskable interrupt (INTKR)
Internal bus
MK
PR
ISP
IE
Vector table
address
generator
Priority
controller
Interrupt
request
Falling edge
detector
IF
1 when MEM = 01H
Standby release
signal
(E) Software interrupt
Internal bus
Vector table
address
generator
Priority
controller
Interrupt
request
IF:
Interrupt request flag
Interrupt enable flag
In-service priority flag
Interrupt mask flag
IE:
ISP:
MK:
PR:
Priority specification flag
MEM: Memory expansion mode register
Data Sheet U14044EJ3V0DS
30
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
7. EXTERNAL DEVICE EXPANSION FUNCTION
The external device expansion function is for connecting external devices to areas other than the internal ROM,
RAM, and SFR. Ports 4 to 6 are used for external device connection.
8. STANDBY FUNCTION
The following two standby modes are available for further reduction of system current consumption.
•
•
HALT mode: In this mode, the CPU operation clock is stopped. The average current consumption can be
reduced by intermittent operation by combining this mode with the normal operation mode.
STOP mode: In this mode, oscillation of the main system clock is stopped. All the operations performed on
the main system clock are suspended, and only the subsystem clock is used, resulting in
extremely small power consumption. This can be used only when the main system clock is
operating (the subsystem clock oscillation cannot be stopped).
Figure 8-1. Standby Function
CSS = 1
Main system
clock operation
Subsystem clock
operationNote
CSS = 0
HALT
instruction
STOP
instruction
HALT
instruction
Interrupt
request
Interrupt
request
Interrupt
request
HALT mode
HALT modeNote
STOP mode
(Main system clock
oscillation stopped)
(Clock supply to CPU halted,
oscillation maintained)
(Clock supply to CPU halted,
oscillation maintained)
Note The current consumption can be reduced by stopping the main system clock. When the CPU is operating
on the subsystem clock, set bit 7 (MCC) of the processor clock control register (PCC) to stop the main system
clock. The STOP instruction cannot be used.
Caution When the main system clock is stopped and the device is operating on the subsystem clock, wait
until the oscillation stabilization time has been secured by the program before switching back
to the main system clock.
Data Sheet U14044EJ3V0DS
31
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
9. RESET FUNCTION
The following two reset methods are available.
•
•
External reset by RESET signal input
Internal reset by watchdog timer runaway time detection
10. MASK OPTION
Table 10.1 Pin Mask Option Selection
Subseries Name
Pins
Mask Option
An on-chip pull-up resistor can be specified in 1-bit units.
µPD780034A Subseries
µPD780034AY Subseries
P30 to P33
P30, P31
The mask option can be used to specify the connection of an on-chip pull-up resistor to P30 to P33Note, in 1-bit
units.
Note The µPD780034AY Subseries has P30 and P31 only.
Data Sheet U14044EJ3V0DS
32
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
11. INSTRUCTION SET
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR,
ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
2nd
Operand
[HL + byte]
[HL + B]
[HL + C]
#byte
A
rNote
sfr
saddr !addr16 PSW
[DE]
[HL]
$addr16
1
None
1st
Operand
A
ADD
MOV
MOV
XCH
MOV
XCH
ADD
MOV
XCH
ADD
MOV
MOV
XCH
MOV
XCH
ADD
MOV
XCH
ADD
ROR
ROL
ADDC
SUB
XCH
ADD
RORC
ROLC
ADDC
SUB
ADDC ADDC
ADDC ADDC
SUB SUB
SUBC SUBC
SUBC
AND
OR
SUB
SUB
SUBC
AND
OR
SUBC
AND
OR
SUBC
AND
OR
XOR
AND
OR
AND
OR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
r
MOV
MOV
ADD
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
DBNZ
DBNZ
B, C
sfr
MOV
MOV
MOV
saddr
MOV
ADD
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16
PSW
MOV
MOV
MOV
PUSH
POP
MOV
MOV
[DE]
[HL]
ROR4
ROL4
[HL + byte]
MOV
[HL + B]
[HL + C]
X
C
MULU
DIVUW
Note Except r = A
Data Sheet U14044EJ3V0DS
33
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
1st Operand
#word
ADDW
AX
rpNote
sfrp
saddrp
MOVW
!addr16
MOVW
SP
None
MOVW
XCHW
MOVW
MOVW
AX
SUBW
CMPW
MOVW
MOVWNote
rp
INCW, DECW
PUSH, POP
sfrp
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
saddrp
!addr16
SP
MOVW
Note Only when rp = BC, DE or HL
(3) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd Operand
1st Operand
A.bit
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
$addr16
None
MOV1
BT
SET1
CLR1
BF
BTCLR
SET1
CLR1
BT
MOV1
MOV1
MOV1
MOV1
sfr.bit
BF
BTCLR
BT
SET1
CLR1
saddr.bit
PSW.bit
BF
BTCLR
BT
SET1
CLR1
BF
BTCLR
BT
SET1
CLR1
[HL].bit
CY
BF
BTCLR
MOV1
MOV1
MOV1
AND1
MOV1
AND1
MOV1
AND1
SET1
CLR1
NOT1
AND1
AND1
OR1
OR1
OR1
OR1
OR1
XOR1
XOR1
XOR1
XOR1
XOR1
(4) Call instructions/branch instructions
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
2nd Operand
AX
!addr16
!addr11
CALLF
[addr5]
CALLT
$addr16
1st Operand
Basic instruction
BR
CALL
BR
BR, BC, BNC
BZ, BNZ
BT, BF
BTCLR
DBNZ
Compound
instruction
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
Data Sheet U14044EJ3V0DS
34
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
12. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage
VDD
–0.3 to +6.5
V
V
V
V
V
AVDD
AVREF
AVSS
VI1
–0.3 to VDD + 0.3Note
–0.3 to VDD + 0.3Note
–0.3 to +0.3
Input voltage
P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47,
P50 to P57, P64 to P67, P70 to P75, X1, X2, XT1, XT2,
RESET
–0.3 to VDD + 0.3Note
VI2
P30 to P33
N-ch open-drain Without pull-up resistor
With pull-up resistor
–0.3 to +6.5
V
V
V
V
–0.3 to VDD + 0.3Note
–0.3 to VDD + 0.3Note
Output voltage
VO
Analog input voltage
VAN
P10 to P17
Per pin
Analog input pin
AVSS – 0.3 to AVREF + 0.3Note
and –0.3 to VDD + 0.3Note
Output current,
high
IOH
IOL
–10
–15
–15
20
mA
mA
mA
mA
Total for P00 to P03, P40 to P47, P50 to P57, P64 to P67, P70 to P75
Total for P20 to P25, P30 to P36
Output current,
low
Per pin for P00 to P03, P20 to P25, P34 to
P36, P40 to P47, P64 to P67, P70 to P75
Per pin for P30 to P33, P50 to P57
30
50
mA
mA
Total for P00 to P03, P40 to P47,
P64 to P67, P70 to P75
Total for P20 to P25
Total for P30 to P36
Total for P50 to P57
20
100
mA
mA
mA
°C
100
Operating ambient TA
temperature
–40 to +85
Storage
Tstg
–65 to +150
°C
temperature
Note 6.5 V or below
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
35
Data Sheet U14044EJ3V0DS
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Input
Symbol
Conditions
MIN.
TYP.
MAX.
15
Unit
pF
CIN
f = 1 MHz
Unmeasured pins returned to 0 V.
capacitance
I/O
CIO
f = 1 MHz
P00 to P03, P20 to P25,
15
pF
capacitance
Unmeasured pins
returned to 0 V.
P34 to P36, P40 to P47,
P50 to P57, P64 to P67,
P70 to P75
P30 to P33
20
pF
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
Main System Clock Oscillator Characteristics (T = –40 to +85°C, VDD = 1.8 to 5.5 V)
A
Recommended
Resonator
Parameter
Conditions
MIN.
TYP.
MAX.
Unit
Circuit
Ceramic
Oscillation
VDD = 4.0 to 5.5 V
1.0
1.0
8.38
5.0
4
MHz
IC
X2
X1
resonator
frequency (fX)Note 1
Oscillation
After VDD reaches
ms
C1
C2
stabilization timeNote 2 oscillation voltage range
MIN.
Crystal
resonator
Oscillation
VDD = 4.0 to 5.5 V
VDD = 4.0 to 5.5 V
VDD = 4.0 to 5.5 V
VDD = 4.0 to 5.5 V
1.0
1.0
8.38
5.0
10
MHz
ms
IC
X2
X1
frequency (fX)Note 1
C1
C2
Oscillation
stabilization timeNote 2
30
External
clock
X1 input
frequency (fX)Note 1
1.0
1.0
50
8.38
5.0
500
500
MHz
ns
X1
X2
X1 input
high-/low-level width
µ
PD74HCU04
85
(tXH, tXL)
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the system is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
Data Sheet U14044EJ3V0DS
36
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Parameter
Conditions
Recommended Circuit
MIN.
32
TYP.
MAX.
35
Unit
kHz
Crystal
Oscillation
IC
32.768
XT2 XT1
R
Note 1
resonator
frequency (fXT)
C4
C3
s
VDD = 4.0 to 5.5 V
1.2
2
Oscillation
Note 2
stabilization time
10
External
clock
XT1 input
38.5
32
5
kHz
Note 1
XT2
XT1
frequency (fXT)
µs
15
XT1 input
µPD74HCU04
high-/low-level width
(tXTH , tXTL)
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
37
Data Sheet U14044EJ3V0DS
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
Recommended Oscillator Constant
Main system clock: Ceramic resonator (TA = –40 to +85°C)
Manufacturer
Part Number
Frequency
(MHz)
Recommended Circuit Constant
C1 (pF) C2 (pF)
100
Oscillation Voltage Range
MIN. (V) MAX. (V)
1.8 5.5
Murata Mfg.
Co., Ltd.
CSB1000J
1.00
100
100
CSA2.00MG040
CST2.00MG040
CSA3.58MG
2.00
2.00
3.58
3.58
4.19
4.19
5.00
5.00
8.00
8.00
8.00
8.00
8.38
8.38
8.38
8.38
3.58
4.19
5.00
8.00
8.38
100
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
1.8
1.8
1.8
2.0
2.0
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
On-chip
30
On-chip
30
CST3.58MGW
CSA4.19MG
On-chip
30
On-chip
30
CST4.19MGW
CSA5.00MG
On-chip
30
On-chip
30
CST5.00MGW
CSA8.00MTZ
CST8.00MTW
CSA8.00MTZ093
CST8.00MTW093
CSA8.38MTZ
CST8.38MTW
CSA8.38MTZ093
CST8.38MTW093
CCR3.58MC3
CCR4.19MC3
CCR5.0MC3
On-chip
30
On-chip
30
On-chip
30
On-chip
30
On-chip
30
On-chip
30
On-chip
30
On-chip
30
On-chip
On-chip
On-chip
On-chip
On-chip
On-chip
On-chip
On-chip
On-chip
On-chip
On-chip
On-chip
TDK
CCR8.0MC5
CCR8.38MC5
Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation.
Oscillationfrequencyprecisionisnotguaranteed. Forapplicationsrequiringoscillationfrequency
precision, the oscillation frequency must be adjusted on the implementation circuit. For details,
contact directly the manufacturer of the resonator used.
Data Sheet U14044EJ3V0DS
38
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
IOH
Conditions
MIN.
TYP.
MAX.
Unit
Output current,
high
Per pin
All pins
–1
–15
10
mA
mA
mA
Output current,
low
IOL
Per pin for P00 to P03, P20 to P25, P34 to P36,
P40 to P47, P64 to P67, P70 to P75
Per pin for P30 to P33, P50 to P57
Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75
Total for P20 to P25
15
20
mA
mA
mA
mA
mA
V
10
Total for P30 to P36
70
Total for P50 to P57
70
Input voltage,
high
VIH1
P10 to P17, P21, P24, P35,
P40 to P47, P50 to P57,
P64 to P67, P74, P75
VDD = 2.7 to 5.5 V
0.7VDD
0.8VDD
VDD
VDD
V
VIH2
VIH3
P00 to P03, P20, P22, P23, P25, VDD = 2.7 to 5.5 V
P34, P36, P70 to P73, RESET
0.8VDD
VDD
V
V
V
0.85VDD
0.7VDD
VDD
P30 to P33
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 4.0 to 5.5 V
VDD = 2.7 to 5.5 V
5.5
(N-ch open-drain)
0.8VDD
VDD – 0.5
VDD – 0.2
0.8VDD
0.9VDD
0
5.5
V
V
V
V
V
V
VIH4
VIH5
VIL1
X1, X2
VDD
VDD
VDD
XT1, XT2
VDD
Input voltage,
low
P10 to P17, P21, P24, P35,
P40 to P47, P50 to P57,
P64 to P67, P74, P75
0.3VDD
0
0.2VDD
V
VIL2
P00 to P03, P20, P22, P23, P25, VDD = 2.7 to 5.5 V
P34, P36, P70 to P73, RESET
0
0.2VDD
0.15VDD
0.3VDD
0.2VDD
0.1VDD
0.4
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0
VIL3
P30 to P33
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
1.8 V ≤ VDD < 2.7 V
VDD = 2.7 to 5.5 V
0
0
0
VIL4
X1, X2
0
0
0.2
VIL5
XT1, XT2
VDD = 4.0 to 5.5 V
0
0.2VDD
0.1VDD
VDD
0
Output voltage,
high
VOH1
VOL1
VDD = 4.0 to 5.5 V, IOH = –1 mA
IOH = –100 µA
VDD – 1.0
VDD – 0.5
VDD
Output voltage,
low
P30 to P33
VDD = 4.0 to 5.5 V,
IOL = 15 mA
2.0
P50 to P57
0.4
2.0
P00 to P03, P20 to P25, P34 to P36, VDD = 4.0 to 5.5 V,
P40 to P47, P64 to P67, P70 to P75 IOL = 1.6 mA
0.4
VOL2
IOL = 400 µA
0.5
V
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
39
Data Sheet U14044EJ3V0DS
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
3
Unit
Input leakage
current, high
ILIH1
VIN = VDD
P00 to P03, P10 to P17, P20 to P25,
µA
P34 to P36, P40 to P47, P50 to P57,
P64 to P67, P70 to P75,
RESET
ILIH2
ILIH3
ILIL1
X1, X2, XT1, XT2
P30 to P33Note 1
20
3
µA
µA
µA
VIN = 5.5 V
VIN = 0 V
Input leakage
current, low
P00 to P03, P10 to P17, P20 to P25,
P34 to P36, P40 to P47, P50 to P57,
P64 to P67, P70 to P75,
RESET
–3
ILIL2
ILIL3
ILOH
X1, X2, XT1, XT2
P30 to P33Note 1
–20
–3
3
µA
µA
µA
Output leakage
current, high
VOUT = VDD
VOUT = 0 V
VIN = 0 V,
Output leakage
current, low
ILOL
R1
–3
90
90
µA
kΩ
kΩ
Mask option
15
15
30
30
pull-up resistance
P30, P31, P32Note 2, P33Note 2
Software pull-
up resistance
R2
VIN = 0 V,
P00 to P03, P20 to P25, P34 to P36, P40 to P47,
P50 to P57, P64 to P67, P70 to P75
Notes 1. µPD780031A, 780032A, 780033A, 780034A:
When pull-up resistors are not connected to P30 to
P33 (specified by the mask option).
µPD780031AY, 780032AY, 780033AY, 780034AY: When pull-up resistors are not connected to P30 and
P31 (specified by the mask option).
2. Only for the µPD780031A, 780032A, 780033A, and 780034A
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U14044EJ3V0DS
40
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
5.5
MAX.
11
Unit
mA
2
Power supply
currentNote 1
IDD1
8.38 MHz
V
V
V
V
V
V
DD = 5.0 V 10%Note
DD = 3.0 V 10%Note
DD = 2.0 V 10%Note
DD = 5.0 V 10%Note
DD = 3.0 V 10%Note
DD = 2.0 V 10%Note
When A/D converter is
stopped
crystal oscillation
operating mode
When A/D converter is
operating
6.5
2
13
4
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
2
3
2
2
3
5.00 MHz
When A/D converter is
stopped
crystal oscillation
operating mode
When A/D converter is
operating
3
6
When A/D converter is
stopped
0.4
1.4
1.1
1.5
4.2
2.2
4.7
0.7
1.7
0.4
1.1
When A/D converter is
operating
IDD2
8.38 MHz
When peripheral functions
are stopped
crystal oscillation
HALT mode
When peripheral functions
are operating
5.00 MHz
When peripheral functions
are stopped
0.35
0.15
crystal oscillation
HALT mode
When peripheral functions
are operating
When peripheral functions
are stopped
When peripheral functions
are operating
IDD3
IDD4
IDD5
32.768 kHz crystal oscillation
operating modeNote 4
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
40
20
80
40
20
60
18
10
30
10
10
µA
µA
µA
µA
µA
µA
µA
µA
µA
10
32.768 kHz crystal oscillation
HALT modeNote 4
30
6
2
XT1 = VDD
0.1
0.05
0.05
STOP mode
When feedback resistor is not used
Notes 1. Total current through the internal power supply (VDD0, VDD1), including the peripheral operation current
(except the current through pull-up resistors of ports and the AVREF pin).
2. When the processor clock control register (PCC) is set to 00H.
3. When PCC is set to 02H.
4. When main system clock operation is stopped.
41
Data Sheet U14044EJ3V0DS
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
AC Characteristics
(1) Basic Operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
0.24
TYP.
122
MAX.
16
Unit
µs
Cycle time
TCY
Operating with
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
(Min. instruction
execution time)
main system clock
0.4
16
µs
1.6
16
µs
Operating with subsystem clock
4.0 V ≤ VDD ≤ 5.5 V
103.9Note 1
2/fsam + 0.1Note 2
2/fsam + 0.2Note 2
2/fsam + 0.5Note 2
125
µs
TI00, TI01 input
high-/low-level
width
tTIH0, tTIL0
µs
2.7 V ≤ VDD < 4.0 V
µs
µs
TI50, TI51 input
frequency
fTI5
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
0
0
4
MHz
kHz
ns
275
TI50, TI51 input
high-/low-level
width
tTIH5, tTIL5
100
1.8
ns
Interrupt request tINTH, tINTL INTP0 to INTP3,
VDD = 2.7 to 5.5 V
1
2
µs
µs
input high-/low
-level width
P40 to P47
RESET
tRSL
VDD = 2.7 to 5.5 V
10
20
µs
µs
low-level width
Notes 1. Value when an external clock is used. When a crystal resonator is used, it is 114 µs (MIN.).
2. Selection of fsam = fX, fX/4, fX/64 is possible using bits 0 and 1 (PRM00, PRM01) of prescaler mode register
0 (PRM0). However, if the TI00 valid edge is selected as the count clock, the value becomes fsam = fX/8.
Data Sheet U14044EJ3V0DS
42
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
TCY vs. VDD (Main system clock operation)
16.0
10.0
µ
Operation
guaranteed
5.0
range
2.0
1.6
1.0
0.4
0.24
0.1
5.5
0
1.0
2.0
3.0
4.0
5.0
6.0
1.8
2.7
Supply voltage VDD [V]
43
Data Sheet U14044EJ3V0DS
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
(2) Read/Write Operation (TA = –40 to +85°C, VDD = 4.0 to 5.5 V)
(1/3)
Parameter
ASTB high-level width
Address setup time
Symbol
tASTH
tADS
Conditions
MIN.
0.3tCY
20
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold time
tADH
6
Input time from address to data
tADD1
tADD2
tRDAD
tRDD1
tRDD2
tRDH
(2 + 2n)tCY – 54
(3 + 2n)tCY – 60
100
Output time from RD↓ to address
Input time from RD↓ to data
0
(2 + 2n)tCY – 87
(3 + 2n)tCY – 93
Read data hold time
RD low-level width
0
tRDL1
tRDL2
tRDWT1
tRDWT2
tWRWT
tWTL
(1.5 + 2n)tCY – 33
(2.5 + 2n)tCY – 33
Input time from RD↓ to WAIT↓
tCY – 43
tCY – 43
Input time from WR↓ to WAIT↓
WAIT low-level width
tCY – 25
(0.5 + n)tCY + 10
(2 + 2n)tCY
Write data setup time
tWDS
60
Write data hold time
tWDH
6
(1.5 + 2n)tCY – 15
6
WR low-level width
tWRL1
tASTRD
tASTWR
tRDAST
Delay time from ASTB↓ to RD↓
Delay time from ASTB↓ to WR↓
2tCY – 15
0.8tCY – 15
Delay time from RD↑ to ASTB↑
1.2tCY
at external fetch
Hold time from RD↑ to address
tRDADH
0.8tCY – 15
1.2tCY + 30
ns
at external fetch
Write data output time from RD↑
Write data output time from WR↓
Hold time from WR↑ to address
Delay time from WAIT↑ to RD↑
Delay time from WAIT↑ to WR↑
tRDWD
tWRWD
tWRADH
tWTRD
40
10
ns
ns
ns
ns
ns
60
0.8tCY – 15
0.8tCY
0.8tCY
1.2tCY + 30
2.5tCY + 25
2.5tCY + 25
tWTWR
Remarks 1. tCY = TCY/4
2. n indicates the number of waits.
3. CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and
ASTB pins.)
Data Sheet U14044EJ3V0DS
44
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
(2) Read/Write Operation (TA = –40 to +85°C, VDD = 2.7 to 4.0 V)
(2/3)
Parameter
ASTB high-level width
Address setup time
Symbol
tASTH
tADS
Conditions
MIN.
0.3tCY
30
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold time
tADH
10
Input time from address to data
tADD1
tADD2
tRDAD
tRDD1
tRDD2
tRDH
(2 + 2n)tCY – 108
(3 + 2n)tCY – 120
200
Output time from RD↓ to address
Input time from RD↓ to data
0
(2 + 2n)tCY – 148
(3 + 2n)tCY – 162
Read data hold time
RD low-level width
0
tRDL1
(1.5 + 2n)tCY – 40
(2.5 + 2n)tCY – 40
tRDL2
Input time from RD↓ to WAIT↓
tRDWT1
tRDWT2
tWRWT
tWTL
tCY – 75
tCY – 60
Input time from WR↓ to WAIT↓
WAIT low-level width
tCY – 50
(0.5 + 2n)tCY + 10
(2 + 2n)tCY
Write data setup time
tWDS
60
10
Write data hold time
tWDH
WR low-level width
tWRL1
tASTRD
tASTWR
tRDAST
(1.5 + 2n)tCY – 30
10
Delay time from ASTB↓ to RD↓
Delay time from ASTB↓ to WR↓
2tCY – 30
0.8tCY – 30
Delay time from RD↑ to ASTB↑
1.2tCY
at external fetch
Hold time from RD↑ to address
tRDADH
0.8tCY – 30
1.2tCY + 60
ns
at external fetch
Write data output time from RD↑
Write data output time from WR↓
Hold time from WR↑ to address
Delay time from WAIT↑ to RD↑
Delay time from WAIT↑ to WR↑
Remarks 1. tCY = TCY/4
tRDWD
tWRWD
tWRADH
tWTRD
tWTWR
40
20
ns
ns
ns
ns
ns
120
0.8tCY – 30
0.5tCY
0.5tCY
1.2tCY + 60
2.5tCY + 50
2.5tCY + 50
2. n indicates the number of waits.
3. CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, AD8 to AD15, RD, WR, WAIT,
and ASTB pins.)
45
Data Sheet U14044EJ3V0DS
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
(2) Read/Write Operation (TA = –40 to +85°C, VDD = 1.8 to 2.7 V)
(3/3)
Parameter
ASTB high-level width
Address setup time
Symbol
tASTH
tADS
Conditions
MIN.
0.3tCY
120
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold time
tADH
20
Input time from address to data
tADD1
tADD2
tRDAD
tRDD1
tRDD2
tRDH
(2 + 2n)tCY – 233
(3 + 2n)tCY – 240
400
Output time from RD↓ to address
Input time from RD↓ to data
0
(2 + 2n)tCY – 325
(3 + 2n)tCY – 332
Read data hold time
RD low-level width
0
tRDL1
tRDL2
tRDWT1
tRDWT2
tWRWT
tWTL
(1.5 + 2n)tCY – 92
(2.5 + 2n)tCY – 92
Input time from RD↓ to WAIT↓
tCY – 350
tCY – 132
tCY – 100
(2 + 2n)tCY
Input time from WR↓ to WAIT↓
WAIT low-level width
(0.5 + 2n)tCY + 10
Write data setup time
tWDS
60
20
Write data hold time
tWDH
WR low-level width
tWRL1
tASTRD
tASTWR
tRDAST
(1.5 + 2n)tCY – 60
20
Delay time from ASTB↓ to RD↓
Delay time from ASTB↓ to WR↓
2tCY – 60
0.8tCY – 60
Delay time from RD↑ to ASTB↑
1.2tCY
at external fetch
Hold time from RD↑ to address
tRDADH
0.8tCY – 60
1.2tCY + 120
ns
at external fetch
Write data output time from RD↑
Write data output time from WR↓
Hold time from WR↑ to address
Delay time from WAIT↑ to RD↑
Delay time from WAIT↑ to WR↑
Remarks 1. tCY = TCY/4
tRDWD
tWRWD
tWRADH
tWTRD
40
40
ns
ns
ns
ns
ns
240
0.8tCY – 60
0.5tCY
0.5tCY
1.2tCY + 120
2.5tCY + 100
2.5tCY + 100
tWTWR
2. n indicates the number of waits.
3. CL = 100pF (CL indicates the load capacitance of the AD0 to AD7, AD8 to AD15, RD, WR, WAIT, and
ASTB pins.)
Data Sheet U14044EJ3V0DS
46
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
(3) Serial Interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(a) 3-wire serial I/O mode (SCK3n... Internal clock output)
Parameter
Symbol
Conditions
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
MIN.
954
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK3n cycle time
tKCY1
1600
3200
SCK3n high-/
low-level width
tKH1, tKL1
tSIK1
VDD = 4.0 to 5.5 V
tKCY1/2 – 50
tKCY1/2 – 100
100
SI3n setup time
4.0 V ≤ VDD ≤ 5.5V
2.7 V ≤ VDD < 4.0V
(to SCK3n↑)
150
300
SI3n hold time
tKSI1
400
(from SCK3n↑)
Note
Delay time from
SCK3n↓ to SO3n
output
tKSO1
C = 100 pF
300
ns
Note C is the load capacitance of the SCK3n, and SO3n output lines.
(b) 3-wire serial I/O mode (SCK3n... External clock input)
Parameter
Symbol
Conditions
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SCK3n cycle time
tKCY2
1600
3200
400
SCK3n high-/
low-level width
tKH2, tKL2
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
800
1600
100
SI3n setup time
tSIK2
tKSI2
tKSO2
(to SCK3n↑)
SI3n hold time
400
ns
ns
(from SCK3n↑)
Note
Delay time from
SCK3n↓ to SO3n
output
C = 100 pF
300
Note C is the load capacitance of the SO3n output line.
Remark µPD780031A, 780032A, 780033A, 780034A:
n = 0,1
µPD780031AY, 780032AY, 780033AY, 780034AY: n = 0
47
Data Sheet U14044EJ3V0DS
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
(c) UART mode (dedicated baud-rate generator output)
Parameter
Transfer rate
Symbol
Conditions
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
MIN.
TYP.
MAX.
131031
78125
39063
Unit
bps
bps
bps
(d) UART mode (external clock input)
Parameter
Symbol
Conditions
MIN.
800
TYP.
MAX.
Unit
ns
ASCK0 cycle time
tKCY3
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
1600
ns
3200
400
ns
ns
ASCK0 high-/low-level width
Transfer rate
tKH3,
tKL3
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
800
ns
ns
1600
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
39063
19531
9766
bps
bps
bps
(e) UART mode (infrared data transfer mode)
Parameter
Transfer rate
Symbol
Conditions
VDD = 4.0 to 5.5 V
VDD = 4.0 to 5.5 V
VDD = 4.0 to 5.5 V
VDD = 4.0 to 5.5 V
MIN.
MAX.
131031
0.87
Unit
bps
%
Bit rate allowable error
Output pulse width
Input pulse width
1.2
0.24/fbrNote
µs
4/fX
µs
Note fbr: Specified baud rate
Data Sheet U14044EJ3V0DS
48
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
(f) I2C bus mode (µPD780031AY, 780032AY, 780033AY, 780034AY only)
Standard Mode
High-Speed Mode
Parameter
SCL0 clock frequency
Symbol
Unit
MIN.
MAX.
100
—
MIN.
0
MAX.
fCLK
tBUF
0
400
kHz
Bus-free time
4.7
1.3
—
µs
(between stop and start conditions)
Hold timeNote 1
tHD:STA
tLOW
4.0
4.7
4.0
4.7
5.0
0Note 2
250
—
—
—
0.6
—
—
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
ns
pF
SCL0 clock low-level width
SCL0 clock high-level width
Start/restart condition setup time
Data hold time CBUS-compatible master
I2C bus
1.3
tHIGH
—
0.6
—
tSU:STA
tHD:DAT
—
0.6
—
—
—
—
—
0Note 2
0.9Note 3
—
Data setup time
tSU:DAT
tR
—
100Note 4
SDA0 and SCL0 signal rise time
SDA0 and SCL0 signal fall time
Stop condition setup time
Spike pulse width controlled by input filter
Capacitive load per bus line
1000
300
—
20 + 0.1CbNote 5
300
300
—
tF
—
20 + 0.1CbNote 5
tSU:STO
tSP
4.0
—
0.6
0
—
50
Cb
—
400
—
400
Notes 1. In the start condition, the first clock pulse is generated after this hold time.
2. To fill in the undefined area of the SCL0 falling edge, it is necessary for the device to internally provide
at least 300 ns of hold time for the SDA0 signal (which is VIHmin. of the SCL0 signal).
3. If the device does not extend the SCL0 signal low hold time (tLOW), only the maximum data hold time
tHD:DAT needs to be fulfilled.
4. The high-speed mode I2C bus is available in a standard mode I2C bus system. At this time, the conditions
described below must be satisfied.
• If the device does not extend the SCL0 signal low state hold time
tSU:DAT ≥ 250 ns
• If the device extends the SCL0 signal low state hold time
Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU:DAT
= 1000 + 250 = 1250 ns by standard mode I2C bus specification).
5. Cb: Total capacitance per bus line (unit: pF)
49
Data Sheet U14044EJ3V0DS
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
AC Timing Measurement Points (Excluding X1, XT1 inputs)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Point of
measurement
Clock Timing
1/f
X
tXL
t
XH
V
V
IH4 (MIN.)
IL4 (MAX.)
X1 Input
1/fXT
t
XTL
t
XTH
V
V
IH5 (MIN.)
IL5 (MAX.)
XT1 Input
TI Timing
tTIL0
tTIH0
TI00, TI01
1/fTI5
tTIL5
tTIH5
TI50, TI51
Data Sheet U14044EJ3V0DS
50
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
Interrupt Request Input Timing
t
INTL
tINTH
INTP0 to INTP3
RESET Input Timing
t
RSL
RESET
51
Data Sheet U14044EJ3V0DS
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
Read/Write Operation
External fetch (no wait):
A8 to A15
Higher 8-bit address
Hi-Z
t
ADD1
AD0 to AD7
Instruction code
Lower 8-bit address
t
RDAD
RDD1
tADS
t
t
ADH
t
RDADH
RDAST
t
ASTH
t
ASTB
RD
t
ASTRD
t
RDL1
t
RDH
External fetch (wait insertion):
A8 to A15
Higher 8-bit address
Hi-Z
t
ADD1
AD0 to AD7
Instruction code
Lower 8-bit address
t
RDAD
t
ADS
t
RDADH
RDAST
t
ADH
t
RDD1
t
ASTH
t
ASTB
RD
t
ASTRD
t
RDL1
t
RDH
WAIT
t
RDWT1
t
WTL
t
WTRD
Data Sheet U14044EJ3V0DS
52
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
External data access (no wait):
A8 to A15
Higher 8-bit address
Read data
t
ADD2
Hi-Z
Hi-Z
AD0 to AD7
Lower 8-bit address
Write data
tRDAD
t
ADS
tRDD2
t
ADH
tASTH
t
RDH
ASTB
RD
tRDWD
tASTRD
t
RDL2
tWDS
tWDH
tWRADH
tWRWD
WR
tASTWR
t
WRL1
External data access (wait insertion):
A8 to A15
Higher 8-bit address
t
ADD2
Hi-Z
Hi-Z
Lower 8-bit
Read data
t
Write data
AD0 to AD7
address
t
RDAD
t
ADH
t
ADS
RDH
t
ASTH
t
RDD2
ASTB
RD
t
ASTRD
t
RDWD
t
RDL2
t
WDS
t
WDH
t
WRWD
WR
t
ASTWR
t
WRL1
t
WRADH
WAIT
t
WTL
t
WTRD
t
RDWT2
t
WTL
t
WRWT
t
WTWR
Data Sheet U14044EJ3V0DS
53
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
tKLm
t
KHm
SCK3n
SI3n
t
SIKm
t
KSIm
Input data
t
KSOm
SO3n
Output data
Remarks 1. m = 1, 2
2. µPD780031A, 780032A, 780033A, 780034A:
n = 0, 1
µPD780031AY, 780032AY, 780033AY, 780034AY: n = 0
UART mode (external clock input):
KCY3
t
t
KL3
tKH3
ASCK0
I2C bus mode (µPD780031AY, 780032AY, 780033AY, 780034AY only):
tLOW
tR
SCL0
tF
tHD:DAT
tHIGH
tSU:STA
tHD:STA
tSP
tSU:STO
tSU:DAT
tHD:STA
SDA0
tBUF
Restart
condition
Stop
condition
Stop
Start
condition condition
Data Sheet U14044EJ3V0DS
54
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = AVREF = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
10
TYP.
10
MAX.
10
Unit
bit
Resolution
Overall errorNotes 1, 2
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF < 4.0 V
1.8 V ≤ AVREF < 2.7 V
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF < 4.0 V
1.8 V ≤ AVREF < 2.7 V
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF < 4.0 V
1.8 V ≤ AVREF < 2.7 V
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF < 4.0 V
1.8 V ≤ AVREF < 2.7 V
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF < 4.0 V
1.8 V ≤ AVREF < 2.7 V
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF < 4.0 V
1.8 V ≤ AVREF < 2.7 V
0.2
0.3
0.6
0.4
0.6
1.2
96
%FSR
%FSR
%FSR
µs
Conversion time
tCONV
14
19
28
96
µs
96
µs
Zero-scale errorNotes 1, 2
Full-scale errorNotes 1, 2
Integral linearity errorNote 1
Differential linearity error
0.4
0.6
1.2
0.4
0.6
1.2
2.5
4.5
8.5
1.5
2.0
3.5
AVREF
AVDD
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
LSB
LSB
LSB
LSB
LSB
LSB
V
Analog input voltage
VIAN
0
Reference voltage
AVREF
RREF
1.8
20
V
Resistance between AVREF and AVSS
When A/D conversion is not performed.
40
kΩ
Notes 1. Excludes quantization error ( 1/2 LSB).
2. This value is indicated as a ratio to the full-scale value.
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T
A
= –40 to +85
°C)
Parameter
Symbol
Conditions
MIN.
1.6
TYP.
MAX.
Unit
V
Data retention power
supply voltage
VDDDR
5.5
30
Data retention power
supply current
IDDDR
Subsystem clock stop (XT1 = VDD) and
feed-back resistor disconnected
0.1
µA
Release signal set time
tSREL
tWAIT
0
µs
s
Oscillation stabilization
wait time
Release by RESET
217/fX
Release by interrupt request
Note
s
Note Selection of 212/fX and 214/fX to 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
Data Sheet U14044EJ3V0DS
55
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
Operating mode
STOP mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
HALT mode
Operating mode
STOP mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
Standby release signal
(interrupt request)
t
WAIT
Data Sheet U14044EJ3V0DS
56
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
13. PACKAGE DRAWINGS
64-PIN PLASTIC SDIP (19.05mm(750))
64
33
32
1
A
K
L
J
I
M
R
F
M
N
C
B
D
H
G
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.17 mm of
its true position (T.P.) at maximum material condition.
+0.68
58.0
A
–0.20
B
C
D
F
1.78 MAX.
1.778 (T.P.)
0.50 0.10
0.9 MIN.
2. Item "K" to center of leads when formed parallel.
G
H
3.2 0.3
0.51 MIN.
+0.26
4.05
I
–0.20
J
K
L
5.08 MAX.
19.05 (T.P.)
17.0 0.2
+0.10
0.25
M
–0.05
N
R
0.17
0 ~ 15°
P64C-70-750A,C-4
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced
version.
Data Sheet U14044EJ3V0DS
57
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
64-PIN PLASTIC QFP (14x14)
A
B
48
49
33
32
detail of lead end
S
C D
Q
R
64
17
16
1
F
P
J
G
M
H
I
K
S
L
N
S
M
NOTE
Each lead centerline is located within 0.15 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
C
D
F
17.6 0.4
14.0 0.2
14.0 0.2
17.6 0.4
1.0
G
1.0
+0.08
0.37
H
–0.07
I
J
0.15
0.8 (T.P.)
1.8 0.2
0.8 0.2
K
L
+0.08
0.17
M
–0.07
N
P
Q
R
S
0.10
2.55 0.1
0.1 0.1
5° 5°
2.85 MAX.
P64GC-80-AB8-5
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced
version.
Data Sheet U14044EJ3V0DS
58
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
64-PIN PLASTIC TQFP (12x12)
A
B
detail of lead end
48
33
32
49
S
P
T
C
D
R
L
U
Q
64
17
16
1
F
G
J
M
H
I
ITEM MILLIMETERS
A
B
C
D
F
14.0 0.2
12.0 0.2
12.0 0.2
14.0 0.2
1.125
K
S
G
1.125
+0.06
0.32
H
−0.10
M
I
0.13
J
K
L
0.65 (T.P.)
1.0 0.2
0.5
N
S
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
+0.03
0.17
M
−0.07
N
P
Q
0.10
1.0
0.1 0.05
+4°
3°
R
−3°
1.1 0.1
0.25
S
T
U
0.6 0.15
P64GK-65-9ET-3
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced
version.
Data Sheet U14044EJ3V0DS
59
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
14. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the following recommended conditions.
For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
Forsolderingmethodsandconditionsotherthanthoserecommendedbelow,contactyourNECsalesrepresentative.
Table 14-1. Surface Mounting Type Soldering Conditions (1/2)
(1) µPD780031AGC-×××-AB8: 64-pin plastic QFP (14 × 14)
µPD780032AGC-×××-AB8: 64-pin plastic QFP (14 × 14)
µPD780033AGC-×××-AB8: 64-pin plastic QFP (14 × 14)
µPD780034AGC-×××-AB8: 64-pin plastic QFP (14 × 14)
µPD780031AYGC-×××-AB8: 64-pin plastic QFP (14 × 14)
µPD780032AYGC-×××-AB8: 64-pin plastic QFP (14 × 14)
µPD780033AYGC-×××-AB8: 64-pin plastic QFP (14 × 14)
µPD780034AYGC-×××-AB8: 64-pin plastic QFP (14 × 14)
Recommended
Soldering Method
Infrared reflow
Soldering Conditions
Condition Symbol
Package peak temperature: 235°C, Time: 30 seconds max.
(at 210°C or higher), Count: Three times or less
IR35-00-3
VPS
Package peak temperature: 215°C, Time: 40 seconds max.
(at 200°C or higher), Count: Three times or less
VP15-00-3
WS60-00-1
Wave soldering
Solder bath temperature: 260°C max., Time: 10 seconds max.,
Count: Once, Preheating temperature: 120°C max. (package surface
temperature)
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
––
Caution Do not use different soldering methods together (except for partial heating).
Data Sheet U14044EJ3V0DS
60
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
Table 14-1. Surface Mounting Type Soldering Conditions (2/2)
(2) µPD780031AGK-×××-9ET: 64-pin plastic TQFP (12 × 12)
µPD780032AGK-×××-9ET: 64-pin plastic TQFP (12 × 12)
µPD780033AGK-×××-9ET: 64-pin plastic TQFP (12 × 12)
µPD780034AGK-×××-9ET: 64-pin plastic TQFP (12 × 12)
µPD780031AYGK-×××-9ET: 64-pin plastic TQFP (12 × 12)
µPD780032AYGK-×××-9ET: 64-pin plastic TQFP (12 × 12)
µPD780033AYGK-×××-9ET: 64-pin plastic TQFP (12 × 12)
µPD780034AYGK-×××-9ET: 64-pin plastic TQFP (12 × 12)
Recommended
Soldering Method
Infrared reflow
Soldering Conditions
Condition Symbol
Package peak temperature: 235°C, Time: 30 seconds max.
(at 210°C or higher),
Count: Two times or less, Exposure limit: 7 daysNote (after that,
IR35-107-2
prebake at 125°C for 10 hours)
VPS
Package peak temperature: 215°C, Time: 40 seconds max.
(at 200°C or higher),
Count: Two times or less, Exposure limit: 7 daysNote (after that,
VP15-107-2
prebake at 125°C for 10 hours)
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
––
Note After opening the dry pack, store it at 25°C or less and 65%RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Table 14-2. Insertion Type Soldering Conditions
µPD780031ACW-×××: 64-pin plastic SDIP (19.05 mm (750))
µPD780032ACW-×××: 64-pin plastic SDIP (19.05 mm (750))
µPD780033ACW-×××: 64-pin plastic SDIP (19.05 mm (750))
µPD780034ACW-×××: 64-pin plastic SDIP (19.05 mm (750))
µPD780031AYCW-×××: 64-pin plastic SDIP (19.05 mm (750))
µPD780032AYCW-×××: 64-pin plastic SDIP (19.05 mm (750))
µPD780033AYCW-×××: 64-pin plastic SDIP (19.05 mm (750))
µPD780034AYCW-×××: 64-pin plastic SDIP (19.05 mm (750))
Soldering Method
Soldering Condition
Wave soldering
(only for pins)
Solder bath temperature: 260°C max., Time: 10 seconds max.
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Caution Apply wave soldering only to the pins and be careful not to bring solder into direct contact with
the package.
Data Sheet U14044EJ3V0DS
61
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD780034A, 780034AY
Subseries.
Also refer to (5) Cautions on Using Development Tools.
(1) Language Processing Software
RA78K0
Assembler package common to 78K/0 Series
CC78K0
C compiler package common to 78K/0 Series
Device file for µPD780034A, 780034AY Subseries
C compiler library source file common to 78K/0 Series
DF780034
CC78K0-L
(2) Flash Memory Writing Tools
Flashpro II (FL-PR2)
Flash programmer dedicated to microcontrollers with on-chip flash memory
Adapter for flash memory writing
Flashpro III (FL-PR3, PG-FP3)
FA-64CW
FA-64GC
FA-64GK-9ET
(3) Debugging Tools
• When using in-circuit emulator IE-78K0-NS
IE-78K0-NS
In-circuit emulator common to 78K/0 Series
IE-70000-MC-PS-B
IE-78K0-NS-PA
Power supply unit for IE-78K0-NS
Performance board to enhance and expand the functions of IE-78K0-NS
IE-70000-98-IF-C
Adapter required when using PC-9800 series as host machine (excluding notebook PCs) (C bus
supported)
IE-70000-CD-IF-A
IE-70000-PC-IF-C
IE-70000-PCI-IF-A
IE-780034-NS-EM1
NP-64CW
PC card and interface cable when using notebook PC as host machine (PCMCIA socket supported)
TM
Adapter required when using IBM PC/AT
or compatible as host machine (ISA bus supported)
Adapter required when using PC in which PCI bus is incorporated as host machine
Emulation board to emulate µPD780034A, 780034AY Subseries
Emulation probe for 64-pin plastic SDIP (CW type)
NP-64GC
Emulation probe for 64-pin plastic QFP (GC-AB8 type)
NP-64GC-TQ
NP-64GK
Emulation probe for 64-pin plastic TQFP (GK-9ET type)
EV-9200GC-64
Conversion socket to connect the NP-64GC and a target system board on which a 64-pin plastic
QFP (GC-AB8 type) can be mounted
TGC-064SAP
TGK-064SBP
Conversion adapter to connect the NP-64GC-TQ and a target system board on which a 64-pin plastic
QFP (GC-AB8 type) can be mounted
Conversion adapter to connect the NP-64GK and a target system board on which a 64-pin plastic
TQFP (GK-9ET type) can be mounted
ID78K0-NS
SM78K0
Integrated debugger for IE-78K0-NS
System simulator common to 78K/0 Series
Device file for µPD780034A, 780034AY Subseries
DF780034
Data Sheet U14044EJ3V0DS
62
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
• When using in-circuit emulator IE-78001-R-A
IE-78001-R-A
In-circuit emulator common to 78K/0 Series
IE-70000-98-IF-C
Adapter required when using PC-9800 series as host machine (excluding notebook PCs) (C bus
supported)
IE-70000-PC-IF-C
IE-70000-PCI-IF-A
IE-78000-R-SV3
IE-780034-NS-EM1
IE-78K0-R-EX1
EP-78240CW-R
EP-78240GC-R
EP-78012GK-R
EV-9200GC-64
Adapter required when using IBM PC/AT or compatible as host machine (ISA bus supported)
Adapter required when using PC in which PCI bus is incorporated as host machine
Interface adapter and cable when using EWS as host machine
Emulation board to emulate µPD780034A, 780034AY Subseries
Emulation probe conversion board necessary when using IE-780034-NS-EM1 on IE-78001-R-A
Emulation probe for 64-pin plastic SDIP (CW type)
Emulation probe for 64-pin plastic QFP (GC-AB8 type)
Emulation probe for 64-pin plastic TQFP (GK-9ET type)
Conversion socket to connect the EP-78240GC-R and a target system board on which a 64-pin
plastic QFP (GC-AB8 type) can be mounted
TGK-064SBP
Conversion adapter to connect the EP-78012GK-R and a target system board on which a 64-pin
plastic TQFP (GK-9ET type) can be mounted
ID78K0
Integrated debugger for IE-78001-R-A
SM78K0
DF780034
System simulator common to 78K/0 Series
Device file for µPD780034A, 780034AY Subseries
(4) Real-Time OS
RX78K0
MX78K0
Real-time OS for 78K/0 Series
OS for 78K/0 Series
Data Sheet U14044EJ3V0DS
63
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
(5) Cautions on Using Development Tools
• The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780034.
• The CC78K0 and RX78K0 are used in combination with the RA78K0 and the DF780034.
• FL-PR2, FL-PR3, FA-64CW, FA-64GC, FA-64GK-9ET, NP-64CW, NP-64GC, NP-64GC-TQ, and NP-64GK are
products made by Naito Densei Machida Mfg. Co., Ltd. (+81-44-822-3813).
• The TGC-064SAP, and TGK-064SBP are products made by TOKYO ELETECH CORPORATION.
Refer to: Daimaru Kogyo, Ltd.
Tokyo Electronic Division (+81-3-3820-7112)
Osaka Electronic Division (+81-6-6244-6672)
• For third-party development tools, see the Single-chip Microcontroller Development Tool Selection Guide
(U11069E).
• The host machines and OSs supporting each software are as follows.
Host Machine
[OS]
PC
EWS
PC-9800 series [Japanese WindowsTM
IBM PC/AT and compatibles
]
HP9000 series 700TM [HP-UXTM
]
SPARCstationTM [SunOSTM, SolarisTM
]
Software
RA78K0
CC78K0
ID78K0-NS
ID78K0
[Japanese/English Windows]
NEWSTM (RISC) [NEWS-OSTM
]
Note
√
√
√
Note
√
√
√
√
–
√
SM78K0
RX78K0
MX78K0
–
√
√
Note
√
Note
√
Note DOS-based software
Data Sheet U14044EJ3V0DS
64
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
APPENDIX B. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
U14046E
µPD780024A, 780034A, 780024AY, 780034AY Subseries User’s Manual
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY Data Sheet
This document
U15132E
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A),
780034AY(A) Data Sheet
µPD78F0034A, 78F0034AY Data Sheet
U14040E
U12326E
78K/0 Series User’s Manual Instructions
Documents Related to Development Tools (User’s Manuals)
Document Name
Document No.
U11802E
RA78K0 Assembler Package
CC78K0 C Compiler
Operation
Assembly Language
Structured Assembly Language
Operation
U11801E
U11789E
U11517E
Language
U11518E
IE-78K0-NS In-circuit Emulator
U13731E
IE-780034-NS-EM1 Emulation Board
U14642E
EP-78240 Emulation Probe
U10332E
SM78K0S, SM78K0 System Simulator Ver. 2.10 or Later Windows based
SM78K Series System Simulator Ver. 2.10 or Later
Operation
U14611E
External Part User Open
Interface Specifications
To be prepared
ID78K0-NS Integrated Debugger Ver. 2.00 or Later Windows based
Operation
Operation
U14379E
U14910E
ID78K0-NS, ID78K0S-NS Integrated Debugger Ver. 2.20 or Later
Windows based
ID78K0 Integrated Debugger Windows based
Reference
Guide
U11539E
U11649E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
Data Sheet U14044EJ3V0DS
65
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
Documents Related to Embedded Software (User’s Manuals)
Document Name
Document No.
U11537E
78K/0 Series Real-time OS
Fundamentals
Installation
U11536E
78K/0 Series OS MX78K0
Fundamental
U12257E
Other Related Documents
Document Name
Document No.
X13769X
SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM)
Semiconductor Device Mounting Technology Manual
C10535E
C11531E
C10983E
C11892E
Quality Grades on NEC Semiconductor Devices
NEC Semiconductor Device Reliability/Quality Control System
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
Data Sheet U14044EJ3V0DS
66
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
[MEMO]
Data Sheet U14044EJ3V0DS
67
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Note: Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use
these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.
FIP and IEBus are trademarks of NEC Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/
or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
Data Sheet U14044EJ3V0DS
68
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.
Benelux Office
Hong Kong
Eindhoven, The Netherlands
Tel: 040-2445845
Tel: 2886-9318
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 01-30-67 58 99
Fax: 0211-65 03 490
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore
Tel: 65-253-8311
NEC Electronics (France) S.A.
Madrid Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 65-250-3583
Fax: 01908-670-290
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: 02-66 75 41
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Fax: 02-2719-5951
Fax: 02-66 75 42 99
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP Brasil
Tel: 55-11-6462-6810
Fax: 55-11-6462-6829
J00.7
Data Sheet U14044EJ3V0DS
69
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
•
The information in this document is current as of November, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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