UPD780306YGF-XXX-3BA [ETC]
MICROCONTROLLER|8-BIT|UPD78K0 CPU|CMOS|QFP|100PIN|PLASTIC ; 微控制器| 8位| UPD78K0 CPU | CMOS | QFP | 100PIN |塑料\n
| 型号： | UPD780306YGF-XXX-3BA |
| 厂家： | 
ETC |
| 描述： | MICROCONTROLLER|8-BIT|UPD78K0 CPU|CMOS|QFP|100PIN|PLASTIC
|
| 文件： | 总72页 (文件大小：532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD780306Y,780308Y
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
µPD780306Y and 780308Y are products in the µPD780308Y subseries within the 78K/0 series, which incorporates LCD
controller/driver, 8-bit resolution A/D converter, timer, serial interface, interrupt functions and many other peripheral
hardwares.
A one-time PROM product capable of operating in the same power supply voltage range as of the mask ROM product,
EPROM product, µPD78P0308Y, and other development tools are available.
For the details of functional description, refer to the following user’s manual.
µPD780308, 780308Y Subseries User’s Manual : U11377E
78K/0 Series User’s Manual (Instruction)
: U12326E
FEATURES
•
Large on-chip ROM & RAM
Item
Program Memory
(ROM)
Data Memory
Product Name
µPD780306Y
µPD780308Y
High-Speed RAM
1024 bytes
Expansion RAM
1024 bytes
LCD Display RAM
48K bytes
60K bytes
40 × 4 bits
• Minimum instruction execution time can be varied from high speed (0.4 µs) to ultra-low speed (122 µs)
• I/O ports: 57 (including segment signal output dual-function pins)
• LCD controller/driver
Supply voltage : VDD = 2.0 to 5.5 V (Operable in any mode)
• 8-bit resolution A/D converter : 8 channels
• Serial interface : 3 channels
• Timer: 5 channels
• Supply voltage : VDD = 2.0 to 5.5 V
APPLICATION FIELD
Celullar phones, compact disk players, cameras, meters, etc.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
The mark shows major revised points.
Document No. U12251EJ2V1DS00 (2nd edition)
Date Published November 2000 N CP(K)
Printed in Japan
1997
©
µPD780306Y, 780308Y
ORDERING INFORMATION
Part Number
Package
µPD780306YGC-×××-8EU
µPD780306YGF-×××-3BA
µPD780308YGC-×××-8EU
µPD780308YGF-×××-3BA
100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
Remark
××× indicates ROM code suffix.
2
Data Sheet U12251EJ2V1DS
µPD780306Y, 780308Y
78K/0 SERIES DEVELOPMENT
The following shows the products organized according to usage. The names in the parallelograms are subseries names.
Products in mass production
Products under development
Y subseries products are compatible with I2C bus.
Control
µ
EMI-noise reduced version of the PD78078
A timer added to the PD78054 and external interface enhanced
ROM-less version of the PD78078
PD78075B
PD78078
µ
µ
100-pin
100-pin
100-pin
100-pin
80-pin
µ
µPD78078Y
µPD78070AY
PD780018AY
µPD78070A
µ
Serial I/O of the
Serial I/O of the
µ
µ
PD78078Y enhanced and the function limited.
PD78054 enhanced and EMI-noise reduced.
µ
PD780058YNote
PD780058
µ
µ
EMI-noise reduced version of the PD78054
µ
µPD78058F
PD78054
µPD78058FY
80-pin
µ
UART and D/A converter enhanced to the PD78014 and I/O enhanced
80-pin
PD78054Y
µ
µ
PD780065
µ
µ
PD780024 increased.
RAM capacity of the
80-pin
PD780034Y
PD780024Y
µ
PD780034
64-pin
64-pin
µ
µ
µ
µ
µ
A/D converter of the PD780024 enhanced
Serial I/O of the µPD78018F added and EMI-noise reduced.
µ
PD780024
PD78014H
PD78018F
PD78083
µ
µ
EMI-noise reduced version of the PD78018F
µ
64-pin
Basic subseries for control
PD78018FY
64-pin
On-chip UART, capable of operating at low voltage (1.8 V)
42/44-pin
Inverter control
PD780988
64-pin
On-chip inverter control circuit and UART. EMI-noise reduced.
µ
FIPTM drive
The I/O and FIP C/D of the
The I/O and FIP C/D of the
µ
µ
PD78044F enhanced. Display output total: 53
PD78044H enhanced. Display output total: 48
100-pin
100-pin
80-pin
80-pin
80-pin
PD780208
PD780228
PD780232
PD78044H
PD78044F
µ
µ
µ
µ
µ
78K/0
Series
For panel control. On-chip FIP and C/D. Display output total: 53
µ
An N-ch open drain I/O added to the PD78044F. Display output total: 34
Basic subseries for driving FIP. Display output total: 34
LCD drive
100-pin
100-pin
100-pin
PD780308
µ
PD780308Y
PD78064Y
µ
µ
The SIO of the PD78064 enhanced, and ROM, RAM capacity increased.
µ
EMI-noise reduced version of the PD78064
PD78064B
PD78064
µ
µ
Basic subseries for driving LCDs, on-chip UART
µ
Bus interface supported
IEBusTM controller added to the
On-chip D-CAN controller
µ
PD78054. EMI-noise reduced.
80-pin
80-pin
µ
µ
PD78098B
PD780948
80-pin
80-pin
PD780701Y
PD780833Y
µ
µ
On-chip D-CAN/IEBus controller
On-chip controller compliant with J1850 (Class 2)
Meter control
80-pin
On-chip automobile meter controller/driver
Ultra low-power consumption. On-chip UART
For industrial meter control
PD780973
µ
µ
µ
80-pin
PD780955
PD780958
100-pin
Note
Under planning
3
Data Sheet U12251EJ2V1DS
µPD780306Y, 780308Y
The following lists the main functional differences between Y subseries products.
Function
ROM
VDD MIN
Serial Interface
I/O
Value
Subseries Name
Capacity
2
88
1.8 V
Control
µPD78078Y
48 K to 60 K
3-wire/2-wire/I C
With automatic transmit/receive function, 3-wire : 1 ch
3-wire/UART : 1 ch
With automatic transmit/receive function, 3-wire : 1 ch
: 1 ch
µPD78070AY
µPD780018AY
61
88
2.7 V
–
48 K to 60 K
Time division 3-wire
: 1 ch
: 1 ch
: 1 ch
2
I C bus (multi master supported)
2
µPD780058BY
68
69
51
1.8 V
24 K to 60 K
3-wire/2-wire/I C
With automatic transmit/receive function, 3-wire : 1 ch
3-wire/Time division UART
: 1 ch
: 1ch
2
µPD78058FY
3-wire/2-wire/I C
2.7 V
2.0 V
1.8 V
48 K to 60 K
16 K to 60 K
8 K to 32 K
With automatic transmit/receive function, 3-wire : 1 ch
µPD78054Y
3-wire/UART
UART
: 1 ch
: 1 ch
: 1 ch
: 1 ch
: 1 ch
µPD780034Y
3-wire
µPD780024Y
µPD78018FY
2
I C bus (multi master supported)
2
53
57
8 K to 60 K
3-wire/2-wire/I C
With automatic transmit/receive function, 3-wire : 1 ch
2
µPD780308Y
µPD78064Y
2.0 V
48 K to 60 K
3-wire/2-wire/I C
3-wire/Time division UART
3-wire
: 1 ch
: 1 ch
: 1 ch
: 1 ch
: 1 ch
LCDdrive
2
16 K to 32 K
3-wire/2-wire/I C
3-wire/UART
Remark The functions other than the serial interface are the same as those of subseries products without the suffix Y.
4
Data Sheet U12251EJ2V1DS
µPD780306Y, 780308Y
OVERVIEW OF FUNCTION
Product Name
µPD780306Y
µPD780308Y
Item
48K bytes
60K bytes
ROM
1024 bytes
1024 bytes
40 × 4 bits
High-speed RAM
Expansion RAM
LCD display RAM
Internal
memory
General registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
On-chip minimum instruction execution time cycle modification function
When main system clock
selected
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (at 5.0 MHz operation)
When subsystem clock
selected
122 µs (at 32.768 kHz operation)
• 16-bit operation
• Multiplication/division (8 bits × 8 bits,16 bits ÷ 8 bits)
• Bit manipulation (set, reset, test, boolean operation)
• BCD correction, etc.
Instruction set
Total
:
:
:
57
02
55
I/O ports
• CMOS input
• CMOS I/O
(including segment signal output pins)
A/D converter
• 8-bit resolution × 8 channels
• Segment signal output : Maximum 40
• Common signal output : Maximum 4
LCD controller/driver
• Bias
:
1/2 or 1/3 switchable
2
•
•
•
3-wire serial I/O/I C bus/2-wire serial I/O mode selectable : 1 channel
Serial interface
3-wire serial I/O/UART mode selectable
3-wire serial I/O mode
:
:
1 channel
1 channel
•
•
•
•
16-bit timer/event counter : 1 channel
8-bit timer/event counter
Watch timer
:
:
:
2 channels
1 channel
1 channel
Timer
Watchdog timer
Timer output
3 (14-bit PWM output capability : 1)
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz,
5.0 MHz (at main system clock: 5.0 MHz operation)
Clock output
32.768 kHz (at subsystem clock: 32.768 kHz operation)
Buzzer output
1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock 5.0 MHz operation)
Internal: 13, external: 6
Internal: 1
Maskable
Vectored
Non-maskable
interrupt
sources
Software
1
Test input
Internal: 1, external: 1
VDD = 2.0 to 5.5 V
Supply voltage
Package
• 100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
• 100-pin plastic QFP (14 × 20 mm)
5
Data Sheet U12251EJ2V1DS
µPD780306Y, 780308Y
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) .......................................................................................................... 7
2. BLOCK DIAGRAM .................................................................................................................................... 10
3. PIN FUNCTIONS ....................................................................................................................................... 11
3.1 PORT PINS ......................................................................................................................................................... 11
3.2 OTHER PINS ...................................................................................................................................................... 13
3.3 PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS ............................................ 14
4. MEMORY SPACE ...................................................................................................................................... 18
5. PERIPHERAL HARDWARE FUNCTION FEATURE.............................................................................. 19
5.1 PORT ................................................................................................................................................................... 19
5.2 CLOCK GENERATOR .......................................................................................................................................20
5.3 TIMER/EVENT COUNTER ................................................................................................................................. 20
5.4 CLOCK OUTPUT CONTROL CIRCUIT ............................................................................................................ 23
5.5 BUZZER OUTPUT CONTROL CIRCUIT .......................................................................................................... 23
5.6 A/D CONVERTER ..............................................................................................................................................24
5.7 SERIAL INTERFACE ......................................................................................................................................... 25
5.8 LCD CONTROLLER/DRIVER ............................................................................................................................ 27
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS .............................................................................. 28
6.1 INTERRUPT FUNCTIONS ................................................................................................................................. 28
6.2 TEST FUNCTIONS ............................................................................................................................................. 32
7. STANDBY FUNCTION .............................................................................................................................. 33
8. RESET FUNCTION.................................................................................................................................... 33
9. INSTRUCTION SET................................................................................................................................... 34
10. ELECTRICAL SPECIFICATIONS............................................................................................................. 37
11. CHARACTERISTIC CURVE (REFERENCE VALUE) ............................................................................. 58
12. PACKAGE DRAWINGS ............................................................................................................................ 60
13. RECOMMENDED SOLDERING CONDITIONS ....................................................................................... 62
APPENDIX A. DEVELOPMENT TOOLS......................................................................................................... 63
APPENDIX B. RELATED DOCUMENTS ........................................................................................................ 66
6
Data Sheet U12251EJ2V1DS
µPD780306Y, 780308Y
1. PIN CONFIGURATION (TOP VIEW)
• 100-pin plastic LQFP (Fine pitch) (14 × 14 mm)
µPD780306YGC-×××-8EU, 780308YGC-×××-8EU
10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
P70/SI2/R D
X
P11/ANI1
P12/ANI2
P13/ANI3
P14/ANI4
P15/ANI5
P16/ANI6
P17/ANI7
1
2
3
4
5
6
75
P27/SCK0/SCL
P26/SO0/SB1/SDA1
P25/SI0/SB0/SDA0
P80/S39
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P81/S38
P82/S37
P83/S36
7
8
V
DD0
P84/S35
P85/S34
P86/S33
P87/S32
P90/S31
9
AVREF
P100
P101
10
11
12
13
14
15
16
17
18
VSS1
P102
P103
P91/S30
P92/S29
P93/S28
P94/S27
P95/S26
P96/S25
P97/S24
S23
P30/TO0
P31/TO1
P32/TO2
60
59
58
P33/TI1
P34/TI2
57
56
55
19
20
P35/PCL
P36/BUZ
P37
21
S22
54
53
52
51
22
23
24
25
S21
COM0
COM1
S20
S19
COM2
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
26 27
Cautions 1. Connect directly the IC (Internally Connected) pin to VSS0 or VSS1.
2. Connect the AVSS pin to VSS0.
Remark When using in applications where noise from inside the microcontroller has to be reduced, it is recommended
that countermeasures against the noise are taken, such as supplying power separately to VDD0 and VDD1, and
connecting VDD0 and VDD1 to ground lines separately.
7
Data Sheet U12251EJ2V1DS
µPD780306Y, 780308Y
• 100-pin plastic QFP (14 × 20 mm)
µPD780306YGF-×××-3BA, 780308YGF-×××-3BA
10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
S20
P26/SO0/SB1/SDA1
P27/SCK0/SCL
1
2
3
4
5
6
80
79
S19
S18
78
77
76
75
74
73
72
71
70
69
68
67
66
P70/SI2/R
X
D
D
S17
S16
S15
S14
P71/SO2/T
X
P72/SCK2/ASCK
IC
7
8
X2
X1
S13
S12
S11
S10
S9
9
V
DD1
10
11
12
13
14
15
16
17
18
XT1/P07
XT2
RESET
S8
P00/INTP0/TI00
P01/INTP1/TI01
P02/INTP2
P03/INTP3
P04/INTP4
S7
S6
S5
S4
65
64
63
S3
S2
S1
S0
P05/INTP5
P110/SI3
62
61
60
19
20
P111/SO3
P112/SCK3
P113/TxD
21
22
23
V
SS0
59
58
57
56
55
54
V
V
LC2
LC1
P114/RxD
P115
24
25
V
LC0
P116
P117
BIAS
26
27
28
COM3
COM2
AVSS
53
52
51
P10/ANI0
29
30
COM1
COM0
P11/ANI1
P12/ANI2
31
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
32
Cautions 1. Connect directly the IC (Internally Connected) pin to VSS0 or VSS1.
2. Connect the AVSS pin to VSS0.
Remark When using in applications where noise from inside the microcontroller has to be reduced, it is recommended
that countermeasures against the noise are taken, such as supplying power separately to VDD0 and VDD1, and
connecting VDD0 and VDD1 to ground lines separately.
8
Data Sheet U12251EJ2V1DS
µPD780306Y, 780308Y
ANI0 to ANI7
ASCK
: Analog Input
: Asynchronous Serial Clock
: Analog Reference Voltage
: Analog Ground
: LCD Power Supply Bias Control
: Buzzer Clock
: Common Output
: Internally Connected
: Interrupt from Peripherals
: Port0
PCL
: Programmable Clock
: Reset
RESET
RxD
AVREF
: Receive Data
: Segment Output
: Serial Bus
AVSS
S0 to S39
SB0, SB1
BIAS
BUZ
SCK0, SCK2, SCK3 : Serial Clock
COM0 to COM3
IC
SCL
: Serial Clock
: Serial Data
: Serial Input
: Serial Output
SDA0, SDA1
SI0, SI2, SI3
SO0, SO2, SO3
INTP0 to INTP5
P00 to P05, P07
P10 to P17
P25 to P27
P30 to P37
P70 to P72
P80 to P87
P90 to P97
P100 to P103
P110 to P117
TI00, TI01, TI1, TI2 : Timer Input
: Port1
: Port2
TO0 to TO2
TxD
: Timer Output
: Port3
: Transmit Data
VDD0, VDD1
VLC0 to VLC2
VSS0, VSS1
X1, X2
: Power Supply
: Port7
: Port8
: LCD Power Supply
: Ground
: Port9
: Crystal (Main System Clock)
: Crystal (Subsystem Clock)
: Port10
: Port11
XT1, XT2
9
Data Sheet U12251EJ2V1DS
µPD780306Y, 780308Y
2. BLOCK DIAGRAM
TO0/P30
TI00/INTP0/P00
TI01/INTP1/P01
P00
16-bit timer/
event counter
PORT 0
P01-P05
P07
TO1/P31
TI1/P33
8-bit timer/
event counter 1
PORT 1
PORT 2
PORT 3
PORT 7
PORT 8
PORT 9
PORT 10
PORT 11
P10-P17
P25-P27
P30-P37
P70-P72
P80-P87
P90-P97
P100-P103
TO2/P32
TI2/P34
8-bit timer/
event counter 2
Watchdog timer
Watch timer
SDA0/SI0/SB0/P25
SDA1/SO0/SB1/P26
SCL/SCK0/P27
Serial
interface 0
78K/0
CPU core
ROM
SI2/RxD/P70
SO2/TxD/P71
RxD/P114
Serial
interface 2
TxD/P113
SCK2/ASCK/P72
P110-P117
S0-S23
SI3/P110
SO3/P111
SCK3/P112
Serial
interface 3
S24/P97-
S31/P90
S32/P97-
S39/P80
RAM
ANI0/P10-
ANI7/P17
A/D converter
LCD
controller/
driver
AVSS
COM0-COM3
AVREF
VLC0-VLC2
INTP0/P00-
INTP5/P05
Interrupt
control
BIAS
f
LCD
BUZ/P36
PCL/P35
Buzzer output
RESET
X1
System
control
Clock output
control
X2
VDD0, VDD1
V
SS0, VSS1
IC
XT1/P07
XT2
Remark The internal ROM capacity varies depending on the product.
10
Data Sheet U12251EJ2V1DS
µPD780306Y, 780308Y
3. PIN FUNCTIONS
3.1 PORT PINS (1/2)
Dual-
Pin Name
I/O
Input
Function
Input only
On Reset
Function Pin
INTP0/TI00
INTP1/TI01
INTP2
P00
P01
Input
P02
Port 0
Input/output can be specified bit-wise.
When used as an input port, internal pull-up
resistor can be used by software.
Input/
7-bit I/O port.
Input
INTP3
P03
output
INTP4
P04
INTP5
P05
P07Note1
Input only
Input
Input
Input
XT1
Port 1
8-bit input/output port.
Input/
P10 to P17
Input/output can be specified bit-wise.
When used as an input port, internal pull-up resistor can be used by
software.Note2
ANI0 to ANI7
output
SI0/SB0/
SDA0
Port 2
P25
P26
P27
3-bit input/output port.
Input/
SO0/SB1/
SDA1
Input
Input
Input
Input/output can be specified bit-wise.
When used as an input port, internal pull-up resistor can be used by
software.
output
SCK0/SCL
TO0
P30
P31
P32
P33
P34
P35
P36
P37
P70
P71
TO1
Port 3
TO2
8-bit input/output port.
TI1
Input/
Input/output can be specified bit-wise.
When used as an input port, internal pull-up resistor can be used by
software.
output
TI2
PCL
BUZ
—
Port 7
SI2/RxD
SO2/TxD
3-bit input/output port.
Input/
Input/output can be specified bit-wise.
When used as an input port, internal pull-up resistor can be used by
software.
output
SCK2/
ASCK
P72
Notes 1. When using the P07/XT1 pins as an input port, set (1) bit 6 (FRC) of the processor clock control register (PCC)
(the on-chip feedback resistor of the subsystem clock oscillator should not be used).
2. When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog input, port 1 is set to input mode.
However, internal pull-up resistor is not automatically used.
Data Sheet U12251EJ2V1DS
11
µPD780306Y, 780308Y
3.1 PORT PINS (2/2)
Dual-
On Reset
Function
Pin Name
I/O
Function Pin
Port 8
8-bit input/output port
Input/output can be specified bit-wise.
Input/
Input
S39 to S32
S31 to S24
—
P80 to P87
When used as an input port, internal pull-up resistor can be used by
software.
output
Input/output port/segment signal output function can be specified in 2-bit
unit by the LCD display control register (LCDC).
Port 9
8-bit input/output port
Input/output can be specified bit-wise.
Input/
P90 to P97
Input
When used as an input port, internal pull-up resistor can be used by
software.
output
Input/output port/segment signal output function can be specified in 2-bit
unit by the LCD display control register (LCDC).
Port 10
4-bit input/output port
Input/
Input/output can be specified bit-wise.
When used as an input port, internal pull-up resistor can be used by
software.
Input
P100 to P103
output
LED direct drive capability.
P110
SI3
Port 11
P111
SO3
SCK3
TxD
RxD
—
8-bit input/output port
P112
Input
Input/
Input/output can be specified bit-wise.
When used as an input port, internal pull-up resistor can be used by
software.
output
P113
P114
Falling edge detection capability.
P115 to P117
12
Data Sheet U12251EJ2V1DS
µPD780306Y, 780308Y
3.2 OTHER PINS (1/2)
Dual-
Function
On Reset
Pin Name
I/O
Function Pin
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
SI0
P00/TI00
P01/TI01
P02
External interrupt request input by which the effective edge (rising
edge, falling edge, or both rising edge and falling edge) can be
specified.
Input
Input
P03
P04
P05
P25/SB0/SDA0
Input
Input
Serial interface serial data input.
Serial interface serial data output.
P70/RxD
P110
SI2
Input
SI3
SO0
P26/SB1/SDA1
P71/TxD
P111
Output
SO2
SO3
SB0
P25/SI0/SDA0
P26/SO0/SDA1
P25/SI0/SB0
P26/SO0/SB1
P27
SB1
Input/
Serial interface serial data input/output.
Serial interface serial clock input/output.
Input
Input
output
SDA0
SDA1
SCK0
SCK2
SCK3
SCL
P72/ASCK
P112
Input/
output
P27/SCK0
P70/SI2, P114
P71/SO2, P113
P72/SCK2
P00/INTP0
P01/INTP1
P33
Input
Asynchronous serial interface serial data input.
Asynchronous serial interface serial data output.
Asynchronous serial interface serial clock input.
External count clock input to 16-bit timer (TM0).
Capture trigger signal input to capture register (CR00).
External count clock input to 8-bit timer (TM1).
External count clock input to 8-bit timer (TM2).
16-bit timer output (shared with 14-bit PWM output).
RxD
Input
Input
Input
Output
Input
TxD
ASCK
TI00
TI01
Input
Input
TI1
TI2
P34
TO0
P30
Output
Input
TO1
P31
8-bit timer output.
TO2
P32
PCL
P35
Clock output (for main system clock, subsystem clock trimming).
Buzzer output.
Input
Input
Output
Output
BUZ
P36
Output
S0 to S23
S24 to S31
S32 to S39
COM0 to COM3
VLC0 to VLC2
BIAS
—
P97 to P90
P87 to P80
—
Output
LCD controller/driver segment signal output.
Input
Output
—
Output
—
LCD controller/driver common signal output.
LCD drive voltage. Split resistors can be incorporated by mask option.
LCD drive power supply.
—
—
—
—
Data Sheet U12251EJ2V1DS
13
µPD780306Y, 780308Y
3.2 OTHER PINS (2/2)
Dual-
Function Pin
On Reset
Pin Name
I/O
Function
Input
Input
Input
—
P10 to P17
ANI0 to ANI7
AVREF
A/D converter analog input.
Reference voltage input of A/D converter and D/A converter
(shared with analog power supply).
—
—
AVSS
Ground potential of A/D converter and D/A converter.
Set the same potential as VSS0.
—
—
Input
Input
—
—
—
—
—
RESET
X1
System reset input.
Main system clock oscillation crystal connection.
Subsystem clock oscillation crystal connection.
—
—
X2
Input
—
P07
—
XT1
XT2
VDD0
VSS0
VDD1
VSS1
IC
Input
—
—
—
—
Positive power supply for port block.
—
—
—
Ground potential for port block.
—
—
—
Positive power supply (except port block).
Ground potential (except port and analog block).
Internally connected. Connect directly to VSS0 or VSS1 pin.
—
—
—
—
—
—
3.3 PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the input/output circuit configuration of each type, refer to Figure 3-1.
Table 3-1. Input/Output Circuit Type of Each Pin (1/2)
Input/output
Circuit Type
I/O
Recommended Connection When Not Used
Connect to VSS0.
Pin Name
2
P00/INTP0/TI00
P01/INTP1/TI01
P02/INTP2
Input
Input/output
Input
8-C
Independently connect to VSS0 through resistor.
P03/INTP3
P04/INTP4
P05/INTP5
16
Connect to VDD0.
P07/XT1
11-B
P10/ANI0 to P17/ANI7
P25/SI0/SB0/SDA0
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P30/TO0
10-B
Independently connect to VDD0 or VSS0 through resistor.
Input/output
P31/TO1
5-H
8-C
P32/TO2
P33/TI1
P34/TI2
14
Data Sheet U12251EJ2V1DS
µPD780306Y, 780308Y
Table 3-1. Input/Output Circuit Type of Each Pin (2/2)
Input/output
Pin Name
P35/PCL
I/O
Recommended Connection When Not Used
Circuit Type
5-H
P36/BUZ
P37
8-C
5-H
8-C
P70/SI2/RxD
P71/SO2/TxD
P72/SCK2/ASCK
P80/S39 to P87/S32
P90/S31 to P97/S24
P100 to P103
P110/SI3
Independently connect to VDD0 or VSS0 through resistor.
17-C
Input/output
5-H
8-C
P111/SO3
P112/SCK3
P113/TxD
P114/RxD
P115 to P117
S0 to S23
COM0 to C0M3
VLC0 to VLC2
BIAS
Independently connect to VDD0 through resistor.
17-B
18-A
Output
Leave unconnected.
—
—
—
Leave unconnected.
RESET
2
Input
XT2
16
Connect to VSS0.
AVREF
—
Connect to VSS0.
AVSS
—
Connect directly to VSS0 or VSS1.
IC
Data Sheet U12251EJ2V1DS
15
µPD780306Y, 780308Y
Figure 3-1. Pin Input/Output Circuits (1/2)
Type 10-B
Type 2
V
DD0
Pull-up
enable
P-ch
V
DD0
IN
Data
P-ch
IN/OUT
Open-drain
output disable
N-ch
V
SS0
Schmitt-triggered input with hysteresis characteristic
Type 11-B
Type 5-H
VDD0
VDD0
Pull-up
enable
P-ch
Pull-up
enable
V
DD0
P-ch
Data
P-ch
VDD0
IN/OUT
Data
P-ch
Output
disable
N-ch
IN/OUT
P-ch
V
SS0
Comparator
Output
disable
+
–
N-ch
N-ch
REF (Threshold voltage)
VSS0
AVSS
V
Input
enable
Input
enable
Type 16
Type 8-C
VDD0
Feedback cut-off
P-ch
Pull-up
enable
P-ch
V
DD0
Data
P-ch
N-ch
IN/OUT
Output
disable
V
SS0
XT1
XT2
16
Data Sheet U12251EJ2V1DS
µPD780306Y, 780308Y
Figure 3-1. Pin Input/Output Circuits (2/2)
Type 17-C
Type 17-B
VLC0
V
DD0
P-ch
N-ch
VLC1
Pull-up
enable
P-ch
P-ch
V
DD0
SEG
data
OUT
Data
P-ch
N-ch
P-ch
N-ch
IN/OUT
VLC2
Output
disable
N-ch
V
SS0
Input
enable
VSS1
V
V
LC0
LC1
Type 18-A
P-ch
N-ch
V
V
LC0
LC1
P-ch
N-ch
P-ch
N-ch
SEG
data
N-ch
P-ch
P-ch
N-ch
P-ch
N-ch
V
LC2
OUT
COM
data
V
SS1
P-ch
N-ch
V
LC2
V
SS1
Data Sheet U12251EJ2V1DS
17
µPD780306Y, 780308Y
4. MEMORY SPACE
The memory map of µPD780306Y and 780308Y is shown in Figure 4-1.
Figure 4-1. Memory Map
FFFFH
Special function register (SFR)
256 × 8 bits
FF00H
FEFFH
General registers
32 × 8 bits
FEE0H
FEDFH
Internal high-speed RAM
1024 × 8 bits
FB00H
FAFFH
nnnnH
Use prohibited
Program area
FA80H
FA7FH
Data memory
space
1000H
0FFFH
LCD display RAM
40 × 4 bits
FA58H
FA57H
CALLF entry area
Use prohibited
0800H
07FFH
F800H
F7FFH
Internal expansion RAM
Program area
1024 × 8 bits
0080H
007FH
F400H
F3FFH
Use prohibited
nnnnH+1
nnnnH
CALLT table area
Vector table area
0040H
003FH
Program
memory
space
Internal ROMNote
0000H
0000H
Note The capacity of Internal ROM differs according to product. (refer to the following table.)
Last Address of Internal ROM
Product Name
nnnnH
µPD780306Y
µPD780308Y
BFFFH
EFFFH
18
Data Sheet U12251EJ2V1DS
µPD780306Y, 780308Y
5. PERIPHERAL HARDWARE FUNCTION FEATURE
5.1 PORT
There are two kinds of I/O port.
• CMOS input (P00, P07)
: 2
• CMOS input/output (P01 to P05, Port 1 to 3, 7 to 11)
Total
: 55
: 57
Table 5-1. Functions of Ports
Name
Port 0
Pin Name
P00, P07
Function
Dedicated input port
Input/output port. Input/output specifiable bit-wise.
P01 to P05
When used as input port, on-chip pull-up resistor can be used by software.
Input/output port. Input/output specifialbe bit-wise.
P10 to P17
P25 to P27
P30 to P37
P70 to P72
Port 1
Port 2
Port 3
Port 7
When used as input port, on-chip pull-up resistor can be used by software.
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Input/output port/segment signal output function specifiable in 2-bit units by LCD display
control register (LCDC).
P80 to P87
P90 to P97
Port 8
Port 9
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Input/output port/segment signal output function specifiable in 2-bit units by LCD display
control register (LCDC).
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Direct LED drive capability.
Port 10
Port 11
P100 to P103
P110 to P117
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used by software.
Test flag (KRIF) is set to 1 by falling edge detection.
Data Sheet U12251EJ2V1DS
19
µPD780306Y, 780308Y
5.2 CLOCK GENERATOR
There are two kinds of clocks, main system clock and subsystem clock.
The minimum instruction execution time can also be changed.
• 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (main system clock: in 5.0 MHz operation)
• 122 µs (subsystem clock: in 32.768 kHz operation)
Figure 5-1. Clock Generator Block Diagram
XT1/P07
Subsystem
clock
oscillator
fXT
Watch timer
Clock output function
XT2
Prescaler
Main
system
clock
X1
X2
fX
Selec-
tor
Prescaler
Clock to
peripheral
hardware
f
XX
oscillator
1/2
Scaler
f
2
X
f
XX
f
XX
f
XX
f
XX
f
2
XT
2
22 23 24
STOP
CPU
clock
Standby
control
circuit
Selec-
tor
(fCPU
)
To INTP0
sampling clock
5.3 TIMER/EVENT COUNTER
Five timer/event counter channels are incorporated.
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter
• Watch timer
: 2 channels
: 1 channel
: 1 channel
• Watchdog timer
Table 5-2. Timer/Event Counter Types and Functions
8-bit Timer/
Event Counter
16-bit Timer/
Event Counter
Watch Timer
Watchdog Timer
Interval timer
Type
1 channel
1 channel
1 output
1 output
2 inputs
1 output
1 output
2
2 channels
1 channel
1 channel
External event counter
2 channels
–
–
–
–
–
–
–
1
–
Timer output
2 outputs
–
PWM output
–
–
Pulse width measurement
–
–
Function
Square wave output
One-shot pulse output
Interrupt request
Test input
2 outputs
–
–
2
–
–
1
–
1 input
Data Sheet U12251EJ2V1DS
20
µPD780306Y, 780308Y
Figure 5-2. 16-Bit Timer/Event Counter Block Diagram
Internal bus
INTP1
TI01/P01/INTP1
16-bit
capture/compare
register (CR00)
Selec-
tor
INTTM00
PWM
pulse
output
control
circuit
Output
control circuit
Match
TO0/P30
Watch Timer Output
2fXX
f
XX
16-bit
timer register
(TM0)
Selec-
tor
f
XX/2
f
XX/22
Clear
Selector
Edge
detector
TI00/P00/INTP0
Match
INTTM01
INTP0
16-bit
capture/compare
register
(CR01)
Internal bus
Figure 5-3. 8-Bit Timer/Event Counter Block Diagram
Internal bus
INTTM1
8-bit
compare
register (CR10)
8-bit
compare register
(CR20)
Output
control
circuit
Selec-
tor
TO2/P32
INTTM2
Match
Match
f
f
XX/2-fXX/29
fx
/211
8-bit
timer register 1
(TM1)
Selec-
tor
X
8-bit
timer register 2
(TM2)
Selec-
tor
TI1/P33
Clear
Clear
XX/2-fXX/29
Selector
Selec-
tor
fx
X
/211
TI2/P34
Output
control
circuit
TO1/P31
Internal bus
Data Sheet U12251EJ2V1DS
21
µPD780306Y, 780308Y
Figure 5-4. Watch Timer Block Diagram
fW
214
5-bit counter
Selector
fXX/27
fXT
fW
Selec-
tor
INTWT
Selector
Prescaler
fW
fW
24
fW
25
fW
26
fW
27
fW
28
fW
29
213
INTTM3
Selector
To 16-bit
timer/event counter
To LCD
controller/driver
Figure 5-5. Watchdog Timer Block Diagram
f
XX
23
Prescaler
f
XX
24
f
XX
25
f
XX
26
f
XX
27
f
XX
28
f
XX
29
fXX
211
INTWDT
maskable
interrupt
request
Control
circuit
RESET
8-bit counter
Selector
INTWDT
non-maskable
interrupt
request
Data Sheet U12251EJ2V1DS
22
µPD780306Y, 780308Y
5.4 CLOCK OUTPUT CONTROL CIRCUIT
Clocks of the following frequency can be output as clock outputs.
• 19.5 kHz/39.1kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 MHz (main system clock: in 5.0
MHz operation)
• 32.768 kHz (subsystem clock: in 32.768 kHz operation)
Figure 5-6. Clock Output Control Circuit Block Diagram
f
XX
f
XX/2
f
f
f
XX/22
XX/23
XX/24
Synchronization
circuit
Output control circuit
Selector
PCL/P35
f
XX/25
XX/26
XX/27
f
f
f
XT
5.5 BUZZER OUTPUT CONTROL CIRCUIT
Clocks of the following frequency can be output as buzzer outputs.
• 1.2 kHz/2.4 kHz/4.9 kHz/9.8 kHz (main system clock : in 5.0 MHz operation)
Figure 5-7. Buzzer Output Control Circuit Block Diagram
f
XX/29
XX/210
XX/211
BUZ/P36
Selector
Output control circuit
f
f
Data Sheet U12251EJ2V1DS
23
µPD780306Y, 780308Y
5.6 A/D CONVERTER
Eight 8-bit resolution A/D converter channels are incorporated.
The following two types of start-up method are available.
• Hardware start
• Software start
Figure 5-8. A/D Converter Block Diagram
Series resistor string
AVREF
ANI0/P10
ANI1/P11
ANI2/P12
ANI3/P13
ANI4/P14
ANI5/P15
ANI6/P16
ANI7/P17
Sample & hold circuit
Voltage comparator
Tap
selec-
tor
Selec-
tor
AVSS
Successive approximation
register (SAR)
Edge
detector
Control
circuit
INTP3/P03
INTAD
INTP3
A/D conversion result
register (ADCR)
Internal bus
Data Sheet U12251EJ2V1DS
24
µPD780306Y, 780308Y
5.7 SERIAL INTERFACE
Three clocked serial interface channels are incorporated.
• Serial interface channel 0
• Serial interface channel 2
• Serial interface channel 3
Table 5-3. Serial Interface Channel Block Diagram
Function
Serial Interface Channel 0
(MSB/LSB-first switchable)
(MSB-first)
Serial Interface Channel 2
Serial Interface Channel 3
3-wire serial I/O mode
(MSB/LSB-first switchable)
(MSB/LSB-first switchable)
2
I C (Inter IC) bus mode
—
—
—
—
—
2-wire serial I/O mode
(MSB-first)
Asynchronous serial interface
(UART) mode
—
(With dedicated baud rate
generator, data I/O pin
switch function)
Figure 5-9. Serial Interface Channel 0 Block Diagram
Internal bus
SI0/SB0/SDA0/P25
SO0/SB1/SDA1/P26
Serial I/O
shift register 0 (SIO0)
Output
latch
Selector
Selector
Busy/acknowledge
output circuit
Stop condition/
start condition/
acknowledge detector
Interrupt request
signal generator
INTCSI0
SCK0/SCL/P27
Serial clock counter
f
XX/2-fXX/28
Serial clock control circuit
Selector
TO2
Data Sheet U12251EJ2V1DS
25
µPD780306Y, 780308Y
Figure 5-10. Serial Interface Channel 2 Block Diagram
Internal bus
Receive buffer
register (RXB/SIO2)
Direction
control circuit
Direction
control circuit
Transmit shift
register (TXS/SIO2)
RXD/P114
Selector
Selector
Receive shift
register (RXS)
Transmit
control circuit
R
X
D/SI2/P70
INTST
TXD/SO2/P71
INTSER
INTSR/INTCSI2
Receive
control circuit
TXD/P113
SCK output
control circuit
ASCK/SCK2/P72
Baud rate
generator
f
XX-fXX/210
Figure 5-11. Serial Interface Channel 3 Block Diagram
Internal bus
Serial I/O
shift register 3 (SIO3)
SI3/P110
SO3/P111
SCK3/P112
Interrupt request
signal generator
INTCSI3
Serial clock counter
f
XX/2-fXX/28
Serial clock control circuit
Selector
Data Sheet U12251EJ2V1DS
26
µPD780306Y, 780308Y
5.8
LCD CONTROLLER/DRIVER
An LCD controller/driver with the following functions is incorporated.
• Selection of 5 types of display mode
• 16 of the segment signal of outputs can be switched to input/output ports in units of 2.
(P80/S39 to P87/S32, P90/S31 to P97/S24)
Table 5-4. Display Mode Types and Maximum Number of Display Pixels
Bias Method
Time Multiplexing
Common Signal Used
COM0 (COM1 to COM3)
COM0, COM1
Maximum Number of Display Pixels
40 (40 segments × 1 common)
80 (40 segments × 2 commons)
Static
2
3
3
4
1/2
1/3
COM0 to COM2
120 (40 segments × 3 commons)
160 (40 segments × 4 commons)
COM0 to COM2
COM0 to COM3
Figure 5-12. LCD Controller/Driver Block Diagram
Internal bus
f
W
26
Prescaler
Display
data memory
f
W
29
f
W
28
f
W
27
LCDCL
Timing controller
Selector
Segment
data selector
Port
output data
LCD drive mode
switch circuit
LCD drive voltage
generator
Common driver
Segment driver
S0
S23 S24/P97
S39/P80
COM0 COM1 COM2 COM3
V
LC2
V
LC1
VLC0 BIAS
Data Sheet U12251EJ2V1DS
27
µPD780306Y, 780308Y
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS
6.1 INTERRUPT FUNCTIONS
There are twenty-one of interrupt sources of three different kinds, as shown below.
• Non-maskable : 1
• Maskable
• Software
: 19
: 1
Data Sheet U12251EJ2V1DS
28
µPD780306Y, 780308Y
Table 6-1. Interrupt Source List
Vector
Table
Address
Basic Con-
figuration
Type Note2
Interrupt Source
Trigger
Interrupt
Type
Default
Priority Note1
Internal/
External
Name
Watchdog timer overflow (with watchdog timer
mode 1 selected)
Non-
maskable
——
0
INTWDT
(A)
Internal
0004H
Watchdog timer overflow (with interval timer
mode selected)
INTWDT
(B)
(C)
1
2
3
4
5
6
7
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTCSI0
0006H
0008H
000AH
000CH
000EH
0010H
0014H
Pin input edge detection
External
(D)
Serial interface channel 0 transfer termination
Serial interface channel 2 UART reception
error generation
8
INTSER
INTSR
0018H
Serial interface channel 2 UART reception
termination
Maskable
9
001AH
Serial interface channel 2 3-wire transfer
termination
INTCSI2
INTST
Serial interface channel 2 UART transmission
termination
10
11
12
13
14
15
001CH
001EH
0020H
0022H
0024H
0026H
Reference time interval signal from watch
timer
INTTM3
INTTM00
INTTM01
INTTM1
INTTM2
(B)
Internal
16-bit timer register and capture/compare
register (CR00) match signal generation
16-bit timer register and capture/compare
register (CR01) match signal generation
8-bit timer/event counter 1 match signal
generation
8-bit timer/event counter 2 match signal
generation
16
17
A/D converter conversion termination
Serial interface channel 3 transfer termination
BRK instruction execution
0028H
002AH
003EH
INTAD
INTCSI3
BRK
——
Software
——
(E)
Notes 1. Default priority is a priority order when more than one maskable interrupt source is generated simultaneously.
0 is the highest and 17 the lowest.
2. Basic configuration types (A) to (E) correspond to those shown on the next page.
Data Sheet U12251EJ2V1DS
29
µPD780306Y, 780308Y
Figure 6-1. Basic Configuration of Interrupt Functions (1/2)
(A) Internal non-maskable interrupt
Internal bus
Priority
control
circuit
Vector table
Interrupt
request
address
generator
Standby release
signal
(B) Intrnal maskable interrupt
Internal bus
IE
MK
PR
ISP
Priority
control
circuit
Vector table
address
Interrupt
request
IF
generator
Standby release
signal
(C) External maskable interrupt (INTP0)
Internal bus
MK
Sampling clock
select register
(SCS)
External interrupt
mode register
(INTM0)
IE
PR
ISP
Priority
control
circuit
Vector table
address
generator
Interrupt
request
Sampling
clock
Edge
detector
IF
Standby
release
signal
Data Sheet U12251EJ2V1DS
30
µPD780306Y, 780308Y
Figure 6-1. Basic Configuration of Interrupt Functions (2/2)
(D) External maskable interrupt (except INTP0)
Internal bus
External interrupt
mode register
(INTM0, INTM1)
MK
IE
PR
ISP
Vector table
address
generator
Priority control
circuit
Interrupt
request
Edge
detector
IF
Standby
release
signal
(E) Software interrupt
Internal bus
Priority
control
circuit
Vector table
address
generator
Interrupt
request
IF : Interrupt request flag
IE : Interrupt enable flag
ISP : In-service priority flag
MK : Interrupt mask flag
PR : Priority hung-up flag
Data Sheet U12251EJ2V1DS
31
µPD780306Y, 780308Y
6.2 TEST FUNCTIONS
There are two test functions as shown in Table 6-2.
Table 6-2. Test Input Source List
Test Input Source
Trigger
Internal/External
Name
INTWT
INTPT11
Watch timer overflow
Internal
External
Port 11 falling edge detection
Figure 6-2. Basic Configuration of Test Function
Internal bus
MK
Standby release
signal
Test input
signal
IF
IF : Test input flag
MK : Test mask flag
Data Sheet U12251EJ2V1DS
32
µPD780306Y, 780308Y
7. STANDBY FUNCTION
The standby function is a function to reduce the current consumption and there are the following two kinds of standby
functions.
• HALT mode : Halts CPU operating clock and can reduce average current consumption by the intermittent operation
along with the normal operation.
• STOP mode : Halts main system clock oscillation. Halts all operations with the main system clock and sets ultra-
low current consumption state with subsystem clock only.
Figure 7-1. Standby Function
CSS=1
Main system clock operation
Subsystem clock operationNote
CSS=0
HALT instruction
STOP
instruction
HALT instruction
HALT modeNote
Clock supply to CPU halted,
oscillation maintained
Interrupt
request
Interrupt
request
Interrupt
request
STOP mode
HALT mode
Main system clock
oscillation halted
Clock supply to CPU halted,
oscillation maintained
(
)
(
)
(
)
Note Halting the main system clock enables the current consumption to be reduced.
When the CPU is operated by the subsystem clock, the main system clock should be halted by setting the bit 7 (MCC)
of the processor clock control register (PCC). The STOP instruction is not available.
Caution When the main system clock is stopped and the system is operated by the subsystem clock, the main
system clock should be returned to after securing the oscillation stabilization time by a program.
8. RESET FUNCTION
There are the following two kinds of resetting methods.
• External reset by RESET pin.
• Internal reset by watchdog timer hung-up time detection.
Data Sheet U12251EJ2V1DS
33
µPD780306Y, 780308Y
9. INSTRUCTION SET
(1) 8-bit instruction
MOV, XCH, ADD, ADDC, SUB, SUBS, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC,
ROR4, ROL4, PUSH, POP, DBNZ
[HL+byte]
[HL+B]
[HL+C]
2nd Operand
#byte
A
rNote
sfr
saddr !addr16 PSW
[DE]
[HL]
$addr16
1
None
1st Operand
A
MOV
XCH
MOV
MOV
MOV
XCH
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
ROR
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
ROL
ADD
ADD
RORC
ROLC
ADDC
ADDC
SUB
SUB
SUBC
SUBC
AND
AND
XOR
CMP
OR
OR
XOR
XOR
XOR
CMP
XOR
CMP
XOR
CMP
CMP
CMP
r
MOV
MOV
ADD
ADDC
SUB
SUBC
AND
OR
INC
DEC
XOR
CMP
B, C
sfr
DBNZ
DBNZ
MOV
MOV
ADD
ADDC
SUB
SUBC
AND
OR
MOV
MOV
saddr
INC
DEC
XOR
CMP
!addr16
PSW
MOV
MOV
MOV
PUSH
POP
[DE]
[HL]
MOV
MOV
ROR4
ROL4
[HL+byte]
[HL+B]
[HL+C]
X
MOV
MULU
C
DIVUW
Note Except r = A
Data Sheet U12251EJ2V1DS
34
µPD780306Y, 780308Y
(2) 16-bit instruction
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
#word
AX
rpNote
sfrp
saddrp
MOVW
!addr16
MOVW
SP
None
1st Operand
AX
ADDW
SUBW
CMPW
MOVW
MOVW
MOVW
XCHW
MOVW
rp
MOVWNote
INCW, DECW
PUSH, POP
sfrp
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
saddrp
!addr16
SP
MOVW
Note Only when rp = BC, DE, HL
(3) Bit manipulation instruction
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd Operand
A.bit
sfr.bit
saddr.bit
PSW.bits
[HL].bit
CY
$addr16
None
1st Operand
A.bit
BT
SET1
CLR1
MOV1
BF
BTCLR
BT
SET1
CLR1
sfr.bit
MOV1
MOV1
MOV1
MOV1
BF
BTCLR
BT
SET1
CLR1
saddr.bit
PSW.bit
[HL].bit
CY
BF
BTCLR
BT
SET1
CLR1
BF
BTCLR
BT
SET1
CLR1
BF
BTCLR
MOV1
AND1
OR1
SET1
CLR1
NOT1
MOV1
MOV1
AND1
OR1
MOV1
AND1
OR1
MOV1
AND1
OR1
AND1
OR1
XOR1
XOR1
XOR1
XOR1
XOR1
Data Sheet U12251EJ2V1DS
35
µPD780306Y, 780308Y
(4) Call instruction/branch instruction
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DNZB
2nd Operand
AX
!addr16
!addr11
CALLF
[addr5]
CALLT
$addr16
1st Operand
Basic instruction
BR
CALL
BR
BR, BC, BNC,
BZ, BNZ
Compound
Instruction
BT, BF,
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
Data Sheet U12251EJ2V1DS
36
µPD780306Y, 780308Y
10. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Parameter
Symbol
Test Conditions
Rating
Unit
V
VDD
–0.3 to +7.0
Supply voltage
AVREF
AVSS
VI
–0.3 to VDD + 0.3
–0.3 to +0.3
V
V
V
V
V
V
Input voltage
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
AVSS – 0.3 to AVREF + 0.3
–10
Output voltage
Analog input voltage
VO
P10-P17
1 pin
Analog input pin
VAN
Output current, high
IOH
Total for P01-P05, P10-P17, P25-P27, P70-P72,
P110-P117
–15
mA
–15
30
mA
mA
mA
mA
mA
mA
mA
mA
mA
°C
Total for P30-P37, P80-P87, P90-P97, P100-P117
Peak value
1 pin
15Note
60
r.m.s. value
Total for P01-P05, P10-P17,
P110-P117
Peak value
r.m.s. value
Peak value
r.m.s. value
Peak value
r.m.s. value
40Note
140
IOL
Output current, low
Total for P30-P37, P100-P103
100Note
50
Total for P25-P27, P70-P72,
P80-P87, P90-P97
20Note
–40 to +85
–65 to +150
Operating ambient temperature
Storage temperature
TA
Tstg
°C
Note The r.m.s. value should be calculated as follows: [r.m.s. value] = [Peak value] × Duty
√
Caution The product quality may be damaged even if a value of only one of the above parameters exceeds the
absolute maximum rating or any value exceeds the absolute maximum rating for an instant. That is, the
absolute maximum rating is a rating value which may cause a product to be damaged physically. The
absolute maximum rating values must therefore be observed in using the product.
Remark Unless specified otherwise, the characteristics of dual-function pins are the same as the those of port pins.
CAPACITANCE (TA= 25 °C, VDD = VSS = 0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
Output capacitance
I/O capacitance
CIN
pF
pF
pF
15
15
15
f = 1 MHz unmeasured
pins returned to 0 V.
COUT
CIO
Data Sheet U12251EJ2V1DS
37
µPD780306Y, 780308Y
MAIN SYSTEM CLOCK OSCILLATION CIRCUIT CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.0Note 4 to 5.5 V)
Recommended
Test conditions
VDD = Oscillator
TYP.
Resonator
Ceramic
Parameter
Oscillator
MIN.
1
MAX.
5
Unit
circuit
X1
IC
R1
X2
MHz
resonator
frequency (fX)Note 1
voltage range
C1
C2
After VDD reaches oscil-
lator voltage range MIN.
Oscillation
stabilization timeNote 2
4
5
ms
VDD = Oscillator
voltage range
Crystal
Oscillator
frequency (fX)Note 1
X1
IC
X2
1
MHz
ms
resonator
R1
VDD = 4.5 to 5.5 VNote 3
10
30
C1
C2
Oscillation
stabilization timeNote 2
Note 3
External clock
X1 input
frequency (fX)Note 1
MHz
ns
5.0
1.0
85
X2
X1
X1 input
µPD74HCU04
high/low level width
(tXH , tXL)
500
Notes 1. Indicates only oscillation circuit characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
3. After VDD reaches the minimum oscillator voltage range.
4. Actually, oscillation start voltage or over, and VDD = 2.0 or over (For an external clock, VDD = 2.0 or over is
OK).
Cautions 1. When using the main system clock oscillator, wiring in the area enclosed with the broken line should
be carried out as follows to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Wiring should be as short as possible.
Wiring should not cross other signal lines.
Wiring should not be placed close to a varying high current.
The potential of the oscillator capacitor ground should be the same as VSS.
Do not ground it to the ground pattern in which a high current flows.
Do not fetch a signal from the oscillator.
2. If the main system clock oscillation circuit is operated by the subsystem clock when the main
system clock is stopped, reswitching to the main system clock should be performed after the stable
oscillation time has been obtained by the program.
Data Sheet U12251EJ2V1DS
38
µPD780306Y, 780308Y
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85°C, VDD = 2.0Note 4 to 5.5 V)
Resonator
Recommended Circuit
Parameter
Test Conditions
MIN.
32
TYP. MAX. Unit
VDD = Oscillator
voltage range
XT2
R2
IC
XT1
Oscillator frequency
(fXT)Note 1
32.768 35
kHz
s
Crystal resonator
VDD = 4.5 to 5.5 VNote 3
1.2
2
C4
C3
Oscillation stabilization
timeNote 2
Note 3
10
XT1 input frequency
(fXT)Note 1
32
5
kHz
100
15
XT2
XT1
External clock
XT1 input high-/low-level
width (tXTH/tXTL)
µs
Notes 1. Indicates only oscillation circuit characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD has reached the minimum oscillation voltage range.
3. After VDD reaches the minimum oscillator voltage range.
4. Actually, oscillation start voltage or over, and VDD = 2.0 or over (For an external clock, VDD = 2.0 or over is
OK).
Cautions 1. When using the subsystem clock oscillator, wiring in the area enclosed with the broken line should
be carried out as follows to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Wiring should be as short as possible.
Wiring should not cross other signal lines.
Wiring should not be placed close to a varying high current.
The potential of the oscillator capacitor ground should be the same as VSS.
Do not ground it to the ground pattern in which a high current flows.
Do not fetch a signal from the oscillator.
2. The subsystem clock oscillation circuit is designed as a low amplification circuit to provide low
consumption current, causing misoperation to noise more frequently than the main system clock
oscillation circuit. Special care should therefore be taken to wiring method when the subsystem
clock is used.
Data Sheet U12251EJ2V1DS
39
µPD780306Y, 780308Y
RECOMMENDED OSCILLATION CIRCUIT CONSTANT
MAIN SYSTEM CLOCK: CERAMIC RESONATOR (TA = –40 to +85 °C)
Frequency
(MHz)
2.00
3.58
4.19
4.91
5.00
1.00
3.58
4.19
4.91
5.00
1.00
2.00
2.00
3.58
3.58
4.19
4.19
4.91
4.91
5.00
5.00
Recommended Circuit Constant
Oscillator Voltage Range
Manufacturer
Product Name
C1 (pF)
Built-in
Built-in
Built-in
Built-in
Built-in
150
C2 (pF)
Built-in
Built-in
Built-in
Built-in
Built-in
150
R1 (kΩ)
MIN. (V)
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
MAX. (V)
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
Matsushita
Electronics
Components
Co., Ltd.
EFOEC2004A5
EFOEC3584A4
EFOEC419A4
EFOEC4914A4
EFOEC5004A4
CCR1000K2
4.7
0
0
0
0
TDK Corp.
0
CCR3.58MC3
CCR4.19MC3
CCR4.91MC3
CCR5.0MC3
Built-in
Built-in
Built-in
Built-in
100
Built-in
Built-in
Built-in
Built-in
100
0
0
0
0
Murata Mfg.
Co., Ltd.
CSB1000J
2.2
0
CSA2.00MG040
CST2.00MG040
CSA3.58MG
100
100
Built-in
30
Built-in
30
0
0
CST3.58MGW
CSA4.19MG
Built-in
30
Built-in
30
0
0
CST4.19MGW
CSA4.91MG
Built-in
30
Built-in
30
0
0
CST4.91MGW
CSA5.00MG
Built-in
30
Built-in
30
0
0
CST5.00MGW
Built-in
Built-in
0
Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation
but do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy
of the oscillation frequency, it is necessary to set the oscillation frequency in the application circuit.
For this, it is necessary to directly contact the manufacturer of the resonator being used.
Data Sheet U12251EJ2V1DS
40
µPD780306Y, 780308Y
DC CHARACTERISTICS (TA = –40 to +85°C, VDD = 2.0 to 5.5 V)
Parameter
Symbol
Test Conditions
P10-P17, P30-P32,
MIN.
TYP.
MAX.
Unit
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
0.7 VDD
VDD
VDD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VIH1
P35-P37, P80-P87,
P90-P97, P100-P103
P00-P05, P25-P27,
P33, P34, P70-P72,
P110-P117, RESET
0.8 VDD
0.8 VDD
VDD
VIH2
VIH3
0.85 VDD
VDD
Input voltage,
high
VDD–0.5
VDD
X1, X2
VDD–0.2
VDD
4.5 ≤ VDD ≤ 5.5 V
2.7 ≤ VDD < 4.5 V
2.0 ≤ VDD < 2.7 VNote
VDD = 2.7 to 5.5 V
0.8 VDD
VDD
0.9 VDD
VDD
VIH4
XT1/P07, XT2
0.9 VDD
VDD
P10-P17, P30-P32,
P35-P37, P80-P87,
P90-P97, P100-P103
P00-P05, P25-P27,
P33, P34, P70-P72,
P110-P117, RESET
0
0.3 VDD
0.2 VDD
0.2 VDD
0.15 VDD
0.4
VIL1
VIL2
0
0
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
0
Input voltage,
low
0
VIL3
VIL4
VOH
X1, X2
0
0.2
4.5 ≤ VDD ≤ 5.5 V
2.7 ≤ VDD < 4.5 V
2.0 ≤ VDD < 2.7 VNote
0
0.2 VDD
0.1 VDD
0.1 VDD
VDD
0
XT1/P07, XT2
0
VDD–1.0
VDD–0.5
VDD = 4.5 to 5.5 V IOH = –1 mA
Output voltage,
high
VDD
IOH = –100 µA
VDD = 4.5 to 5.5 V,
0.6
2.0
0.4
V
P100-P103
IOL = 15 mA
VOL1
P01-P05, P10-P17,
P25-P27, P30-P37,
P70-P72, P80-P87,
P90-P97, P110-P117
VDD = 4.5 to 5.5 V,
IOL = 1.6 mA
V
Output voltage,
low
VDD = 4.5 to 5.5 V,
open-drain,
VOL2
VOL3
0.2 VDD
0.5
V
V
SB0, SB1, SCK0
pulled up (R = 1 kΩ)
IOL = 400 µA
Note When used as P07, the inverse phase of P07 should be input to XT2 using an inverter.
Remark Unless specified otherwise, the characteristics of dual-function pins are the same as the those of port pins.
Data Sheet U12251EJ2V1DS
41
µPD780306Y, 780308Y
DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.0 to 5.5 V)
Parameter
Symbol
Test Conditions
P00-P05, P10-P17, P25-P27,
MIN.
TYP.
MAX.
3
Unit
µA
P30-P37, P70-P72, P80-P87,
P90-P97, P100-P103,
P110-P117
Input leakage
current, high
ILIH1
VIN = VDD
ILIH2
X1, X2, XT1/P07, XT2
20
µA
P00-P05, P10-P17, P25-P27,
P30-P37, P70-P72, P80-P87,
P90-P97, P100-P103,
P110-P117
Input leakage
current, low
ILIL1
–3
µA
VIN = 0 V
ILIH2
ILOH
X1, X2, XT1/P07, XT2
–20
3
µA
µA
Output leakage
current, high
VOUT = VDD
VOUT = 0 V
Output leakage
current, low
ILOL
–3
90
µA
kΩ
P01-P05, P10-P17, P25-
P27, P30-P37, P70-P72,
P80-P87, P90-P97, P100-
P103, P110-P117
Software
R
VIN = 0 V
15
45
pull-up resistor
VDD = 5.0 V ± 10 %Note 5
VDD = 3.0 V ± 10 %Note 6
VDD = 2.2 V ± 10 %Note 6
VDD = 5.0 V ± 10 %Note 5
4
12
1.8
1.05
19.5
2.4
4.2
1500
840
4.8
1950
120
64
mA
mA
mA
mA
mA
mA
µA
µA
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
5.00 MHz, Crystal oscillation
(fXX = 2.5 MHz)Note 2
operating mode
0.6
0.35
6.5
0.8
1.4
500
280
1.6
650
60
IDD1
5.00MHz,Crystaloscillation(fXX
=5.0MHz)Note3 operatingmode
VDD = 3.0 V ± 10 %Note 6
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 2.2 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 2.2 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 2.2 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 2.2 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 2.2 V ± 10 %
5.00 MHz, Crystal oscillation
(fXX = 2.5 MHz)Note 2
HALT mode
IDD2
5.00MHz,Crystaloscillation(fXX
= 5.0 MHz)Note 3 HALT mode
Supply
currentNote 1
32.768 kHz, Crystal oscillation
operating modeNote 4
IDD3
IDD4
IDD5
IDD6
32
24
48
25
55
32.768 kHz, Crystal oscillation
HALT modeNote 4
5
15
2.5
1
12.5
30
XT1 = VDD
STOP mode
When feedback resistor is
connected
0.5
0.3
0.1
0.05
0.05
10
10
XT1 = VDD
STOP mode
When feedback resistor is
disconnected
30
10
10
Notes 1. Current flowing VDD pin. Not including A/D converter, ports, on-chip pull-up resistors or LCD dividing resistors.
2. Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H)
3. Main system clock fXX = fX operation (when OSMS is set to 01H)
4. When the main system clock is stopped.
5. High-speed mode operation (when processor clock control register (PCC) is set to 00H)
6. Low-speed mode operation (when PCC is set to 04H)
Remark Unless specified otherwise, the characteristics of dual-function pins are the same as the those of port pins.
Data Sheet U12251EJ2V1DS
42
µPD780306Y, 780308Y
LCD CONTROLLER/DRIVER CHARACTERISTICS (AT NORMAL OPERATION)
(1) Static Display Mode (TA = –10 to +85 °C, VDD = 2.0 to 5.5 V)
Parameter
Symbol
VLCD
Test Conditions
MIN.
2.0
TYP.
100
MAX.
VDD
Unit
V
LCD drive voltage
LCD dividing resistor
RLCD
60
150
kΩ
LCD output voltage
deviationNote (common)
VODC
IO = ±5 µA
IO = ±1 µA
0
0
±0.2
±0.2
V
V
VLCD0 = VLCD
LCD output voltage
deviationNote (segment)
VODS
Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and
common outputs (VLCDn; n = 0, 1, 2).
(2) 1/3 Bias Method (TA = –10 to +85 °C, VDD = 2.5 to 5.5 V)
Parameter
Symbol
VLCD
Test Conditions
MIN.
2.5
TYP.
100
MAX.
VDD
Unit
V
LCD drive voltage
LCD dividing resistor
RLCD
60
150
kΩ
LCD output voltage
deviationNote (common)
VLCD0 = VLCD
VODC
VODS
IO = ±5 µA
IO = ±1 µA
0
0
±0.2
±0.2
V
V
VLCD1 = VLCD × 2/3
VLCD2 = VLCD × 1/3
LCD output voltage
deviationNote (segment)
Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and
common outputs (VLCDn; n = 0, 1, 2).
(3) 1/2 Bias Method (TA = –10 to +85 °C, VDD = 2.7 to 5.5 V)
Parameter
Symbol
VLCD
Test Conditions
MIN.
2.7
TYP.
100
MAX.
VDD
Unit
V
LCD drive voltage
LCD dividing resistor
RLCD
60
150
kΩ
LCD output voltage
deviationNote (common)
VODC
VODS
IO = ±5 µA
IO = ±1 µA
0
0
±0.2
±0.2
V
V
VLCD0 = VLCD
VLCD1 = VLCD × 1/2
LCD output voltage
deviationNote(segment)
VLCD2 = VLCD1
Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and
common outputs (VLCDn; n = 0, 1, 2).
Data Sheet U12251EJ2V1DS
43
µPD780306Y, 780308Y
LCD CONTROLLER/DRIVER CHARACTERISTICS (AT LOW-VOLTAGE OPERATION)
(1) Static Display Mode (TA = –10 to +85 °C, 2.0 V ≤ VDD < 3.4 V)
Parameteter
LCD drive voltage
LCD dividing resistor
Symbol
VLCD
Test Conditions
MIN.
2.0
TYP.
100
MAX.
VDD
Unit
V
RLCD
60
150
kΩ
LCD output voltage
deviationNote (common)
VODC
IO = ±5 µA
IO = ±1 µA
0
0
±0.2
±0.2
V
V
VLCD0 = VLCD
LCD output voltage
deviationNote (segment)
VODS
Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and
common outputs (VLCDn; n = 0, 1, 2).
(2) 1/3 Bias Method (TA = –10 to +85 °C, 2.0 V ≤ VDD < 3.4 V)
Parameter
Symbol
VLCD
Test Conditions
MIN.
2.0
TYP.
100
MAX.
VDD
Unit
V
LCD drive voltage
LCD dividing resistor
RLCD
60
150
kΩ
LCD output voltage
deviationNote (common)
VODC
IO = ±5 µA
IO = ±1 µA
0
0
±0.2
±0.2
V
V
VLCD0 = VLCD
VLCD1 = VLCD × 2/3
VLCD2 = VLCD × 1/3
LCD output voltage
deviationNote (segment)
VODS
Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and
common outputs (VLCDn; n = 0, 1, 2).
(3) 1/2 Bias Method (TA = –10 to +85 °C, 2.0 V ≤ VDD < 3.4 V)
Parameter
LCD drive voltage
LCD dividing resistor
Symbol
VLCD
Test Conditions
MIN.
2.0
TYP.
100
MAX.
VDD
Unit
V
RLCD
60
150
kΩ
LCD output voltage
deviationNote (common)
VODC
VODS
IO = ±5 µA
IO = ±1 µA
0
0
±0.2
±0.2
V
V
VLCD0 = VLCD
VLCD1 = VLCD × 1/2
LCD output voltage
deviationNote(segment)
VLCD2 = VLCD1
Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and
common outputs (VLCDn; n = 0, 1, 2).
Data Sheet U12251EJ2V1DS
44
µPD780306Y, 780308Y
AC CHARACTERISTICS
(1) Basic Operation (TA = –40 to +85 °C, VDD = 2.0 to 5.5 V)
Parameter
Symbol
Test Conditions
Operating on main system clock
MIN.
0.8
TYP.
MAX.
64
Unit
µs
TCY
VDD = 2.7 to 5.5 V
(fXX = 2.5 MHz)Note 1
2.0
64
µs
Cycle time
(Min. instruction
execution time)
Operating on main system clock
(fXX = 5.0 MHz)Note 2
3.5 ≤ VDD ≤ 5.5 V
2.7 ≤ VDD < 3.5 V
0.4
32
µs
0.8
32
µs
Operating on subsystem clock
fTI00 = tTIH00 + tTIL00
40Note 3
0
122
125
1/tTI00
µs
TI00 input
fTI00
MHz
frequency
4
4
4
TI00 input high/
low-level width
tTIH00,
tTIL00
3.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 3.5 V
2.0 V ≤ VDD < 2.7 V
VDD = 2.7 to 5.5 V
2/fsam+0.1Note
µs
µs
2/fsam+0.2Note
2/fsam+0.5Note
µs
TI01 input
fTI01
0
0
100
50
kHz
kHz
µs
frequency
TI01 input high/
low-level width
TI1, TI2 input
frequency
tTIH01,
tTIL01
fTI1
VDD = 2.7 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
INTP0
10
20
0
µs
4
MHz
kHz
ns
0
275
TI1, TI2 input
high/low-level width
Interrupt request
input high/low-
level width
tTIH,
tTIL
100
1.8
µs
4
4
4
tINTH,
tINTH,
tINTH,
tINTL
3.5 V ≤ VDD ≤ 5.5 V 2/fsam+0.1Note
2.7 V ≤ VDD < 3.5 V 2/fsam+0.2Note
2.0 V ≤ VDD < 2.7 V 2/fsam+0.5Note
µs
µs
µs
INTP1-INTP5, P110-P117
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
10
20
10
20
µs
µs
RESET low level
width
tRST
µs
µs
Notes 1. Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H)
2. Main system clock fXX = fX operation (when OSMS is set to 01H)
3. This is the value when the external clock is used. The value is 114 µs (min.) when the crystal resonator is used.
4. In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register (SCS), selection of fsam is
possible between fXX/2N+1, fXX/32, fXX/64 and fXX/128 (when N = 0 to 4).
Data Sheet U12251EJ2V1DS
45
µPD780306Y, 780308Y
TCY vs VDD (At main system clock fXX = fX/2 operation)
TCY vs VDD (At main system clock fXX = fX operation)
60
60
32
10
10
µ
µ
Guaranteed
Guaranteed
Operation Range
Operation Range
2.0
2.0
1.0
0.8
1.0
0.8
0.4
0.4
0
1
2
2.7
3
4
5
6
0
1
2
3
4
5
6
3.5
Supply Voltage VDD [V]
Supply Voltage VDD [V]
Data Sheet U12251EJ2V1DS
46
µPD780306Y, 780308Y
(2) Serial Interface (TA = –40 to +85 °C, VDD = 2.0 to 5.5 V)
(a) Serial interface channel 0
(i) 3-wire serial I/O mode (SCK0... Internal clock output)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK0 cycle time
tKCY1
2.7 V ≤ VDD < 4.5 V
1600
3200
tKH1,
tKL1
VDD = 4.5 to 5.5 V
tKCY1/2–50
tKCY1/2–100
100
SCK0 high/low-level width
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
SI0 setup time (to SCK0↑)
tSIK1
150
300
SI0 hold time (from SCK0↑)
SO0 output delay time
from SCK0↓
tKSI1
400
tKSO1
C = 100 pFNote
300
ns
Note C is the load capacitance of SCK0, SO0 output line.
(ii) 3-wire serial I/O mode (SCK0...External clock input)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
tKCY2
2.7 V ≤ VDD < 4.5 V
1600
3200
400
SCK0 cycle time
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
tKH2,
tKL2
800
SCK0 high/low-level width
1600
100
tSIK2
tKSI2
SI0 setup time (to SCK0↑)
SI0 hold time (from SCK0↑)
SO0 output delay time
from SCK0↓
400
tKSO2
C = 100 pFNote
300
ns
ns
tR2,
tF2
1000
SCK0 rise, fall time
Note C is the load capacitance of SO0 output line.
Data Sheet U12251EJ2V1DS
47
µPD780306Y, 780308Y
(iii) 2-wire serial I/O mode (SCK0... Internal clock output)
Parameter
Symbol
Test Conditions
VDD = 2.7 to 5.5 V
MIN.
1600
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK0 cycle time
tKCY3
3200
VDD = 2.7 to 5.5 V
VDD = 4.5 to 5.5 V
tKCY3/2–160
tKCY3/2–190
tKCY3/2–50
tKCY3/2–100
300
SCK0 high-level width
SCK0 low-level width
tKH3
tKL3
R = 1 kΩ,
C = 100 pFNote
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
SB0, SB1 setup time
tSIK3
350
(to SCK0↑)
400
SB0, SB1 hold time
(from SCK0↑)
600
ns
ns
tKSI3
SB0, SB1 output delay
time from SCK0↓
300
tKSO3
Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output line.
(iv) 2-wire serial I/O mode (SCK0... External clock input)
Parameter
Symbol
Test Conditions
VDD = 2.7 to 5.5 V
MIN.
1600
3200
650
TYP.
MAX.
Unit
ns
SCK0 cycle time
tKCY4
ns
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
ns
SCK0 high-level width
SCK0 low-level width
tKH4
tKL4
1300
800
ns
ns
1600
ns
SB0, SB1 setup time
(to SCK0↑)
tSIK4
tKSI4
tKSO4
100
ns
ns
SB0, SB1 hold time
(from SCK0↑)
tKCY4/2
SB0, SB1 output delay
time from SCK0↓
R = 1 kΩ,
VDD = 4.5 to 5.5 V
0
0
300
500
ns
ns
C = 100 pFNote
tR4,
tF4
SCK0 rise, fall time
1000
ns
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output line.
Data Sheet U12251EJ2V1DS
48
µPD780306Y, 780308Y
(v) I2C bus mode (SCL...Internal clock output)
Parameter
SCL cycle time
Symbol
Test Conditions
VDD = 2.7 to 5.5 V
MIN.
10
TYP.
MAX.
Unit
µs
µs
ns
ns
ns
ns
ns
ns
tKCY5
20
VDD = 2.7 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 2.7 to 5.5 V
tKCY5–160
tKCY5–190
tKCY5–50
tKCY5–100
200
SCL high-level width
SCL low-level width
tKH5
tKL5
SDA0, SDA1 setup time
tSIK5
tKSI5
tKSO5
(to SCL↑)
300
R = 1 kΩ ,
SDA0, SDA1 hold time
C = 100 pFNote
0
ns
(to SCL↓)
VDD = 4.5 to 5.5 V
0
0
300
500
ns
ns
SDA0, SDA1 output
delay time (from SCL↓)
SDA0, SDA1↓ from SCL↑
or SDA0, SDA1↑ from
SCL↑
200
ns
tKSB
tSBK
tSBH
400
500
ns
ns
SCL↓ from SDA0, SDA1↓
SDA0, SDA1 high-level
width
Note
R and C are the load resistance and load capacitance of SCL, SDA0, and SDA1 output line.
(vi) I2C bus mode (SCL...External clock output)
Parameter
SCL cycle time
Symbol
Test Conditions
MIN.
1000
400
TYP.
MAX.
Unit
ns
tKCY6
tKH5, tKL6
tSIK6
ns
SCL high/low-level width
SDA0, SDA1 setup time
(to SCL↑)
200
0
ns
ns
SDA0, SDA1 hold time
(to SCL↓)
tKSI6
VDD = 4.5 to 5.5 V
0
0
300
500
ns
ns
SDA0, SDA1 output delay
time (from SCL↓)
SDA0, SDA1↓ from SCL↑
or SDA0, SDA1↑ from
SCL↑
R = 1 kΩ ,
C = 100 pFNote
tKSO6
tKSB
200
ns
tSBK
tSBH
400
500
ns
ns
SCL↓ from SDA0, SDA1↓
SDA0, SDA1 high-level
width
tR6, tF6
1000
ns
SCL rise, fall time
Note
R and C are the load resistance and load capacitance of SCL, SDA0, and SDA1 output line.
Data Sheet U12251EJ2V1DS
49
µPD780306Y, 780308Y
(b) Serial interface channel 2
(i) 3-wire serial I/O mode (SCK2... Internal clock output)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK2 cycle time
tKCY7
2.7 V ≤ VDD < 4.5 V
1600
3200
SCK2 high/low-level width
tKH7,
tKL7
VDD = 4.5 to 5.5 V
tKCY7/2–50
tKCY7/2–100
100
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
SI2 setup time (to SCK2↑)
tSIK7
150
300
SI2 hold time (from SCK2↑)
SO2 output delay time
from SCK2↓
tKSI7
400
tKSO1
C = 100 pFNote
300
ns
Note C is the load capacitance of SCK2, SO2 output line.
(ii) 3-wire serial I/O mode (SCK2...External clock input)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
tKCY8
2.7 V ≤ VDD < 4.5 V
1600
3200
400
SCK2 cycle time
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
tKH8,
tKL8
800
SCK2 high/low-level width
1600
100
tSIK8
tKSI8
SI2 setup time (to SCK2↑)
SI2 hold time (from SCK2↑)
SO2 output delay time
from SCK2↓
400
tKSO8
C = 100 pFNote
300
ns
ns
tR8,
tF8
1000
SCK2 rise, fall time
Note C is the load capacitance of SO2 output line.
Data Sheet U12251EJ2V1DS
50
µPD780306Y, 780308Y
(iii) UART mode (Dedicated baud rate generator output)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
MIN.
TYP.
MAX.
78125
39063
19531
Unit
bps
bps
bps
Transfer rate
(iv) UART mode (External clock input)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ASCK cycle time
tKCY9
2.7 V ≤ VDD < 4.5 V
1600
3200
400
ns
ns
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
ns
tKH9,
tKL9
ASCK high/low-level width
800
ns
1600
ns
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
39063
19531
9766
bps
bps
bps
Transfer rate
tR9,
tF9
ASCK rise, fall time
1000
ns
Data Sheet U12251EJ2V1DS
51
µPD780306Y, 780308Y
(c) Serial interface channel 3
(i) 3-wire serial I/O mode (SCK3... Internal clock output)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK3 cycle time
tKCY10
2.7 V ≤ VDD < 4.5 V
1600
3200
tKH10,
tKL10
VDD = 4.5 to 5.5 V
tKCY10/2–50
tKCY10/2–100
100
SCK3 high/low-level width
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
SI3 setup time (to SCK3↑)
tSIK10
150
300
SI3 hold time (from SCK3↑)
SO3 output delay time
from SCK3↓
tKSI10
400
tKSO10
C = 100 pFNote
300
ns
Note C is the load capacitance of SCK3, SO3 output line.
(ii) 3-wire serial I/O mode (SCK3...External clock input)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
SCK3 cycle time
tKCY11
2.7 V ≤ VDD < 4.5 V
1600
3200
400
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
tKH11,
tKL11
SCK3 high/low-level width
800
1600
100
SI3 setup time (to SCK3↑)
SI3 hold time (from SCK3↑)
SO3 output delay time
from SCK3↓
tSIK11
tKSI11
400
tKSO11
C = 100 pFNote
300
ns
ns
tR11,
tF11
SCK3 rise, fall time
1000
Note C is the load capacitance of SO3 output line.
Data Sheet U12251EJ2V1DS
52
µPD780306Y, 780308Y
AC Timing Test Point (Excluding X1, XT1 Input)
0.8 VDD
0.8 VDD
0.2 VDD
Test Points
0.2 VDD
Clock Timing
1/f
X
t
XL
t
XH
V
IH3 (MIN.)
IL3 (MAX.)
X1 Input
V
1/fXT
t
XTL
t
XTH
V
IH4 (MIN.)
XT1 Input
VIL4 (MAX.)
TI Timing
1/fTI00, 01
t
TIL00, tTIL01
t
TIH00, tTIH01
TI00, TI01
1/fTI1
t
TIL1
t
TIH1
TI1, TI2
Data Sheet U12251EJ2V1DS
53
µPD780306Y, 780308Y
Serial Transfer Timing
3-wire serial I/O mode:
tKCYm
tKLm
tKHm
tRn
tFn
SCK0, SCK2,
SCK3
tSIKm
tKSIm
SI0, SI2, SI3
Input data
tKSOm
SO0, SO2, SO3
Output data
m = 1, 2, 7, 8, 10, 11
n = 2, 8, 11
2-wire serial I/O mode:
t
KCY3, 4
t
KL3, 4
t
KH3, 4
t
R4
t
F4
SCK0
t
SIK3, 4
t
KSI3, 4
t
KSO3, 4
SB0, SB1
I2C bus mode:
t
F6
t
R6
t
KCY5, 6
SCL
t
KSB
t
KSB
t
KH5, 6
t
SIK5, 6
t
KL5, 6
t
KSI5, 6
t
SBK
t
KSO5, 6
SDA0, SDA1
t
SBH
t
SBK
Data Sheet U12251EJ2V1DS
54
µPD780306Y, 780308Y
UART mode:
t
KCY9
t
KL9
t
KH9
t
R9
t
F9
ASCK
A/D Converter (TA = –40 to +85 °C, AVDD = VDD = 2.0 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Resolution
Symbol
Test Conditions
MIN.
8
TYP.
8
MAX.
8
Unit
bit
%
Overall errorNote 1
2.7 V ≤ AVREF ≤ 5.5
±0.6
±1.4
200
2.0 V ≤ AVREF < 2.7 V
%
Conversion time
Sampling time
tCONV
tSAMP
VIAN
19.1
12/fXX
AVSS
2.0
µs
µs
V
Analog input voltage
Reference voltage
AVREF-AVSS resistance
AVREF current
AVREF
AVDD
AVREF
RREF
AIREF
V
When not operating A/D conversion
When operating A/D conversionNote 2
When not operating A/D conversionNote 3
4
14
2.5
0.5
kΩ
mA
mA
5.0
1.5
Notes 1. Quantization error (±1/2 LSB) is not included. This is expressed in proportion to the full-scale value.
2. Indicates current flowing to AVREF pin when the CS bit of the A/D converter mode register (ADM) is 1.
3. Indicates current flowing to AVREF pin when the CS bit of the ADM is 0.
Data Sheet U12251EJ2V1DS
55
µPD780306Y, 780308Y
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = –40 to +85 °C)
Parameter
Symbol
Test Conditions
MIN.
1.6
TYP.
MAX.
5.5
Unit
V
Data retention supply voltage
VDDDR
Data retention power supply
current
VDDDR = 1.6 V
IDDDR
Subsystem clock stop and
0.1
10
µA
feed-back resistor disconnected
Release signal set time
tSREL
tWAIT
0
µs
ms
ms
Oscillation stabilization wait
time
Release by RESET
Release by interrupt
217/fX
Note
Note In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register (OSTS), selection
of 212/fXX and 214/fXX to 217/fXX is possible.
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
t
SREL
STOP Instruction Execution
RESET
t
WAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
V
DD
V
DDDR
t
SREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
t
WAIT
Data Sheet U12251EJ2V1DS
56
µPD780306Y, 780308Y
Interrupt Request Input Timing
tINTL
tINTH
INTP0–INTP5
RESET Input Timing
t
RSL
RESET
Data Sheet U12251EJ2V1DS
57
µPD780306Y, 780308Y
11. CHARACTERISTICS CURVE (REFERENCE VALUE)
I
DD vs VDD (f
X
= fXX = 5.0 MHz)
(TA = 25 °C)
10.0
5.0
PCC = 00H
PCC = 01H
PCC = 02H
PCC = 03H
PCC = 04H
PCC = 30H
HALT (X1 oscillation, XT1 oscillation)
1.0
0.5
0.1
0.05
0.01
0.005
0.001
0
2
3
4
5
6
7
8
Supply Voltage VDD (V)
Data Sheet U12251EJ2V1DS
58
µPD780306Y, 780308Y
I
DD vs VDD (f = 5.0 MHz, fXX = 2.5 MHz)
X
(TA = 25 °C)
10.0
5.0
PCC = 00H
PCC = 01H
PCC = 02H
PCC = 03H
PCC = 04H
PCC = 30H
HALT (X1 oscillation, XT1 oscillation)
1.0
0.5
0.1
PCC = B0H
0.05
HALT (X1 stopped, XT1 oscillation)
0.01
0.005
0.001
0
2
3
4
5
6
7
8
Supply Voltage VDD (V)
Data Sheet U12251EJ2V1DS
59
µPD780306Y, 780308Y
12. PACKAGE DRAWINGS
100 PIN PLASTIC LQFP (FINE PITCH) (14×14)
A
B
75
76
51
50
detail of lead end
S
C
D
R
Q
100
1
26
25
F
M
H
I
J
G
K
L
P
M
N
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.08 mm (0.003 inch) of
its true position (T.P.) at maximum material condition.
A
B
16.00±0.20
14.00±0.20
0.630±0.008
+0.009
0.551
–0.008
+0.009
0.551
C
D
14.00±0.20
16.00±0.20
–0.008
0.630±0.008
F
1.00
1.00
0.039
0.039
G
+0.05
0.22
H
0.009±0.002
–0.04
I
0.08
0.003
J
0.50 (T.P.)
0.020 (T.P.)
+0.009
0.039
K
L
1.00±0.20
0.50±0.20
–0.008
+0.008
0.020
–0.009
+0.03
0.17
+0.001
0.007
M
–0.07
–0.003
N
P
Q
0.08
0.003
1.40±0.05
0.10±0.05
0.055±0.002
0.004±0.002
+7°
3°
+7°
3°
R
S
–3°
–3°
1.60 MAX.
0.063 MAX.
S100GC-50-8EU
Remark Dimensions and materials of ES products are the same as those of the mass production product.
Data Sheet U12251EJ2V1DS
60
µPD780306Y, 780308Y
100PIN PLASTIC QFP (14x20)
A
B
51
50
80
81
detail of lead end
C D
S
R
Q
31
30
100
1
F
J
G
M
H
I
P
K
M
N
L
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.
A
23.6±0.4
0.929±0.016
+0.009
0.795
B
20.0±0.2
–0.008
+0.009
0.551
C
14.0±0.2
–0.008
D
F
17.6±0.4
0.8
0.693±0.016
0.031
G
0.6
0.024
+0.004
0.012
H
0.30±0.10
–0.005
I
0.15
0.006
J
0.65 (T.P.)
0.026 (T.P.)
+0.008
0.071
K
L
1.8±0.2
0.8±0.2
–0.009
+0.009
0.031
–0.008
+0.10
0.15
+0.004
0.006
M
–0.05
–0.003
N
P
0.10
0.004
+0.005
0.106
2.7±0.1
–0.004
Q
R
S
0.1±0.1
5°±5°
0.004±0.004
5°±5°
3.0 MAX.
0.119 MAX.
P100GF-65-3BA1-3
Remark Dimensions and materials of ES products are the same as those of the mass production product.
Data Sheet U12251EJ2V1DS
61
µPD780306Y, 780308Y
13. RECOMMENDED SOLDERING CONDITIONS
The µPD780306Y and 780308Y should be soldered and mounted under the conditions recommended in the table below.
For detail of recommended soldering conditions, refer to the information document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact our sales personnel.
Table 13-1. Surface Mounting Type Soldering Conditions
(1) µPD780306YGF-×××-3BA: 100-pin plastic QFP (14 × 20 mm)
µPD780308YGF-×××-3BA: 100-pin plastic QFP (14 × 20 mm)
Recommended
Soldering Method
Infrared reflow
Soldering Conditions
Soldering Symbols
IR35-00-3
Package peak temperature: 235 °C, Duration: 30 sec. max. (at 210 °C or above),
Number of times: Three times max.
VPS
Package peak temperature: 215 °C, Duration: 40 sec. (at 200 °C or above),
VP15-00-3
WS60-00-1
—
Number of times: Three times max.
Wave soldering
Partial heating
Solder bath temperature: 260 °C max., Duration: 10 sec. max., Number of times:
Once, Preheating temperature: 120 °C max. (Package surface temperature)
Pin temperature: 300 °C max., Duration: 3 sec. max. (per device side)
(2) µPD780306YGC-×××-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
µPD780308YGC-×××-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
Recommended
Soldering Method
Infrared reflow
Soldering Conditions
Soldering Symbols
Package peak temperature: 235 °C, Duration: 30 sec. max. (at 210 °C or above),
IR35-00-2
VP15-00-2
—
Number of times: Twice max.
VPS
Package peak temperature: 215 °C, Duration: 40 sec. (at 200 °C or above),
Number of times: Twice max.
Partial heating
Pin temperature: 300 °C max., Duration: 3 sec. max. (per device side)
Caution Use of more than one soldering method should be avoided (except in the case of partial heating).
Data Sheet U12251EJ2V1DS
62
µPD780306Y, 780308Y
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using µPD780306Y/780308Y.
Also refer to (5) Notes on using development tools.
(1) Language Processing Software
RA78K/0
78K/0 series common assembler package
CC78K/0
DF780308
CC78K/0-L
78K/0 series common C compiler package
Device file common to µPD780308 subseries (Part number : µS××××DF78064)
78K/0 series common C compiler library source file
(2) PROM Writing Tools
PG-1500
PROM programmer
PA-78P0308GC
PA-78P0308GF
PA-78P0308KL-T
Programmer adapters connected to PG-1500
PG-1500 control program
PG-1500 controller
(3) Debugging Tools
• When in-circuit emulator IE-78K0-NS is used
IE-78K0-NS
IE-70000-MC-PS-B
In-circuit emulator common to 78K/0 series
Power supply unit for IE-78K0-NS
IE-70000-98-IF-C
Interface adapter used when PC-9800 series (except notebook type) is used as host
machine
IE-70000-CD-IF
PC card and interface cable used when notebook type PC-9800 series is used as host
machine
IE-70000-PC-IF-C
IE-780308-NS-EM1
NP-100GC
Interface adapter used when IBM PC/ATTM compatible machine is used as host machine
Emulation board to emulate µPD780308 subseries
Emulation probe for 100-pin plastic LQFP (GC-3EU type)
NP-100GF
Emulation probe for 100-pin plastic QFP (GF-3BA type)
TGC-100SDW
Conversion adapter to connect NP-100GC and a target system board made to be mounted
on 100-pin plastic LQFP (GC-8EU type)
EV-9200GF-100
ID78K0-NS
SM78K0
Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type)
Integrated debugger for IE-78K0-NS
78K/0 series common system simulator
DF780308
µPD780308 subseries device file (Part number: µS××××DF78064)
Data Sheet U12251EJ2V1DS
63
µPD780306Y, 780308Y
• When in-circuit emulator IE-78001-R-A is used
IE-78001-R-A
IE-70000-98-IF-B
In-circuit emulator common to 78K/0 series
Interface adapter used when PC-9800 series (except notebook type) is used as host machine
IE-70000-98-IF-C
IE-70000-PC-IF-B
IE-70000-PC-IF-C
Interface adapter used when IBM PC/AT compatible machine is used as host machine
IE-78000-R-SV3
Interface adapter and cable used when EWS is used as host machine
IE-780308-NS-EM1
IE-780308-R-EM
Emulation board to emulate µPD780308 subseries
IE-78K0-R-EX1
NP-100GC
Emulation probe conversion board necessary when using IE-780308-NS-EM1 on IE-78001-R-A
Emulation probe for 100-pin plastic LQFP (GC-3EU type)
NP-100GF
Emulation probe for 100-pin plastic QFP (GF-3BA type)
TGC-100SDW
Conversion adapter to connect NP-100GC and a target system board made to be mounted
on 100-pin plastic LQFP (GC-8EU type)
EV-9200GF-100
ID78K0
Socket mounted on board of target system created for 100-pin plastic QFP (GF-3BA type)
Integrated debugger for IE-78001-R-A
SM78K0
System simulator common to 78K/0 series
DF780308
Device file for µPD780308 subseries (Part number: µS××××DF78064)
(4) Real-Time OS
RX78K/0
MX78K0
78K/0 series real-time OS
78K/0 series OS
Data Sheet U12251EJ2V1DS
64
µPD780306Y, 780308Y
(5) Notes on using development tools
•
•
•
•
The package name of DF780308 is the DF78064.
Use ID78K0-NS, ID78K0, and SM78K0 in combination with DF780308.
Use CC78K/0 and RX78K/0 in combination with RA78K/0 and DF780308.
NP-100GC and NP-100GF are products of Naito Densei Machida Mfg. Co., Ltd. (TEL (044) 822-3813). Consult your
NEC distributor when purchasing these products.
•
TGC-100SDW is a product of Tokyo Eletech Corp.
Reference: Daimaru Kogyo Ltd. Electronics Dept. (TEL: Tokyo 03-3820-7112)
Electronics 2nd Dept. (TEL: Osaka 06-244-6672)
•
•
For development tools made by third parties, refer to Single-chip Microcontroller Development Tool Selection
Guide (U11069E).
The host machine corresponding to each software package is as follows:
Host Machine
[OS]
PC
EWS
PC-9800 series [WindowsTM
]
HP9000 series 700TM [HP-UXTM
]
IBM PC/AT Compatible Machines
[Japanese/English Windows]
SPARCstationTM [SunOSTM, SolarisTM
]
Software
NEWS (RISC)TM [NEWS-OSTM
]
Note
Note
Note
RA78K/0
CC78K/0
PG-1500 controller
ID78K0-NS
ID78K0
—
—
SM78K0
—
Note
Note
RX78K/0
MX78K0
Note
This software is based on DOS.
Data Sheet U12251EJ2V1DS
65
µPD780306Y, 780308Y
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document Name
µPD780308, 780308Y Subseries User’s Manual
µPD780306, 780308 Data Sheet
Document No.
U11377E
U11105E
µPD780306Y, 780308Y Data Sheet
µPD78P0308 Data Sheet
This document
U11776E
µPD78P0308Y Data Sheet
U11832E
78K/0 Series User’s Manual (Instruction)
78K/0 Series Application Note
U12326E
Basic (III)
U10182E
Development Tool Related Documents (User’s Manual) (1/2)
Document Name
Document No.
U11802E
RA78K0 Assembler Package
CC78K0 C Compiler
Operation
Assembly language
U11801E
Structured assembly language
Operation
U11789E
U11517E
U11518E
U11940E
U13731E
Planned
Language
PG-1500 PROM Programmer
IE-78K0-NS In-circuit Emulator
IE-78K0-R-EX1 In-circuit Emulator
IE-780308-NS-EM1 Emulation Board
IE-780308-R-EM Emulation Board
EP-78064 Emulation Probe
U13304E
U11362E
EEU-1469
Caution The above related documents are subject to change without notice. For design purpose, etc.,
be sure to use the latest documents.
Data Sheet U12251EJ2V1DS
66
µPD780306Y, 780308Y
Development Tool Related Documents (User’s Manual) (2/2)
Document Name
Document No.
U14611E
SM78K0S, SM78K0 System Sumilator Ver. 2.10 or lator Windows Based
SM78K Series System Simulator Ver. 2.10 or lator
Operation
External part user open
interface specifications
Planned
ID78K0-NS Integrated Debugger Ver. 2.00 or lator Windows Based
Operation
U14379E
U14910E
U11539E
U11649E
ID78K0-NS, ID78K0S-NS Integrated Debugger Ver. 2.20 or lator Windows Based Operation
ID78K0 Integrated Debugger Windows Based
Reference
Guide
Embedded Software Related Documents (User’s Manual)
Document Name
Document No.
U11537E
78K/0 Series Real-Time OS
Fundamentals
Installation
U11536E
78K/0 Series OS MX78K0
Fundamental
U12257E
Other Related Documents
Document Name
Document No.
X13769X
SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM)
Semiconductor Device Mounting Technology Manual
Quality Grades on Semiconductor Devices
C10535E
C11531E
C10983E
C11892E
NEC Semiconductor Device Reliability and Quality Control
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Caution The above related documents are subject to change without notice. For design purpose, etc.,
be sure to use the latest documents.
Data Sheet U12251EJ2V1DS
67
µPD780306Y, 780308Y
[MEMO]
Data Sheet U12251EJ2V1DS
68
µPD780306Y, 780308Y
[MEMO]
Data Sheet U12251EJ2V1DS
69
µPD780306Y, 780308Y
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet U12251EJ2V1DS
70
µPD780306Y, 780308Y
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.
Benelux Office
Hong Kong
Eindhoven, The Netherlands
Tel: 040-2445845
Tel: 2886-9318
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 01-30-67 58 99
Fax: 0211-65 03 490
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore
Tel: 65-253-8311
NEC Electronics (France) S.A.
Madrid Office
Madrid, Spain
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 65-250-3583
Tel: 91-504-2787
Fax: 01908-670-290
Fax: 91-504-2860
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: 02-66 75 41
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Fax: 02-2719-5951
Fax: 02-66 75 42 99
Tel: 08-63 80 820
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP Brasil
Tel: 55-11-6462-6810
Fax: 55-11-6462-6829
Fax: 08-63 80 388
J00.7
Data Sheet U12251EJ2V1DS
71
µPD780306Y, 780308Y
Some of related document may be preliminary, but is not marked as such.
FIP and IEBus are trademarks of NEC Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or
other countries.
PC/AT and PC DOS are trademarks of IBM Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS and Solaris are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
•
The information in this document is current as of December, 1998. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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