UPD789830_技术文档

User’s Manual

µPD789830 Subseries

8-Bit Single-Chip Microcontrollers

µPD789830

µPD78F9831

Document No. U13679EJ2V0UD00 (2nd edition)

Date Published June 2002 N CP(K)

1998

©

Printed in Japan

[MEMO]

2

User's Manual U13679EJ2V0UD

NOTES FOR CMOS DEVICES

1

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V^DDor GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

EEPROM and FIP are trademarks of NEC Corporation.

Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the

United States and/or other countries.

PC/AT is a trademark of International Business Machines Corporation.

HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun-Microsystems, Inc.

3

User's Manual U13679EJ2V0UD

The export of these products from Japan is regulated by the Japanese government. The export of some or all of these

products may be prohibited without governmental license. To export or re-export some or all of these products from a

country other than Japan may also be prohibited without a license from that country. Please call an NEC sales

representative.

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•

The information in this document is current as of March, 2002. The information is subject to change

without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data

books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products

and/or types are available in every country. Please check with an NEC sales representative for

availability and additional information.

•

No part of this document may be copied or reproduced in any form or by any means without prior

written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.

NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of

third parties by or arising from the use of NEC semiconductor products listed in this document or any other

liability arising from the use of such products. No license, express, implied or otherwise, is granted under any

patents, copyrights or other intellectual property rights of NEC or others.

•

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of customer's equipment shall be done under the full

responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third

parties arising from the use of these circuits, software and information.

While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers

agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize

risks of damage to property or injury (including death) to persons arising from defects in NEC

semiconductor products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment, and anti-failure features.

NEC semiconductor products are classified into the following three quality grades:

"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products

developed based on a customer-designated "quality assurance program" for a specific application. The

recommended applications of a semiconductor product depend on its quality grade, as indicated below.

Customers must check the quality grade of each semiconductor product before using it in a particular

application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's

data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not

intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness

to support a given application.

(Note)

(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.

(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for

NEC (as defined above).

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Regional Information

Some information contained in this document may vary from country to country. Before using any NEC

product in your application, pIease contact the NEC office in your country to obtain a list of authorized

representatives and distributors. They will verify:

•

Device availability

Ordering information

Product release schedule

Availability of related technical literature

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

•

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California

Tel: 408-588-6000

800-366-9782

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

• Filiale Italiana

Milano, Italy

Tel: 02-66 75 41

Fax: 02-66 75 42 99

Fax: 2886-9022/9044

Fax: 408-588-6130

800-729-9288

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-528-0303

Fax: 02-528-4411

• Branch The Netherlands

Eindhoven, TheNetherlands

Tel: 040-244 58 45

NEC do Brasil S.A.

Electron Devices Division

Guarulhos-SP, Brasil

Tel: 11-6462-6810

Fax: 040-244 45 80

• Branch Sweden

Taeby, Sweden

Tel: 08-63 80 820

Fax: 08-63 80 388

NEC Electronics Shanghai, Ltd.

Shanghai, P.R. China

Tel: 021-6841-1138

Fax: 11-6462-6829

NEC Electronics (Europe) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 01

Fax: 021-6841-1137

• United Kingdom Branch

Milton Keynes, UK

Tel: 01908-691-133

Fax: 01908-670-290

Fax: 0211-65 03 327

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-2719-2377

• Sucursal en España

Madrid, Spain

Fax: 02-2719-5951

Tel: 091-504 27 87

Fax: 091-504 28 60

NEC Electronics Singapore Pte. Ltd.

Novena Square, Singapore

Tel: 253-8311

• Succursale Française

Vélizy-Villacoublay, France

Tel: 01-30-67 58 00

Fax: 250-3583

Fax: 01-30-67 58 99

J02.4

5

User's Manual U13679EJ2V0UD

Major Revisions in This Edition

Page

p. 31

Description

Addition of description on timer to 1.7 Overview of Functions

Addition of description on pin processing to 2.3.14 V^PP

p. 38

p. 41

Modification of Table 2-1 Types of Pin I/O Circuits and Recommended Connection of

Unused Pins (µPD789830)

p. 42

Modification of Table 2-2 Types of Pin I/O Circuits and Recommended Connection of

Unused Pins (µPD78F9831)

p. 87

Addition of Note to 5.3 (2) Suboscillation mode register (SCKM)

Addition of Caution to 6.2 (1) 16-bit compare register 40 (CR40)

Addition of Caution to 6.4.1 Operation as interval timer

p. 97

p. 99

p. 105

p. 117

p. 180

p. 198

p. 211

p. 212

p. 213

p. 204

Addition of description to 7.3 8-Bit Timer 00 Control Registers

Modification of Caution in 9.3 (2) Watchdog timer mode register (WDTM)

Overall modification of descriptions in CHAPTER 16 µPD78F9831

Addition of CHAPTER 18 ELECTRICAL SPECIFICATIONS

Addition of CHAPTER 19 PACKAGE DRAWINGS

Addition of CHAPTER 20 RECOMMENDED SOLDERING CONDITIONS

Overall modification of descriptions in APPENDIX A DEVELOPMENT TOOLS

Addition of APPENDIX C REVISION HISTORY

p. 205 in 1st

edition

Deletion of APPENDIX B EMBEDDED SOFTWARE

The mark

shows major revised points.

6

User's Manual U13679EJ2V0UD

INTRODUCTION

Target Readers

This manual is intended for users who wish to understand the functions of the

µPD789830 Subseries and to design and develop application systems and programs

using these microcontrollers.

• µPD789830 Subseries: µPD789830 and µPD78F9831

Purpose

This manual is intended to give users an understanding of the functions described in

the Organization below.

Organization

The µPD789830 Subseries User’s Manual is divided into two parts: this manual and

instructions (common to the 78K/0S Series).

µPD789830 Subseries

User's Manual

78K/0S Series

User's Manual

Instructions

(This manual)

• Pin functions

• CPU functions

• Internal block functions

• Interrupt functions

• Instruction set

• Explanation of each

instruction

• Other on-chip peripheral functions

• Electrical specifications

How to Read This Manual

It is assumed that the reader of this manual has general knowledge in the fields of

electrical engineering, logic circuits, and microcontrollers.

To understand the functions in general:

→ Read this manual in the order of the contents.

How to interpret the register format:

→ For the bit whose number is enclosed with < >, its bit name is defined as a

reserved word in the RA78K0S, and in the CC78K0S, already defined in the

header file named sfrbit.h.

When you know a register name and want to confirm its details:

→ Read APPENDIX B REGISTER INDEX.

To know the µPD789830 Subseries instruction functions in detail:

→ Refer to 78K/0S Series Instruction User's Manual (U11047E).

To know the electrical specifications of the µPD789830 Subseries

→ Refer to CHAPTER 18 ELECTRICAL SPECIFICATIONS.

Conventions

Data significance:

Higher digits on the left and lower digits on the right

Active low representation: ××× (overscore over pin or signal name)

Note:

Footnote for item marked with Note in the text

Information requiring particular attentions

Supplementary information

Caution:

Remark:

Numerical representation: Binary ... ×××× or ××××B

Decimal ... ××××

Hexadecimal ... ××××H

7

User's Manual U13679EJ2V0UD

Other Related Documents

Document Name

SEMICONDUCTOR SELECTION GUIDE - Products & Packages -

Semiconductor Device Mounting Technology Manual

Document No.

X13769E

C10535E

Quality Grades on NEC Semiconductor Devices

C11531E

NEC Semiconductor Device Reliability/Quality Control System

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)

C10983E

C11892E

Caution The related documents listed above are subject to change without notice. Be sure to use the

latest version of each document for designing.

8

User's Manual U13679EJ2V0UD

CONTENTS

CHAPTER 1 GENERAL...........................................................................................................................20

1.1 Features.......................................................................................................................................20

1.2 Applications................................................................................................................................20

1.3 Ordering Information .................................................................................................................21

1.4 Pin Configuration (Top View)....................................................................................................22

1.5 78K/0Series Lineup ....................................................................................................................27

1.6 Block Diagram ............................................................................................................................30

1.7 Overview of Functions...............................................................................................................31

CHAPTER 2 PIN FUNCTIONS ...............................................................................................................32

2.1 Pin Function List ........................................................................................................................32

2.2 Description of Pin Functions (µPD789830)..............................................................................35

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

2.2.7

2.2.8

2.2.9

2.2.10

2.2.11

2.2.12

2.2.13

P00 to P07 (Port 0)......................................................................................................................35

P10, P11 (Port 1).........................................................................................................................35

P20 to P26 (Port 2)......................................................................................................................35

P30 to P34 (Port 3)......................................................................................................................36

P50 to P57 (Port 5)......................................................................................................................36

S0 to S31.....................................................................................................................................36

COM0 to COM15.........................................................................................................................36

RESET ........................................................................................................................................36

X1, X2..........................................................................................................................................36

XT1, XT2 .....................................................................................................................................36

V^DD0, V^DD1....................................................................................................................................36

V^SS0, V^SS1.....................................................................................................................................36

IC0...............................................................................................................................................37

2.3 Description of Pin Functions (µPD78F9831)............................................................................38

2.3.1

P00 to P07 (Port 0)......................................................................................................................38

P10 to P17 (Port 1)......................................................................................................................38

P20 to P26 (Port 2)......................................................................................................................38

P30 to P34 (Port 3)......................................................................................................................38

P40, P41 (Port 4).........................................................................................................................39

P50 to P57 (Port 5)......................................................................................................................39

S0 to S31.....................................................................................................................................39

COM0 to COM15.........................................................................................................................39

RESET ........................................................................................................................................39

X1, X2..........................................................................................................................................39

XT1, XT2 .....................................................................................................................................39

V^DD0, V^DD1....................................................................................................................................39

V^SS0, V^SS1.....................................................................................................................................39

V^PP...............................................................................................................................................40

IC0...............................................................................................................................................40

IC2...............................................................................................................................................40

2.3.2

2.3.3

2.3.4

2.3.5

2.3.6

2.3.7

2.3.8

2.3.9

2.3.10

2.3.11

2.3.12

2.3.13

2.3.14

2.3.15

2.3.16

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User's Manual U13679EJ2V0UD

2.3.17

NC ...............................................................................................................................................40

2.4 Pin I/O Circuits and Recommended Connection of Unused Pins.........................................41

CHAPTER 3 CPU ARCHITECTURE ......................................................................................................45

3.1 Memory Space............................................................................................................................45

3.1.1

3.1.2

3.1.3

3.1.4

Internal program memory space .................................................................................................47

Internal data memory space........................................................................................................48

Special function register (SFR) area ...........................................................................................48

Data memory addressing ............................................................................................................49

3.2 Processor Registers ..................................................................................................................51

3.2.1

3.2.2

3.2.3

Control registers..........................................................................................................................51

General-purpose registers...........................................................................................................54

Special function register (SFR) ...................................................................................................55

3.3 Instruction Address Addressing ..............................................................................................58

3.3.1

3.3.2

3.3.3

3.3.4

Relative addressing.....................................................................................................................58

Immediate addressing.................................................................................................................59

Table indirect addressing............................................................................................................60

Register addressing ....................................................................................................................60

3.4 Operand Address Addressing ..................................................................................................61

3.4.1

3.4.2

3.4.3

3.4.4

3.4.5

3.4.6

3.4.7

Direct addressing ........................................................................................................................61

Short direct addressing ...............................................................................................................62

Special function register (SFR) addressing.................................................................................63

Register addressing ....................................................................................................................64

Register indirect addressing........................................................................................................65

Based addressing .......................................................................................................................66

Stack addressing.........................................................................................................................66

CHAPTER 4 PORT FUNCTIONS ...........................................................................................................67

4.1 Port Functions............................................................................................................................67

4.2 Port Configuration......................................................................................................................70

4.2.1

4.2.2

4.2.3

4.2.4

4.2.5

4.2.6

4.2.7

Port 0...........................................................................................................................................71

Port 1: µPD789830.....................................................................................................................72

Port 1: µPD78F9831...................................................................................................................73

Port 2...........................................................................................................................................74

Port 3...........................................................................................................................................77

Port 4: µPD78F9831...................................................................................................................78

Port 5...........................................................................................................................................79

4.3 Port Function Control Registers...............................................................................................80

4.4 Operation of Port Functions .....................................................................................................83

4.4.1

4.4.2

4.4.3

Writing to I/O port ........................................................................................................................83

Reading from I/O port..................................................................................................................83

Arithmetic operation of I/O port ...................................................................................................83

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User's Manual U13679EJ2V0UD

CHAPTER 5 CLOCK GENERATOR.......................................................................................................84

5.1 Clock Generator Functions .......................................................................................................84

5.2 Clock Generator Configuration.................................................................................................84

5.3 Clock Generator Control Registers ..........................................................................................86

5.4 System Clock Oscillators ..........................................................................................................89

5.4.1

5.4.2

5.4.3

5.4.4

Main system clock oscillator........................................................................................................89

Subsystem clock oscillator ..........................................................................................................90

Frequency divider........................................................................................................................92

When no subsystem clocks are used..........................................................................................92

5.5 Clock Generator Operation .......................................................................................................93

5.6 Changing Setting of System Clock and CPU Clock................................................................94

5.6.1

5.6.2

Time required for switching between system clock and CPU clock ............................................94

Switching between system clock and CPU clock........................................................................95

CHAPTER 6 16-BIT TIMER 40 ..............................................................................................................96

6.1 16-Bit Timer 40 Functions .........................................................................................................96

6.2 16-Bit Timer 40 Configuration...................................................................................................96

6.3 16-Bit Timer 40 Control Register ..............................................................................................98

6.4 16-Bit Timer 40 Operation..........................................................................................................99

6.4.1

6.4.2

Operation as interval timer ..........................................................................................................99

Operation as free-running timer ................................................................................................100

6.5 Notes on Using 16-Bit Timer 40 ..............................................................................................102

CHAPTER 7 8-BIT TIMER 00 ..............................................................................................................103

7.1 8-Bit Timer 00 Functions .........................................................................................................103

7.2 8-Bit Timer 00 Configuration...................................................................................................103

7.3 8-Bit Timer 00 Control Registers ............................................................................................105

7.4 8-Bit Timer 00 Operation..........................................................................................................106

7.4.1

Operation as interval timer ........................................................................................................106

7.5 Notes on Using 8-Bit Timer 00 ................................................................................................108

CHAPTER 8 WATCH TIMER................................................................................................................109

8.1 Watch Timer Functions............................................................................................................109

8.2 Watch Timer Configuration .....................................................................................................110

8.3 Watch Timer Control Register.................................................................................................111

8.4 Watch Timer Operation............................................................................................................112

8.4.1

8.4.2

Operation as watch timer ..........................................................................................................112

Operation as interval timer ........................................................................................................112

CHAPTER 9 WATCHDOG TIMER........................................................................................................114

9.1 Watchdog Timer Functions.....................................................................................................114

9.2 Watchdog Timer Configuration...............................................................................................115

9.3 Watchdog Timer Control Registers........................................................................................116

9.4 Watchdog Timer Operation .....................................................................................................118

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User's Manual U13679EJ2V0UD

9.4.1

9.4.2

Operation as watchdog timer ....................................................................................................118

Operation as interval timer ........................................................................................................119

CHAPTER 10 CLOCK OUTPUT CIRCUIT..........................................................................................120

10.1 Clock Output Circuit Functions..............................................................................................120

10.2 Clock Output Circuit Configuration........................................................................................120

10.3 Clock Output Circuit Control Registers.................................................................................121

10.4 Clock Output Circuit Operation ..............................................................................................123

10.4.1

10.4.2

PCL output operation ................................................................................................................123

Buzzer output operation............................................................................................................124

CHAPTER 11 SERIAL INTERFACE UART00.....................................................................................125

11.1 Serial Interface UART00 Functions ........................................................................................125

11.2 Serial Interface UART00 Configuration..................................................................................126

11.3 Serial Interface UART00 Control Registers ...........................................................................127

11.4 Serial Interface UART00 Operation.........................................................................................131

11.4.1

11.4.2

Operation stop mode.................................................................................................................131

Asynchronous serial interface (UART) mode............................................................................132

CHAPTER 12 LCD CONTROLLER/DRIVER .......................................................................................143

12.1 LCD Controller/Driver Functions............................................................................................143

12.2 LCD Controller/Driver Configuration......................................................................................143

12.3 LCD Controller/Driver Control Registers...............................................................................145

12.4 Setting Up LCD Controller/Driver ...........................................................................................148

12.5 LCD Display Data Memory.......................................................................................................148

12.6 Supplying LCD Drive Voltage..................................................................................................151

12.7 LCD Display ..............................................................................................................................152

CHAPTER 13 INTERRUPT FUNCTIONS.............................................................................................153

13.1 Interrupt Function Types.........................................................................................................153

13.2 Interrupt Sources and Configuration .....................................................................................154

13.3 Interrupt Function Control Registers.....................................................................................156

13.4 Interrupt Servicing Operation .................................................................................................163

13.4.1

13.4.2

13.4.3

13.4.4

Non-maskable interrupt request acknowledgement operation..................................................163

Maskable interrupt acknowledgement operation.......................................................................165

Multiple interrupt servicing ........................................................................................................166

Pending interrupt request..........................................................................................................168

CHAPTER 14 STANDBY FUNCTION ..................................................................................................169

14.1 Standby Function and Configuration.....................................................................................169

14.1.1

14.1.2

Standby function .......................................................................................................................169

Standby function control register...............................................................................................170

14.2 Standby Function Operation...................................................................................................171

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User's Manual U13679EJ2V0UD

14.2.1

14.2.2

HALT mode ...............................................................................................................................171

STOP mode...............................................................................................................................174

CHAPTER 15 RESET FUNCTION........................................................................................................177

CHAPTER 16 µPD78F9831 ...................................................................................................................180

16.1 Flash Memory Programming...................................................................................................181

16.1.1

16.1.2

16.1.3

16.1.4

16.1.5

Selecting communication mode ................................................................................................181

Function of flash memory programming....................................................................................182

Flashpro III connection..............................................................................................................183

Setting with Flashpro III.............................................................................................................184

On-board pin connections .........................................................................................................185

CHAPTER 17 INSTRUCTION SET.......................................................................................................188

17.1 Operation...................................................................................................................................188

17.1.1

17.1.2

17.1.3

Operand identifiers and description methods............................................................................188

Description of "Operation" column ............................................................................................189

Description of "flag operation" column ......................................................................................189

17.2 Operation List...........................................................................................................................190

17.3 Instructions Listed by Addressing Type................................................................................195

CHAPTER 18 ELECTRICAL SPECIFICATIONS .................................................................................198

CHAPTER 19 PACKAGE DRAWINGS ................................................................................................211

CHAPTER 20 RECOMMENDED SOLDERING CONDITIONS ...........................................................212

APPENDIX A DEVELOPMENT TOOLS...............................................................................................213

A.1 Software Package.....................................................................................................................215

A.2 Language Processing Software..............................................................................................215

A.3 Control Software ......................................................................................................................216

A.4 Flash Memory Writing Tools ...................................................................................................217

A.5 Debugging Tools (Hardware) ..................................................................................................217

A.6 Debugging Tools (Software) ...................................................................................................218

A.7 Package Drawings of Conversion Adapter (TGC-100SDW).................................................219

APPENDIX B REGISTER INDEX..........................................................................................................220

B.1 Register Name Index (Alphabetic Order) ...............................................................................220

B.2 Register Symbol Index (Alphabetic Order)............................................................................222

APPENDIX C REVISION HISTORY......................................................................................................224

13

User's Manual U13679EJ2V0UD

LIST OF FIGURES (1/4)

Figure No.

2-1

Title

Page

Pin I/O Circuits....................................................................................................................................43

3-1

3-2

3-3

3-4

3-5

3-6

3-7

3-8

3-9

3-10

Memory Map (µPD789830) ................................................................................................................45

Memory Map (µPD78F9831) ..............................................................................................................46

Data Memory Addressing (µPD789830).............................................................................................49

Data Memory Addressing (µPD78F9831)...........................................................................................50

Program Counter Configuration..........................................................................................................51

Program Status Word Configuration...................................................................................................51

Stack Pointer Configuration................................................................................................................53

Data to Be Saved to Stack Memory....................................................................................................53

Data to Be Restored from Stack Memory...........................................................................................53

General-Purpose Register Configuration ...........................................................................................54

4-1

Port Types (µPD789830)....................................................................................................................67

Port Types (µPD78F9831)..................................................................................................................68

Block Diagram of P00 to P07 .............................................................................................................71

Block Diagram of P10 and P11 (µPD789830)....................................................................................72

Block Diagram of P10 to P17 (µPD78F9831).....................................................................................73

Block Diagram of P20, P21, and P26.................................................................................................74

Block Diagram of P22.........................................................................................................................75

Block Diagram of P23 and P25 ..........................................................................................................75

Block Diagram of P24.........................................................................................................................76

Block Diagram of P30 to P34 .............................................................................................................77

Block Diagram of P40 and P41 (µPD78F9831)..................................................................................78

Block Diagram of P50 to P57 .............................................................................................................79

Format of Port Mode Register (µPD789830)......................................................................................81

Format of Port Mode Register (µPD78F9831)....................................................................................81

Format of Pull-Up Resistor Option Register 0 ....................................................................................82

4-2

4-3

4-4

4-5

4-6

4-7

4-8

4-9

4-10

4-11

4-12

4-13

4-14

4-15

5-1

5-2

5-3

5-4

5-5

5-6

5-7

5-8

Block Diagram of Clock Generator.....................................................................................................85

Format of Processor Clock Control Register......................................................................................86

Format of Suboscillation Mode Register.............................................................................................87

Format of Subclock Control Register..................................................................................................88

External Circuit of Main System Clock Oscillator ...............................................................................89

External Circuit of Subsystem Clock Oscillator ..................................................................................90

Example of Incorrect Resonator Connection......................................................................................91

Switching Between System Clock and CPU Clock.............................................................................95

14

User's Manual U13679EJ2V0UD

LIST OF FIGURES (2/4)

Figure No.

Title

Page

6-1

6-2

6-3

6-4

6-5

6-6

6-7

Block Diagram of 16-Bit Timer 40.......................................................................................................97

Format of Timer 40 Control Register ..................................................................................................98

Settings of Timer 40 Control Register at Interval Timer Operation.....................................................99

Operating Timing of 16-Bit Timer 40 Used as Interval Timer ...........................................................100

Settings of Timer 40 Control Register at Free-Running Timer Operation.........................................100

Operating Timing of 16-Bit Timer 40 Used as Free-Running Timer .................................................101

Start Timing of 16-Bit Timer Counter 40...........................................................................................102

7-1

7-2

7-3

7-4

7-5

Block Diagram of 8-Bit Timer 00.......................................................................................................104

8-Bit Timer Mode Control Register 00 Format..................................................................................105

Settings of 8-Bit Timer Mode Control Register 00 in Interval Timer Operation.................................106

Operating Timing of 8-Bit Timer 00 Used as Interval Timer .............................................................107

Start Timing of 8-Bit Timer Counter 00.............................................................................................108

8-1

8-2

8-3

Block Diagram of Watch Timer.........................................................................................................109

Format of Watch Timer Mode Control Register................................................................................111

Watch Timer/Interval Timer Operation Timing..................................................................................113

9-1

9-2

9-3

Block Diagram of Watchdog Timer...................................................................................................115

Format of Timer Clock Selection Register 2.....................................................................................116

Format of Watchdog Timer Mode Register.......................................................................................117

10-1

10-2

10-3

10-4

10-5

10-6

Block Diagram of Clock Output Circuit .............................................................................................120

Format of PCL/BUZ Control Register 0 ............................................................................................121

Format of Port Mode Register 2 .......................................................................................................122

Setting of PCL/BUZ Control Register 0 for PCL Output Operation...................................................123

PCL Output Timing ...........................................................................................................................123

Setting of PCL/BUZ Control Register 0 for Buzzer Output Operation...............................................124

11-1

11-2

11-3

11-4

11-5

11-6

11-7

11-8

11-9

Block Diagram of Serial Interface UART00 ......................................................................................125

Format of Asynchronous Serial Interface Mode Register 00............................................................128

Format of Asynchronous Serial Interface Status Register 00...........................................................129

Format of Baud Rate Generator Control Register 00 .......................................................................130

Permissible Error in Baud Rate with Sampling Error Considered (Where k = 0)..............................137

Asynchronous Serial Interface Transmission/Reception Data Format .............................................138

Asynchronous Serial Interface Transmission Completion Interrupt Request Timing........................140

Asynchronous Serial Interface Reception Completion Interrupt Request Timing.............................141

Receive Error Timing........................................................................................................................142

15

User's Manual U13679EJ2V0UD

LIST OF FIGURES (3/4)

Figure No.

Title

Page

12-1

12-2

12-3

12-4

12-5

12-6

12-7

12-8

Block Diagram of LCD Controller/Driver...........................................................................................144

Format of LCD20 Mode Register......................................................................................................145

Format of Alternate Port Function Switching Register......................................................................146

Format of LCD20 Clock Selection Register......................................................................................147

Relationships Between LCD Display Data Memory Contents and Segment/Common Outputs.......148

Example LCD Drive Waveform Between Segment Signal and Common Signal..............................150

Connection of Power Supply for LCD Drive......................................................................................151

Example of Connecting LCD Panel..................................................................................................152

13-1

Basic Configuration of Interrupt Function .........................................................................................155

Format of Interrupt Request Flag Register (µPD789830).................................................................157

Format of Interrupt Request Flag Register (µPD78F9831)...............................................................157

Format of Interrupt Mask Flag Register (µPD789830)......................................................................158

Format of Interrupt Mask Flag Register (µPD78F9831) ...................................................................158

Format of External Interrupt Mode Register 0 ..................................................................................159

Format of External Interrupt Mode Register 1 (µPD78F9831)..........................................................160

Program Status Word Configuration.................................................................................................161

Format of Key Return Mode Register 00..........................................................................................161

Block Diagram of Falling Edge Detector...........................................................................................162

Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgement........................164

Timing of Non-Maskable Interrupt Request Acknowledgement........................................................164

Acknowledgement of Non-Maskable Interrupt Request ...................................................................164

Interrupt Request Acknowledgement Program Algorithm.................................................................165

Interrupt Request Acknowledgement Timing (Example of MOV A,r)................................................166

Interrupt Request Acknowledgement Timing (When Interrupt Request Flag Is Generated at the

Last Clock During Instruction Execution)..........................................................................................166

Example of Multiple Interrupt............................................................................................................167

13-2

13-3

13-4

13-5

13-6

13-7

13-8

13-9

13-10

13-11

13-12

13-13

13-14

13-15

13-16

13-17

14-1

14-2

14-3

14-4

14-5

Format of Oscillation Stabilization Time Selection Register.............................................................170

Releasing HALT Mode by Interrupt ..................................................................................................172

Releasing HALT Mode by RESET Input...........................................................................................173

Releasing STOP Mode by Interrupt..................................................................................................175

Releasing STOP Mode by RESET Input ..........................................................................................176

15-1

15-2

15-3

15-4

Block Diagram of Reset Function.....................................................................................................177

Reset Timing by RESET Input..........................................................................................................178

Reset Timing by Overflow in Watchdog Timer .................................................................................178

Reset Timing by RESET Input in STOP Mode .................................................................................178

16

User's Manual U13679EJ2V0UD

LIST OF FIGURES (4/4)

Figure No.

Title

Page

16-1

16-2

16-3

16-4

16-5

16-6

Format of Communication Mode Selection.......................................................................................181

Flashpro III Connection Example......................................................................................................183

V^PPPin Connection Example............................................................................................................185

Signal Conflict (Serial Interface Input Pin)........................................................................................186

Malfunction of Another Device..........................................................................................................186

Signal Conflict (RESET Pin) .............................................................................................................187

A-1

A-2

Development Tools...........................................................................................................................214

TGC-100SDW Package Drawings (for Reference) (Unit: mm).........................................................219

17

User's Manual U13679EJ2V0UD

LIST OF TABLES (1/2)

Table No.

Title

Page

2-1

2-2

Types of Pin I/O Circuits and Recommended Connection of Unused Pins (µPD789830)..................41

Types of Pin I/O Circuits and Recommended Connection of Unused Pins (µPD78F9831) ...............42

3-1

3-2

3-3

3-4

Internal ROM Capacity .......................................................................................................................47

Vector Table .......................................................................................................................................47

Internal RAM Capacity........................................................................................................................48

Special Function Registers ................................................................................................................56

4-1

4-2

4-3

4-4

Port Functions (µPD789830)..............................................................................................................69

Port Functions (µPD78F9831)............................................................................................................69

Configuration of Port...........................................................................................................................70

Port Mode Register and Output Latch Settings for Using Alternate Functions...................................80

5-1

5-2

Configuration of Clock Generator.......................................................................................................84

Maximum Time Required for Switching CPU Clock ...........................................................................94

6-1

6-2

6-3

Interval Time of 16-Bit Timer 40 .........................................................................................................96

16-Bit Timer 40 Configuration.............................................................................................................96

Interval Time of 16-Bit Timer 40 .........................................................................................................99

7-1

7-2

7-3

Interval Time of 8-Bit Timer 00 .........................................................................................................103

Configuration of 8-Bit Timer 00.........................................................................................................103

Interval Time of 8-Bit Timer 00 .........................................................................................................106

8-1

8-2

8-3

Interval Generated Using Interval Timer...........................................................................................110

Watch Timer Configuration...............................................................................................................110

Interval Generated Using Interval Timer...........................................................................................112

9-1

9-2

9-3

9-4

9-5

Inadvertent Loop Detection Time of Watchdog Timer......................................................................114

Interval Time.....................................................................................................................................114

Configuration of Watchdog Timer.....................................................................................................115

Inadvertent Loop Detection Time of Watchdog Timer......................................................................118

Interval Time of Interval Timer..........................................................................................................119

11-1

11-2

11-3

11-4

Serial Interface UART00 Configuration ............................................................................................126

Relation Between Source Clock of 5-Bit Counter and Value n.........................................................136

Example of Relationships Between Main System Clock and Baud Rate .........................................137

Receive Error Causes ......................................................................................................................142

18

User's Manual U13679EJ2V0UD

LIST OF TABLES (2/2)

Table No.

Title

Page

12-1

12-2

12-3

Configuration of LCD Controller/Driver.............................................................................................143

LCD Frame Frequencies ..................................................................................................................147

LCD Drive Voltage............................................................................................................................149

13-1

13-2

13-3

13-4

Maskable Interrupt Sources of µPD789830 Subseries.....................................................................153

Interrupt Sources..............................................................................................................................154

Interrupt Request Signals and Corresponding Flags........................................................................156

Time from Generation of Maskable Interrupt Request to Servicing..................................................165

14-1

14-2

14-3

14-4

Operation Statuses in HALT Mode...................................................................................................171

Operation After Release of HALT Mode...........................................................................................173

Operation Statuses in STOP Mode ..................................................................................................174

Operation After Release of STOP Mode ..........................................................................................176

15-1

State of Hardware After Reset..........................................................................................................179

16-1

16-2

16-3

16-4

Differences Between µPD78F9831 and µPD789830 .......................................................................180

Communication Mode.......................................................................................................................181

Functions of Flash Memory Programming........................................................................................182

Setting with Flashpro III....................................................................................................................184

17-1

20-1

Operand Identifiers and Description Methods ..................................................................................188

Surface Mounting Soldering Conditions ...........................................................................................212

19

User's Manual U13679EJ2V0UD

CHAPTER 1 GENERAL

1.1 Features

• ROM and RAM capacity

Item

Program Memory

Data Memory

LCD Display RAM

80 KB

Product Name

RAM

µPD789830

24 KB (mask ROM)

48 KB (flash memory)

1 KB

2 KB

µPD78F9831

•

Minimum instruction execution time changeable from high speed (0.56 µs: Main system clock 3.58 MHz

operation) to ultra-low speed (122 µs: Subsystem clock 32.768 kHz operation)

I/O port

•

µPD789830: 30 (one N-ch open drain)

µPD78F9831: 38 (one N-ch open drain)

•

Serial interface (UART00): 1 channel

Timer: 4 channels

•

16-bit timer:

8-bit timer:

1 channel

Watch timer:

Watchdog timer: 1 channel

•

Pulse output: clock output/buzzer output

LCD controller/driver

•

Segment signal output: 40 lines MAX.

Common signal output: 16 lines MAX.

1/5 bias mode

•

Vectored interrupt source

•

µPD789830: 15

µPD78F9831: 17

•

On-chip key return signal detector

Supply voltage: V^DD= 2.7 to 5.5 V

Supply format

•

µPD789830: 88-pin bare chip

•

µPD78F9831: 100-pin plastic LQFP (fine pitch)

1.2 Applications

Card readers, etc.

20

User's Manual U13679EJ2V0UD

CHAPTER 1 GENERAL

1.3 Ordering Information

Part Number

µPD789830P-×××

µPD78F9831GC-8EU

Supply Format

Internal ROM

Mask ROM

88-pin bare chip

100-pin plastic LQFP (fine pitch) (14 × 14)

Flash memory

Remark ××× indicates ROM code suffix.

21

User's Manual U13679EJ2V0UD

CHAPTER 1 GENERAL

1.4 Pin Configuration (Top View)

(1) µPD789830

•

88-pin bare chip

µPD789830P-×××

Minimum pad pitch: 110.04 µm

Pad aperture:

80.04 µm

Y-axis

66

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

X-axis

22

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21

22

User's Manual U13679EJ2V0UD

CHAPTER 1 GENERAL

Pin Name

No.

1

Pin Name

COM14

No.

Pin Name

No.

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

Pin Name

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

S28

S29

S30

S31

RESET

X2

2

COM15

S0

3

X1

4

S1

V^SS0

V^DD0

XT2

XT1

5

S2

P57/S32

P56/S33

P55/S34

P54/S35

P53/S36

P52/S37

P51/S38

P50/S39

P11

6

S3

7

S4

8

S5

P26/RxD00

P25/TxD00

P24

9

S6

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

S7

S8

P23/PCL

P22/INTP2/BUZ

P21/INTP1

P20/INTP0

COM0

S9

S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

S23

S24

S25

S26

S27

P10

V^DD1

V^SS1

COM1

P34

COM2

P33

COM3

P32

COM4

P31

COM5

P30

COM6

P07

COM7

P06

COM8

P05

COM9

P04

COM10

COM11

COM12

COM13

P03

P02

P01

P00

IC0

Remark For details of pin coordinates, contact an NEC sales representative.

23

User's Manual U13679EJ2V0UD

CHAPTER 1 GENERAL

BUZ:

Buzzer clock

PCL:

Programming clock

Reset

COM0 to COM15: RC oscillator

RESET:

RxD00:

IC0:

Internally connected

Receive data

INTP0 to INTP2: Interrupt from peripherals

S0 to S39: Segment output

TxD00: Transmit data

V^DD0, V^DD1: Power supply

P00 to P07:

P10, P11:

Port 0

Port 1

Port 2

Port 3

Port 5

P20 to P26:

P30 to P34:

P50 to P57:

V^SS0, V^SS1:

X1, X2:

Ground

Crystal (Main system clock)

Crystal (Subsystem clock)

XT1, XT2:

24

User's Manual U13679EJ2V0UD

CHAPTER 1 GENERAL

(2) µPD78F9831

•

100-pin plastic LQFP (fine pitch) (14 × 14)

µPD78F9831GC-8EU

84 83 82 81 80 79 78 77 76

95 94 93 92 91 90 89 88 87 86 85

98

96

97

99

100

1

2

3

4

5

6

7

8

9

COM14

COM15

S0

P41/INTP4

XT1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

XT2

S1

V

DD0

S2

SS0

S3

X1

S4

X2

S5

RESET

S6

V

PP

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

S7

IC2

S8

P00

P01

P02

P03

P04

P05

P06

P07

P30

P31

P32

P33

P34

S9

S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

V

SS1

DD1

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Cautions 1. Connect the VPP pin directly to the VSS0 or VSS1 pin in normal operation mode.

2. Connect the IC0 pin directly to the VSS0 or VSS1 pin.

3. Leave the IC2 pin open.

25

User's Manual U13679EJ2V0UD

CHAPTER 1 GENERAL

BUZ:

Buzzer clock

PCL:

Programming clock

Reset

COM0 to COM15: RC oscillator

RESET:

RxD00:

IC0, IC2:

Internally connected

Receive data

INTP0 to INTP4: Interrupt from peripherals

S0 to S39: Segment output

TxD00: Transmit data

V^DD0, V^DD1: Power supply

NC:

Non-connection

Port 0

P00 to P07:

P10 to P17:

P20 to P26:

P30 to P34:

P40, P41:

P50 to P57:

Port 1

V^PP:

Programming power supply

Port 2

V^SS0, V^SS1:

X1, X2:

XT1, XT2:

Ground

Port 3

Crystal (Main system clock)

Crystal (Subsystem clock)

Port 4

Port 5

26

User's Manual U13679EJ2V0UD

CHAPTER 1 GENERAL

1.5 78K/0Series Lineup

The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.

Products in mass production

Products under development

Y Subseries products support SMB.

Small-scale package, general-purpose applications

µ

PD789074 with added subsystem clock

44-pin

µ

PD789046

PD789026

PD789088

PD789074

PD789014

PD789062

PD789052

42/44-pin

30-pin

28-pin

20-pin

PD789014 with enhanced timer and increased ROM and RAM capacity

PD789074 with enhanced timer and increased ROM and RAM capacity

PD789026 with enhanced timer

On-chip UART and capable of low voltage (1.8 V) operation

RC oscillation version of PD789026 with enhanced timer

µ

PD789060 without EEPROM^TM, POC, and LVI

Small-scale package, general-purpose applications and A/D converter

µ

PD789167 with enhanced A/D converter (10 bits)

PD789104A with enhanced timer

µ

PD789177

µ

PD789177Y

PD789167Y

44-pin

30-pin

µ

PD789167

PD789156

PD789146

PD789134A

PD789124A

PD789114A

PD789104A

PD789146 with enhanced A/D converter (10 bits)

PD789104A with added EEPROM

PD789124A with enhanced A/D converter (10 bits)

RC oscillation version of the

µ

PD789104A

PD789104A with enhanced A/D converter (10 bits)

PD789026 with added A/D converter and multiplier

µ

LCD drive

144-pin

88-pin

80-pin

µ

PD789835

PD789830

UART, 8-bit A/D converter, and dot LCD (Display output total: 96)

UART and dot LCD (40 × 16)

SIO, 10-bit A/D converter, and on-chip voltage booster type LCD (28 × 4)

SIO, 8-bit A/D converter, and resistance division type LCD (28 × 4)

µ

PD789488

PD789478

PD789417A

PD789407A

PD789456

PD789446

PD789436

PD789426

PD789316

PD789306

PD789467

80-pin

µ

PD789407A with enhanced A/D converter (10 bits)

78K/0S

Series

SIO, 8-bit A/D converter, and resistance division type LCD (28 × 4)

80-pin

64-pin

52-pin

µ

PD789446 with enhanced A/D converter (10 bits)

SIO, 8-bit A/D converter, and on-chip voltage booster type LCD (15 × 4)

µ

PD789426 with enhanced A/D converter (10 bits)

SIO, 8-bit A/D converter, and on-chip voltage booster type LCD (5 × 4)

µ

RC oscillation version of the PD789306

SIO and on-chip voltage booster type LCD (24 × 4)

8-bit A/D converter and on-chip voltage booster type LCD (23 × 4)

SIO and resistance division type LCD (24 × 4)

µ

PD789327

USB

64-pin

44-pin

µ

For PC keyboard, on-chip USB HUB function

For PC keyboard, on-chip USB function

PD789803

PD789800

Inverter control

µ

44-pin

30-pin

PD789842

On-chip inverter controller and UART

On-chip CAN controller

On-chip bus controller

µ

PD789850

Keyless entry

30-pin

20-pin

PD789860 with enhanced timer, added SIO, and increased ROM, RAM capacity

µ

PD789862

PD789861

PD789860

µ

RC oscillation version of the PD789860

On-chip POC and key return circuit

VFD drive

PD789871

On-chip VFD controller (display output total: 25)

52-pin

64-pin

µ

Meter control

PD789881

µ

UART and resistance division type LCD (26 × 4)

Remark VFD (Vacuum Fluorescent Display) is referred to as FIP^TM(Fluorescent Indicator Panel) in some

documents, but the functions of the two are the same.

27

User's Manual U13679EJ2V0UD

CHAPTER 1 GENERAL

The major differences between subseries are shown below.

Series for LCD drive, general-purpose applications

ROM

Capacity

Timer

8-Bit 16-Bit Watch WDT

8-Bit 10-Bit

Serial

Interface

I/O V^DD

Remarks

Function

A/D

MIN.

Value

Subseries Name

Small-scale µPD789046

16 KB

1 ch 1 ch

3 ch

1 ch

−

1 ch (UART: 34 1.8 V

1 ch)

−

package,

general-

µPD789026

4KB to16KB

−

µPD789088

16 KB to

32 KB

24

purpose

applications

µPD789074

µPD789014

µPD789062

2KB to8KB 1 ch

2KB to4KB 2 ch

4 KB

−

22

−

14

RC oscillation

version

µPD789052

−

Small-scale µPD789177

16 KB to

24 KB

3 ch 1 ch

1 ch

−

8 ch

−

8 ch 1 ch (UART: 31 1.8 V

package,

general-

purpose

applications

and A/D

1 ch)

µPD789167

−

µPD789156

µPD789146

8 KB to

16 KB

−

4 ch

−

20

On-chip

EEPROM

4 ch

−

µPD789134A 2 KB to

4 ch

−

RC oscillation

version

converter

8 KB

µPD789124A

4 ch

−

µPD789114A

µPD789104A

4 ch

−

4 ch

LCD drive µPD789835

24 KB to

60 KB

6 ch

–

1 ch

1 ch 3 ch

–

1 ch (UART: 37 1.8 V Dot LCD

1 ch)

Note supported

µPD789830

µPD789488

µPD789478

24 KB

32 KB

1 ch 1 ch

3 ch

–

30 2.7 V

8 ch 2 ch (UART: 45 1.8 V

−

1 ch)

24 KB to

32 KB

8 ch

−

µPD789417A 12 KB to

−

7 ch

−

7 ch 1 ch (UART: 43

24 KB

1 ch)

µPD789407A

−

µPD789456

µPD789446

µPD789436

µPD789426

µPD789316

12 KB to

16 KB

2 ch

6 ch

–

30

40

6 ch

–

6 ch

–

6 ch

–

8 KB to

16 KB

2 ch (UART: 23

1 ch)

RC oscillation

version

µPD789306

µPD789467

µPD789327

–

4 KB to

24 KB

–

1 ch

–

18

21

–

1 ch

Note Flash memory version: 3.0 V

28

User's Manual U13679EJ2V0UD

CHAPTER 1 GENERAL

Series for ASSP

Subseries Name

Function

ROM

Timer

8-Bit 10-Bit

Serial

I/O V^DD

Remarks

Capacity

A/D

Interface

8-Bit 16-Bit Watch WDT

MIN.

Value

USB

µPD789803

µPD789800

2 ch

–

−

1 ch

–

2 ch

(USB: 1 ch)

41 3.6 V

31 4.0 V

−

8 KB to 16 KB

8 KB

Inverter

control

µPD789842

8 KB to

16 KB

3 ch Note 1 1 ch

1 ch 8 ch

1 ch 4 ch

−

1 ch (UART: 30 4.0 V

1 ch)

−

On-chip

bus

µPD789850

16 KB

1 ch 1 ch

−

2 ch (UART: 18 4.0 V

1 ch)

controller

Keyless

entry

µPD789861

4 KB

2 ch

−

1 ch

−

–

14 1.8 V RC oscillation

version,

on-chip

EEPROM

µPD789860

µPD789862

On-chip

EEPROM

1 ch 2 ch

1 ch (UART: 22

1 ch)

16 KB

VFD drive µPD789871

3 ch

–

1 ch

–

1 ch

33 2.7 V

–

4 KB to 8 KB

16 KB

Meter

µPD789881

2 ch 1 ch

–

1 ch (UART: 28 2.7 V

control

1 ch)

Note 2

Notes 1. 10-bit timer: 1 channel

2. Flash memory version: 3.0 V

29

User's Manual U13679EJ2V0UD

CHAPTER 1 GENERAL

1.6 Block Diagram

(1) µPD789830

8-bit timer

counter 00

P00 to P07

P10, P11

Port 0

Port 1

Port 2

Port 3

Port 5

16-bit timer

counter 40

78K/0S

ROM

CPU core

PCL/P23

BUZ/P22/

INTP2

PCL/buzzer

unit (PBU)

P20 to P26

P30 to P34

P50 to P57

RxD00/P26

TxD00/P25

UART 00

Watch timer

Watchdog timer

RAM

RESET

X1

System

control

X2

XT1

XT2

S0 to S31

S32/P57 to S39/P50

COM0 to COM15

LCD controller/

driver 20

IC0

V

SS0

SS1

V

DD0

DD1

INTP0/P20

V

Interrupt

control

INTP1/P21

INTP2/BUZ/P22

(2) µPD78F9831

8-bit timer

counter 00

P00 to P07

P10 to P17

P20 to P26

P30 to P34

Port 0

16-bit timer

counter 40

Port 0

PCL/P23

BUZ/P22/

INTP2

PCL/buzzer

unit (PBU)

Port 2

Port 3

RxD00/P26

TxD00/P25

UART 00

Flash

78K/0S

memory

CPU core

P40, P41

Port 4

Port 5

Watch timer

Watchdog timer

P50 to P57

RESET

X1

RAM

S0 to S31

S32/P57 to S39/P50

COM0 to COM15

System

Control

LCD controller/

driver 20

X2

XT1

XT2

INTP0/P20

INTP1/P21

Interrupt

Control

INTP2/BUZ/P22

IC0

IC2

V

SS0

SS1

INTP3/P40

INTP4/P41

V

DD0

DD1

V

VPP

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CHAPTER 1 GENERAL

1.7 Overview of Functions

Item

µPD789830

µPD78F9831

Flash memory

Internal memory

ROM structure

ROM

Mask ROM

24 KB

1 KB

48 KB

2 KB

RAM

LCD display RAM

80 bytes

Minimum instruction execution time

• 0.56/2.23 µs (@ 3.58 MHz operation with main system clock)

• 122 µs (@ 32.768 kHz operation with subsystem clock)

Instruction set

• 16-bit operations

• Bit manipulations (such as set, reset, and test)

I/O ports

Total of 30 port pins

Total of 38 port pins

29 CMOS I/O pins

37 CMOS I/O pins

1 N-ch open-drain I/O pin

Serial interface

Timers

UART: 1 channel

• 16-bit timer: 1 channel

• 8-bit timer: 1 channel

• Watch timer: 1 channel

• Watchdog timer: 1 channel

Pulse output

Clock output/buzzer output

LCD controller/driver

• Segment signal output: 40 lines MAX.

• Common signal output: 16 lines MAX.

• 1/5 bias mode

Vectored interrupt

sources

Maskable

Internal: 10, external: 4

Internal: 1

Internal: 10, external: 6

Non-maskable

Power supply voltage

V^DD= 2.7 to 5.5 V

T^A= −20°C to +60°C

88-pin bare chip

Operating ambient temperature

Supply format

100-pin plastic LQFP (fine pitch)

(14 × 14)

The outline of the timer is as follows.

16-Bit Timer 40

8-Bit Timer 00

Watch Timer

Watchdog Timer

Operating

mode

Interval timer

1 channel

1 channel^{Note 1}

1 channel^{Note 2}

External event counter

Timer outputs

−

3

−

1

−

2

−

2

Function

Square-wave outputs

Capture

Interrupt sources

Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.

2. The watchdog timer provides the watchdog timer function and interval timer function. Use either of the

functions.

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CHAPTER 2 PIN FUNCTIONS

2.1 Pin Function List

(1) Port pins (µPD789830)

Pin Name

I/O

Function

After Reset

Input

Alternate Function

P00 to P07

Port 0

−

8-bit I/O port

Input/output can be specified in 1-bit units.

When used as an input port, connection of an on-chip pull-up

resistor can be specified by setting pull-up resistor option register 0

(PU0).

P10, P11

I/O

Port 1

Input

−

2-bit I/O port

Input/output can be specified in 1-bit units.

When used as an input port, connection of an on-chip pull-up

resistor can be specified by setting pull-up resistor option register 0

(PU0).

P20

Port 2

INTP0

INTP1

INTP2/BUZ

PCL

7-bit I/O port

P21

Input/output can be specified in 1-bit units.

P24 can be used as an N-ch open-drain I/O port pin.

P22

P23

P24

−

P25

TxD00

RxD00

−

P26

P30 to P34

I/O

Port 3

Input

5-bit I/O port

Input/output can be specified in 1-bit units.

When used as an input port, connection of an on-chip pull-up

resistor can be specified by setting pull-up resistor option register 0

(PU0).

P50 to P57

Port 5

S39 to S32

8-bit I/O port

Input/output can be specified in 1-bit units.

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CHAPTER 2 PIN FUNCTIONS

(2) Port pins (µPD78F9831)

Pin Name

I/O

Function

After Reset

Input

Alternate Function

P00 to P07

Port 0

−

8-bit I/O port

Input/output can be specified in 1-bit units.

When used as an input port, connection of an on-chip pull-up

resistor can be specified by setting pull-up resistor option register 0

(PU0).

P10 to P17

I/O

Port 1

Input

−

8-bit I/O port

Input/output can be specified in 1-bit units.

When used as an input port, connection of an on-chip pull-up

resistor can be specified by setting pull-up resistor option register 0

(PU0).

P20

Port 2

INTP0

INTP1

INTP2/BUZ

PCL

7-bit I/O port

P21

Input/output can be specified in 1-bit units.

P24 can be used as an N-ch open-drain I/O port pin.

P22

P23

P24

−

P25

TxD00

RxD00

−

P26

P30 to P34

I/O

Port 3

Input

5-bit I/O port

Input/output can be specified in 1-bit units.

When used as an input port, connection of an on-chip pull-up

resistor can be specified by setting pull-up resistor option register 0

(PU0).

P40

P41

I/O

Port 4

INTP3

INTP4

2-bit I/O port

Input/output can be specified in 1-bit units.

P50 to P57

Port 5

Input

S39 to S32

8-bit I/O port

Input/output can be specified in 1-bit units.

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CHAPTER 2 PIN FUNCTIONS

(3) Non-port pins

Pin Name

INTP0

I/O

Function

After Reset

Input

Alternate Function

P20

Input

External interrupt input for which the valid edge (rising edge,

falling edge, or both rising and falling edges) can be specified.

INTP1

P21

INTP2

P22/BUZ

P40

INTP3^Note

INTP4^Note

RxD00

TxD00

P41

Input

Serial data input to asynchronous serial interface

Input

Output

P26

Output Serial data output from asynchronous serial interface

Output Buzzer output

P25

BUZ

P22/INTP2

P23

PCL

Output Clock output

S0 to S31

S32 to S39

Output Segment signal output from LCD controller/driver

−

P57 to P50

−

COM0 to

COM15

Output Common signal output from LCD controller/driver

Output

X1

Input

−

Connected to crystal for main system clock oscillation

Connected to crystal for subsystem clock oscillation

−

X2

−

XT1

XT2

RESET

V^DD0

V^DD1

V^SS0

V^SS1

IC0

Input

−

Input

−

System reset input

Input

−

Positive supply voltage for ports

Positive supply voltage for circuits other than ports

Port section ground potential

−

Ground potential of circuits other than ports

This pin is internally connected. Connect this pin directly to the

V^SS0or V^SS1pin.

IC2^Note

NC^Note

This pin is internally connected. Leave this pin open.

−

This pin is not internally connected. Connect this pin directly to

the V^SS0or V^SS1pin (it can also be left open).

V^PP^Note

This pin is used to set flash memory programming mode and

applies a high voltage when a program is written or verified.

−

Note µPD78F9831 only

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CHAPTER 2 PIN FUNCTIONS

2.2 Description of Pin Functions (µPD789830)

2.2.1 P00 to P07 (Port 0)

These pins constitute an 8-bit I/O port and can be set to input or output port mode in 1-bit units by using port

mode register 0 (PM0). When these pins are used as an input port, an on-chip pull-up resistor can be used by

setting pull-up resistor option register 0 (PU0).

2.2.2 P10, P11 (Port 1)

These pins constitute a 2-bit I/O port and can be set to input or output port mode in 1-bit units by using port mode

register 1 (PM1). When these pins are used as an input port, an on-chip pull-up resistor can be used by setting pull-

up resistor option register 0 (PU0).

2.2.3 P20 to P26 (Port 2)

These pins constitute a 7-bit I/O port. In addition, these pins provide a function to perform input to the external

interrupt, to output the buzzer, to output the pulse, and to input/output the data of UART.

Port 2 can be specified in the following operation modes in 1-bit units.

(1) Port mode

In port mode, P20 to P26 function as a 7-bit I/O port. Port 2 can be set to input or output mode in 1-bit units

by using port mode register 2 (PM2). P24 is an N-ch open-drain I/O port.

(2) Control mode

In this mode, P20 to P26 function as the external interrupt input, buzzer output, pulse output, and

input/output of UART data.

(a) INTP0 to INTP2

External interrupt input pins for which the valid edge (rising edge, falling edge, or both the rising and

falling edges) can be specified.

(b) PCL

Pulse output pin of clock output circuit.

(c) BUZ

Buzzer output pin of clock output circuit.

(d) RxD00, TxD00

Serial data I/O pins of UART.

Caution When using P20 to P26 as data I/O pins of UART, the input/output mode and output

latch must be set according to the functions to be used. For details of the setting, see

(1) in Section 11.3.

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CHAPTER 2 PIN FUNCTIONS

2.2.4 P30 to P34 (Port 3)

These pins constitute a 5-bit I/O port. Port 3 can be set to input or output mode in 1-bit units by using port mode

register 3 (PM3). When these pins are used as an input port, an on-chip pull-up resistor can be used by setting pull-

up resistor option register 0 (PU0). This port can be also used to detect a key return signal in 1-bit units.

2.2.5 P50 to P57 (Port 5)

These pins constitute an 8-bit I/O port. In addition, these pins provide the function to output the LCD

controller/driver segment signal. Port 5 can be specified in the following operation modes in 1-bit units.

(1) Port mode

In port mode, P50 to P57 function as an 8-bit I/O port. Port 5 can be set to input or output mode in 1-bit

units by using port mode register 5 (PM5).

(2) Control mode

In this mode, P50 to P57 function as a segment signal output of the LCD controller/driver (S32 to S39).

2.2.6 S0 to S31

These pins are used to output the segment signal of the LCD controller/driver.

2.2.7 COM0 to COM15

These pins are used to output the common signal of the LCD controller/driver.

2.2.8 RESET

This pin inputs an active-low system reset signal.

2.2.9 X1, X2

These pins are used to connect a crystal resonator for main system clock oscillation.

2.2.10 XT1, XT2

These pins are used to connect a crystal resonator for subsystem clock oscillation.

2.2.11 V^DD0, VDD1

V^DD0supplies positive power to the ports.

V^DD1supplies positive power to circuits other than those of the ports.

2.2.12 V^SS0, VSS1

V^SS0is the ground pin for the ports.

V^SS1is the ground pin for circuits other than those of the ports.

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CHAPTER 2 PIN FUNCTIONS

2.2.13 IC0

The IC0 (Internally Connected) pin is used to set the µPD789830 Subseries in test mode before shipment. In

normal operation mode, directly connect this pin to the V^SS0or V^SS1pin with as short a wiring length as possible.

If a potential difference is generated between the IC0 pin and V^SS0or V^SS1pin due to a long wiring length

between the IC0 pin and V^SS0or V^SS1pin or an external noise superimposed on the IC0 pin, a user program may not

run correctly.

• Directly connect the IC0 pin to the V^SS0or V^SS1pin.

V

SS0,

V

SS1

IC0

Keep short

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CHAPTER 2 PIN FUNCTIONS

2.3 Description of Pin Functions (µPD78F9831)

2.3.1 P00 to P07 (Port 0)

These pins constitute an 8-bit I/O port and can be set to input or output port mode in 1-bit units by using port

mode register 0 (PM0). When these pins are used as an input port, an on-chip pull-up resistor can be used by

setting pull-up resistor option register 0 (PU0).

2.3.2 P10 to P17 (Port 1)

These pins constitute an 8-bit I/O port and can be set to input or output port mode in 1-bit units by using port

mode register 1 (PM1). When these pins are used as an input port, an on-chip pull-up resistor can be used by

setting pull-up resistor option register 0 (PU0).

2.3.3 P20 to P26 (Port 2)

These pins constitute a 7-bit I/O port. In addition, these pins provide a function to perform input to the external

interrupt, to output the buzzer, to output the pulse, and to input/output the data of UART.

Port 2 can be specified in the following operation modes in 1-bit units.

(1) Port mode

In port mode, P20 to P26 function as a 7-bit I/O port. Port 2 can be set to input or output mode in 1-bit units

by using port mode register 2 (PM2). P24 is an N-ch open-drain I/O port.

(2) Control mode

In this mode, P20 to P26 function as the external interrupt input, buzzer output, pulse output, and

input/output of UART data.

(a) INTP0 to INTP2

External interrupt input pins whose valid edge (rising edge, falling edge, or both rising and falling edges)

can be specified.

(b) PCL

Pulse output pin of clock output circuit.

(c) BUZ

Buzzer output pin of clock output circuit.

(d) RxD00, TxD00

Serial data I/O pins of UART.

Caution When using P20 to P26 as data I/O pins of UART, the input/output mode and output latch

must be set according to the functions to be used. For details of the setting, see (1) in

Section 11.3.

2.3.4 P30 to P34 (Port 3)

These pins constitute a 5-bit I/O port. Port 3 can be set to input or output mode in 1-bit units by using port mode

register 3 (PM3). When these pins are used as an input port, an on-chip pull-up resistor can be used by setting pull-

up resistor option register 0 (PU0). This port can be also used to detect a key return signal in 1-bit units.

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CHAPTER 2 PIN FUNCTIONS

2.3.5 P40, P41 (Port 4)

These pins constitute a 2-bit I/O port. In addition, these pins provide the function to perform input to the external

interrupt. Port 4 can be specified in the following operation modes in 1-bit units.

(1) Port mode

In port mode, P40 and P41 function as a 2-bit I/O port. Port 4 can be set to input or output mode in 1-bit

units by using port mode register 4 (PM4).

(2) Control mode

In this mode, P40 and P41 function as an external interrupt input (INTP3, INTP4).

2.3.6 P50 to P57 (Port 5)

These pins constitute an 8-bit I/O port. In addition, these pins provide the function to output the LCD

controller/driver segment signal. Port 5 can be specified in the following operation modes in 1-bit units.

(1) Port mode

In port mode, P50 to P57 function as an 8-bit I/O port. Port 5 can be set to input or output mode in 1-bit

units by using port mode register 5 (PM5).

(2) Control mode

In this mode, P50 to P57 function as a segment signal output of the LCD controller/driver (S32 to S39).

2.3.7 S0 to S31

These pins are used to output the segment signal of the LCD controller/driver.

2.3.8 COM0 to COM15

These pins are used to output the common signal of the LCD controller/driver.

2.3.9 RESET

This pin inputs an active-low system reset signal.

2.3.10 X1, X2

These pins are used to connect a crystal resonator for main system clock oscillation.

2.3.11 XT1, XT2

These pins are used to connect a crystal resonator for subsystem clock oscillation.

2.3.12 V^DD0, VDD1

V^DD0supplies positive power to the ports.

V^DD1supplies positive power to circuits other than those of the ports.

2.3.13 V^SS0, VSS1

V^SS0is the ground pin for the ports.

V^SS1is the ground pin for circuits other than those of the ports.

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CHAPTER 2 PIN FUNCTIONS

2.3.14 VPP

A high voltage should be applied to this pin when the flash memory programming mode is set and when the

program is written or verified.

Handle this pin in either of the following ways.

• Connect a 10 kΩ pull-down resistor to the pin.

• Provide a jumper on the board so that the pin is connected to a dedicated flash programmer in programming

mode and to V^SS0or V^SS1directly in normal operation mode.

2.3.15 IC0

The IC0 pin is connected internally. Connect this pin to V^SS0or V^SS1.

2.3.16 IC2

The IC2 pin is connected internally. Leave this pin open.

2.3.17 NC

The NC (Non-connection) pin is not connected internally. Connect this pin to V^SS0or V^SS1(it can be also left

open).

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CHAPTER 2 PIN FUNCTIONS

2.4 Pin I/O Circuits and Recommended Connection of Unused Pins

The I/O circuit type of each pin and recommended connection of unused pins are shown in Tables 2-1 and 2-2.

For the I/O circuit configuration of each type, refer to Figure 2-1.

Table 2-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (µPD789830)

Pin Name

P00 to P07

P10, P11

I/O Circuit Type

5-H

I/O

Recommended Connection of Unused Pins

Input:

Independently connect to V^DD0, V^DD1, V^SS0, or V^SS1via a

resistor.

Output: Leave open.

P20/INTP0

P21/INTP1

P22/INTP2/BUZ

P23/PCL

8-H

Input:

Independently connect to V^SS0or V^SS1via a resistor.

Output: Leave open.

5-S

Input:

Independently connect to VDD0, VDD1, VSS0, or VSS1 via a

resistor.

Output: Leave open.

P24

13-AB

Input:

Independently connect to V^DD0or V^DD1via a resistor.

Output: Leave open.

P25/TxD00

P26/RxD00

P30 to P34

5-S

8-H

8-C

17-I

Input:

Independently connect to VDD0, VDD1, VSS0, or VSS1 via a

resistor.

Output: Leave open.

Leave open.

P50/S39 to

P57/S32

S0 to S31

17-H

18-C

Output

COM0 to

COM15

XT1

16

Input

−

Connect directly to V^SS0or V^SS1.

Leave open.

XT2

RESET

IC0

2

Input

−

Connect directly to V^SS0or V^SS1.

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CHAPTER 2 PIN FUNCTIONS

Table 2-2. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (µPD78F9831)

Pin Name

P00 to P07

P10 to P17

I/O Circuit Type

5-H

I/O

Recommended Connection of Unused Pins

Input:

Independently connect to V^DD0, V^DD1, V^SS0, or V^SS1via a

resistor.

Output: Leave open.

P20/INTP0

P21/INTP1

P22/INTP2/BUZ

P23/PCL

8-H

Input:

Independently connect to V^SS0or V^SS1via a resistor.

Output: Leave open.

5-S

Input:

Independently connect to VDD0, VDD1, VSS0, or VSS1 via a

resistor.

Output: Leave open.

P24

13-AB

Input:

Independently connect to V^DD0or V^DD1via a resistor.

Output: Leave open.

P25/TxD00

P26/RxD00

P30 to P34

P40/INTP3

P41/INTP4

5-S

8-H

8-C

8-H

Input:

Independently connect to VDD0, VDD1, VSS0, or VSS1 via a

resistor.

Output: Leave open.

Input:

Independently connect to V^SS0or V^SS1via a resistor.

Output: Leave open.

P50/S39 to

P57/S32

17-I

Input:

Independently connect to VDD0, VDD1, VSS0, or VSS1 via a

resistor.

Output: Leave open.

S0 to S31

17-H

18-C

Output

Leave open.

COM0 to

COM15

XT1

XT2

RESET

IC0

16

Input

−

Connect directly to V^SS0or V^SS1.

Leave open.

2

2-B

−

Input

−

Connect directly to V^SS0or V^SS1.

Leave open.

IC2

−

NC

V^PP

Independently connect a 10 kΩ pull-down resistor or connect

directly to V^SS0or V^SS1.

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CHAPTER 2 PIN FUNCTIONS

Figure 2-1. Pin I/O Circuits (1/2)

Type 2

Type 5-S

V

DD0

Data

P-ch

IN/OUT

IN

Output

disable

N-ch

VSS0

Input

enable

Schmitt-triggered input with hysteresis characteristics

VDD0

Type 2-B

Type 8-C

Pull-up

enable

P-ch

VDD0

IN

Data

P-ch

Input

IN/OUT

enable

Output

disable

N-ch

VSS0

V

DD0

Type 5-H

Type 8-H

Data

Pull-up

enable

VDD0

P-ch

V

DD0

IN/OUT

Data

P-ch

Output

disable

N-ch

IN/OUT

VSS0

Output

disable

N-ch

VSS0

Input

enable

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CHAPTER 2 PIN FUNCTIONS

Figure 2-1. Pin I/O Circuits (2/2)

Type 13-AB

Type 17-I

VDD0

P-ch

IN/OUT

Data

N-ch

Output

VSS0

disable

IN/OUT

VDD0

Output

disable

N-ch

VSS0

P-ch

RD

Input

enable

Port

Read

P-ch

Input buffer with intermediate withstanding voltage

VLC0

VLC3

N-ch

P-ch

N-ch

Type 16

feedback

cut-off

P-ch

N-ch

SEG

data

P-ch

N-ch

P-ch

N-ch

VLC2

N-ch

VSS1

XT1

XT2

Type 17-H

Type 18-C

VLC0

P-ch

N-ch

V^LC0

P-ch

N-ch

P-ch

N-ch

P-ch

N-ch

VLC3

VLC1

P-ch

N-ch

P-ch

N-ch

OUT

SEG

data

COM

data

N-ch

P-ch

N-ch

P-ch

N-ch

VLC2

VLC4

N-ch

VSS1

V^SS1

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CHAPTER 3 CPU ARCHITECTURE

3.1 Memory Space

The µPD789830 Subseries can access up to 64 KB of memory space.

Figures 3-1 and 3-2 show the memory maps.

Figure 3-1. Memory Map (µPD789830)

FFFFH

Special function register

256 × 8 bits

FF00H

FEFFH

Internal high-speed RAM

1,024 × 8 bits

FB00H

FAFFH

Reserved

FA50H

FA4FH

LCD display RAM

80 × 8 bits

Data memory space

FA00H

5FFFH

F9FFH

Reserved

6000H

5FFFH

Program area

0080H

007FH

Internal ROM

Program memory

space

24,576 × 8 bits

CALLT table area

0040H

003FH

Program area

0020H

001FH

Vector table area

0000H

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Figure 3-2. Memory Map (µPD78F9831)

FFFFH

Special function register

256 × 8 bits

FF00H

FEFFH

Internal high-speed RAM

1,024 × 8 bits

FB00H

FAFFH

Reserved

FA50H

FA4FH

LCD display RAM

80 × 8 bits

FA00H

F9FFH

Data memory space

Reserved

F700H

F6FFH

Internal low-speed RAM

1,024 × 8 bits

F300H

F2FFH

BFFFH

Reserved

C000H

BFFFH

Program area

0080H

007FH

Internal flash memory

CALLT table area

Program memory

space

49,152 × 8 bits

0040H

003FH

Program area

0024H

0023H

Vector table area

0000H

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CHAPTER 3 CPU ARCHITECTURE

3.1.1 Internal program memory space

The internal program memory space stores programs and table data. This space is usually addressed by the

program counter (PC).

The µPD789830 Subseries provide the following internal ROMs (or flash memory) containing the following

capacities.

Table 3-1. Internal ROM Capacity

Part Number

Internal ROM

Structure

Capacity

24,576 × 8 bits

49,152 × 8 bits

µPD789830

µPD78F9831

Mask ROM

Flash memory

The following areas are allocated to the internal program memory space.

(1) Vector table area

A 32-byte area of addresses 0000H to 001FH (µPD789830) or a 36-byte area of address 0000H to 0023H

(µPD78F9831) is reserved as a vector table area. This area stores program start addresses to be used

when branching by the RESET input or an interrupt request generation. Of a 16-bit program address, the

lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd address.

Table 3-2. Vector Table

Vector Table Address

0000H

Interrupt Request

RESET input

Vector Table Address

0014H

Interrupt Request

INTTM41

0004H

INTWDT

INTP0

0016H

INTTM4

INTTM00

INTWTI

INTWT

0006H

0018H

0008H

INTP1

001AH

001CH

001EH

0020H^Note

0022H^Note

000AH

INTP2

000CH

INTSER00

INTSR00

INTST00

INTTM40

INTKR00

INTP3^Note

INTP4^Note

000EH

0010H

0012H

Note µPD78F9831 only

(2) CALLT instruction table area

In a 64-byte area of addresses 0040H to 007FH, the subroutine entry address of a 1-byte call instruction

(CALLT) can be stored.

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CHAPTER 3 CPU ARCHITECTURE

3.1.2 Internal data memory space

The µPD789830 Subseries provide the following RAM.

(1) Internal RAM

Each member of the µPD789830 Subseries provides the following internal RAM.

Table 3-3. Internal RAM Capacity

Part Number

µPD789830

Capacity

Address

FB00H to FEFFH

1,024 × 8 bits

2,048 × 8 bits

µPD78F9831

FB00H to FEFFH (1,024 × 8 bits)

F300H to F6FFH (1,024 × 8 bits)

The internal RAM is also used as a stack.

(2) LCD display RAM

An LCD display RAM is allocated in the area between FA00H and FA4FH. The LCD display RAM can also

be used as ordinary RAM.

3.1.3 Special function register (SFR) area

Special function registers (SFRs) of on-chip peripheral hardware are allocated to an area of FF00H to FFFFH

(see Table 3-4).

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3.1.4 Data memory addressing

Each of the µPD789830 Subseries is provided with a wide range of addressing modes to make memory

manipulation as efficient as possible. A data memory area (FB00H to FFFFH) can be accessed using a unique

addressing mode according to its use, such as a special function register (SFR). Figures 3-3 and 3-4 illustrate the

data memory addressing modes.

Figure 3-3. Data Memory Addressing (µPD789830)

FFFFH

Special function register (SFR)

SFR addressing

256 × 8 bits

FF20H

FF1FH

FF00H

FEFFH

Short direct addressing

Internal high-speed RAM

1,024 × 8 bits

FE20H

FE1FH

FB00H

FAFFH

Direct addressing

Reserved

Register indirect addressing

Based addressing

FA50H

FA4FH

LCD display RAM

80 × 8 bits

FA00H

F9FFH

Reserved

6000H

5FFFH

Internal ROM

24,576 × 8 bits

0000H

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Figure 3-4. Data Memory Addressing (µPD78F9831)

FFFFH

Special function register (SFR)

SFR addressing

256 × 8 bits

FF20H

FF1FH

FF00H

FEFFH

Internal high-speed RAM

Short direct addressing

1,024 × 8 bits

FE20H

FE1FH

FB00H

FAFFH

FA50H

FA4FH

Reserved

Direct addressing

Register indirect addressing

Based addressing

LCD display RAM

80 × 8 bits

FA00H

F9FFH

F700H

F6FFH

Reserved

Internal low-speed RAM

1,024 × 8 bits

F300H

F2FFH

C000H

BFFFH

Reserved

Internal flash memory

49,152 × 8 bits

0000H

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3.2 Processor Registers

The µPD789830 Subseries provide the following on-chip processor registers.

3.2.1 Control registers

The control registers contain special functions to control the program sequence statuses and stack memory. A

program counter, a program status word, and a stack pointer are control registers.

(1) Program counter (PC)

The program counter is a 16-bit register which holds the address information of the next program to be

executed.

In normal operation, the PC is automatically incremented according to the number of bytes of the instruction

to be fetched. When a branch instruction is executed, immediate data or register contents is set.

RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.

Figure 3-5. Program Counter Configuration

15

0

PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

(2) Program status word (PSW)

The program status word is an 8-bit register consisting of various flags to be set/reset by instruction

execution.

Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW

instruction execution and are automatically restored upon execution of the RETI and POP PSW

instructions.

RESET input sets the PSW to 02H.

Figure 3-6. Program Status Word Configuration

7

0

IE

Z

0

AC

0

1

CY

PSW

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CHAPTER 3 CPU ARCHITECTURE

(a) Interrupt enable flag (IE)

This flag controls interrupt request acknowledge operations of the CPU.

When IE = 0, the IE is set to interrupt disabled (DI) status. All interrupt requests except non-maskable

interrupt are disabled.

When IE = 1, the IE is set to interrupt enabled (EI) status and interrupt request acknowledgment is

controlled with an interrupt mask flag for various interrupt sources.

This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI

instruction execution.

(b) Zero flag (Z)

When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases.

(c) Auxiliary carry flag (AC)

If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all

other cases.

(d) Carry flag (CY)

This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out

value upon rotate instruction execution and functions as a bit accumulator during bit manipulation

instruction execution.

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(3) Stack pointer (SP)

This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed

RAM area can be set as the stack area.

Figure 3-7. Stack Pointer Configuration

15

0

SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore)

from the stack memory.

Each stack operation saves/restores data as shown in Figures 3-8 and 3-9.

Caution

Since RESET input makes SP contents undefined, be sure to initialize the SP before

instruction execution.

Figure 3-8. Data to Be Saved to Stack Memory

Interrupt

PUSH rp

instruction

CALL, CALLT

instructions

_

SP

3

2

1

_

SP

2

1

SP

2

1

PC7 to PC0

PC15 to PC8

PSW

Lower half

register pairs

_

PC7 to PC0

Upper half

register pairs

PC15 to PC8

SP

Figure 3-9. Data to Be Restored from Stack Memory

POP rp

RET instruction

RETI instruction

instruction

Lower half

register pairs

SP

PC7 to PC0

SP

PC7 to PC0

PC15 to PC8

PSW

Upper half

register pairs

PC15 to PC8

SP + 1

SP + 2

SP + 1

SP + 2

SP + 1

SP + 2

SP + 3

SP

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3.2.2 General-purpose registers

A general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H).

In addition that each register can be used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit

register (AX, BC, DE, and HL).

They can be described in terms of functional names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute

names (R0 to R7 and RP0 to RP3).

Figure 3-10. General-Purpose Register Configuration

(a) Absolute names

16-bit processing

8-bit processing

R7

RP3

R6

R5

R4

RP2

RP1

RP0

R3

R2

R1

R0

15

0

7

0

(b) Functional names

16-bit processing

HL

8-bit processing

H

L

D

E

DE

BC

AX

B

C

A

X

15

0

7

0

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CHAPTER 3 CPU ARCHITECTURE

3.2.3 Special function register (SFR)

Unlike a general-purpose register, each special function register has a special function.

It is allocated in the 256-byte area FF00H to FFFFH.

The special function register can be manipulated, like the general-purpose register, with the operation, transfer,

and bit manipulation instructions. Manipulatable bit units (1, 8, and 16) differ depending on the special function

register type.

Each manipulation bit unit can be specified as follows.

• 1-bit manipulation

Describes a symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit). This

manipulation can also be specified with an address.

• 8-bit manipulation

Describes a symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr). This

manipulation can also be specified with an address.

• 16-bit manipulation

Describes a symbol reserved with assembler for the 16-bit manipulation instruction operand. When specifying

an address, describe an even address.

Table 3-4 lists the special function register. The meanings of the symbols in this table are as follows:

• Symbol

Indicates the addresses of the implemented special function registers. The symbols shown in this column are

the reserved words of the assembler, and have already been defined in the header file called "sfrbit.h" of C

compiler. Therefore, these symbols can be used as instruction operands if assembler or integrated debugger

is used.

• R/W

Indicates whether the special function register in question can be read or written.

R/W: Read/write

R:

Read only

Write only

W:

• Number of bits manipulated simultaneously

Indicates the bit units (1, 8, and 16) in which the special function register in question can be manipulated.

• After reset

Indicates the status of the special function register when the RESET signal is input.

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Table 3-4. Special Function Registers (1/2)

Address

Special Function Register (SFR) Name

Symbol

R/W

Manipulatable Bit Unit

After

Reset

1 Bit

8 Bits 16 Bits

FF00H Port 0

FF01H Port 1

FF02H Port 2

FF03H Port 3

FF04H Port 4^{Note 1}

FF05H Port 5

P0

P1

P2

P3

P4

P5

R/W

√

−

√

−

00H

−

Note 2

FF16H 16-bit compare register 40

FF17H

CR40L CR40

CR40H

PM0

√

0000H

FFH

FF20H Port mode register 0

√

−

√

−

√

−

√

−

√

−

FF21H Port mode register 1

PM1

FF22H Port mode register 2

PM2

FF23H Port mode register 3

PM3

FF24H Port mode register 4^{Note 1}

PM4

FF25H Port mode register 5

PM5

FF40H PCL/BUZ control register 0

FF42H Timer clock selection register 2

FF4AH Watch timer mode control register

FF50H 8-bit compare register 00

FF51H 8-bit timer counter 00

PBS0

TCL2

00H

WTM

CR00

TM00

TMC00

TMC40

ASIM00

ASIS00

BRGC00

TXS00

RXB00

LCDM20

PF5

W

R

Undefined

00H

FF53H 8-bit timer mode control register 00

FF5BH Timer 40 control register

FFA0H Asynchronous serial interface mode register 00

FFA1H Asynchronous serial interface status register 00

FFA2H Baud rate generator control register 00

FFA3H Transmission shift register 00

Reception buffer register 00

R/W

R

R/W

W

FFH

00H

R

FFB0H LCD20 mode register

R/W

FFB1H Alternate port function selection register

FFB2H LCD20 clock selection register

FFE0H Interrupt request flag register 0

FFE1H Interrupt request flag register 1

FFE4H Interrupt mask flag register 0

FFE5H Interrupt mask flag register 1

Notes 1. µPD78F9831 only

LCDC20

IF0

IF1

MK0

FFH

MK1

2. 16-bit access is allowed only with short direct addressing.

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Table 3-4. Special Function Registers (2/2)

Address

Special Function Register (SFR) Name

Symbol

R/W

Manipulatable Bit Unit

After

Reset

1 Bit

−

8 Bits 16 Bits

FFECH External interrupt mode register 0

FFEDH External interrupt mode register 1^Note

FFF0H Suboscillation mode register

FFF2H Subclock control register

INTM0

R/W

√

−

00H

INTM1

SCKM

CSS

−

√

FFF5H Key return mode register 00

FFF7H Pull-up resistor option register 0

FFF9H Watchdog timer mode register

FFFAH Oscillation stabilization time selection register

FFFBH Processor clock control register

Note µPD78F9831 only

KRM00

PU0

−

√

WDTM

OSTS

PCC

√

−

04H

02H

√

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3.3 Instruction Address Addressing

An instruction address is determined by program counter (PC) contents. PC contents are normally incremented

(+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another

instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC

and branched by the following addressing (For details of each instruction, refer to 78K/0S Series Instruction User's

Manual (U11047E)).

3.3.1 Relative addressing

[Function]

The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the

start address of the following instruction is transferred to the program counter (PC) and branched. The

displacement value is treated as signed two's complement data (−128 to +127) and bit 7 becomes a sign bit. In

other words, the range of branch in relative addressing is between −128 and +127 of the start address of the

following instruction.

This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.

[Illustration]

15

0

...

PC is the start address of

the next instruction of

a BR instruction.

PC

+

8

7

6

α

S

jdisp8

15

0

PC

When S = 0, α indicates all bits "0".

When S = 1, α indicates all bits "1".

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3.3.2 Immediate addressing

[Function]

Immediate data in the instruction word is transferred to the program counter (PC) and branched.

This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed.

CALL !addr16 and BR !addr16 instructions can branch to all the memory spaces.

[Illustration]

In case of CALL !addr16 and BR !addr16 instructions

7

0

CALL or BR

Low addr.

High addr.

15

8 7

0

PC

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3.3.3 Table indirect addressing

[Function]

Table contents (branch destination address) of the particular location to be addressed by the immediate data of

an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched.

Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can

refer to the address stored in the memory table 40H to 7FH and branch to all the memory spaces.

[Illustration]

7

6

1

5

1

0

Instruction code

Effective address

0

ta4−0

15

8

0

7

0

6

1

5

1

0

7

Memory (table)

Low addr.

0

High addr.

Effective address + 1

15

8

7

0

PC

3.3.4 Register addressing

[Function]

Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC)

and branched.

This function is carried out when the BR AX instruction is executed.

[Illustration]

7

0

8

7

0

rp

A

X

15

PC

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3.4 Operand Address Addressing

The following various methods are available to specify the register and memory (addressing) which undergo

manipulation during instruction execution.

3.4.1 Direct addressing

[Function]

The memory indicated by immediate data in an instruction word is directly addressed.

[Operand format]

Identifier

addr16

Description

Label or 16-bit immediate data

[Description example]

MOV A, !FE00H; When setting !addr16 to FE00H

Instruction code

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

OP code

00H

FEH

[Illustration]

7

0

OP code

addr16 (low)

addr16 (high)

Memory

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3.4.2 Short direct addressing

[Function]

The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.

The fixed space where this addressing is applied is the 256-byte space FE20H to FF1FH. An internal high-

speed RAM and a special function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH,

respectively.

The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of all SFR areas. In this

area, ports which are frequently accessed in a program and a compare register of the timer/event counter are

mapped, and these SFRs can be manipulated with a small number of bytes and clocks.

When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,

bit 8 is set to 1. See [Illustration].

[Operand format]

Identifier

saddr

Description

Label or FE20H to FF1FH immediate data

saddrp

Label or FE20H to FF1FH immediate data (even address only)

[Description example]

MOV FE30H, #50H; When setting saddr to FE30H and the immediate data to 50H

Instruction code

1

0

1

0

1

0

1

0

1

0

1

0

OP Code

30H (saddr-offset)

50H (immediate data)

[Illustration]

7

0

OP code

saddr-offset

Short direct memory

15

8

0

Effective

address

1

α

When 8-bit immediate data is 20H to FFH, = 0.

α

When 8-bit immediate data is 00H to 1FH, = 1.

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3.4.3 Special function register (SFR) addressing

[Function]

The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction

word.

This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR

mapped at FF00H to FF1FH can be accessed with short direct addressing.

[Operand format]

Identifier

sfr

Description

Special function register name

[Description example]

MOV PM0, A; When selecting PM0 for sfr

Instruction code

1

0

1

0

1

0

1

0

1

0

1

0

[Illustration]

7

0

OP code

sfr-offset

SFR

15

1

8 7

0

Effective

address

1

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3.4.4 Register addressing

[Function]

The general-purpose register is accessed as an operand. The general-purpose register to be accessed is

specified with register specification code and functional name in the instruction code.

Register addressing is carried out when an instruction with the following operand format is executed. When an

8-bit register is specified, one of the eight registers is specified with three bits in the instruction code.

[Operand format]

Identifier

Description

r

X, A, C, B, E, D, L, H

AX, BC, DE, HL

rp

'r' and 'rp' can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A,

C, B, E, D, L, H, AX, BC, DE, and HL).

[Description example]

MOV A, C; When selecting the C register for r

Instruction code

0

1

0

1

0

1

0

1

Register specification

code

INCW DE; When selecting the DE register pair for rp

Instruction code

1

0

1

0

Register specification

code

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3.4.5 Register indirect addressing

[Function]

The memory is addressed with the contents of the register pair specified as an operand. The register pair to be

accessed is specified with the register pair specification code in the instruction code. This addressing can be

carried out for all the memory spaces.

[Operand format]

Identifier

Description

−

[DE], [HL]

[Description example]

MOV A, [DE]; When selecting register pair [DE]

Instruction code

0

1

0

1

0

1

[Illustration]

15

8

7

0

DE

D

E

Memory address specified

by register pair DE

The contents of addressed

memory are transferred

7

0

A

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3.4.6 Based addressing

[Function]

8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is

used to address the memory. Addition is performed by expanding the offset data as a positive number to 16

bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier

Description

−

[HL+byte]

[Description example]

MOV A, [HL+10H]; When setting byte to 10H

Instruction code

0

1

0

1

0

1

0

1

0

3.4.7 Stack addressing

[Function]

The stack area is indirectly addressed with the stack pointer (SP) contents.

This addressing method is automatically employed when the PUSH, POP, subroutine call, and RETURN

instructions are executed or the register is saved/restored upon generation of an interrupt request.

Stack addressing enables to access the internal high-speed RAM area only.

[Description example]

In the case of PUSH DE

Instruction code

1

0

1

0

1

0

1

0

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CHAPTER 4 PORT FUNCTIONS

4.1 Port Functions

The µPD789830 Subseries is provided with the ports shown in Figures 4-1 and 4-2. These ports are used to

enable several types of control. Tables 4-1 and 4-2 list the functions of each port.

These ports, while originally designed as digital input/output ports, can also be used for other functions, as

summarized in CHAPTER 2.

Figure 4-1. Port Types (µPD789830)

P00

P07

P30

P34

Port 3

Port 0

P10

P11

P50

P57

Port 1

Port 2

Port 5

P20

P26

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Figure 4-2. Port Types (µPD78F9831)

P00

P30

P34

Port 3

Port 0

Port 1

Port 2

P07

P10

P40

P41

Port 4

P50

P57

P17

P20

Port 5

P26

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Table 4-1. Port Functions (µPD789830)

Name

Port 0

Pin Name

P00 to P07

Function

I/O port

Input/output can be specified in 1-bit units.

When used as an input port, connection of an on-chip pull-up resistor can be specified

by setting pull-up resistor option register 0 (PU0).

Port 1

P10, P11

I/O port

Input/output can be specified in 1-bit units.

When used as an input port, connection of an on-chip pull-up resistor can be specified

by setting pull-up resistor option register 0 (PU0).

Port 2

Port 3

P20 to P26

P30 to P34

I/O port

Input/output can be specified in 1-bit units.

P24 is an N-ch open-drain input/output port.

I/O port

Input/output can be specified in 1-bit units.

When used as an input port, connection of an on-chip pull-up resistor can be specified

by setting pull-up resistor option register 0 (PU0).

Port 5

P50 to P57

I/O port

Input/output can be specified in 1-bit units.

Table 4-2. Port Functions (µPD78F9831)

Name

Pin Name

Function

Port 0

P00 to P07

I/O port

Input/output can be specified in 1-bit units.

When used as an input port, connection of an on-chip pull-up resistor can be specified

by setting pull-up resistor option register 0 (PU0).

Port 1

P10 to P17

I/O port

Input/output can be specified in 1-bit units.

When used as an input port, connection of an on-chip pull-up resistor can be specified

by setting pull-up resistor option register 0 (PU0).

Port 2

Port 3

P20 to P26

P30 to P34

I/O port

Input/output can be specified in 1-bit units.

P24 is an N-ch open-drain input/output port.

I/O port

Input/output can be specified in 1-bit units.

When used as an input port, connection of an on-chip pull-up resistor can be specified

by setting pull-up resistor option register 0 (PU0).

Port 4

Port 5

P40, P41

I/O port

Input/output can be specified in 1-bit units.

P50 to P57

I/O port

Input/output can be specified in 1-bit units.

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4.2 Port Configuration

Ports include the following hardware.

Table 4-3. Configuration of Port

Item

Configuration

Control register

Port mode register (PMm)

m = 0 to 3, 5 (µPD789830)

m = 0 to 5 (µPD78F9831)

Pull-up resistor option register (PU0)

Port

• µPD789830

Total: 30 (CMOS I/O: 29, N-ch open-drain I/O: 1)

• µPD78F9831

Total: 38 (CMOS I/O: 37, N-ch open-drain I/O: 1)

Pull-up resistor

• µPD789830

Total: 15 (software control: 15)

• µPD78F9831

Total: 21 (software control: 21)

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CHAPTER 4 PORT FUNCTIONS

4.2.1 Port 0

This is an 8-bit I/O port with an output latch. Port 0 can be specified in input or output mode in 1-bit units by

using port mode register 0 (PM0). When P00 to P07 pins are used as input port pins, on-chip pull-up resistors can

be connected in 8-bit units by setting pull-up resistor option register 0 (PU0).

RESET input sets port 0 to input mode.

Figure 4-3 shows the block diagram of port 0.

Figure 4-3. Block Diagram of P00 to P07

V

DD0

WR^PU0

PU0

P-ch

RD

WRPORT

WRPM

Output latch

(P00 to P07)

P00 to P07

PM00 to PM07

PU0: Pull-up resistor option register 0

PM: Port mode register

RD: Port 0 read signal

WR: Port 0 write signal

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4.2.2 Port 1: µPD789830

This is a 2-bit I/O port with an output latch. Port 1 can be specified in input or output mode in 1-bit units by using

port mode register 1 (PM1). When P10 and P11 pins are used as input port pins, on-chip pull-up resistors can be

connected in 2-bit units by setting pull-up resistor option register 0 (PU0).

RESET input sets port 1 to input mode.

Figure 4-4 shows the block diagram of port 1.

Figure 4-4. Block Diagram of P10 and P11 (µPD789830)

V

DD0

WR^PU0

PU0

P-ch

RD

WRPORT

WRPM

Output latch

(P10, P11)

P10, P11

PM10, PM11

PU0: Pull-up resistor option register 0

PM: Port mode register

RD: Port 1 read signal

WR: Port 1 write signal

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4.2.3 Port 1: µPD78F9831

This is an 8-bit I/O port with an output latch. Port 1 can be specified in input or output mode in 1-bit units by

using port mode register 1 (PM1). When P10 to P17 pins are used as input port pins, on-chip pull-up resistors can

be connected in 8-bit units by setting pull-up resistor option register 0 (PU0).

RESET input sets port 1 to input mode.

Figure 4-5 shows the block diagram of port 1.

Figure 4-5. Block Diagram of P10 to P17 (µPD78F9831)

V

DD0

WR^PU0

PU0

P-ch

RD

WRPORT

WRPM

Output latch

(P10 to P17)

P10 to P17

PM10 to PM17

PU0: Pull-up resistor option register 0

PM: Port mode register

RD: Port 1 read signal

WR: Port 1 write signal

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4.2.4 Port 2

This is a 7-bit I/O port with an output latch. Port 2 can be specified in input or output mode in 1-bit units by using

port mode register 2 (PM2).

P24 is an N-ch open-drain I/O port. This port is pulled up to V^DD0when it is read.

The port is also used as an external interrupt input, pulse output, clock output, and a data I/O to and from the

asynchronous serial interface.

RESET input sets port 2 to input mode.

Figures 4-6 to 4-9 show block diagrams of port 2.

Figure 4-6. Block Diagram of P20, P21, and P26

Alternate

function

RD

WRPORT

Output latch

(P20, P21, P26)

P20/INTP0,

P21/INTP1,

P26/RxD00

WRPM

PM20, PM21,

PM26

PU0: Pull-up resistor option register 0

PM: Port mode register

RD: Port 2 read signal

WR: Port 2 write signal

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Figure 4-7. Block Diagram of P22

Alternate

function

RD

WRPORT

WRPM

P22/INTP2/

BUZ

Output latch

(P22)

PM22

Alternate

function

PM: Port mode register

RD: Port 2 read signal

WR: Port 2 write signal

Figure 4-8. Block Diagram of P23 and P25

RD

WRPORT

WRPM

P23/PCL,

P25/TxD00

Output latch

(P23, P25)

PM23, PM25

Alternate

function

PM: Port mode register

RD: Port 2 read signal

WR: Port 2 write signal

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Figure 4-9. Block Diagram of P24

V

DD0

RD

P-ch

P24

WR^PORT

Output latch

N-ch

(P24)

WRPM

PM24

PM: Port mode register

RD: Port 2 read signal

WR: Port 2 write signal

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4.2.5 Port 3

This is a 5-bit I/O port with an output latch. Port 3 can be specified in input or output mode in 1-bit units by using

port mode register 3 (PM3).

This port can be also used to detect a key return signal in 1-bit units. For how to set the ports, see (6) in Section

13.3.

RESET input sets port 3 to input mode.

Figure 4-10 shows the block diagram of port 3.

Figure 4-10. Block Diagram of P30 to P34

VDD0

KRM00

PU0

P-ch

Key return

signal

RD

WR^PORT

Output latch

(P30 to P34)

P30 to P34

WRPM

PM30 to PM34

PU0:

Pull-up resistor option register 0

KRM00: Key return mode register 00

PM:

RD:

WR:

Port mode register

Port 3 read signal

Port 3 write signal

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4.2.6 Port 4: µPD78F9831

This is a 2-bit I/O port with an output latch. Port 4 can be specified in input or output mode in 1-bit units by using

port mode register 4 (PM4).

The port is also used as an external interrupt input.

RESET input sets port 4 to input mode.

Figure 4-11 shows the block diagram of port 4.

Figure 4-11. Block Diagram of P40 and P41 (µPD78F9831)

Alternate

function

RD

WRPORT

Output latch

(P40, P41)

P40/INTP3,

P41/INTP4

WRPM

PM40, PM41

PM: Port mode register

RD: Port 4 read signal

WR: Port 4 write signal

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4.2.7 Port 5

This is an 8-bit I/O port with an output latch. Port 5 can be specified in input or output mode in 1-bit units by

using port mode register 5 (PM5).

The port is also used as a segment output.

RESET input sets port 5 to input mode.

Figure 4-12 shows the block diagram of port 5.

Figure 4-12. Block Diagram of P50 to P57

RD

WR^PORT

Output latch

(P50 to P57)

P50/S39 to

P57/S32

WRPM

PM50 to PM57

Segment

output

WRPF5

PF5

PF5: Alternate port function switching register

PM: Port mode register

RD: Port 5 read signal

WR: Port 5 write signal

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4.3 Port Function Control Registers

The following two types of registers are used to control the ports.

• Port mode registers (PM0 to PM5^Note

• Pull-up resistor option register 0 (PU0)

)

(1) Port mode registers (PM0 to PM5^Note

)

The port mode registers separately specify each port bit as being for input or output.

Each port mode register is manipulated using a 1-bit or 8-bit memory manipulation instruction.

A RESET input writes FFH into the port mode registers.

When port pins are used for alternate functions, the corresponding port mode register and output latch must

be set or reset as described in Table 4-4.

Caution When ports 2 and 4^Noteare acting as an output port, and its output level is changed, an

interrupt request flag is set, because this port is also used as the input for an external

interrupt. To use ports 2 and 4 in output mode, therefore, the interrupt mask flag must be

set to 1 in advance.

Note PM4 and port 4 are provided to the µPD78F9831 only.

Table 4-4. Port Mode Register and Output Latch Settings for Using Alternate Functions

Pin Name

Alternate Function

Input/Output

PM××

P××

Name

P20

INTP0

INTP1

INTP2

BUZ

Input

1

0

1

×

0

×

P21

P22

Input

Output

Input

P23

PCL

P40^{Note 1}

P41^{Note 1}

P50 to P57

INTP3

INTP4

Input

S39 to S32^{Note 2}

Output

Notes 1. µPD78F9831 only

2. When using the alternate function, set the alternate port function switching register (PF5) to 1 (see (2)

in Section 12.3).

Caution When using the pins of port 2 as the serial interface, the I/O or output latch must be set

according to the function to be used. For how to set the latches, see (1) in Section 11.3.

Remark ×:

Don't care

PM××: Port mode register

P××: Port output latch

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Figure 4-13. Format of Port Mode Register (µPD789830)

Symbol

PM0

7

6

5

4

3

2

1

0

Address

FF20H

After reset

FFH

R/W

PM07

PM06

PM05

PM04

PM03

PM02

PM01

PM00

PM1

PM2

PM3

PM5

1

PM11

PM21

PM31

PM51

PM10

PM20

PM30

PM50

FF21H

FF22H

FF23H

FF25H

FFH

R/W

PM26

1

PM25

1

PM24

PM34

PM54

PM23

PM33

PM53

PM22

PM32

PM52

1

PM57

PMmn

PM56

PM55

Pmn pin I/O mode selection

(m = 0 to 3, 5 n = 0 to 7)

0

1

Output mode (output buffer ON)

Input mode (output buffer OFF)

Figure 4-14. Format of Port Mode Register (µPD78F9831)

Symbol

PM0

7

6

5

4

3

2

1

0

Address

FF20H

After reset

FFH

R/W

PM07

PM06

PM05

PM04

PM03

PM02

PM01

PM00

PM1

PM2

PM3

PM4

PM5

PM17

PM16

PM26

1

PM15

PM25

1

PM14

PM24

PM34

1

PM13

PM23

PM33

1

PM12

PM22

PM32

1

PM11

PM21

PM31

PM41

PM51

PM10

PM20

PM30

PM40

PM50

FF21H

FF22H

FF23H

FF24H

FF25H

FFH

R/W

1

PM57

PMmn

PM56

PM55

PM54

PM53

PM52

Pmn pin I/O mode selection

(m = 0 to 5 n = 0 to 7)

0

1

Output mode (output buffer ON)

Input mode (output buffer OFF)

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(2) Pull-up resistor option register 0 (PU0)

This register specifies whether an on-chip pull-up resistor is connected to ports 0, 1, and 3.

On the port which is specified to use the on-chip pull-up resistor in PU0, the pull-up resistor can be

internally used only for the bits set in input mode. No on-chip pull-up resistors can be used in the bits set in

output mode in spite of setting PU0. On-chip pull-up resistors cannot be used even when the pins are used

as the alternate-function output pins.

PU0 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears PU0 to 00H.

Figure 4-15. Format of Pull-Up Resistor Option Register 0

Symbol

PU0

7

0

6

0

5

0

4

0

<3>

2

0

<1>

<0>

Address

FFF7H

After reset

00H

R/W

PU03

PU01

PU00

Pm on-chip pull-up resistor selection

(m = 0, 1, 3)

PU0m

0

1

On-chip pull-up resistor not used

On-chip pull-up resistor used

Caution Bits 2, 4 to 7 must all be set to 0.

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4.4 Operation of Port Functions

The operation of a port differs depending on whether the port is set in input or output mode, as described below.

4.4.1 Writing to I/O port

(1) In output mode

A value can be written to the output latch of a port by using a transfer instruction. The contents of the

output latch can be output from the pins of the port.

The data once written to the output latch is retained until new data is written to the output latch.

(2) In input mode

A value can be written to the output latch by using a transfer instruction. However, the status of the port pin

is not changed because the output buffer is OFF.

The data once written to the output latch is retained until new data is written to the output latch.

Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port.

However, this instruction accesses the port in 8-bit units. When this instruction is

executed to manipulate a bit of an input/output port, therefore, the contents of the output

latch of the pin that is set in input mode and not subject to manipulation become

undefined.

4.4.2 Reading from I/O port

(1) In output mode

The contents of the output latch can be read by using a transfer instruction. The contents of the output

latch are not changed.

(2) In input mode

The status of a pin can be read by using a transfer instruction. The contents of the output latch are not

changed.

4.4.3 Arithmetic operation of I/O port

(1) In output mode

An arithmetic operation can be performed with the contents of the output latch. The result of the operation

is written to the output latch. The contents of the output latch are output from the port pins.

The data once written to the output latch is retained until new data is written to the output latch.

(2) In input mode

The contents of the output latch become undefined. However, the status of the pin is not changed because

the output buffer is OFF.

Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port.

However, this instruction accesses the port in 8-bit units. When this instruction is

executed to manipulate a bit of an input/output port, therefore, the contents of the output

latch of the pin that is set in input mode and not subject to manipulation become

undefined

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5.1 Clock Generator Functions

The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two

types of system clock oscillators are used.

• Main system clock oscillator

This circuit oscillates at 2.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or

setting the processor clock control register (PCC).

• Subsystem clock oscillator

This circuit oscillates at 32.768 kHz. Oscillation can be stopped by setting the suboscillation mode register

(SCKM).

5.2 Clock Generator Configuration

The clock generator includes the following hardware.

Table 5-1. Configuration of Clock Generator

Item

Configuration

Control register

Processor clock control register (PCC)

Suboscillation mode register (SCKM)

Subclock control register (CSS)

Oscillator

Main system clock oscillator

Subsystem clock oscillator

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Figure 5-1. Block Diagram of Clock Generator

Internal bus

Suboscillation mode register

(SCKM)

SCC

FRC

Subsystem

clock

oscillator

XT1

XT2

fXT

Watch timer

clock output circuit

LCD controller/driver

Prescaler

1/2

Clock for

peripheral

hardware

Main system

clock

oscillator

X1

X2

fXT

Prescaler

2

f

X

f

X

2²

Standby

controller

Wait

controller

CPU clock

(f^CPU

)

STOP

PCC1

MCC

CLS CSS0

Subclock control

register (CSS)

Processor clock

control register (PCC)

Internal bus

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5.3 Clock Generator Control Registers

The clock generator is controlled by the following register.

• Processor clock control register (PCC)

• Suboscillation mode register (SCKM)

• Subclock control register (CSS)

(1) Processor clock control register (PCC)

PCC sets CPU clock selection and the ratio of division.

PCC is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets PCC to 02H.

Figure 5-2. Format of Processor Clock Control Register

Symbol

PCC

<7>

6

0

5

0

4

0

3

0

2

0

<1>

0

Address

FFFBH

After reset

02H

R/W

MCC

PCC1

MCC

Control of main system clock oscillator operation

0

1

Operation enabled

Operation disabled

CSS0

PCC1

CPU clock (fCPU) selection^Note

0

1

0

1

0

1

f

X

µ

(0.28 s)

2

f

/2 (1.12 s)

µ

f

XT/2 (61 s)

µ

Note The CPU clock is selected according to a combination of the PCC1 flag in the processor clock control

register (PCC) and the CSS0 flag in the subclock control register (CSS). See (3) in Section 5.3.

Cautions 1. Bits 0 and 2 to 6 must all be set to 0.

2. MCC can be set only when the subsystem clock has been selected as the CPU clock.

3. If an external clock pulse is input, do not set MCC, because the X2 pin is pulled up to VDD0 or

VDD1.

Remarks 1. f^X: Main system clock oscillation frequency

2. f^XT: Subsystem clock oscillation frequency

3. The parenthesized values apply to operation at f^X= 3.58 MHz or f^XT= 32.768 kHz.

4. Minimum instruction execution time: 2f^CPU

• f^CPU= 0.28 µs: 0.56 µs

• f^CPU= 1.12 µs: 2.23 µs

• f^CPU= 61 µs: 122 µs

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(2) Suboscillation mode register (SCKM)

SCKM selects a feedback resistor for the subsystem clock, and controls the oscillation of the clock.

SCKM is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears SCKM to 00H.

Figure 5-3. Format of Suboscillation Mode Register

Symbol

SCKM

7

0

6

0

5

0

4

0

3

0

2

0

1

<0>

Address

FFF0H

After reset

00H

R/W

FRC

SCC

FRC

Feedback resistor selection^Note

0

1

On-chip feedback resistor used

On-chip feedback resistor not used

SCC

Control of subsystem clock oscillator ooperation

0

1

Operation enabled

Operation disabled

Note The feedback resistor is necessary to adjust the bias point of the oscillation waveform to close to the mid

point of the supply voltage. Only when the subclock is not used, the power consumption in STOP mode

can be further reduced by setting FRC = 1.

Cautions 1. Bits 2 to 7 must all be set to 0.

2. If an external clock pulse is input, do not set SCC, because the XT2 pin is pulled up to V^DD0

or VDD1.

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(3) Subclock control register (CSS)

CSS specifies whether the main system or subsystem clock oscillator is to be selected. It also specifies

how the CPU clock operates.

CSS is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears CSS to 00H.

Figure 5-4. Format of Subclock Control Register

Symbol

CSS

7

0

6

0

5

4

3

0

2

0

1

0

Address

FFF2H

After reset

00H

R/W

CLS

CSS0

R/W^Note

CLS

0

CPU clock operation status

Operation based on the output of the divided main system clock

Operation based on the subsystem clock

1

CSS0

Selection of main system or subsystem clock oscillator

Divided output from the main system clock oscillator

Output from the subsystem clock oscillator

0

1

Note Bit 5 is read-only.

Caution Bits 0 to 3, 6, and 7 must all be set to 0.

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5.4 System Clock Oscillators

5.4.1 Main system clock oscillator

The main system clock oscillator is oscillated by the crystal or ceramic resonator (3.58 MHz TYP.) connected

across the X1 and X2 pins.

An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the

reversed signal to the X2 pin.

Figure 5-5 shows the external circuit of the main system clock oscillator.

Figure 5-5. External Circuit of Main System Clock Oscillator

(a) Crystal or ceramic oscillation

(b) External clock

External

clock

V

SS0

X1

X2

Crystal

or

ceramic resonator

Cautions 1. If an external clock pulse is input, do not set the STOP instruction and MCC (bit 7 of the

processor clock control register (PCC)) to 1, because doing so stops the main system clock,

thus causing the X2 pin to be pulled up to VDD0 or VDD1.

2. When using the main system clock oscillator and subsystem clock oscillator, wire as

follows in the area enclosed by the broken lines in Figures 5-5 and 5-6 to avoid an adverse

effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with other signal lines. Do not route the wiring near a signal line

through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS0. Do

not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

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5.4.2 Subsystem clock oscillator

The subsystem clock oscillator is oscillated by the crystal resonator (32.768 kHz TYP.) connected across the

XT1 and XT2 pins.

An external clock can also be input to the circuit. In this case, input the clock signal to the XT1 pin, and input the

reversed signal to the XT2 pin.

Figure 5-6 shows the external circuit of the subsystem clock oscillator.

Figure 5-6. External Circuit of Subsystem Clock Oscillator

(a) Crystal oscillation

(b) External clock

External

clock

V

XT1

SS0

XT1

32.768

kHz

XT2

Cautions 1. If an external clock pulse is input, do not set the SCC (bit 0 of the suboscillation mode

register (SCKM)) to 1, because doing so causes the subsystem clock oscillator to stop

operating, thus causing the XT2 pin to be pulled up to V^DD0or VDD1.

2. When using the main system clock oscillator and subsystem clock oscillator, wire as

follows in the area enclosed by the broken lines in Figures 5-5 and 5-6 to avoid an adverse

effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with other signal lines. Do not route the wiring near a signal line

through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS0. Do

not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

When using the subsystem clock, pay special attention because the subsystem clock oscillator has low

amplification to minimize current consumption.

Figure 5-7 shows incorrect resonator connections.

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Figure 5-7. Example of Incorrect Resonator Connection (1/2)

(a) Wiring too long

(b) Crossed signal line

PORTn

(n = 0 to 5)^Note

V

SS0

X1

X2

VSS0

X1

X2

Note PORT4 is not provided to the µPD789830.

(c) Wiring near high alternating current

(d) Current flowing through ground line of oscillator

(potential at points A, B, and C fluctuates)

V

DD

P

mn

X1

X2

VSS0

V

SS0

X1

X2

High current

A

B

C

High current

Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a

resistor to the XT2 in series.

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Figure 5-7. Example of Incorrect Resonator Connection (2/2)

(e) Signal is extracted

X1

X2

VSS0

Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a

resistor to the XT2 in series.

5.4.3 Frequency divider

The frequency divider divides the main system clock oscillator output (f^X) and generates clocks.

5.4.4 When no subsystem clocks are used

If it is not necessary to use subsystem clocks for low power consumption operations and clock operations,

connect the XT1 and XT2 pins as follows.

XT1: Connect to V^SS0or V^SS1

XT2: Open

In this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator

when the main system clock stops. To minimize the leakage current, the above internal feedback resistor can be

removed by setting bit 1 (FRC) of the suboscillation mode register (SCKM). In this case, also connect the XT1 and

XT2 pins as described above.

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5.5 Clock Generator Operation

The clock generator generates the following clocks and controls operation modes of the CPU, such as standby

mode:

• Main system clock

• Subsystem clock

• CPU clock

f^X

fXT

fCPU

• Clock to peripheral hardware

The operation of the clock generator is determined by the processor clock control register (PCC), suboscillation

mode register (SCKM), and subclock control register (CSS), as follows.

(a) The slow mode 2f^CPU(2.23 µs: at 3.58 MHz operation) of the main system clock is selected when the

RESET signal is generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of

the main system clock is stopped.

(b) Three types of CPU clocks f^CPU(0.28 µs and 1.12 µs: main system clock (at 3.58 MHz operation), 61

µs: subsystem clock (at 32.768 kHz operation)) can be selected by the PCC, SCKM, and CSS

settings.

(c) Two standby modes, STOP and HALT, can be used with the main system clock selected. In a system

where no subsystem clock is used, setting bit 1 (FRC) of SCKM so that the on-chip feedback resistor

cannot be used reduces current drain during STOP mode. In a system where a subsystem clock is

used, setting SCKM bit 0 to 1 can cause the subsystem clock to stop oscillation.

(d) CSS bit 4 (CSS0) can be used to select the subsystem clock so that low power dissipation operation is

used (at 122 µs, 32.768 kHz operation).

(e) With the subsystem clock selected, it is possible to cause the main system clock to stop oscillating

according to bit 7 (MCC) of PCC. HALT mode can be used, but STOP mode cannot.

(f) The clock pulse for the peripheral hardware is generated by dividing the frequency of the main system

clock. The subsystem clock pulse is supplied to the clock output circuit, LCD controller/driver, and

watch timer only. So, also at standby, the clock output circuit, LCD controller/driver, and clock function

can keep running. The other hardware stops when the main system clock stops, because it runs

based on the main system clock (except for external clock pulses).

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5.6 Changing Setting of System Clock and CPU Clock

5.6.1 Time required for switching between system clock and CPU clock

The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit 4

(CSS0) of the subclock control register (CSS).

Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old

clock is used for the duration of several instructions after that (see Table 5-2).

Table 5-2. Maximum Time Required for Switching CPU Clock

Set Value Before Switching

Set Value After Switching

CSS0

PCC1

CSS0

0

PCC1

0

CSS0

0

PCC1

1

CSS0

1

PCC1

×

0

1

×

4 clocks

2 clocks

2f^X/f^XTclocks

(219 clocks)

2 clocks

f^X/2f^XTclocks

(55 clocks)

1

Remarks 1. Two clocks are the minimum instruction execution time of the CPU clock before switching.

2. The parenthesized values apply to operation at f^X= 3.58 MHz or f^XT= 32.768 kHz.

3. ×: Don't care

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CHAPTER 5 CLOCK GENERATOR

5.6.2 Switching between system clock and CPU clock

The following figure illustrates how the CPU clock and system clock switch.

Figure 5-8. Switching Between System Clock and CPU Clock

V

DD

RESET

Interrupt request signal

f

X

f

X

f

XT

f

X

System clock

CPU clock

Slow

operation

Fast operation

Subsystem clock

operation

Wait (9.15 ms: at 3.58 MHz operation)

Internal reset operation

<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is

released when the RESET pin is later made high, and the main system clock starts oscillating. At this time,

the time during which oscillation stabilizes (2¹⁵/f^X) is automatically secured.

After that, the CPU starts instruction execution at the slow speed of the main system clock (2.23 µs: at

3.58 MHz operation).

<2> After the time required for the V^DDvoltage to rise to the level at which the CPU can operate at the high

speed has elapsed, bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the

subclock control register (CSS) are rewritten so that the high-speed operation can be selected.

<3> A drop of the V^DDvoltage is detected with an interrupt request signal. The clock is switched to the

subsystem clock. (At this moment, the subsystem clock must be in the oscillation stabilized status.)

<4> A recover of the V^DDvoltage is detected with an interrupt request signal. Bit 7 (MCC) of PCC is set to 0,

and then the main system clock starts oscillating. After the time required for the oscillation to stabilize has

elapsed, PCC1 and CSS0 are rewritten so that high-speed operation can be selected again.

Caution When the main system clock is stopped and the subsystem clock is operating, allow

sufficient time for the oscillation to stabilize by coding the program before switching

again from the subsystem clock to the main system clock.

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CHAPTER 6 16-BIT TIMER 40

6.1 16-Bit Timer 40 Functions

16-bit timer 40 has the following functions.

(1) Interval timer

This timer generates an interrupt (INTTM40) if the TM40 count matches the comparison value.

Table 6-1. Interval Time of 16-Bit Timer 40

Minimum Interval Time

1/f^X(0.28 µs)

2²/f^X(1.12 µs)

2⁵/f^X(8.94 µs)

2¹⁰/f^X(286.0 µs)

Maximum Interval Time

2¹⁶/f^X(18.3 ms)

Resolution

1/f^X(0.28 µs)

2²/f^X(1.12 µs)

2⁵/f^X(8.94 µs)

2¹⁸/f^X(73.2 ms)

2²¹/f^X(585.8 ms)

2²⁶/f^X(18.7 s)

2¹⁰/f^X(286.0 µs)

Remarks 1. f^X: Main system clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 3.58 MHz.

(2) Free-running timer

This timer generates an interrupt (INTTM41) upon the occurrence of a timer overflow.

6.2 16-Bit Timer 40 Configuration

16-bit timer 40 includes the following hardware.

Table 6-2. 16-Bit Timer 40 Configuration

Item

Timer counter

Register

Configuration

16 bits × 1 (TM40)

Compare register: 16 bits × 1 (CR40)

Timer 40 control register (TMC40)

Control register

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CHAPTER 6 16-BIT TIMER 40

Figure 6-1. Block Diagram of 16-Bit Timer 40

INTTM41

Overflow controller

Clear

fX

f

X

/2²

/2⁵

16-bit timer counter 40

(TM40)

fX

OVF

f

X

/2¹⁰

Match

INTTM40

INTTM4

16-bit compare counter 40

(CR40)

2

TCE40 TMM40 OVF40 TCL401 TCL400

Timer 40 control register (TMC40)

Internal bus

(1) 16-bit compare register 40 (CR40)

A value specified in CR40 is compared with the count in 16-bit timer counter 40 (TM40). If they match, an

interrupt request (INTTM40) is issued.

CR40 is set with a 16-bit memory manipulation instruction^Note. Any value from 0000H to FFFFH can be set.

RESET input sets CR40 to 0000H.

Note For CR40, 16-bit access can be performed only in short direct addressing.

Cautions 1. Do not write to CR40 during the count operation; otherwise the timer counter may not

operate normally.

2. When the 16-bit timer is used as a free-running timer, do not set CR40 to 0000H or FFFEH;

otherwise noise may be superimposed on the interrupt request signal (INTTM4).

3. If CR40 is overwritten during a count operation, prevent this from recurring by setting

interrupt mask flag registers 0 and 1 (MK0 and MK1) to disable interrupts. If CR40 is

overwritten while interrupts are enabled, an interrupt request may be issued at the point of

overwrite.

(2) 16-bit timer counter 40 (TM40)

TM40 is a 16-bit register used to count the number of pulses.

TM40 cannot be read from or written to.

TM40 is cleared to 0000H:

• when a RESET signal is input;

• when TCE40 (bit 7 of the timer 40 control register (TMC40)) is 0;

• immediately after the TM40 count matches the CR40 comparison value in clear and start mode (TMM40 (bit 6

of TMC40) = 0); or

• immediately after a TM40 overflow occurs in free-running mode (TMM40 = 1).

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CHAPTER 6 16-BIT TIMER 40

6.3 16-Bit Timer 40 Control Register

The following register is used to control 16-bit timer 40.

• Timer 40 control register (TMC40)

(1) Timer 40 control register (TMC40)

TMC40 controls the count clock and operation mode settings of 16-bit timer 40.

TMC40 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears TMC40 to 00H.

Figure 6-2. Format of Timer 40 Control Register

Symbol

TMC40

<7>

6

5

0

4

0

<3>

2

0

1

0

Address

FF5BH

After reset

00H

R/W

TCE40

TMM40

OVF40

TCL401 TCL400

R/W^Note

TCE40

16-bit timer 40 count operation control

0

1

TM40 count operation disabled (TM40 = 0000H)

TM40 count operation enabled

TMM40

16-bit timer 40 operation mode control

0

1

Clear (immediately after TM40 matches CR40) and start mode

Free-running mode

OVF40

Overflow status

A timer overflow occurs when OVF40 is 1.

0

1

A timer overflow occurs when OVF40 is 0.

TCL401 TCL400

16-bit timer 40 count clock selection

0

1

0

1

0

1

f

X (3.58 MHz)

X

/2²(895 kHz)

X

/2⁵(112 kHz)

X

/2¹⁰(3.50 kHz)

Note Bit 3 is read-only.

Cautions 1. Bits 2, 4, and 5 must be fixed to 0.

2. Do not write to TMM40, TCL400, or TCL401 while the timer is operating. To write to these

bits, first stop the TM40 count operation (TCE40 = 0).

Remarks 1. f^X: Main system clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 3.58 MHz.

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CHAPTER 6 16-BIT TIMER 40

6.4 16-Bit Timer 40 Operation

6.4.1 Operation as interval timer

The interval timer can repeatedly generate an interrupt at intervals specified by the preset count value of 16-bit

compare register 40 (CR40).

To operate 16-bit timer 40 as an interval timer, the following settings are required.

• Set count values to CR40.

• Set timer 40 control register (TMC40) as shown in Figure 6-3.

Figure 6-3. Settings of Timer 40 Control Register at Interval Timer Operation

TCE40 TMM40

TCL401 TCL400

TMC40

1

0

0/1

Setting of count clock

Setting of clear & start mode

Enables operation of 16-bit

timer counter 40 (TM40)

When the count value of 16-bit timer counter 40 (TM40) matches the set value of CR40, the value of TM40 is

cleared to 0000H, TM40 continues counting, and an interrupt request signal (INTTM40) is generated.

Table 6-3 shows interval time, and Figure 6-4 shows timing of interval timer operation.

Cautions 1. When using 16-bit timer 40 as an interval timer, set 16-bit timer 40 to clear & start mode

(TMM40 = 0).

2. Be sure to execute the following processing when rewriting the value in CR40 during a

count operation.

• Set interrupt disabled (set TMMK40 (bit 7 of interrupt mask flag register 0 (MK0)) to 1).

If the value in CR40 is rewritten in the interrupt-enabled state, an interrupt request may

occur at the moment of rewrite.

Table 6-3. Interval Time of 16-Bit Timer 40

TCL400

TCL401

Minimum Interval Time

1/f^X(0.28 µs)

2²/f^X(1.12 µs)

2⁵/f^X(8.94 µs)

2¹⁰/f^X(286 µs)

Maximum Interval Time

2¹⁶/f^X(18.3 ms)

Resolution

1/f^X(0.28 µs)

2²/f^X(1.12 µs)

2⁵/f^X(8.94 µs)

2¹⁰/f^X(286 µs)

0

1

0

1

0

1

2¹⁸/f^X(73.2 ms)

2²¹/f^X(586 ms)

2²⁶/f^X(18.7 s)

Remarks 1. fX : Main system clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 3.58 MHz.

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CHAPTER 6 16-BIT TIMER 40

Figure 6-4. Operating Timing of 16-Bit Timer 40 Used as Interval Timer

t

Count clock

TM40 count value

0000

0001

N

0000 0001

Clear

N

0000 0001

Clear

N

CR40

N

TCE40

Count start

INTTM40

Interrupt acknowledgement

Interval time

Interrupt acknowledgement

Interval time

Remark Interval time = (N + 1) × t: N = 0000H to FFFFH

6.4.2 Operation as free-running timer

The free-running timer can repeatedly generate interrupts at the value set to 16-bit compare register 40 (CR40) in

advance based on the intervals of the value set in TCL400 and TCL401.

To operate 16-bit timer 40 as a free-running timer, the following settings are required.

• Set the count value to CR40

• Set timer 40 control register (TMC40) as shown in Figure 6-5

Figure 6-5. Settings of Timer 40 Control Register at Free-Running Timer Operation

TCE40 TMM40

TCL401 TCL400

OVF40

-

TMC40

1

0

0/1

0

Setting of count clock

Setting of free-running mode

Enables operation of 16-bit timer

counter 40 (TM40)

When the count value of 16-bit timer counter 40 (TM40) matches the set value of CR40, TM40 continues

counting, and an interrupt request signal (INTTM40) is generated. If TM40 continues counting and an overflow

occurs as a result, another interrupt request signal (INTTM41) is generated. In addition, an interrupt request signal

(INTTM4) is generated as a result of a logical OR between INTTM40 and INTTM41.

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CHAPTER 6 16-BIT TIMER 40

Cautions 1. When using 16-bit timer 40 as a free-running timer, set 16-bit timer 40 to free-running mode

(TMM40 = 1).

2. When CR40 is set to FFFFH, the interrupt request signal (INTTM40) cannot be generated.

3. When 16-bit timer 40 is used as a free-running timer, do not set CR40 to 0000H or FFFEH;

otherwise noise may be superimposed on the interrupt request signal (INTTM4).

Figure 6-6 shows the operating timing of the free-running timer.

Figure 6-6. Operating Timing of 16-Bit Timer 40 Used as Free-Running Timer

t

Count clock

TM40 count value

0000 0001

N

N+1

FFFF 0000

Clear

N

N+1

FFFF 0000

Clear

N

N+1

N

CR40

N

TCE40

Count start

INTTM40

Interrupt acknowledgement

INTTM41

INTTM4

OVF40

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CHAPTER 6 16-BIT TIMER 40

6.5 Notes on Using 16-Bit Timer 40

(1) Error on starting timer

An error of up to 1 clock occurs after the timer has been started until a match signal is generated. This is

because 16-bit timer counter 40 (TM40) is started asynchronously to the count pulse.

Figure 6-7. Start Timing of 16-Bit Timer Counter 40

Count pulse

TM40

0000H

0001H

0002H

0003H

0004H

count value

Timer start

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CHAPTER 7 8-BIT TIMER 00

7.1 8-Bit Timer 00 Functions

8-bit timer 00 has the following function.

(1) Interval timer

When 8-bit timer 00 is used as an interval timer, it generates an interrupt at any time intervals set in

advance.

Table 7-1. Interval Time of 8-Bit Timer 00

Minimum Interval Time

1/f^X(0.28 µs)

2⁵/f^X(8.94 µs)

Maximum Interval Time

2⁸/f^X(71.5 µs)

2¹³/f^X(2.23 ms)

Resolution

1/f^X(0.28 µs)

2⁵/f^X(8.94 µs)

Remarks 1. f^X: Main system clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 3.58 MHz.

7.2 8-Bit Timer 00 Configuration

8-bit timer 00 includes the following hardware.

Table 7-2. Configuration of 8-Bit Timer 00

Configuration

Item

Timer counter

Register

8 bits × 1 (TM00)

Compare register: 8 bits × 1 (CR00)

8-bit timer control register 00 (TMC00)

Control register

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CHAPTER 7 8-BIT TIMER 00

Figure 7-1. Block Diagram of 8-Bit Timer 00

Internal bus

8-bit compare register 00

(CR00)

Match

INTTM00

fX

8-bit timer counter 00

(TM00)

f

/2⁵

X

Clear

Selector

TCE00 TCL00

8-bit timer mode control register 00

(TMC00)

Internal bus

(1) 8-bit compare register 00 (CR00)

This is an 8-bit register to compare the value set to CR00 with 8-bit timer counter 00 (TM00) count value,

and if they match, generates an interrupt request (INTTM00).

CR00 is set with an 8-bit memory manipulation instruction. The 00H to FFH values can be set.

RESET input makes CR00 undefined.

Caution Stop the timer operation before rewriting CR00; otherwise the match interrupt request

signal may be generated immediately.

(2) 8-bit timer counter 00 (TM00)

This is an 8-bit register to count pulses.

TM00 is read with an 8-bit memory manipulation instruction.

RESET input clears TM00 to 00H.

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CHAPTER 7 8-BIT TIMER 00

7.3 8-Bit Timer 00 Control Registers

The following register is used to control 8-bit timer 00.

• 8-bit timer mode control register 00 (TMC00)

(1) 8-bit timer mode control register 00 (TMC00)

This is a register used to enable or disable operation of 8-bit timer counter 00 (TM00) and set the count

clock of 8-bit timer 00.

TMC00 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears TMC00 to 00H.

Figure 7-2. 8-Bit Timer Mode Control Register 00 Format

Symbol

<7>

6

0

5

0

4

0

3

0

2

0

1

0

Address After reset

FF53H 00H

R/W

TMC00 TCE00

TCL00

TCE00

8-bit timer 00 count operation control

0

1

Operation disabled (TM00 is cleared to 0.)

Operation enabled

TCL00

8-bit timer 00 operation mode control

0

1

f^X(3.58 MHz)

f^X/2⁵(112 kHz)

Caution Always stop the timer before setting TMC00.

Remarks 1. f^X: Main system clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 3.58 MHz.

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CHAPTER 7 8-BIT TIMER 00

7.4 8-Bit Timer 00 Operation

7.4.1 Operation as interval timer

The interval timer repeatedly generates an interrupt at time intervals specified by the count value set to 8-bit

compare register 00 (CR00) in advance.

To operate 8-bit timer 00 as an interval timer, the following settings are required.

• Set count values to CR00.

• Set 8-bit timer mode control register 00 (TMC00) as shown in Figure 7-3.

Figure 7-3. Settings of 8-Bit Timer Mode Control Register 00 in Interval Timer Operation

TCE00

1

TCL00

0/1

TMC00

0

Setting of count clock

Enables operation of 8-bit

timer counter 00 (TM00)

When the count value of 8-bit timer counter 00 (TM00) matches the value set to CR00, the value of TM00 is

cleared to 00H and TM00 continues counting. At the same time, an interrupt request signal (INTTM00) is generated.

Table 7-3 shows interval time, and Figure 7-4 shows the timing of interval timer operation.

Table 7-3. Interval Time of 8-Bit Timer 00

TCL00

Minimum Interval Time

1/f^X(0.28 µs)

2⁵/f^X(8.94 µs)

Maximum Interval Time

2⁸/f^X(71.5 µs)

2¹³/f^X(2.23 ms)

Resolution

1/f^X(0.28 µs)

2⁵/f^X(8.94 µs)

0

1

Remarks 1. f^X: Main system clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 3.58 MHz.

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CHAPTER 7 8-BIT TIMER 00

Figure 7-4. Operating Timing of 8-Bit Timer 00 Used as Interval Timer

t

Count clock

TM00 count value

00

01

N

00

01

N

00

01

N

Clear

CR00

N

TCE00

Count start

INTTM00

Interrupt acknowledgement

Interval time

Interrupt acknowledgement

Interval time

Remark Interval time = (N + 1) × t: N = 00H to FFH

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CHAPTER 7 8-BIT TIMER 00

7.5 Notes on Using 8-Bit Timer 00

(1) Error on starting timer

An error of up to 1 clock occurs after the timer has been started until a match signal is generated. This is

because 8-bit timer counter 00 (TM00) is started asynchronously to the count pulse.

Figure 7-5. Start Timing of 8-Bit Timer Counter 00

Count pulse

TM00 count value

00H

01H

02H

03H

04H

Timer start

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CHAPTER 8 WATCH TIMER

8.1 Watch Timer Functions

The watch timer has the following functions.

• Watch timer

• Interval timer

The watch and interval timers can be used at the same time.

Figure 8-1 is a block diagram of the watch timer.

Figure 8-1. Block Diagram of Watch Timer

Clear

f

/2⁷

X

5-bit counter

INTWT

INTWTI

9-bit prescaler

f

W

f

W

f

W

f

W

f

W

f

W

f

W

2⁹

Clear

2⁴2⁵2⁶2⁷2⁸

f

XT

WTM7 WTM6 WTM5 WTM4

0

WTM1 WTM0

Watch timer mode

control register (WTM)

Internal bus

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CHAPTER 8 WATCH TIMER

(1) Watch timer

The 4.19 MHz main system clock or 32.768 kHz subsystem clock is used to issue an interrupt request

(INTWT) at 0.5-second intervals.

Caution When the main system clock is operating at 3.58 MHz, it cannot be used to generate a 0.5-

second interval. In this case, the subsystem clock, which operates at 32.768 kHz, should

be used instead.

(2) Interval timer

The interval timer is used to generate an interrupt request (INTWTI) at specified intervals.

Table 8-1. Interval Generated Using Interval Timer

Interval

2⁴× 1/f^W

At f^X= 3.58 MHz

572 µs

At f^X= 4.19 MHz

489 µs

At f^XT= 32.768 kHz

488 µs

2⁵× 1/f^W

2⁶× 1/f^W

2⁷× 1/f^W

2⁸× 1/f^W

2⁹× 1/f^W

1.14 ms

2.29 ms

4.58 ms

9.15 ms

18.3 ms

978 µs

977 µs

1.96 ms

3.91 ms

7.82 ms

15.6 ms

1.95 ms

3.91 ms

7.81 ms

15.6 ms

Remark f^W: Watch timer clock frequency (f^X/2⁷or f^XT)

f^X: Main system clock oscillation frequency

f^XT: Subsystem clock oscillation frequency

8.2 Watch Timer Configuration

The watch timer includes the following hardware.

Table 8-2. Watch Timer Configuration

Configuration

Item

Counter

5 bits × 1

Prescaler

9 bits × 1

Control register

Watch timer mode control register (WTM)

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CHAPTER 8 WATCH TIMER

8.3 Watch Timer Control Register

The following register is used to control the watch timer.

•

Watch timer mode control register (WTM)

WTM selects a count clock for the watch timer and specifies whether to enable clocking of the timer. It also

specifies the prescaler interval and how the 5-bit counter is controlled.

WTM is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears WTM to 00H.

Figure 8-2. Format of Watch Timer Mode Control Register

Symbol

WTM

7

6

5

4

3

0

2

0

<1>

<0>

Address

FF4AH

After reset

00H

R/W

WTM7

WTM6

WTM5

WTM4

WTM1

WTM0

WTM7

Watch timer count clock selection

f

X

/2⁷(27.9 kHz)

0

1

f

^XT(32.768 kHz)

WTM6

WTM5

WTM4

Prescaler interval selection

2⁴/f

2⁵/f

2⁶/f

2⁷/f

2⁸/f

2⁹/f

W

0

1

0

1

0

1

0

1

0

1

Other than above

Setting prohibited

WTM1

Control of 5-bit counter operation

0

1

Cleared after stop

Started

WTM0

Watch timer operation

0

1

Operation disabled (both prescaler and timer cleared)

Operation enabled

Remarks 1. f^W: Watch timer clock frequency (f^X/2⁷or f^XT)

2. f^X: Main system clock oscillation frequency

3. f^XT: Subsystem clock oscillation frequency

4. The parenthesized values apply to operation at f^X= 3.58 MHz or f^XT= 32.768 kHz.

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CHAPTER 8 WATCH TIMER

8.4 Watch Timer Operation

8.4.1 Operation as watch timer

The main system clock (4.19 MHz: ceramic/crystal oscillation) or subsystem clock (32.768 kHz) is used as a

watch timer which generates 0.5-second intervals.

The watch timer is used to generate an interrupt request at specified intervals.

The watch timer starts counting by setting bits 0 and 1 (WTM0 and WTM1) of the watch timer mode control

register (WTM) to 1. By setting them to 0, the 5-bit counter is cleared and the watch timer stops counting.

Only the watch timer can be started form zero seconds by clearing WTM1 to 0 when the interval timer and watch

timer operate at the same time. In this case, however, an error of up to 2⁹× 1/f^Wmay occur in the overflow (INTWT)

after the zero-second start of the watch timer because the 9-bit prescaler is not cleared to 0.

8.4.2 Operation as interval timer

The interval timer is used to repeatedly generate an interrupt request at the interval specified by a count value

set in advance.

The interval timer can be selected by bits 4 to 6 (WTM4 to WTM6) of the watch timer mode control register

(WTM).

Table 8-3. Interval Generated Using Interval Timer

WTM6

WTM5

WTM4

Interval

2⁴× 1/f^W

2⁵× 1/f^W

2⁶× 1/f^W

2⁷× 1/f^W

2⁸× 1/f^W

2⁹× 1/f^W

At f^X= 3.58 MHz

572 µs

At f^XT= 32.768 kHz

488 µs

0

1

0

1

0

1

0

1

0

1

1.14 ms

2.29 ms

4.58 ms

9.15 ms

18.3 ms

977 µs

1.95 ms

3.91 ms

7.81 ms

15.6 ms

Other than above

Setting prohibited

Remark f^X: Main system clock oscillation frequency

f^XT: Subsystem clock oscillation frequency

f^W: Watch timer clock frequency (f^X/2⁷or f^XT)

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CHAPTER 8 WATCH TIMER

Figure 8-3. Watch Timer/Interval Timer Operation Timing

5-bit counter

0H

Overflow

Start

Overflow

Count clock

/2⁹

f

W

Watch timer

interrupt

INTWT

Watch timer interrupt time (0.5 s)

Interval timer

interrupt

INTWTI

Interval

T

timer (T)

Remark f^W: Watch timer clock frequency

The parenthesized values apply to operation at f^W= 32.768 kHz.

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CHAPTER 9 WATCHDOG TIMER

9.1 Watchdog Timer Functions

The watchdog timer has the following functions.

• Watchdog timer

• Interval timer

Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode

register (WDTM).

(1) Watchdog timer

The watchdog timer is used to detect inadvertent program loops. When an inadvertent loop is detected, a

non-maskable interrupt request or the RESET signal can be generated.

Table 9-1. Inadvertent Loop Detection Time of Watchdog Timer

Inadvertent Loop Detection Time

2¹¹× 1/f^X

At f^X= 3.58 MHz

572 µs

2¹³× 1/f^X

2¹⁵× 1/f^X

2¹⁷× 1/f^X

2.29 ms

9.15 ms

36.6 ms

f^X: Main system clock oscillation frequency

(2) Interval timer

The interval timer generates an interrupt at a given interval set in advance.

Table 9-2. Interval Time

Interval

At f^X= 3.58 MHz

2¹¹× 1/f^X

2¹³× 1/f^X

2¹⁵× 1/f^X

2¹⁷× 1/f^X

572 µs

2.29 ms

9.15 ms

36.6 ms

f^X: Main system clock oscillation frequency

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CHAPTER 9 WATCHDOG TIMER

9.2 Watchdog Timer Configuration

The watchdog timer includes the following hardware.

Table 9-3. Configuration of Watchdog Timer

Configuration

Item

Control register

Timer clock selection register 2 (TCL2)

Watchdog timer mode register (WDTM)

Figure 9-1. Block Diagram of Watchdog Timer

Internal bus

f

X

2⁴

TMMK4

Prescaler

f

X

2⁶

f

X

2⁸

f

X

2¹⁰

RUN

Clear

7-bit counter

INTWDT

maskable

TMIF4

interrupt request

RESET

INTWDT

non-maskable

interrupt request

3

TCL22 TCL21 TCL20

WDTM4 WDTM3

Timer clock selection register 2

(TCL2)

Watchdog timer mode register (WDTM)

Internal bus

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CHAPTER 9 WATCHDOG TIMER

9.3 Watchdog Timer Control Registers

The following two types of registers are used to control the watchdog timer.

•

Timer clock selection register 2 (TCL2)

Watchdog timer mode register (WDTM)

(1) Timer clock selection register 2 (TCL2)

This register sets the watchdog timer count clock.

TCL2 is set with an 8-bit memory manipulation instruction.

RESET input clears TCL2 to 00H.

Figure 9-2. Format of Timer Clock Selection Register 2

Symbol

TCL2

7

0

6

0

5

0

4

0

3

0

2

1

0

Address

FF42H

After reset

00H

R/W

TCL22

TCL21

TCL20

TCL22

TCL21

TCL20

Interval

Watchdog timer count clock selection

/2⁴(223.8 kHz)

2¹¹/f

2¹³/f

2¹⁵/f

2¹⁷/f

X

(572 µs)

fX

0

1

0

1

0

1

0

/2⁶(55.9 kHz)

(2.29 ms)

(9.15 ms)

(36.6 ms)

/2⁸(14.0 kHz)

/2¹⁰(3.50 kHz)

Other than above

Setting prohibited

Remarks 1. f^X: Main system clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 3.58 MHz.

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(2) Watchdog timer mode register (WDTM)

This register sets an operation mode of the watchdog timer, and enables/disables counting of the watchdog

timer.

WDTM is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears WDTM to 00H.

Figure 9-3. Format of Watchdog Timer Mode Register

Symbol

WDTM

<7>

6

0

5

0

4

3

2

0

1

0

Address

FFF9H

After reset

00H

R/W

RUN

WDTM4 WDTM3

Watchdog timer operation selection^{Note 1}

RUN

0

1

Stops counting.

Clears counter and starts counting.

Watchdog timer operation mode selection^{Note 2}

WDTM4 WDTM3

0

1

0

1

0

1

Operation stop

Interval timer mode (overflow and maskable interrupt occur)^{Note 3}

Watchdog timer mode 1 (overflow and non-maskable interrupt occur)

Watchdog timer mode 2 (overflow occurs and reset operation started)

Notes 1. Once RUN has been set to 1, it cannot be cleared to 0 by software. Therefore, when counting is

started, it cannot be stopped by any means other than RESET input.

2. Once WDTM3 and WDTM4 have been set to 1, they cannot be cleared to 0 by software.

3. The watchdog timer starts operations as an interval timer when RUN is set to 1.

Cautions 1. When the watchdog timer is cleared by setting 1 to RUN, the actual overflow time is up

to 0.8% shorter than the time set by timer clock selection register 2 (TCL2).

2. In watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming the WDTIF (bit 0 of

interrupt request mask flag register 0 (IF0)) being set to 0. When watchdog timer mode

1 or 2 is selected under the condition where WDTIF is 1, a non-maskable interrupt

occurs at the completion of rewriting.

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9.4 Watchdog Timer Operation

9.4.1 Operation as watchdog timer

The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode

register (WDTM) is set to 1.

The count clock (inadvertent loop detection time interval) of the watchdog timer can be selected by bits 0 to 2

(TCL20 to TCL22) of timer clock selection register 2 (TCL2). By setting bit 7 (RUN) of WDTM to 1, the watchdog

timer is started. Set RUN to 1 within the set inadvertent loop detection time interval after the watchdog timer has

been started. By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and

the inadvertent loop detection time is exceeded, the system is reset or a non-maskable interrupt is generated by the

value of bit 3 (WDTM3) of WDTM.

The watchdog timer continues operation in HALT mode, but stops in STOP mode. Therefore, set RUN to 1

before entering STOP mode to clear the watchdog timer, and then execute the STOP instruction.

Caution The actual inadvertent loop detection time may be up to 0.8% shorter than the set time.

Table 9-4. Inadvertent Loop Detection Time of Watchdog Timer

TCL22

TCL21

TCL20

Inadvertent Loop Detection Time

At f^X= 3.58 MHz

572 µs

0

1

0

1

0

1

0

2¹¹× 1/f^X

2¹³× 1/f^X

2¹⁵× 1/f^X

2¹⁷× 1/f^X

2.29 ms

9.15 ms

36.6 ms

f^X: Main system clock oscillation frequency

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CHAPTER 9 WATCHDOG TIMER

9.4.2 Operation as interval timer

When bits 4 and 3 (WDTM4 and WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1,

respectively, the watchdog timer also operates as an interval timer that repeatedly generates an interrupt at intervals

specified by a count value set in advance.

Select a count clock (or interval) by setting bits 0 to 2 (TCL20 to TCL22) of timer clock selection register 2

(TCL2). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set to 1.

In interval timer mode, the interrupt mask flag (WDTMK: bit 0 of interrupt mask flag register 0 (MK0)) is valid, and

a maskable interrupt (INTWDT) can be generated. The priority of INTWDT is set as the highest of all the maskable

interrupts.

The interval timer continues operation in HALT mode, but stops in STOP mode. Therefore, set RUN to 1 before

entering STOP mode to clear the interval timer, and then execute the STOP instruction.

Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when watchdog timer mode is selected), interval

timer mode is not set, unless the RESET signal is input.

2. The interval time immediately after the setting by WDTM may be up to 0.8% shorter than the

set time.

Table 9-5. Interval Time of Interval Timer

TCL22

TCL21

TCL20

Interval

At f^X= 3.58 MHz

572 µs

0

1

0

1

0

1

0

2¹¹× 1/f^X

2¹³× 1/f^X

2¹⁵× 1/f^X

2¹⁷× 1/f^X

2.29 ms

9.15 ms

36.6 ms

f^X: Main system clock oscillation frequency

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CHAPTER 10 CLOCK OUTPUT CIRCUIT

10.1 Clock Output Circuit Functions

The clock output circuit (PBU) has the following functions.

(1) PCL output

Pulse clocks are output from the PCL/P23 pin, and are supplied to peripheral LSIs.

(2) Buzzer output

A signal having the buzzer frequency is output from the BUZ/P22/INTP2 pin.

10.2 Clock Output Circuit Configuration

Figure 10-1 is a block diagram of the clock output circuit (PBU).

Figure 10-1. Block Diagram of Clock Output Circuit

Internal bus

PCL/BUZ control register 0

(PBS0)

BZOE0 BCS01 BCS00 CLOE0 CSS01 CSS00

2

f

X

/2⁹

BUZ/P22/

INTP2

f

X

/2¹⁰

PCL/P23

f

X

f

X

/2

f

X

/2²

f

XT

P23

P22

PM23

PM22

Output latch Output latch

Internal bus

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CHAPTER 10 CLOCK OUTPUT CIRCUIT

10.3 Clock Output Circuit Control Registers

The following two types of registers are used to control the clock output circuit (PBU).

•

PCL/BUZ control register 0 (PBS0)

Port mode register 2 (PM2)

(1) PCL/BUZ control register 0 (PBS0)

PBS0 controls clock pulse output and buzzer output.

PBS0 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears PBS0 to 00H.

Figure 10-2. Format of PCL/BUZ Control Register 0

Symbol

<7>

6

5

<4>

3

0

2

0

1

0

Address

FF40H

After reset

00H

R/W

PBS0 BZOE0

BCS01

BCS00 CLOE0

CSS01

CSS00

BZOE0

Buzzer output control

0

1

Clock divider operation and buzzer output disabled

Clock divider operation and buzzer output enabled

BCS01

Count clock selection

0

1

Count clock selected by BCS00 (bit 5 of PBS0)

BCS00-selected count clock divided-by-4

BCS00

Buzzer count clock selection

/2⁹(6.9 kHz)

/2¹⁰(3.5 kHz)

0

1

f

X

f

CLOE0

Pulse clock output control

0

1

Pulse clock output disabled

Pulse clock output enabled

CSS01

CSS00

Pulse clock count clock selection

0

1

0

1

0

1

f

X

(3.58 MHz)

/2 (1.79 MHz)

/2²(895 MHz)

XT (32.768 MHz)

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Cautions 1. Bits 2 and 3 must be fixed to 0.

2. Do not write to BCS01, BCS00, CSS01, and CSS00 while buzzer or clock pulses are being

output. To change the count clocks, first disable buzzer output (BZOE0 = 0) and pulse

clock output (CLOE0 = 0).

Remarks 1. f^X: Main system clock oscillation frequency

2. f^XT: Subsystem clock oscillation frequency

3. The parenthesized values apply to operation at f^X= 3.58 MHz or at f^XT= 32.768 kHz.

(2) Port mode register 2 (PM2)

PM2 sets each bit of port 2 to either input or output. To use the P22/BUZ/INTP2 pin for buzzer output, set both

PM22 and the output latch for P22 to 0.

To use the P23/PCL pin for pulse clock output, set both PM23 and the output latch for P23 to 0.

PM2 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears PM2 to 00H.

Figure 10-3. Format of Port Mode Register 2

Symbol

PM2

7

1

6

5

4

3

2

1

0

Address

FF22H

After reset

FFH

R/W

PM26

PM25

PM24

PM23

PM22

PM21

PM20

PM22

P22 pin I/O mode selection

P23 pin I/O mode selection

0

1

Output mode (output buffer ON)

Input mode (output buffer OFF)

PM23

0

1

Output mode (output buffer ON)

Input mode (output buffer OFF)

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CHAPTER 10 CLOCK OUTPUT CIRCUIT

10.4 Clock Output Circuit Operation

10.4.1 PCL output operation

The PCL/P23 pin outputs a pulse clock to the peripheral LSI.

To use the clock output circuit for PCL output, make the following setting:

• Set P23 to output mode (PM23 = 0).

• Clear the output latch of P23 to 0.

• Set PCL/BUZ control register 0 (PBS0) as shown in Figure 10-4.

Figure 10-4. Setting of PCL/BUZ Control Register 0 for PCL Output Operation

CLOE0

1

CSS01 CSS00

PBS0

−

0

0/1

Selects count clock

Enables output of pulse clock

Figure 10-5 shows the timing of PCL output.

Figure 10-5. PCL Output Timing

Count Clock

CLOE0

PCL

Output

Disabled

Output

Enabled

Because the pulse clock output enable signal is latched when the count clock goes low, PCL output is always

started from the low level of the count clock even if the output is enabled asynchronously (CLOE0 = 1).

If the output is disabled asynchronously (CLOE0 = 0), the high level of the count clock is guaranteed before the

output is stopped.

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10.4.2 Buzzer output operation

The BUZ/P22/INTP2 pin can be used to output a buzzer frequency.

To use the clock output circuit for buzzer output, make the following setting:

• Set P22 to output mode (PM22 = 0).

• Clear the output latch of P22 to 0.

• Set PCL/BUZ control register 0 (PBS0) as shown in Figure 10-6.

Figure 10-6. Setting of PCL/BUZ Control Register 0 for Buzzer Output Operation

BZOE0 BCS01 BCS00

1

0/1 0/1

−

PBS0

Selects count clock

Enables pulse clock output

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CHAPTER 11 SERIAL INTERFACE UART00

11.1 Serial Interface UART00 Functions

Serial interface UART00 has the following two types of modes.

•

Operation stop mode

Asynchronous serial interface (UART) mode

(1) Operation stop mode

This mode is used when serial transfer is not performed. Power consumption is minimized in this mode.

(2) Asynchronous serial interface (UART) mode

This mode is used to send and receive the one byte of data that follows a start bit. It supports full-duplex

communication.

Serial interface UART00 contains a UART-dedicated baud rate generator, enabling communication over a

wide range of baud rates. The UART-dedicated baud rate generator, for example, enables the use of a MIDI

standard baud rate (31.25 kbps).

Figure 11-1 is a block diagram of serial interface UART00.

Figure 11-1. Block Diagram of Serial Interface UART00

Internal bus

Reception buffer

register 00

TXE00 RXE00 PS001 PS000 CL00 SL00 ISRM00

(RXB00)

Asynchronous serial interface

mode register 00 (ASIM00)

Asynchronous serial interface

status register 00 (ASIS00)

Transmission

shift register 00

(TXS00)

Reception shift

register 00

(RXS00)

PE00

OVE00

FE00

P26/RxD00

P25/TxD00

Reception

controller

(Parity Check)

INTSER00

INTSR00

Transmission

controller

INTST00

(Parity Addition)

Baud rate

generator

fX/2 to fX

/2⁸

5-bit prescaler

TPS002 TPS001 TPS000 MDL003 MDL002 MDL001 MDL000

Internal bus

Baud rate generator control

register 00 (BRGC00)

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11.2 Serial Interface UART00 Configuration

Serial interface UART00 includes the following hardware.

Table 11-1. Serial Interface UART00 Configuration

Configuration

Item

Register

Transmission shift register 00 (TXS00)

Reception shift register 00 (RXS00)

Reception buffer register 00 (RXB00)

Control register

Asynchronous serial interface mode register 00 (ASIM00)

Asynchronous serial interface status register 00 (ASIS00)

Baud rate generator control register 00 (BRGC00)

(1) Transmission shift register 00 (TXS00)

TXS00 is a register in which transmission data is prepared. The transmission data is output from TXS00

bit-serially.

When the data length is seven bits, bits 0 to 6 of the data in TXS00 will be transmission data. Writing data

to TXS00 triggers transmission.

TXS00 can be write-accessed, using an 8-bit memory manipulation instruction, but cannot be read-

accessed.

RESET input sets TXS00 to FFH.

Caution Do not write to TXS00 during transmission.

TXS00 and reception buffer register 00 (RXB00) are mapped at the same address, such

that any attempt to read from TXS00 results in a value being read from the RXB00.

(2) Reception shift register 00 (RXS00)

RXS00 is a register in which serial data, received at the RxD00 pin, is converted to parallel data. Once one

entire byte has been received, RXS00 feeds the reception data to reception buffer register 00 (RXB00).

RXS00 cannot be manipulated directly by a program.

(3) Reception buffer register 00 (RXB00)

RXB00 is used to hold reception data. Once reception shift register 00 (RXS00) has received one entire

byte of data, it feeds that data into RXB00.

When the data length is seven bits, the reception data is sent to bits 0 to 6 of RXB00, in which the MSB is

fixed to 0.

RXB00 can be read-accessed, using an 8-bit memory manipulation instruction, but cannot be write-

accessed.

RESET input sets RXB00 to FFH.

Caution RXB00 and transmission shift register 00 (TXS00) are mapped at the same address, such

that any attempt to write to RXB00 results in a value being written to TXS00.

(4) Transmission controller

The transmission controller controls transmission. For example, it adds start, parity, and stop bits to the

data in transmission shift register 00 (TXS00), according to the setting of asynchronous serial interface

mode register 00 (ASIM00).

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(5) Reception controller

The reception controller controls reception according to the setting of asynchronous serial interface mode

register 00 (ASIM00). It also checks for errors, such as parity errors, during reception. If an error is

detected, asynchronous serial interface status register 00 (ASIS00) is set according to the status of the

error.

11.3 Serial Interface UART00 Control Registers

The following three types of registers are used to control serial interface UART00.

•

Asynchronous serial interface mode register 00 (ASIM00)

Asynchronous serial interface status register 00 (ASIS00)

Baud rate generator control register 00 (BRGC00)

(1) Asynchronous serial interface mode register 00 (ASIM00)

ASIM00 is an 8-bit register that is used to control the serial transfer operation of serial interface UART00.

ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears ASIM00 to 00H.

Caution When using the serial interface function in UART mode, set the related output latches to 0,

and the port mode registers (PM××) as follows.

• For reception

Set P26 (RxD00) to input mode (PM26 = 1).

• For transmission

Set P25 (TxD00) to output mode (PM25 = 0).

• For transmission and reception

Set P26 and P25 to input and output mode, respectively.

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Figure 11-2. Format of Asynchronous Serial Interface Mode Register 00

Symbol

ASIM00

<7>

<6>

5

4

3

2

1

0

Address

FFA0H

After reset

00H

R/W

TXE00

RXE00

PS001

PS000

CL00

SL00

ISRM00

TXE00

RXE00

Operation mode

Function of RxD00/P26 pin

Port function (P26)

Function of TxD00/P25 pin

Port function (P25)

0

1

0

1

0

1

Operation disabled

UART mode (reception only)

Serial function (RxD00)

UART mode (transmission only) Port function (P26)

Serial function (TxD00)

UART mode (transmission and Serial function (RxD00)

reception)

PS001

PS000

Parity bit specification

0

1

No parity

At transmission, the parity bit is fixed to 0.

At reception, a parity check is not made; no parity error is reported.

1

0

1

Odd parity

Even parity

CL00

Character length specification

0

1

7 bits

8 bits

SL00

Transmission data stop bit length specification

0

1

1 bit

2 bits

ISRM00

Reception completion interrupt control at error occurrence

0

1

An interrupt request is generated at error occurrence.

An interrupt request is not generated at error occurrence.

Cautions 1. Bit 0 must be fixed to 0.

2. Switch operation mode from one mode to another after stopping both serial

transmission and reception.

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(2) Asynchronous serial interface status register 00 (ASIS00)

ASIS00 is used to display the type of a reception error, if it occurs while UART mode is set.

ASIS00 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears ASIS00 to 00H.

Figure 11-3. Format of Asynchronous Serial Interface Status Register 00

Symbol

ASIS00

7

0

6

0

5

0

4

0

3

0

2

1

0

Address

FFA1H

After reset

00H

R/W

R

PE00

FE00

OVE00

PE00

Parity error flag

0

1

Parity error not generated

Parity error generated (when the transmit parity and receive parity do not match)

FE00

Framing error flag

Framing error not generated

0

1

Framing error generated^{Note 1}(when stop bit is not detected)

OVE00

Overrun error flag

0

1

Overrun error not generated

Overrun error generated^{Note 2}(when the next receive operation is completed before the data is read from

reception buffer register 00)

Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL00) of asynchronous serial

interface mode register 00 (ASIM00), the stop bit detection in the case of reception is performed

with 1 bit.

2. Be sure to read reception buffer register 00 (RXB00) when an overrun error occurs. If not, every

time the data is received an overrun error is generated.

(3) Baud rate generator control register 00 (BRGC00)

BRGC00 is used to specify the serial clock for the serial interface.

BRGC00 is set with an 8-bit memory manipulation instruction.

RESET input clears BRGC00 to 00H.

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Figure 11-4. Format of Baud Rate Generator Control Register 00

Symbol

7

0

6

5

4

3

2

1

0

Address

FFA2H

After reset

00H

R/W

BRGC00

TPS002 TPS001 TPS000 MDL003 MDL002 MDL001 MDL000

TPS002 TPS001

5-bit counter source clock selection

TPS000

0

1

0

1

0

1

0

1

0

1

0

1

0

1

f^X/2 (1.79 MHz)

f^X/2²(895 kHz)

fX/2³(448 kHz)

fX/2⁴(224 kHz)

fX/2⁵(112 kHz)

fX/2⁶(56 kHz)

fX/2⁷(28 kHz)

fX/2⁸(14 kHz)

MDL003 MDL002

Baud rate generator input clock selection

MDL001 MDL000

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

f^SCK/16

fSCK/17

f^SCK/18

fSCK/19

f^SCK/20

f^SCK/21

f^SCK/22

f^SCK/23

f^SCK/24

f^SCK/25

f^SCK/26

f^SCK/27

f^SCK/28

f^SCK/29

f^SCK/30

Setting prohibited

Cautions 1. Bit 7 must be fixed to 0.

2. When writing to BRGC00 is performed during a communication operation, the output of

baud rate generator is disrupted and communications cannot be performed normally. Be

sure not to write to BRGC00 during communication operation.

Remarks 1. f^X: Main system clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 3.58 MHz.

3. f^SCK: Source clock of the 5-bit counter

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11.4 Serial Interface UART00 Operation

Serial interface UART00 provides the following two types of modes.

• Operation stop mode

• Asynchronous serial interface (UART) mode

11.4.1 Operation stop mode

In operation stop mode, serial transfer is not executed, therefore, the power consumption can be reduced. In this

mode, the pins can be used as normal I/O ports.

(1) Register setting

Operation mode is set by asynchronous serial interface mode register 00 (ASIM00).

ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears ASIM00 to 00H.

Symbol

ASIM00

<7>

<6>

5

4

3

2

1

0

Address

FFA0H

After reset

00H

R/W

TXE00

RXE00

PS001

PS000

CL00

SL00

ISRM00

TXE00

RXE00

Operation mode

Operation disabled

UART mode (reception only)

Function of RxD00/P26 pin

Port function (P26)

Function of TxD00/P25 pin

Port function (P25)

0

1

0

1

0

1

Serial function (RxD00)

UART mode (transmission only) Port function (P26)

Serial function (TxD00)

UART mode (transmission and Serial function (RxD00)

reception)

Caution Switch operation mode from one mode to another after stopping both serial transmission

and reception.

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11.4.2 Asynchronous serial interface (UART) mode

In this mode, the one-byte data following the start bit is transmitted/received and thus full-duplex communication

is possible.

The serial interface contains a UART-dedicated baud rate generator that enables communications at a desired

baud rate from many options.

The UART-dedicated baud rate generator also can output the 31.25-kbps baud rate that complies with the MIDI

standard.

(1) Register setting

UART mode is set by asynchronous serial interface mode register 00 (ASIM00), asynchronous serial

interface status register 00 (ASIS00), and baud rate generator control register 00 (BRGC00).

(a) Asynchronous serial interface mode register 00 (ASIM00)

ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears ASIM00 to 00H.

Caution When using the asynchronous serial interface function (UART mode), set the related

output latches to 0, and port mode register 2 (PM2) as follows.

• For reception

Set P26 (RxD00) to input mode (PM26 = 1).

• For transmission

Set P25 (TxD00) to output mode (PM25 = 0).

• For transmission and reception

Set P26 and P25 to input and output mode, respectively.

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Symbol

ASIM00

<7>

<6>

5

4

3

2

1

0

Address

FFA0H

After Reset

00H

R/W

TXE00

RXE00

PS001

PS000

CL00

SL00

ISRM00

TXE00

RXE00

Operation Mode

Operation disabled

UART mode (reception only)

Function of RxD00/P26 Pin

Port function (P26)

Function of TxD00/P25 Pin

Port function (P25)

0

1

0

1

0

1

Serial function (RxD00)

UART mode (transmission only) Port function (P26)

Serial function (TxD00)

UART mode (transmission and Serial function (RxD00)

reception)

PS001

PS000

Parity Bit Specification

0

1

No parity

At transmission, the parity bit is fixed to 0.

At reception, a parity check is not made; no parity error is reported.

1

0

1

Odd parity

Even parity

CL00

Character Length Specification

0

1

7 bits

8 bits

SL00

Transmission Data Stop Bit Length Specification

0

1

1 bit

2 bits

ISRM00

Reception Completion Interrupt Control at Error Occurrence

0

1

An interrupt request is generated at error occurrence.

An interrupt request is not generated at error occurrence.

Cautions 1. Bit 0 must be fixed to 0.

2. Switch operation mode from one mode to another after stopping both serial

transmission and reception.

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(b) Asynchronous serial interface status register 00 (ASIS00)

ASIS00 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears ASIS00 to 00H.

Symbol

ASIS00

7

0

6

0

5

0

4

0

3

0

2

1

0

Address

FFA1H

After reset

00H

R/W

R

PE00

FE00

OVE00

PE00

Parity error flag

0

1

Parity error not generated

Parity error generated (when the parity of transmission data does not match)

Framing error flag

FE00

0

1

Framing error not generated

Framing error generated^{Note 1}(when stop bit is not detected)

OVE00

Overrun error flag

Overrun error not generated

0

1

Overrun error generated^{Note 2}(when the next receive operation is completed before the data is read from

reception buffer register 00)

Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL00) of asynchronous serial

interface mode register 00 (ASIM00), the stop bit detection in the case of reception is

performed with 1 bit.

2. Be sure to read reception buffer register 00 (RXB00) when an overrun error occurs. If not,

every time the data is received an overrun error is generated.

Caution Bits 3 to 7 must be fixed to 0.

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(c) Baud rate generator control register 00 (BRGC00)

BRGC00 is set with an 8-bit memory manipulation instruction.

RESET input clears BRGC00 to 00H.

Symbol

7

0

6

5

4

3

2

1

0

Address

FFA2H

After reset

00H

R/W

BRGC00

TPS002 TPS001 TPS000 MDL003 MDL002 MDL001 MDL000

TPS002 TPS001

5-bit counter source clock selection

TPS000

0

1

0

1

0

1

0

1

0

1

0

1

0

1

fX

/2 (1.79 MHz)

/2²(895 kHz)

/2³(448 kHz)

/2⁴(224 kHz)

/2⁵(112 kHz)

/2⁶(56 kHz)

/2⁷(28 kHz)

/2⁸(14 kHz)

MDL003 MDL002

Baud rate generator input clock selection

MDL001 MDL000

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

f

SCK/16

SCK/17

SCK/18

SCK/19

SCK/20

SCK/21

SCK/22

SCK/23

SCK/24

SCK/25

SCK/26

SCK/27

SCK/28

SCK/29

SCK/30

Setting prohibited

Cautions 1. Bit 7 must be fixed to 0.

2. When writing to BRGC00 is performed during a communication operation, the

output of baud rate generator is disrupted and communications cannot be

performed normally. Be sure not to write to BRGC00 during communication

operation.

Remarks 1. f^X: Main system clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 3.58 MHz.

3. f^SCK: Source clock of the 5-bit counter

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The baud rate transmit/receive clock to be generated is a signal scaled from the main system clock.

•

Generation of baud rate transmit/receive clock by means of main system clock

The transmit/receive clock is generated by scaling the main system clock. The baud rate generated

from the main system clock is estimated by using the following expression.

fX

[Baud rate] =

[Hz]

2^{n + 1}(k + 16)

f^X: Main system clock oscillation frequency

Table 11-2 shows the relation between the source clock of the 5-bit counter assigned to bits 4 to 6 (TPS000

to TPS002) of BRGC00, and value n.

Table 11-2. Relation Between Source Clock of 5-Bit Counter and Value n

TPS002

TPS001

TPS000

5-Bit Counter Source Clock Selection

f^X/2 (1.79 MHz)

n

0

1

2

3

4

5

6

7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

f^X/2²(895 kHz)

f^X/2³(448 kHz)

f^X/2⁴(224 kHz)

f^X/2⁵(112 kHz)

f^X/2⁶(56 kHz)

f^X/2⁷(28 kHz)

f^X/2⁸(14 kHz)

Remarks 1. f^X: Main system clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 3.58 MHz.

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•

Permissible error range of baud rate

The permissible error range of the baud rate is dependent upon the number of bits of one frame and the

division ratio of the counter [1/(16 + k)]. Table 11-3 shows the relationship between the main system

clock and baud rate, while Figure 11-5 shows an example of the permissible error in the baud rate.

Table 11-3. Example of Relationships Between Main System Clock and Baud Rate

Baud Rate

[bps]

f^X= 5.0 MHz

f^X= 4.1943 MHz

BRGC00 Error (%)

f^X= 3.58 MHz

BRGC00

Error (%)

−

BRGC00

Error (%)

−

75

110

−

150

−

300

−

7BH

6BH

5BH

4BH

3BH

2BH

1BH

11H

0BH

−

1.14

-1.31

1.14

−

77H

67H

57H

47H

37H

27H

17H

0CH

07H

−

1.33

-1.24

1.33

−

600

70H

60H

50H

40H

30H

20H

14H

10H

00H

−

1.73

0.00

1.73

−

1,200

2,400

4,800

9,600

19,200

31,250

38,400

76,800

115,200

−

Remark f^X: Main system clock oscillation frequency

Figure 11-5. Permissible Error in Baud Rate with Sampling Error Considered (Where k = 0)

Ideal sampling

point

32T

64T

256T

320T

352T

288T

336T

304T

P

Basic timing

(clock cycle T)

START

D7

D0

STOP

15.5T

STOP

High-speed clock that can

be received normally

(clock cycle T')

START

D0

P

D7

Sampling error

0.5T

15.5T

304.5T

60.9T

30.45T

33.55T

Low-speed clock that can

be received normally

(clock cycle T")

P

STOP

335.5T

D0

D7

67.1T

301.95T

Remark T: Source clock cycle of 5-bit counter

15.5

320

Permissible error range of baud rate (where k = 0) =

× 100 = 4.8438 (%)

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(2) Communication operation

(a) Data format

The transmission/reception data format is as shown in Figure 11-6.

Figure 11-6. Asynchronous Serial Interface Transmission/Reception Data Format

One data frame

Start

bit

Parity

bit

Stop bit

D0

D1

D3

D2

D4

D7

D5

D6

Character bit

One data frame consists of the following bits:

• Start bit: 1 bit

• Character bits: 7 bits/8 bits

• Parity bits:

• Stop bit(s):

Even parity/odd parity/0 parity/no parity

1 bit/2 bits

The specification of character bit length, parity selection, and specification of stop bit length for each

data frame is carried out with asynchronous serial interface mode register 00 (ASIM00).

When 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in

transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is

always "0".

The serial transfer rate is selected by means of ASIM00 and baud rate generator control register 00

(BRGC00).

If a serial data receive error is generated, the receive error contents can be determined by reading the

status of asynchronous serial interface status register 00 (ASIS00).

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(b) Parity types and operation

The parity bit is used to detect a bit error in the communication data. Normally, the same parity bit is

used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd

number) error can be detected. With 0 parity and no parity, an error cannot be detected.

(i) Even parity

• At transmission

The transmission operation is controlled so that the number of bits with a value of "1" in the

transmission data including parity bit may be even. The parity bit value should be as follows.

The number of bits with a value of "1" is an odd number in transmission data: 1

The number of bits with a value of "1" is an even number in transmission data: 0

• At reception

The number of bits with a value of "1" in the reception data including parity bit is counted, and if

the number is odd, a parity error is generated.

(ii) Odd parity

• At transmission

Conversely to the even parity, the transmission operation is controlled so that the number of bits

with a value of "1" in the transmission data including parity bit may be odd. The parity bit value

should be as follows.

The number of bits with a value of "1" is an odd number in transmission data: 0

The number of bits with a value of "1" is an even number in transmission data: 1

• At reception

The number of bits with a value of "1" in the reception data including parity bit is counted, and if

the number is even, a parity error is generated.

(iii) 0 parity

When transmitting, the parity bit is set to "0" irrespective of the transmission data.

At reception, a parity bit check is not performed. Therefore, a parity error is not generated,

irrespective of whether the parity bit is set to "0" or "1".

(iv) No parity

A parity bit is not added to the transmission data. At reception, data is received assuming that

there is no parity bit. Since there is no parity bit, a parity error is not generated.

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(c) Transmission

A transmit operation is started by writing transmission data to transmission shift register 00 (TXS00).

The start bit, parity bit, and stop bit(s) are added automatically.

When the transmit operation starts, the data in TXS00 is shifted out, and when TXS00 is empty, a

transmission completion interrupt request (INTST00) is generated.

The transmission completion interrupt timing is shown in Figure 11-7.

Figure 11-7. Asynchronous Serial Interface Transmission Completion Interrupt Request Timing

(i)

Stop bit length: 1

STOP

TxD00 (output)

D0

D1

D2

D6

D7

Parity

START

INTST00

(ii) Stop bit length: 2

D0

D1

D2

D6

D7

Parity

TxD00 (Output)

INTST00

STOP

START

Caution Do not replace asynchronous serial interface mode register 00 (ASIM00) during a

transmit operation. If the ASIM00 register is replaced during transmission,

subsequent transmission may not be performed (the normal state is restored by

RESET input).

It is possible to determine whether transmission is in progress by software by using a

transmission completion interrupt request (INTST00) or the interrupt request flag

(STIF00) set by INTST00.

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(d) Reception

When bit 6 (RXE00) of asynchronous serial interface mode register 00 (ASIM00) is set to 1, a receive

operation is enabled and sampling of the RxD00 pin input is performed.

RxD00 pin input sampling is performed using the serial clock specified by ASIM00.

When the RxD00 pin input becomes low, the 5-bit counter of the baud rate generator starts counting,

and at the time when the half time determined by the specified baud rate has passed, the data sampling

start timing signal is output. If the RxD00 pin input sampled again as a result of this start timing signal

is low, it is identified as a start bit, the 5-bit counter is initialized and starts counting, and data sampling

is performed. When character data, a parity bit, and one stop bit are detected after the start bit,

reception of one frame of data ends.

When one frame of data has been received, the reception data in the shift register is transferred to

reception buffer register 00 (RXB00), and a reception completion interrupt request (INTSR00) is

generated.

Even if an error is generated, the reception data in which the error was generated is still transferred to

RXB00. If bit 1 (ISRM00) of ASIM00 is cleared to 0 when an error is generated, INTSR00 is generated

(see Figure 11-9). If the ISRM00 bit is set to 1, INTSR00 is not generated.

If the RXE00 bit is cleared to 0 during the receive operation, the receive operation is stopped

immediately. In this case, the contents of RXB00 and ASIS00 are not changed, and INTSR00 and

INTSER00 are not generated.

Figure 11-8 shows the asynchronous serial interface reception completion interrupt request timing.

Figure 11-8. Asynchronous Serial Interface Reception Completion Interrupt Request Timing

STOP

D0

D1

D2

D6

D7

Parity

RxD00 (input)

INTSR00

START

Caution Be sure to read reception buffer register 00 (RXB00) even if a receive error occurs. If

RXB00 is not read, an overrun error will be generated when the next data is received,

and the receive error state will continue indefinitely.

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(e) Receive errors

The following three errors may occur during a receive operation: a parity error, framing error, or

overrun error. If the error flag in asynchronous serial interface status register 00 (ASIS00) is set to 1 as

a result of data reception, a reception error interrupt request (INTSER00) is generated. The reception

error interrupt occurs before the reception completion interrupt request (INTSR00). Receive error

causes are shown in Table 11-4.

It is possible to determine what kind of error was generated during reception by reading the contents of

ASIS00 in the reception error interrupt servicing (INTSER00) (see Table 11-4 and Figure11-9).

The contents of ASIS00 are cleared to 0 by reading reception buffer register 00 (RXB00) or receiving

the next data (if there is an error in the next data, the corresponding error flag is set).

Table 11-4. Receive Error Causes

Receive Errors

Parity error

Cause

ASIS00 Value

Transmission-time parity specification and reception data parity do not match

Stop bit not detected

04H

02H

01H

Framing error

Overrun error

Reception of next data is completed before data is read from reception buffer

register 00

Figure 11-9. Receive Error Timing

STOP

RxD00 (input)

START D0

D1

D2

D6

D7

Parity

INTSR00^Note

INTSER00

(Framing error or overrun

error generated)

INTSER00

(Parity error generated)

Note INTSR00 is not generated if the receive error is generated when the ISRM00 bit is set to 1.

Cautions 1. The contents of asynchronous serial interface status register 00 (ASIS00) are

cleared to 0 by reading reception buffer register 00 (RXB00) or receiving the next

data. To ascertain the error contents, read ASIS00 before reading RXB00.

2. Be sure to read reception buffer register 00 (RXB00) even if a receive error is

generated. If RXB00 is not read, an overrun error will be generated when the next

data is received, and the receive error state will continue indefinitely.

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CHAPTER 12 LCD CONTROLLER/DRIVER

12.1 LCD Controller/Driver Functions

The LCD controller/driver (LCD20) has the following functions:

(1) Automatic output of segment and common signals based on automatic display data memory read

(2) Operation in 1/16 duty (1/5 bias) display mode

Up to 640 pixels (40 segments × 16 commons)

(3) Four different frame frequencies selectable

(4) Up to 40 segment signal outputs (S0 to S39) and 16 common signal outputs (COM0 to COM15)

Of these segment signal outputs, 8 outputs can be switched to input/output ports bit by bit (P50/S39 to

P57/S32).

(5) Operation with a subsystem clock

12.2 LCD Controller/Driver Configuration

The LCD controller/driver (LCD20) includes the following hardware.

Table 12-1. Configuration of LCD Controller/Driver

Item

Configuration

Display output

40 segment signals (32 dedicated segment signals and 8 segment and input/output port signals)

16 common signals

Control register

LCD20 mode register (LCDM20)

Alternate port function switching register (PF5)

LCD20 clock selection register (LCDC20)

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12.3 LCD Controller/Driver Control Registers

The following three types of registers are used to control the LCD controller/driver (LCD20).

• LCD20 mode register (LCDM20)

• Alternate port function switching register (PF5)

• LCD20 clock selection register (LCDC20)

(1) LCD20 mode register (LCDM20)

LCDM20 specifies whether to enable display operation. It also specifies the operation mode and LCD drive

power supply.

LCDM20 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears LCDM20 to 00H.

Figure 12-2. Format of LCD20 Mode Register

Symbol

<7>

<6>

5

0

<4>

3

0

2

0

1

0

Address

FFB0H

After reset

00H

R/W

LCDM20 LCDON20 VAON20

LIPS20

LCDON20

Control of LCD display

0

1

Display OFF

Display ON

VAON20

LCD controller/driver operation mode^Note

0

1

Normal operation

Low-voltage operation

LIPS20

LCD drive power supply selection

0

1

LCD drive power is not supplied.

LCD drive power is supplied.

Note Clear VAON20 to 0 to reduce the power consumption when LCD display is not performed.

Cautions 1. Bits 0 to 3 and bit 5 must be fixed to 0.

2. When manipulating VAON20, clear LCDON20 to 0 and turn off the LCD display.

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(2) Alternate port function switching register (PF5)

PF5 controls port and segment signal output switching.

PF5 is set with an 8-bit memory manipulation instruction.

RESET input clears PF5 to 00H.

Figure 12-3. Format of Alternate Port Function Switching Register

Symbol

PF5

7

6

5

4

3

2

1

0

Address

FFB1H

After reset

00H

R/W

PF57

PF56

PF55

PF54

PF53

PF52

PF51

PF50

PF57

P57/S32

PF56

P56/S33

PF55

P55/S34

PF54

PF53

P53/S36

PF52

P52/S37

PF51

P51/S38

PF50

P50/S39

P54/S35

0

1

Used as ports (P5n)

Used as segments (S×)

Remark n = 0 to 7

× = 32 to 39

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(3) LCD20 clock selection register (LCDC20)

LCDC20 specifies the LCD clock and LCD frame frequency.

LCDC20 is set with an 8-bit memory manipulation instruction.

RESET input clears LCDC20 to 00H.

Figure 12-4. Format of LCD20 Clock Selection Register

Symbol

7

0

6

0

5

0

4

0

3

2

1

0

Address

FFB2H

After reset

00H

R/W

LCDC20

LCDC203 LCDC202 LCDC201 LCDC200

LCDC203 LCDC202

LCD clock (fLCD) selection

0

1

0

1

0

1

f

X

/2⁶(55.9 kHz)

/2⁷(28.0 kHz)

/2⁸(14.0 kHz)

XT

(32.768 kHz)

LCDC201 LCDC200

LCD clock frequency selection

LCD/2³

LCD/2⁴

LCD/2⁵

LCD/2⁶

0

1

0

1

0

1

f

Caution Bits 4 to 7 must be fixed to 0.

Remarks1. f^X: Main system clock oscillation frequency

2. f^XT: Subsystem clock oscillation frequency

3. The parenthesized values apply to operation at f^X= 3.58 MHz or at f^XT= 32.768 kHz.

Table 12-2 lists the frame frequencies used when f^XT(32.768 kHz) is supplied to the LCD clock (f^LCD).

Table 12-2. LCD Frame Frequencies

LCDC201

LCDC200

LCD Clock Frequency

4,096 Hz

Frame Frequency

256 Hz

0

1

0

1

0

1

2,048 Hz

128 Hz

64 Hz

32 Hz

1,024 Hz

512 Hz

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12.4 Setting Up LCD Controller/Driver

Set up the LCD controller/driver using the following procedure.

<1> Set initial values in display data memory (FA00H to FA4FH).

<2> Set pins to be used for segment output in the alternate port function switching register (PF5).

<3> Enable the LCD display and set the operation modes in the LCD20 mode register (LCDM20).

<4> Set the LCD clock in the LCD20 clock selection register (LCDC20).

12.5 LCD Display Data Memory

The LCD display data memory is mapped at addresses FA00H to FA4FH. Data in the LCD display data memory

can be displayed on the LCD panel using the LCD controller/driver.

Figure 12-5 shows the relationships between the contents of the LCD display data memory and the

segment/common outputs.

That part of the display data memory which is not used for display can be used as ordinary RAM.

Figure 12-5. Relationships Between LCD Display Data Memory Contents and Segment/Common Outputs

S0

S1

S2

• • • •

S37/P52

S38/P51

S39/P50

↑

b7

b6

b5

b4

b3

b2

b1

b0

→

COM15

COM14

COM13

COM12

COM11

COM10

COM9

COM8

Address

FA01H

FA03H

FA05H

• • • •

FA4BH

FA4DH

FA4FH

b7

b6

b5

b4

b3

b2

b1

b0

→

COM7

COM6

COM5

COM4

COM3

COM2

COM1

COM0

Address

FA00H

FA02H

FA04H

• • • •

FA4AH

FA4CH

FA4EH

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CHAPTER 12 LCD CONTROLLER/DRIVER

Each pixel of the LCD panel becomes on when the potential difference between the corresponding common and

segment signals becomes higher than a specific voltage (2V^LCD). It becomes off when the potential difference

becomes lower than 2V^LCD(for details, see (1) below).

A segment signal is converted to a select voltage if the contents of the corresponding bit of each display data

memory are 1; if the contents of the bit are 0, they are converted to an unselect voltage and output to a segment pin

(S0 to S39). Note that S32 to S39 can be used also as an I/O port.

Check, with the information given above, what combination of the front-surface electrodes (corresponding to the

segment signals) and the rear-surface electrodes (corresponding to the common signals) forms display patterns in

the LCD display data memory, and write the bit data that corresponds to the desired display pattern on a one-to-one

basis.

Applying DC voltage as the common and segment signals for an LCD panel would deteriorate it. To avoid this

problem, this LCD panel is driven with AC voltage.

(1) Output waveforms of common and segment signals

Voltages listed in Table 12-3 are output as common and segment signals.

When both common and segment signals are at the select voltage, a display on-voltage of V^LCDis

obtained. The other combinations of the signals correspond to the display off-voltage. Figure 12-6 shows

an example LCD drive waveform between a segment signal and a common signal.

Table 12-3. LCD Drive Voltage

Segment Signal

Select Signal Level

V^SS0/V^LC0

Deselect Signal Level

Common Signal

V^LC3/V^LC2

3

5

3

Select signal level

V^LC0/V^SS0

+V^LCD/-V^LCD

+

-

V^LCD/-

V^LCD/+

V^LCD

5

1

5

1

5

Deselect signal level

V^LC4/V^LC1

1

+

V^LCD/-

V^LCD

5

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Figure 12-6. Example LCD Drive Waveform Between Segment Signal and Common Signal

VLC0

VLC1

VLC2

VLC3

VLC4

COM0

VSS0

VLC0

VLC1

VLC2

VLC3

VLC4

COM1

VSS0

VLC0

V

LC1

LC2

LC3

LC4

V

S0

VSS0

0

1

0

1

0

1

0

1

0

+VLCD

+4/5VLCD

+3/5VLCD

+2/5VLCD

+1/5VLCD

0

COM0-S0

(Turn off)

−1/5^LCD

−2/5VLCD

−3/5VLCD

−4/5VLCD

−VLCD

+VLCD

+4/5VLCD

+3/5VLCD

+2/5VLCD

+1/5VLCD

0

COM1-S0

(Turn on)

−1/5^LCD

−2/5VLCD

−3/5VLCD

−4/5VLCD

−VLCD

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12.6 Supplying LCD Drive Voltage

The µPD789830 Subseries has a divider resistor that is used to supply power to drive an LCD.

The LCD drive voltage is selected by manipulating LIPS20 (bit 4 of the LCD20 mode register (LCDM20)).

When LIPS20 = 0, the current flowing through the divider resistor is cut off.

When LIPS20 = 1, the supply voltage V^DDis divided by the divider resistor and LCD drive voltages V^LCD0through

V^LCD4are supplied.

Figure 12-7 shows the connection of the power supply for the LCD drive.

Figure 12-7. Connection of Power Supply for LCD Drive

V

DD0

LIPS20

P-ch

VLC0

VLC1

VLC2

R

V

LCD

V

LC3

R

V

LC4

V

SS0

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CHAPTER 12 LCD CONTROLLER/DRIVER

12.7 LCD Display

The µPD789830 Subseries can display 8 columns × 2 rows on an LCD panel. The first row displays 12345678,

while the second row displays ABCDEFGH. These characters correspond to the contents of the display data

memory (FA00H to FA4FH). Figure 12-8 shows the connection of the segment signals (S0 to S39) and common

signals (COM0 to COM15) of an LCD panel having 8 columns × 2 rows.

Figure 12-8. Example of Connecting LCD Panel

F

A

4

8

H

F

A

4

C

H

F

A

4

6

H

F

A

4

E

H

F

A

4

A

H

F

A

2

A

H

F

A

2

E

H

F

A

3

4

H

F

A

3

8

H

F

A

2

8

H

F

A

3

0

H

F

A

3

2

H

F

A

3

A

H

F

A

3

E

H

F

A

4

2

H

F

A

2

C

H

F

A

3

6

H

F

A

3

C

H

F

A

4

0

H

F

A

4

H

F

A

1

6

H

F

A

1

A

H

F

A

2

0

H

F

A

2

4

H

F

A

1

4

H

F

A

1

C

H

F

A

1

E

H

F

A

2

6

H

F

A

0

C

H

F

A

1

0

H

F

A

1

8

H

F

A

2

H

F

A

0

A

H

F

A

1

2

H

F

A

0

2

H

F

A

0

6

H

F

A

0

E

H

F

A

0

H

F

A

0

8

H

F

A

0

4

H

0

1

0

1

0

0 0 0

1 1 1

0 1 0

1 0 0

0 1 0

0 0 1

1 1 0

0

1

0

1

0

1

0

0 0 0

0 1 0

1 1 0

0 1 0

1 1 1

0 1 0

0

0 0 0

1 0 0

1 1 0

0

1

0

1

0 0 0

1 1 0

0 0 1

0 1 0

1 0 0

0 0 0

1 1 1

0

1

0

1

0

1

0

1

0

0 0 0

1 1 1

0 0 0

1 1 0

0 0 1

1 1 0

0

1

0

0 0 0

1 1 0

0 0 0

1 1 0

0 0 1

1 1 0

0

1

0

0 0 0

1 1 1

0 0 1

0 1 0

1 0 0

0 0 0

0

1

0

1

0

0 0 0

1 1 0

0 0 1

1 1 0

0 0 1

1 1 0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

BIT0

BIT1

BIT2

BIT3

BIT4

BIT5

BIT6

BIT7

1

0

1

0

1

0

1

0

1

0

1

F

A

4

9

H

F

A

4

D

H

F

A

4

7

H

F

A

4

F

H

F

A

4

B

H

F

A

2

B

H

F

A

2

F

H

F

A

3

5

H

F

A

3

9

H

F

A

2

9

H

F

A

3

1

H

F

A

3

H

F

A

3

B

H

F

A

3

F

H

F

A

4

3

H

F

A

2

D

H

F

A

3

7

H

F

A

3

D

H

F

A

4

1

H

F

A

4

5

H

F

A

1

7

H

F

A

1

B

H

F

A

2

1

H

F

A

2

5

H

F

A

1

5

H

F

A

1

D

H

F

A

1

F

H

F

A

2

7

H

F

A

0

D

H

F

A

1

H

F

A

1

9

H

F

A

2

3

H

F

A

0

B

H

F

A

1

3

H

F

A

0

3

H

F

A

0

7

H

F

A

0

F

H

F

A

0

1

H

F

A

0

9

H

F

A

0

5

H

0

1

0

1 1 0

0 0 1

0 0 0

0 0 1

1 1 0

0 0 0

1

0

1

0

1

0

1 0 0

0 1 0

0 0 1

0 1 0

1 0 0

0 0 0

0

1

0

1 1 0

0 0 1

1 1 1

0 0 1

0 0 0

1

0

1 1 0

0 0 1

1 1 0

0 0 1

1 1 0

0 0 0

1

0

1 1 1

0 0 0

1 1 1

0 0 0

1 1 1

0 0 0

1

0

1 1 1

0 0 0

1 1 0

0 0 0

0

1

0

1 1 0

0 0 1

0 0 0

1 1 1

0 0 1

1 1 1

0 0 0

1

0

0 0 1

1 1 1

0 0 1

0 0 0

1

0

1

0

1

0

1

0

BIT0

BIT1

BIT2

BIT3

BIT4

BIT5

BIT6

BIT7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

S

38

S

37

S

39

S S

3536

S

29

S

S S

2526

S

28

S

3

S

7

S

8

S

S S

S

27

S

S S

S

2

S

4

S

9

S

S S

S

10

S S

S

11

18 19 20

30

31 32 3334

21 22

0

1

5

6

12

1314 1516

17

23 24

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

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CHAPTER 13 INTERRUPT FUNCTIONS

13.1 Interrupt Function Types

The following two types of interrupt functions are used.

(1) Non-maskable interrupt

This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top

priority over all other interrupt requests.

A standby release signal is generated.

The non-maskable interrupt has one source of interrupt from the watchdog timer.

(2) Maskable interrupt

These interrupts undergo mask control. If two or more interrupts with the same priority are simultaneously

generated, each interrupt has a predetermined priority (priority) as shown in Table 13-2.

A standby release signal is generated.

Table 13-1 lists the number of maskable sources in the µPD789830 Subseries.

Table 13-1. Maskable Interrupt Sources of µPD789830 Subseries

External Interrupt Sources

Internal Interrupt Sources

10

Total

14

µPD789830

4

6

µPD78F9831

16

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CHAPTER 13 INTERRUPT FUNCTIONS

13.2 Interrupt Sources and Configuration

Table 13-2. Interrupt Sources

Interrupt

Type

Priority^{Note 1}

Interrupt Source

Trigger

Internal/

External

Vector Table

Address

Basic

Configuration

Type^{Note 2}

Name

Non-

−

INTWDT Watchdog timer overflow

(when watchdog timer mode 1 is

selected)

Internal

0004H

(A)

maskable

interrupt

Maskable

interrupt

0

INTWDT Watchdog timer overflow

(when interval timer mode is selected)

(B)

(C)

1

2

3

4

INTP0

INTP1

INTP2

Pin input edge detection

External

Internal

0006H

0008H

000AH

000CH

INTSER00 Occurrence of reception error of serial

interface (UART00)

(B)

5

6

7

8

9

INTSR00 Completion of reception by serial

interface (UART00)

000EH

0010H

0012H

0014H

0016H

INTST00 Completion of transmission by serial

interface (UART00)

INTTM40 Generation of match signal for 16-bit

timer counter 40

INTTM41 Occurrence of overflow of 16-bit timer

counter 40

INTTM4

Logical sum of match signal and

overflow signal of 16-bit timer counter

40

10

INTTM00 Generation of match signal for 8-bit

timer counter 00

0018H

11

12

INTWTI

INTWT

Interval timer interrupt for watch timer

Watch timer interrupt

001AH

001CH

13

INTKR00 Detection of key return signal

External

001EH

0020H

0022H

(C)

14^{Note 3}

15^{Note 3}

INTP3

INTP4

Pin input edge detection

Notes 1. The priority regulates which maskable interrupt is higher, when two or more maskable interrupts are

requested simultaneously. With the µPD789830, 0 indicates the highest priority and 13 indicates the

lowest priority. With the µPD78F9831, 0 indicates the highest priority, and 15 indicates the lowest

priority.

2. Basic configuration types (A), (B), and (C) correspond to (A), (B), and (C) in Figure 13-1, respectively.

3. µPD78F9831 only

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CHAPTER 13 INTERRUPT FUNCTIONS

Figure 13-1. Basic Configuration of Interrupt Function

(A) Internal non-maskable interrupt

Internal bus

Vector table

address generator

Interrupt request

Standby release signal

(B) Internal maskable interrupt

Internal bus

IE

MK

Vector table

address generator

Interrupt request

IF

Standby release signal

(C) External maskable interrupt

Internal bus

INTM0, INTM1, KRM00

MK

IE

Vector table

address generator

Interrupt

request

Edge

detector

IF

Standby

release signal

INTM0:

External interrupt mode register 0

INTM1^Note: External interrupt mode register 1

KRM00: Key return mode register 00

IF:

Interrupt request flag

Interrupt enable flag

Interrupt mask flag

IE:

MK:

Note µPD78F9831 only

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CHAPTER 13 INTERRUPT FUNCTIONS

13.3 Interrupt Function Control Registers

The interrupt functions are controlled by the following registers.

• Interrupt request flag registers 0 and 1 (IF0, IF1)

• Interrupt mask flag registers 0 and 1 (MK0, MK1)

• External interrupt mode registers 0 and 1 (INTM0, INTM1^Note

)

• Program status word (PSW)

Note µPD78F9831 only

Table 13-3 lists interrupt requests, the corresponding interrupt request flags, and interrupt mask flags.

Table 13-3. Interrupt Request Signals and Corresponding Flags

Interrupt Request Signal

INTWDT

Interrupt Request Flag

Interrupt Mask Flag

WDTIF

PIF0

WDTMK

PMK0

INTP0

INTP1

PIF1

PMK1

INTP2

PIF2

PMK2

INTSER00

INTSR00

INTST00

INTTM40

INTTM41

INTTM4

INTTM00

INTWTI

INTWT

SERIF00

SRIF00

STIF00

TMIF40

TMIF41

TMIF4

SERMK00

SRMK00

STMK00

TMMK40

TMMK41

TMMK4

TMMK00

WTIMK

WTMK

TMIF00

WTIIF

WTIF

INTKR00

INTP3^Note

INTP4^Note

KRIF00

PIF3^Note

PIF4^Note

KRMK00

PMK3^Note

PMK4^Note

Note µPD78F9831 only

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CHAPTER 13 INTERRUPT FUNCTIONS

(1) Interrupt request flag registers 0 and 1 (IF0, IF1)

An interrupt request flag is set to 1, when the corresponding interrupt request is issued, or when the related

instruction is executed. It is cleared to 0, when the interrupt request is acknowledged, when a RESET

signal is input, or when a related instruction is executed.

IF0 and IF1 are set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears IF0 and IF1 to 00H.

Figure 13-2. Format of Interrupt Request Flag Register (µPD789830)

Symbol

IF0

<7>

<6>

<5>

<4>

<3>

PIF2

<3>

<2>

PIF1

<1>

PIF0

<1>

<0>

WDTIF

<0>

Address After reset

R/W

TMIF40

STIF00

SRIF00 SERIF00

FFE0H

00H

7

0

6

0

<5>

<4>

<2>

IF1

KRIF00

WTIF

WTIIF

TMIF00

TMIF4

TMIF41

FFE1H

00H

R/W

××IF

Interrupt request flag

0

1

No interrupt request signal has been issued.

An interrupt request signal has been issued; an interrupt request has been made.

Cautions 1. Bits 6 and 7 of IF1 must all be set to 0.

2. The WDTIF flag can be read- and write-accessed only when the watchdog timer is

being used as an interval timer. It must be cleared to 0 if the watchdog timer is used in

watchdog timer mode 1 or 2.

3. When port 2 is being used as an output port, and its output level is changed, an

interrupt request flag is set, because this port is also used as an external interrupt

input. To use port 2 in output mode, therefore, the interrupt mask flag must be set to 1

in advance.

Figure 13-3. Format of Interrupt Request Flag Register (µPD78F9831)

Symbol

IF0

<7>

TMIF40

<7>

<6>

STIF00

<6>

<5>

<4>

<3>

PIF2

<3>

<2>

PIF1

<1>

PIF0

<1>

<0>

WDTIF

<0>

Address After reset

R/W

SRIF00 SERIF00

FFE0H

00H

<5>

<4>

<2>

IF1

PIF4

PIF3

KRIF00

WTIF

WTIIF

TMIF00

TMIF4

TMIF41

FFE1H

00H

R/W

××IF

Interrupt request flag

0

1

No interrupt request signal has been issued.

An interrupt request signal has been issued; an interrupt request has been made.

Cautions 1. The WDTIF flag can be read- and write-accessed only when the watchdog timer is

being used as an interval timer. It must be cleared to 0 if the watchdog timer is used in

watchdog timer mode 1 or 2.

2. When ports 2 and 4 are being used as an output port, and its output level is changed,

an interrupt request flag is set, because this port is also used as an external interrupt

input. To use ports 2 and 4 in output mode, therefore, the interrupt mask flag must be

set to 1 in advance.

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CHAPTER 13 INTERRUPT FUNCTIONS

(2) Interrupt mask flag registers 0 and 1 (MK0, MK1)

The interrupt mask flags are used to enable and disable the corresponding maskable interrupts.

MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets MK0 and MK1 to FFH.

Figure 13-4. Format of Interrupt Mask Flag Register (µPD789830)

Symbol

MK0

<7>

<6>

<5>

<4>

<3>

PMK2

<3>

<2>

PMK1

<2>

<1>

PMK0

<1>

<0>

WDTMK

<0>

Address

FFE4H

After reset R/W

TMMK40 STMK00 SRMK00 SERMK00

FFH

R/W

7

1

6

1

<5>

<4>

MK1

KRMK00

WTMK

WTIMK

TMMK00

TMMK4

TMMK41

FFE5H

FFH

R/W

××MK

Interrupt servicing control

0

1

Enable interrupt servicing.

Disable interrupt servicing.

Cautions 1. Bits 6 and 7 of MK1 must all be set to 0.

2. The WDTMK flag can be read- and write-accessed only when the watchdog timer is

being used as an interval timer. It must be cleared to 0 if the watchdog timer is used in

watchdog timer mode 1 or 2.

3. When port 2 is being used as an output port, and its output level is changed, an

interrupt request flag is set, because this port is also used as an external interrupt

input. To use port 2 in output mode, therefore, the interrupt mask flag must be set to 1

in advance.

Figure 13-5. Format of Interrupt Mask Flag Register (µPD78F9831)

Symbol

MK0

<7>

<6>

<5>

<4>

<3>

PMK2

<3>

<2>

PMK1

<2>

<1>

PMK0

<1>

<0>

WDTMK

<0>

Address

FFE4H

After reset R/W

TMMK40 STMK00 SRMK00 SERMK00

FFH

R/W

<7>

<6>

<5>

<4>

MK1

PMK4

PMK3

KRMK00

WTMK

WTIMK

TMMK00

TMMK4

TMMK41

FFE5H

FFH

R/W

××MK

Interrupt servicing control

0

1

Enable interrupt servicing.

Disable interrupt servicing.

Cautions 1. The WDTMK flag can be read- and write-accessed only when the watchdog timer is

being used as an interval timer. It must be cleared to 0 if the watchdog timer is used in

watchdog timer mode 1 or 2.

2. When ports 2 and 4 are being used as an output port, and its output level is changed,

an interrupt request flag is set, because this port is also used as an external interrupt

input. To use ports 2 and 4 in output mode, therefore, the interrupt mask flag must be

set to 1 in advance.

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CHAPTER 13 INTERRUPT FUNCTIONS

(3) External interrupt mode register 0 (INTM0)

INTM0 is used to specify a valid edge for INTP0 to INTP2.

INTM0 is set with an 8-bit memory manipulation instruction.

RESET input clears INTM0 to 00H.

Figure 13-6. Format of External Interrupt Mode Register 0

Symbol

INTM0

7

6

5

4

3

2

1

0

Address

FFECH

After reset R/W

00H R/W

ES21

ES20

ES11

ES10

ES01

ES00

ES21

ES20

INTP2 valid edge selection

INTP1 valid edge selection

INTP0 valid edge selection

0

1

0

1

0

1

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

ES11

ES10

0

1

0

1

0

1

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

ES01

ES00

0

1

0

1

0

1

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

Cautions 1. Bits 0 and 1 must all be set to 0.

2. Set the corresponding interrupt mask flag to 1 to disable interrupts before setting

INTM0.

To enable interrupts, clear to 0 the corresponding interrupt request flag, then the

corresponding interrupt mask flag.

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CHAPTER 13 INTERRUPT FUNCTIONS

(4) External interrupt mode register 1 (INTM1)^Note

INTM1 is used to specify a valid edge for INTP3 and INTP4.

INTM1 is set with an 8-bit memory manipulation instruction.

RESET input clears INTM1 to 00H.

Note µPD78F9831 only

Figure 13-7. Format of External Interrupt Mode Register 1 (µPD78F9831)

Symbol

INTM1

7

0

6

0

5

0

4

0

3

2

1

0

Address

FFEDH

After reset R/W

00H R/W

ES41

ES40

ES31

ES30

ES41

ES40

INTP4 valid edge selection

0

1

0

1

0

1

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

ES31

ES30

INTP3 valid edge selection

0

1

0

1

0

1

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

Cautions 1. Bits 4 to 7 must all be set to 0.

2. Set the corresponding interrupt mask flag to 1 to disable interrupts before setting

INTM1.

To enable interrupts, clear to 0 the corresponding interrupt request flag, then the

corresponding interrupt mask flag.

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CHAPTER 13 INTERRUPT FUNCTIONS

(5) Program status word (PSW)

The program status word is used to hold the instruction execution result and the current status of the

interrupt requests. The IE flag, used to enable and disable maskable interrupts, is mapped to PSW.

PSW can be read- and write-accessed in 8-bit units, as well as in 1-bit units when using bit manipulation

instructions and dedicated instructions (EI and DI). When a vectored interrupt is acknowledged, PSW is

automatically saved to a stack, and the IE flag is reset to 0.

RESET input sets PSW to 02H.

Figure 13-8. Program Status Word Configuration

Symbol

PSW

7

6

Z

5

0

4

3

0

2

0

1

0

After reset

02H

IE

AC

CY

Used in the execution of ordinary instructions

IE

0

Whether to enable/disable interrupt acknowledgement

Disable

Enable

1

(6) Key return mode register 00 (KRM00)

KRM00 is used to select a pin that detects a key return signal (falling edge of port 3).

KRM00 is set with an 8-bit memory manipulation instruction.

RESET input clears KRM00 to 00H.

Figure 13-9. Format of Key Return Mode Register 00

Symbol

KRM00

7

0

6

0

5

0

4

3

2

1

0

Address After reset

FFF5H 00H

R/W

KRM004

KRM003

KRM002

KRM001

KRM000

KRM00n

P3n key return signal detect selection

0

1

Not detected

Detected (falling edge of port 3)

Cautions 1. Bits 5 to 7 must all be set to 0.

2. Set bit 5 (KRMK00) of MK1 to 1 to disable interrupts before setting KRM00. After

setting KRM00, set bit 5 (KRIF00) of IF1 to 1, then clear KRMK00 to 0 to enable the

interrupt.

Remark n = 0 to 4

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CHAPTER 13 INTERRUPT FUNCTIONS

Figure 13-10. Block Diagram of Falling Edge Detector

Key return mode register 00 (KRM00)

Note

P30

P31

P32

P33

P34

KRIF00 set signal

Falling edge detector

KRMK00

Standby release

signal

Note Selector that selects a pin used to input the falling edge.

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CHAPTER 13 INTERRUPT FUNCTIONS

13.4 Interrupt Servicing Operation

13.4.1 Non-maskable interrupt request acknowledgement operation

The non-maskable interrupt is unconditionally acknowledged even when interrupts are disabled. It is not subject

to interrupt priority control and takes precedence over all other interrupts.

When the non-maskable interrupt request is acknowledged, PSW and PC are saved to the stack in that order,

the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.

Figure 13-11 shows the flowchart from non-maskable interrupt request generation to acknowledgement. Figure

13-12 shows the timing of non-maskable interrupt request acknowledgement.

acknowledgement operation if multiple non-maskable interrupts are generated.

Figure 13-13 shows the

Caution During a non-maskable interrupt servicing program execution, do not input another non-

maskable interrupt request; otherwise the interrupt servicing program will be interrupted and

the new interrupt request will be acknowledged.

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CHAPTER 13 INTERRUPT FUNCTIONS

Figure 13-11. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgement

Start

WDTM4 = 1

No

(watchdog timer mode

is selected)

Interval timer

Yes

No

WDT

overflows

Yes

WDTM3 = 0

(non-maskable interrupt

is selected)

Reset processing

Yes

Interrupt request is generated

Interrupt servicing is started

WDTM: Watchdog timer mode register

WDT: Watchdog timer

Figure 13-12. Timing of Non-Maskable Interrupt Request Acknowledgement

Interrupt servicing

program

Saving PSW and PC, and

jump to interrupt servicing

CPU processing

TMIF4

Instruction

Figure 13-13. Acknowledgement of Non-Maskable Interrupt Request

Main routine

First interrupt servicing

NMI request

(second)

NMI request

(first)

Second interrupt servicing

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CHAPTER 13 INTERRUPT FUNCTIONS

13.4.2 Maskable interrupt acknowledgement operation

A maskable interrupt can be acknowledged when the interrupt request flag is set to 1 and the corresponding

interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in the interrupt enabled status

(when the IE flag is set to 1).

The time required to start the interrupt servicing after a maskable interrupt request has been generated is shown

in Table 13-4.

See Figures 13-15 and 13-16 for the interrupt request acknowledgement timing.

Table 13-4. Time from Generation of Maskable Interrupt Request to Servicing

Minimum Time

9 clocks

Maximum Time^Note

19 clocks

Note The wait time is maximum when an interrupt request is generated immediately before BT and BF

instruction.

1

f^CPU

Remark 1 clock:

(f^CPU: CPU clock)

When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting

from the interrupt request assigned the highest priority.

An interrupt that is held pending is acknowledged when the status where it can be acknowledged is set.

Figure 13-14 shows the algorithm of acknowledging interrupt requests.

When a maskable interrupt request is acknowledged, the contents of PSW and PC are saved to the stack in that

order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the

PC, and execution branches.

To return from interrupt servicing, use the RETI instruction.

Figure 13-14. Interrupt Request Acknowledgement Program Algorithm

Start

No

××IF = 1 ?

Yes (Interrupt request generated)

No

××MK = 0 ?

Yes

Interrupt request held pending

No

IE = 1 ?

Yes

Interrupt request held pending

Vectored interrupt

servicing

××IF: Interrupt request flag

××MK: Interrupt mask flag

IE:

Flag to control maskable interrupt request acknowledgement (1 = enable, 0 = disable)

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CHAPTER 13 INTERRUPT FUNCTIONS

Figure 13-15. Interrupt Request Acknowledgement Timing (Example of MOV A,r)

8 Clocks

Clock

Saving PSW and PC, jump

to interrupt servicing

Interrupt servicing program

CPU

MOV A,r

Interrupt

If an interrupt request flag (××IF) is set before an instruction clock n (n = 4 to 10) under execution becomes n − 1,

the interrupt is acknowledged after the instruction under execution completes. Figure 13-15 shows an example of

the interrupt request acknowledgement timing for an 8-bit data transfer instruction MOV A,r. Since this instruction is

executed for 4 clocks, if an interrupt occurs for 3 clocks after the execution starts, the interrupt acknowledgement

processing is performed after the MOV A,r instruction is completed.

Figure 13-16. Interrupt Request Acknowledgement Timing (When Interrupt Request Flag Is Generated

at the Last Clock During Instruction Execution)

8 clocks

Clock

Interrupt

servicing

program

Saving PSW and PC, jump

CPU

NOP

MOV A,r

to interrupt servicing

Interrupt

If an interrupt request flag (××IF) is set at the last clock of the instruction, the interrupt acknowledgement

processing starts after the next instruction is executed.

Figure 13-16 shows an example of the interrupt acknowledgement timing for an interrupt request flag that is set

at the second clock of NOP (2-clock instruction). In this case, the MOV A,r instruction after the NOP instruction is

executed, and then the interrupt acknowledgement processing is performed.

Caution Interrupt requests are reserved while interrupt request flag registers 0 or 1 (IF0 or IF1) or

interrupt mask flag register 0 or 1 (MK0 or MK1) is being accessed.

13.4.3 Multiple interrupt servicing

Multiple interrupt servicing in which another interrupt is acknowledged while an interrupt is serviced can be

processed by priority. When two or more interrupts are generated at once, interrupt servicing is performed according

to the priority assigned to each interrupt request in advance (see Table 13-2).

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Figure 13-17. Example of Multiple Interrupt

Example 1. A multiple interrupt is acknowledged

INTxx servicing

INTyy servicing

Main processing

IE = 0

EI

INTxx

INTyy

RETI

During interrupt INTxx processing, interrupt request INTyy is acknowledged, and a multiple interrupt is

generated. An EI instruction is issued before each interrupt request acknowledgement, and the interrupt request

acknowledgement enable state is set.

Example 2. A multiple interrupt is not generated because interrupts are not enabled

INTxx processing

INTyy processing

Main processing

EI

IE = 0

INTyy is held pending

INTyy

RETI

INTxx

IE = 0

RETI

Because interrupts are not enabled in interrupt INTxx servicing (an EI instruction is not issued), interrupt request

INTyy is not acknowledged, and a multiple interrupt is not generated. The INTyy request is held pending and

acknowledged after the INTxx servicing is performed.

IE = 0: Interrupt request acknowledgement

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13.4.4 Pending interrupt request

Some instructions may hold the acknowledgement of an instruction request until the completion of the execution

of the next instruction even if the interrupt request (maskable interrupt, non-maskable interrupt, and external

interrupt) is generated during the execution. The following shows such instructions (interrupt request hold

instruction).

• Manipulation instruction for interrupt request flag registers 0 and 1 (IF0, IF1)

• Manipulation instruction for interrupt mask flag registers 0 and 1 (MK0, MK1)

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CHAPTER 14 STANDBY FUNCTION

14.1 Standby Function and Configuration

14.1.1 Standby function

The standby function is used to reduce the power consumption of the system and the following two modes are

available:

(1) HALT mode

This mode is set when the HALT instruction is executed. HALT mode stops the operation clock of the CPU.

The system clock oscillator continues oscillating. This mode does not reduce the power consumption as

much as STOP mode, but is useful for resuming processing immediately when an interrupt request is

generated, or for intermittent operations.

(2) STOP mode

This mode is set when the STOP instruction is executed. STOP mode stops the system clock oscillator and

stops the entire system. The power consumption of the CPU can be substantially reduced in this mode.

The low voltage (V^DD= 1.8 V) of the data memory can be retained. Therefore, this mode is useful for

retaining the contents of the data memory at a low current.

STOP mode can be released by an interrupt request, so that this mode can be used for intermittent

operation. However, some time is required until the system clock oscillator stabilizes after STOP mode has

been released. If processing must be resumed immediately by using an interrupt request, therefore, use

HALT mode.

In both modes, the previous contents of the registers, flags, and data memory before stabilizing standby mode

are all retained. In addition, the statuses of the output latch of the I/O ports and output buffer are also retained.

Caution To set STOP mode, be sure to stop the operations of the peripheral hardware, and then execute

the STOP instruction.

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14.1.2 Standby function control register

The wait time after STOP mode is released upon interrupt request until the oscillation stabilizes is controlled with

the oscillation stabilization time selection register (OSTS).

OSTS is set with an 8-bit memory manipulation instruction.

RESET input sets OSTS to 04H. However, the oscillation stabilization time after RESET input is 2¹⁵/f^X.

Figure 14-1. Format of Oscillation Stabilization Time Selection Register

6

0

5

0

4

0

3

0

2

1

0

Address

After reset

04H

R/W

Symbol

OSTS

7

0

OSTS2

OSTS1

OSTS0 FFFAH

OSTS2 OSTS1

OSTS0

Oscillation stabilization time selection

0

1

0

1

0

2¹²/f

2¹⁵/f

2¹⁷/f

X

(1.02 ms)

X

(8.19 ms)

(32.8 ms)

Other than above

Setting prohibited

Caution The wait time after STOP mode is released does not include the time from STOP mode release

to clock oscillation start ("a" in the figure below), regardless of release by RESET input or by

interrupt generation.

STOP mode release

X1 pin voltage

waveform

a

Remarks 1. f^X: Main system clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 3.58 MHz.

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14.2 Standby Function Operation

14.2.1 HALT mode

(1) Setting and operation status of HALT mode

HALT mode is set by executing the HALT instruction.

The operation status in HALT mode is shown in the following table.

Table 14-1. Operation Statuses in HALT Mode

Item

HALT Mode Operation Status While Main

System Clock Is Operating

HALT Mode Operation Status While Subsystem

Clock Is Operating

While Subsystem

Clock Is Operating

While Subsystem Clock While Main System

Is Not Operating Clock Is Operating

While Main System Clock

Is Not Operating

Main system clock

CPU

Oscillation enabled

Operation disabled

Oscillation disabled

Port (output latch)

16-bit timer counter

8-bit timer counter

Watch timer

Remains in the state existing before the selection of HALT mode

Operation enabled

Operation disabled

Operation enabled^{Note 2}

Operation enabled

Operation enabled^{Note 4}

Operation enabled^{Note 1}

Operation enabled

Operation disabled

Operation enabled

Watchdog timer

Clock output circuit

Serial interface

LCD controller/driver

External interrupt

Operation enabled^{Note 3}

Operation disabled

Operation enabled

Operation enabled^{Note 2}

Notes 1. Operation is enabled while the main system clock is selected.

2. Operation is enabled while the subsystem clock is selected.

3. Operation is enabled in the pulse clock output circuit while the subsystem clock is selected.

4. Maskable interrupt that is not masked

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(2) Releasing HALT mode

HALT mode can be released by the following three types of sources.

(a) Releasing by unmasked interrupt request

HALT mode is released by an unmasked interrupt request. In this case, if the interrupt is enabled to be

acknowledged, vectored interrupt servicing is performed. If the interrupt acknowledgement is disabled,

the instruction at the next address is executed.

Figure 14-2. Releasing HALT Mode by Interrupt

HALT

instruction

Wait

Standby

release signal

Operating

mode

HALT mode

Operating mode

Oscillation

Clock

Remarks 1. The broken line indicates the case where the interrupt request that has released standby

mode is acknowledged.

2. The wait time is as follows.

• When vectored interrupt servicing is performed:

9 to 10 clocks

• When vectored interrupt servicing is not performed: 1 to 2 clocks

(b) Releasing by non-maskable interrupt request

HALT mode is released regardless of whether the interrupt is enabled or disabled, and vectored

interrupt servicing is performed.

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(c) Releasing by RESET input

When HALT mode is released by the RESET signal, execution branches to the reset vector address in

the same manner as the ordinary reset operation, and program execution is started.

Figure 14-3. Releasing HALT Mode by RESET Input

HALT

instruction

Wait 2¹⁵/f

(9.15 ms)

X

RESET

signal

Oscillation

stabilization

wait status

Reset

period

Operating

mode

Operating

mode

HALT mode

Oscillation

stop

Oscillation

Clock

Remarks 1. f^X: Main system clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 3.58 MHz.

Table 14-2. Operation After Release of HALT Mode

Releasing Source

MK××

IE

0

Operation

Maskable interrupt request

0

1

−

Executes next address instruction

Executes interrupt servicing

Retains HALT mode

1

×

Non-maskable interrupt request

RESET input

×

Executes interrupt servicing

Reset processing

−

×: Don't care

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CHAPTER 14 STANDBY FUNCTION

14.2.2 STOP mode

(1) Setting and operation status of STOP mode

STOP mode is set by executing the STOP instruction.

Cautions 1. When STOP mode is set, the X2 pin is internally pulled up to V^DD0or VDD1 to suppress

the current leakage of the oscillator block. Therefore, do not use STOP mode in a

system where the external clock is used as the system clock.

2. Because standby mode can be released by an interrupt request signal, standby mode

is released as soon as it is set if there is an interrupt source whose interrupt request

flag is set and interrupt mask flag is reset. When STOP mode is set, therefore, HALT

mode is set immediately after the STOP instruction has been executed, the wait time

set by the oscillation stabilization time selection register (OSTS) elapses, and then

operating mode is set.

The operation status in STOP mode is shown in the following table.

Table 14-3. Operation Statuses in STOP Mode

Item

STOP Mode Operation Status While Main System Clock Is Operating

While Subsystem Clock Is Operating

Oscillation disabled

While Subsystem Clock Is Not Operating

Main system clock

CPU

Operation disabled

Port (output latch)

16-bit timer counter

8-bit timer counter

Watch timer

Remains in the state existing before the selection of STOP mode

Operation disabled

Operation enabled^{Note 1}

Operation disabled

Watchdog timer

Clock output circuit

Serial interface

LCD controller/driver

External interrupt

Operation disabled

Operation enabled^{Note 2}

Operation disabled

Operation enabled^{Note 1}

Operation enabled^{Note 3}

Notes 1. Operation is enabled while the subsystem clock is selected.

2. Operation is enabled in the pulse clock output circuit while the subsystem clock is selected.

3. Maskable interrupt that is not masked

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(2) Releasing STOP mode

STOP mode can be released by the following two types of sources.

(a) Releasing by unmasked interrupt request

STOP mode can be released by an unmasked interrupt request. In this case, if the interrupt is enabled

to be acknowledged, vectored interrupt servicing is performed, after the oscillation stabilization time has

elapsed. If the interrupt acknowledgement is disabled, the instruction at the next address is executed.

Figure 14-4. Releasing STOP Mode by Interrupt

Wait

STOP

instruction

(set time by OSTS)

Standby

release signal

Oscillation stabilization

wait status

Operating

mode

Operating

mode

STOP mode

Oscillation

stop

Oscillation

Clock

Remark The broken line indicates the case where the interrupt request that has released standby

mode is acknowledged.

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CHAPTER 14 STANDBY FUNCTION

(b) Releasing by RESET input

When STOP mode is released by the RESET signal, the reset operation is performed after the

oscillation stabilization time has elapsed.

Figure 14-5. Releasing STOP Mode by RESET Input

STOP

instruction

Wait 2¹⁵/f

(9.15 ms)

X

RESET

signal

Oscillation

stabilization

wait status

Operating

mode

Reset

period

Operating

mode

STOP mode

Oscillation

stop

Oscillation

Clock

Remarks 1. f^X: Main system clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 3.58 MHz.

Table 14-4. Operation After Release of STOP Mode

Releasing Source

MK××

IE

0

Operation

Maskable interrupt request

0

1

−

Executes next address instruction

Executes interrupt servicing

Retains STOP mode

1

×

RESET input

−

Reset processing

×: Don't care

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CHAPTER 15 RESET FUNCTION

The following two operations are available to generate reset signals.

(1) External reset input with RESET pin

(2) Internal reset by inadvertent program loop time detected with watchdog timer

External and internal reset have no functional differences. In both cases, program execution starts at the

address at 0000H and 0001H by reset signal input.

When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each

hardware is set to the status shown in Table 15-1. Each pin has a high impedance during reset input or during

oscillation stabilization time just after reset clear.

When a high level is input to the RESET pin, the reset is cleared and program execution is started after the

oscillation stabilization time has elapsed (2¹⁵/f^X). The reset applied by the watchdog timer overflow is automatically

cleared after reset, and program execution is started after the oscillation stabilization time has elapsed (2¹⁵/f^X) (see

Figures 15-2 to 15-4).

Cautions 1. For an external reset, input a low level for 10 µs or more to the RESET pin.

2. When STOP mode is cleared by reset, STOP mode contents are held during reset input.

However, the port pins become high impedance.

Figure 15-1. Block Diagram of Reset Function

Reset controller

Reset signal

RESET

Over-

flow

Count clock

Watchdog timer

Stop

Interrupt function

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Figure 15-2. Reset Timing by RESET Input

X1

Reset period

(oscillation

stops)

Oscillation

stabilization

time wait

During normal

operation

Normal operation

(reset processing)

RESET

Internal

reset signal

Delay

Hi-Z

Port pin

Figure 15-3. Reset Timing by Overflow in Watchdog Timer

X1

Reset period

(oscillation

continues)

Oscillation

stabilization

time wait

Normal operation

(reset processing)

During normal operation

Overflow in

watchdog timer

Internal

reset signal

Hi-Z

Port pin

Figure 15-4. Reset Timing by RESET Input in STOP Mode

X1

STOP instruction execution

Oscillation

Stop status

(oscillation

stops)

Reset period

(oscillation

stops)

Normal operation

(reset processing)

stabilization

time wait

During normal operation

RESET

Internal

reset signal

Delay

Hi-Z

Port pin

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Table 15-1. State of Hardware After Reset

Hardware

State After Reset

Program counter (PC)^{Note 1}

Loaded with the contents of

the reset vector table

(0000H, 0001H)

Stack pointer (SP)

Program status word (PSW)

RAM

Undefined

02H

Data memory

Undefined^{Note 2}

00H

General-purpose register

Ports (P0 to P3, P4^{Note 3}, P5) (output latch)

Port mode registers (PM0 to PM3, PM4^{Note 3}, PM5)

Pull-up resistor option register (PU0)

FFH

00H

Processor clock control register (PCC)

Suboscillation mode register (SCKM)

02H

00H

Subclock control register (CSS)

00H

Oscillation stabilization time selection register (OSTS)

04H

16-bit timer counter

Compare register (CR40)

0000H

00H

Control register (TMC40)

8-bit timer counter

Timer register (TM00)

00H

Compare register (CR00)

Undefined

00H

Mode control register (TMC00)

Watch timer

Mode control register (WTM)

00H

Watchdog timer

Timer clock selection register (TCL2)

Mode register (WDTM)

00H

Clock output circuit

Serial interface

Control register (PBS0)

00H

Asynchronous serial interface mode register (ASIM00)

Asynchronous serial interface status register (ASIS00)

Baud rate generator control register (BRGC00)

Transmission shift register (TXS00)

Reception buffer register (RXB00)

Mode register (LCDM20)

00H

FFH

LCD controller/driver

Interrupts

00H

FFH

00H

Alternate port function switching register (PF5)

Clock selection register (LCDC20)

Request flag registers (IF0, IF1)

Mask flag registers (MK0, MK1)

External interrupt mode register (INTM0)

External interrupt mode register (INTM1)^{Note 3}

Key return mode register (KRM00)

Notes 1. While a reset signal is being input, and during the oscillation stabilization period, the contents of the

PC will be undefined, while the remainder of the hardware will be the same as after the reset.

2. In standby mode, the RAM enters the hold state after a reset.

3. µPD78F9831 only

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CHAPTER 16 µPD78F9831

The µPD78F9831 is produced by replacing the internal ROM of the mask ROM version µPD789830 with larger

flash memory, and by adding I/O ports to the µPD789830. Unlike bare chips of mask ROM versions, the shipped

µPD78F9831 is contained in a 100-pin plastic LQFP package. Table 16-1 lists differences between the

µPD78F9831 and µPD789830.

Table 16-1. Differences Between µPD78F9831 and µPD789830

Item

Flash Memory Version

Mask ROM Version

µPD78F9831

µPD789830

Internal memory

I/O ports

ROM

48 KB (flash memory)

24 KB (mask ROM)

RAM

2 KB

1 KB

LCD display RAM

80 bytes

Total: 38 port pins

Total: 30 port pins

P00 to P07, P10 to P17, P20 to P26,

P30 to P34, P40, P41, P50 to P57

P00 to P07, P10, P11, P20 to P26, P30

to P34, P50 to P57

External interrupt input pins

Total: 5 pins

Total: 3 pins

INTP0 to INTP4

INTP0 to INTP2

V^PPpin

Provided

Not provided

Form of shipment

Electrical characteristics

100-pin plastic LQFP

88-pin bare chip

Refer to CHAPTER 18 ELECTRICAL SPECIFICATIONS.

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CHAPTER 16 µPD78F9831

16.1 Flash Memory Programming

The on-chip program memory in the µPD78F9831 is a flash memory.

The flash memory can be written with the µPD78F9831 mounted on the target system (on-board). Connect the

dedicated flash writer (Flashpro III (part number: PG-FR3)) to the host machine and target system to write the flash

memory.

16.1.1 Selecting communication mode

The flash memory is written by using Flashpro III and by means of serial communication. Select a

communication mode from those listed in Table 16-2. To select a communication mode, the format shown in Figure

16-1 is used. Each communication mode is selected by the number of V^PPpulses shown in Table 16-2.

Table 16-2. Communication Mode

Communication Mode

Pins Used^{Note 1}

Number of V^PPPulses

UART

Pseudo 3-wire mode^{Note 2}

TxD00/P25

RxD00/P26

8

P10 (Serial clock input)

P11 (Serial data output)

P12 (Serial data input)

12

Notes 1. Shifting to the flash memory programming mode sets all pins not used for flash memory programming

to the same state as the immediately after reset. If the external device connected to each port does

not acknowledge the state immediately after reset, pin handling such as connecting to V^DDor V^SSvia a

resistor is required.

2. Serial transfer is performed by controlling a port by software.

Caution Be sure to select a communication mode depending on the number of V^PPpulses shown in

Table 16-2.

Figure 16-1. Format of Communication Mode Selection

10 V

V

PP

V

DD

1

2

n

V

SS

V

PP pulse

V

DD

RESET

V

SS

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16.1.2 Function of flash memory programming

By transmitting/receiving commands and data in the selected communication mode, operations such as writing to

the flash memory are performed. Table 16-3 shows the major functions of flash memory programming.

Table 16-3. Functions of Flash Memory Programming

Function

Batch erase

Description

Erases all contents of memory

Batch blank check

Data write

Checks erased state of entire memory

Writes to flash memory based on write start address and number of data written (number of bytes)

Compares all contents of memory with input data

Batch verify

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16.1.3 Flashpro III connection

Connection between Flashpro III and the µPD78F9831 differs depending on the communication mode (UART or

pseudo 3-wire mode). Figure 16-2 shows the connection in the respective modes.

Figure 16-2. Flashpro III Connection Example

(a) UART

Flashpro III

µ

PD78F9831

VPP1

VDD

V

PP

DD0, VDD1

RESET

SO

RESET

RxD00

TxD00

SI

GND

V

SS0, VSS1

(b) Pseudo 3-Wire Mode

Flashpro III

µ

PD78F9831

VPP1

VDD

V

PP

DD0, VDD1

RESET

CLK^Note

SCK

RESET

X1

P10 (Serial clock)

P12 (Serial input)

P11 (Serial output)

SO

SI

GND

VSS0, VSS1

Note Connect the CLK pin when the system clock is input from Flashpro III. When a resonator has already

been connected to the X1 pin, there is no need to connect the CLK pin to the X1 pin.

Caution Be sure to connect the VDD pin to the VDD pin of Flashpro III, even if it is already connected to

the power supply. When using the power supply, be sure to apply voltage before starting

programming.

Remark There is no need to connect the CLK pin to the X1 pin, because the clock of the resonator connected

to the X1 pin is always used when UART is used in Flashpro III.

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16.1.4 Setting with Flashpro III

Perform the setting shown in Table 16-4 when writing data to the flash memory by using Flashpro III.

Table 16-4. Setting with Flashpro III

Communication Mode

UART

Setting with Flashpro III

78 K(2)

V^PPPulse Count^{Note 1}

Type

8

RAM

128

ROM

Flash

START ADDRESS

END ADDRESS

COMM PORT

CPU CLK

0

BFFF

UART ch-0

On Target Board

4.91/5.0 MHz

9,600 bps^{Note 2}

78 K(2)

On Target Board

UART BPS

Type

Pseudo 3-wire mode

12

RAM

128

ROM

Flash

START ADDRESS

END ADDRESS

COMM PORT

CPU CLK

0

BFFF

Port A

On Target Board

In Flashpro

4.1/5.0 MHz

On Target Board

On Target Board: 5.0 MHz SIO CLK 3.6 kHz (MAX.)

On Target Board: 4.1 MHz SIO CLK 3.1 kHz (MAX.)

In Flashpro

SIO CLK

1.56 MHz

1 kHz

Notes 1. The number of V^PPpulses supplied from Flashpro III when serial communication is initialized. These

pulses determine the pins used for communication.

2. Select 9,600 bps, 19,200 bps, 38,400 bps, or 76,800 bps.

Remark COMM PORT: Selects serial port.

SIO CLK:

CPU CLK:

Selects serial clock frequency.

Selects source of CPU clock to be input.

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CHAPTER 16 µPD78F9831

16.1.5 On-board pin connections

When programming on the target system, provide a connector on the target system to connect to the dedicated

flash programmer.

There may be cases in which an on-board function that switches from the normal operation mode to flash

memory programming mode is required.

<V^PPpin>

Input 0 V to the V^PPpin in the normal operation mode. A writing voltage of 10.0 V (TYP.) is supplied to the V^PP

pin in the flash memory programming mode. Therefore, Handle this pin in either of the following ways (1) and

(2).

(1) Connect a pull-down resistor of RV^PP= 10 kΩ to the V^PPpin.

(2) Set the jumper on the board to switch the input of V^PPpin to the programmer side or directly to GND.

The following shows an example of V^PPpin connection.

Figure 16-3. V^PPPin Connection Example

PD78F9831

µ

Connection pin of dedicated flash programmer

VPP

Pull-down resistor (RVPP

)

The following shows the pins used by each serial interface.

Serial Interface

Pins Used

UART

TxD00/P25, RxD00/P26

P10, P11, P12

Pseudo 3-wire

Note that signal conflict or malfunction of other devices may occur when an on-board serial interface pin that

is connected to another device is connected to the dedicated flash programmer.

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(1) Signal conflict

A signal conflict occurs if the dedicated flash programmer (output) is connected to a serial interface pin

(input) connected to another device (output). To prevent this signal conflict, isolate the connection with the

other device or put the other device in the output high impedance status.

Figure 16-4. Signal Conflict (Serial Interface Input Pin)

µ

PD78F9831

Input pin

Connection pin of dedicated flash

programmer

Signal conflict

Other device

Output pin

In the flash memory programming mode, the signal

output by another device and the signal sent by the

dedicated flash programmer conflict. To prevent this,

isolate the signal on the device side.

(2) Malfunction of another device

When the dedicated flash programmer (output or input) is connected to a serial interface pin (input or

output) connected to another device (input), a signal may be output to the device, causing a malfunction.

To prevent such malfunction, isolate the connection with other device or set so that the input signal to the

device is ignored.

Figure 16-5. Malfunction of Another Device

µ

PD78F9831

Connection pin of dedicated flash

programmer

Other device

Input pin

If the signal output by the

flash memory programming mode, isolate the signal on the device side.

µ

PD78F9831 affects another device in the

µ

PD78F9831

Connection pin of dedicated flash

programmer

Other device

Input pin

If the signal output by the dedicated flash programmer affects another

device, isolate the signal on the device side.

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When the reset signal of the dedicated flash programmer is connected to the RESET signal connected to the

reset signal generator on the board, a signal conflict occurs. To prevent this signal conflict, isolate the

connection with the reset signal generator.

If a reset signal is input from the user system in the flash memory programming mode, a normal programming

operation will not be performed. Do not input signals other than reset signals from the dedicated flash

programmer during this period.

Figure 16-6. Signal Conflict (RESET Pin)

µ

PD78F9831

RESET

Connection pin of dedicated

flash writer

Signal conflict

Reset signal generator

Output pin

In the flash memory programming mode, the signal output

by the reset signal generator and the signal output by the

dedicated flash writer conflict, therefore, isolate the

signal on the reset signal generator side

Shifting to the flash memory programming mode sets all the pins except those used for flash memory

programming communication to the status immediately after reset.

Therefore, if the external device does not acknowledge an initial status such as the output high impedance

status, connect the external device to V^DD0or V^SS0via a resistor.

When using an on-board clock, connection of X1 and X2 must conform to the methods in the normal operation

mode.

When using the clock output of the flash programmer, directly connect it to the X1 pin with the on-board main

resonator disconnected, and leave the X2 pin open. The subclock (XT1 and XT2) conforms to the method in the

normal operation mode.

To use the power output of the flash programmer, connect the V^DD0and V^DD0pins to VDD of the flash

programmer, and the V^SS0and V^SS1pins to GND of the flash programmer.

To use the on-board power supply, connection must conform to that in the normal operation mode. However,

because the voltage is monitored by the flash programmer, therefore, VDD of the flash programmer must be

connected.

Handle other pins (S0 to S31 and COM0 to COM15) in the same manner as is in the normal operation mode.

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CHAPTER 17 INSTRUCTION SET

This chapter lists the instruction set of the µPD789830 Subseries. For the details of the operation and machine

language (instruction code) of each instruction, refer to 78K/0S Series Instruction User's Manual (U11047E).

17.1 Operation

17.1.1 Operand identifiers and description methods

Operands are described in "Operand" column of each instruction in accordance with the description method of

the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more

description methods, select one of them. Alphabetic letters in capitals and symbols, #, !, $, and [ ] are key words

and are described as they are. Each symbol has the following meaning.

• #: Immediate data specification

• !: Absolute address specification

• $: Relative address specification

• [ ]: Indirect address specification

In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to

describe the #, !, $ and [ ] symbols.

For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in

parentheses in the table below, R0, R1, R2, etc.) can be used for description.

Table 17-1. Operand Identifiers and Description Methods

Identifier

Description Method

r

X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)

AX (RP0), BC (RP1), DE (RP2), HL (RP3)

Special function register symbol

rp

sfr

saddr

FE20H to FF1FH Immediate data or labels

saddrp

FE20H to FF1FH Immediate data or labels (even addresses only)

addr16

addr5

0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions)

0040H to 007FH Immediate data or labels (even addresses only)

word

byte

bit

16-bit immediate data or label

8-bit immediate data or label

3-bit immediate data or label

Remark See Table 3-4 for symbols of special function registers.

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17.1.2 Description of "Operation" column

A:

A register; 8-bit accumulator

X:

X register

B:

B register

C:

C register

D:

D register

E:

E register

H:

H register

L:

L register

AX:

BC:

DE:

HL:

PC:

SP:

AX register pair; 16-bit accumulator

BC register pair

DE register pair

HL register pair

Program counter

Stack pointer

PSW: Program status word

CY:

AC:

Z:

Carry flag

Auxiliary carry flag

Zero flag

IE:

Interrupt request enable flag

NMIS: Flag indicating non-maskable interrupt servicing in progress

( ): Memory contents indicated by address or register contents in parentheses

×^H, ×^L: Higher 8 bits and lower 8 bits of 16-bit register

∧:

∨:

Logical product (AND)

Logical sum (OR)

Exclusive logical sum (exclusive OR)

Inverted data

:

addr16: 16-bit immediate data or label

jdisp8: Signed 8-bit data (displacement value)

17.1.3 Description of "flag operation" column

(Blank): Unchanged

0:

1:

×

Cleared to 0

Set to 1

Set/cleared according to the result

Previously saved value is stored

R:

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17.2 Operation List

Mnemonic

MOV

Operands

Byte

Clock

Operation

Flag

Z

AC CY

r, #byte

3

2

3

2

1

2

1

2

1

2

6

4

8

6

4

6

4

6

8

r ← byte

saddr, #byte

sfr, #byte

A, r ^{Note 1}

(saddr) ← byte

sfr ← byte

A ← r

r, A ^{Note 1}

r ← A

A, saddr

saddr, A

A, sfr

A ← (saddr)

(saddr) ← A

A ← sfr

sfr, A

sfr ← A

A, !addr16

!addr16, A

PSW, #byte

A, PSW

PSW, A

A, [DE]

A ← (addr16)

(addr16) ← A

PSW ← byte

A ← PSW

PSW ← A

A ← (DE)

(DE) ← A

A ← (HL)

×

[DE], A

A, [HL]

[HL], A

(HL) ← A

A, [HL + byte]

[HL + byte], A

A, X

A ← (HL + byte)

(HL + byte) ← A

A ↔ X

XCH

A, r ^{Note 2}

A ↔ r

A, saddr

A, sfr

A ↔ (saddr)

A ↔ sfr

A, [DE]

A ↔ (DE)

A ↔ (HL)

A, [HL]

A, [HL + byte]

A ↔ (HL + byte)

Notes 1. Except r = A.

2. Except r = A, X.

Remark One instruction clock cycle is one CPU clock cycle (f^CPU) selected by the processor clock control

register (PCC).

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Mnemonic

MOVW

Operands

Byte

Clock

Operation

Flag

Z

AC CY

rp, #word

3

2

1

2

3

2

3

1

2

3

2

3

1

2

3

2

3

1

2

6

8

4

8

4

6

4

8

6

4

6

4

8

6

4

6

4

8

6

rp ← word

AX, saddrp

saddrp, AX

AX, rp ^Note

rp, AX ^Note

AX, rp ^Note

A, #byte

AX ← (saddrp)

(saddrp) ← AX

AX ← rp

rp ← AX

XCHW

ADD

AX ↔ rp

A, CY ← A + byte

×

saddr, #byte

A, r

(saddr), CY ← (saddr) + byte

A, CY ← A + r

A, saddr

A, CY ← A + (saddr)

A, !addr16

A, [HL]

A, CY ← A + (addr16)

A, CY ← A + (HL)

A, [HL + byte]

A, #byte

A, CY ← A + (HL + byte)

A, CY ← A + byte + CY

(saddr), CY ← (saddr) + byte + CY

A, CY ← A + r + CY

ADDC

saddr, #byte

A, r

A, saddr

A, CY ← A + (saddr) + CY

A, CY ← A + (addr16) + CY

A, CY ← A + (HL) + CY

A, CY ← A + (HL + byte) + CY

A, CY ← A − byte

A, !addr16

A, [HL]

A, [HL + byte]

A, #byte

SUB

saddr, #byte

A, r

(saddr), CY ← (saddr) − byte

A, CY ← A − r

A, saddr

A, CY ← A − (saddr)

A, !addr16

A, [HL]

A, CY ← A − (addr16)

A, CY ← A − (HL)

A, [HL + byte]

A, CY ← A − (HL + byte)

Note Only when rp = BC, DE, or HL.

Remark One instruction clock cycle is one CPU clock cycle (f^CPU) selected by the processor clock control

register (PCC).

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Mnemonic

SUBC

Operands

Byte

Clock

Operation

Flag

Z

×

AC CY

A, #byte

2

3

2

3

1

2

3

2

3

1

2

3

2

3

1

2

3

2

3

1

2

4

6

4

8

6

4

6

4

8

6

4

6

4

8

6

4

6

4

8

6

A, CY ← A − byte − CY

×

saddr, #byte

A, r

(saddr), CY ← (saddr) − byte − CY

A, CY ← A − r − CY

A, CY ← A − (saddr) − CY

A, CY ← A − (addr16) − CY

A, CY ← A − (HL) − CY

A, CY ← A − (HL + byte) − CY

A ← A ∧ byte

A, saddr

A, !addr16

A, [HL]

A, [HL + byte]

A, #byte

saddr, #byte

A, r

AND

(saddr) ← (saddr) ∧ byte

A ← A ∧ r

A, saddr

A, !addr16

A, [HL]

A ← A ∧ (saddr)

A ← A ∧ (addr16)

A ← A ∧ (HL)

A, [HL + byte]

A, #byte

saddr, #byte

A, r

A ← A ∧ (HL + byte)

A ← A ∨ byte

OR

(saddr) ← (saddr) ∨ byte

A ← A ∨ r

A, saddr

A, !addr16

A, [HL]

A ← A ∨ (saddr)

A ← A ∨ (addr16)

A ← A ∨ (HL)

A, [HL + byte]

A, #byte

saddr, #byte

A, r

A ← A ∨ (HL + byte)

A ← A ∨ byte

XOR

(saddr) ← (saddr) ∨ byte

A ← A ∨ r

A, saddr

A, !addr16

A, [HL]

A ← A ∨ (saddr)

A ← A ∨ (addr16)

A ← A ∨ (HL)

A, [HL + byte]

A ← A ∨ (HL + byte)

Remark One instruction clock cycle is one CPU clock cycle (f^CPU) selected by the processor clock control

register (PCC).

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CHAPTER 17 INSTRUCTION SET

Mnemonic

CMP

Operands

Byte

Clock

Operation

Flag

Z

×

AC CY

A, #byte

2

3

2

3

1

2

3

2

1

3

2

3

2

3

2

3

2

1

4

6

4

8

6

4

2

6

4

6

10

6

4

6

10

2

A − byte

×

saddr, #byte

A, r

(saddr) − byte

A − r

A, saddr

A, !addr16

A, [HL]

A, [HL + byte]

AX, #word

r

A − (saddr)

A − (addr16)

A − (HL)

A − (HL + byte)

ADDW

SUBW

CMPW

INC

AX, CY ← AX + word

AX, CY ← AX − word

AX − word

r ← r + 1

saddr

r

(saddr) ← (saddr) + 1

r ← r − 1

DEC

saddr

rp

(saddr) ← (saddr) − 1

rp ← rp + 1

INCW

DECW

ROR

rp

rp ← rp − 1

A, 1

(CY, A⁷← A⁰, A^m−1← A^m) × 1

(CY, A⁰← A⁷, A^m+1← A^m) × 1

(CY ← A⁰, A⁷← CY, A^m−1← A^m) × 1

(CY ← A⁷, A⁰← CY, A^m+1← A^m) × 1

(saddr.bit) ← 1

sfr.bit ← 1

×

ROL

A, 1

RORC

ROLC

SET1

A, 1

saddr.bit

sfr.bit

A.bit

A.bit ← 1

PSW.bit

[HL].bit

saddr.bit

sfr.bit

PSW.bit ← 1

×

(HL).bit ← 1

CLR1

(saddr.bit) ← 0

sfr.bit ← 0

A.bit

A.bit ← 0

PSW.bit

[HL].bit

CY

PSW.bit ← 0

×

(HL).bit ← 0

SET1

CLR1

NOT1

CY ← 1

1

0

×

CY

CY ← 0

CY

CY ← CY

Remark One instruction clock cycle is one CPU clock cycle (f^CPU) selected by the processor clock control

register (PCC).

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Mnemonic

Operands

Byte

Clock

Operation

Flag

Z

AC CY

CALL

!addr16

[addr5]

3

1

6

8

(SP − 1) ← (PC + 3)^H, (SP − 2) ← (PC + 3)^L,

PC ← addr16, SP ← SP − 2

CALLT

(SP − 1) ← (PC + 1)^H, (SP − 2) ← (PC + 1)^L,

PC^H← (00000000, addr5 + 1),

PC^L← (00000000, addr5), SP ← SP − 2

RET

1

6

8

PC^H← (SP + 1), PC^L← (SP), SP ← SP + 2

RETI

PC^H← (SP + 1), PC^L← (SP),

R

PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0

PUSH

POP

PSW

1

2

3

2

1

2

4

3

4

3

4

2

3

2

4

(SP − 1) ← PSW, SP ← SP − 1

(SP − 1) ← rp^H, (SP − 2) ← rp^L, SP ← SP − 2

PSW ← (SP), SP ← SP + 1

rp

PSW

4

rp

6

rp^H← (SP + 1), rp^L← (SP), SP ← SP + 2

SP ← AX

MOVW

BR

SP, AX

AX, SP

!addr16

$addr16

AX

8

6

AX ← SP

6

PC ← addr16

6

PC ← PC + 2 + jdisp8

6

PC^H← A, PC^L← X

BC

$saddr16

6

PC ← PC + 2 + jdisp8 if CY = 1

PC ← PC + 2 + jdisp8 if CY = 0

PC ← PC + 2 + jdisp8 if Z = 1

PC ← PC + 2 + jdisp8 if Z = 0

PC ← PC + 4 + jdisp8 if (saddr.bit) = 1

PC ← PC + 4 + jdisp8 if sfr.bit = 1

PC ← PC + 3 + jdisp8 if A.bit = 1

PC ← PC + 4 + jdisp8 if PSW.bit = 1

PC ← PC + 4 + jdisp8 if (saddr.bit) = 0

PC ← PC + 4 + jdisp8 if sfr.bit = 0

PC ← PC + 3 + jdisp8 if A.bit = 0

PC ← PC + 4 + jdisp8 if PSW.bit = 0

B ← B − 1, then PC ← PC + 2 + jdisp8 if B ≠ 0

C ← C − 1, then PC ← PC + 2 + jdisp8 if C ≠ 0

BNC

BZ

6

BNZ

BT

6

saddr.bit, $addr16

sfr.bit, $addr16

A.bit, $addr16

PSW.bit, $addr16

saddr.bit, $addr16

sfr.bit, $addr16

A.bit, $addr16

PSW.bit, $addr16

B, $addr16

10

8

10

8

BF

10

6

DBNZ

C, $addr16

6

saddr, $addr16

8

(saddr) ← (saddr) − 1, then

PC ← PC + 3 + jdisp8 if (saddr) ≠ 0

NOP

EI

1

3

1

2

6

2

No Operation

IE ← 1 (Enable Interrupt)

IE ← 0 (Disable Interrupt)

Set HALT Mode

DI

HALT

STOP

Set STOP Mode

Remark One instruction clock cycle is one CPU clock cycle (f^CPU) selected by the processor clock control

register (PCC).

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17.3 Instructions Listed by Addressing Type

(1) 8-bit instructions

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,

POP, DBNZ

2nd Operand

1st Operand

#byte

A

r

sfr

saddr !addr16

PSW

MOV

[DE]

[HL]

$addr16

1

None

[HL + byte]

A

ADD

MOV^NoteMOV

XCH^NoteXCH

ADD

MOV

XCH

ADD

ADDC

SUB

SUBC

AND

OR

MOV

XCH

MOV

XCH

ADD

ADDC

SUB

SUBC

AND

OR

MOV

XCH

ADD

ADDC

SUB

SUBC

AND

OR

ROR

ADDC

SUB

SUBC

AND

OR

ROL

ADD

ADDC

SUB

SUBC

AND

OR

RORC

ROLC

ADDC

SUB

SUBC

XOR

CMP

AND

OR

XOR

CMP

XOR

CMP

XOR

CMP

XOR

CMP

r

MOV

INC

DEC

B, C

sfr

DBNZ

MOV

saddr

MOV

ADD

ADDC

SUB

SUBC

AND

OR

INC

DEC

XOR

CMP

!addr16

PSW

MOV

PUSH

POP

[DE]

MOV

[HL]

[HL + byte]

Note Except r = A.

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(2) 16-bit instructions

MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW

2nd Operand

1st Operand

#word

AX

rp^Note

saddrp

SP

None

AX

ADDW

MOVW

XCHW

MOVW

SUBW

CMPW

rp

MOVW

MOVW^Note

INCW

DECW

PUSH

POP

saddrp

SP

MOVW

Note Only when rp = BC, DE, or HL.

(3) Bit manipulation instructions

SET1, CLR1, NOT1, BT, BF

2nd Operand

1st Operand

$addr16

None

A.bit

BT

BF

SET1

CLR1

sfr.bit

BT

BF

SET1

CLR1

saddr.bit

PSW.bit

[HL].bit

CY

BT

BF

SET1

CLR1

BT

BF

SET1

CLR1

SET1

CLR1

SET1

CLR1

NOT1

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CHAPTER 17 INSTRUCTION SET

(4) Call instructions/branch instructions

CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ

2nd Operand

1st Operand

AX

!addr16

[addr5]

$addr16

Basic instructions

BR

CALL

BR

CALLT

BR

BC

BNC

BZ

BNZ

Compound instructions

DBNZ

(5) Other instructions

RET, RETI, NOP, EI, DI, HALT, STOP

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CHAPTER 18 ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25°C) (µPD789830)

Parameter

Supply voltage

Symbol

V^DD

Conditions

Ratings

Unit

V

−0.3 to +6.5

Input voltage

V^I1

P00 to P07, P10, P11, P20 to P23, P25,

P26, P30 to P34, P50 to P57, X1, X2, XT1,

XT2, RESET

−0.3 to V^DD+ 0.3^Note

V

V^I2

V^O

I^OH

P24 (N-ch open drain)

−0.3 to +13

−0.3 to V^DD+ 0.3^Note

V

Output voltage

V

Output current, high

Per pin

−10

−30

mA

°C

Total for all pins

Per pin

Output current, low

I^OL

30

Total for all pins

160

Operating temperature

Storage temperature

T^A

−20 to +60

−65 to +150

T^stg

°C

Note 6.5 V or lower

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for

any parameter. That is, the absolute maximum ratings are rated values at which the product is

on the verge of suffering physical damage, and therefore the product must be used under

conditions that ensure that the absolute maximum ratings are not exceeded.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port

pins.

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Absolute Maximum Ratings (TA = 25°C) (µPD78F9831)

Parameter

Supply voltage

Symbol

V^DD

Conditions

Ratings

−0.3 to +6.5

Unit

V

V^PP

−0.3 to +10.5

−0.3 to V^DD+ 0.3^Note

V

Input voltage

V^I1

P00 to P07, P10 to P17, P20 to P23, P25,

P26, P30 to P34, P40, P41, P50 to P57,

X1, X2, XT1, XT2, RESET

V

V^I2

V^O

I^OH

P24 (N-ch open drain)

−0.3 to +13

−0.3 to V^DD+ 0.3^Note

−10

V

Output voltage

V

Output current, high

Per pin

mA

°C

Total for all pins

Per pin

−30

Output current, low

I^OL

30

Total for all pins

During normal operation

During flash memory programming

160

Operating ambient temperature

T^A

−20 to +60

10 to 40

−40 to +125

°C

Storage temperature

T^stg

°C

Note 6.5 V or lower

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for

any parameter. That is, the absolute maximum ratings are rated values at which the product is

on the verge of suffering physical damage, and therefore the product must be used under

conditions that ensure that the absolute maximum ratings are not exceeded.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port

pins.

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Main System Clock Oscillator Characteristics (TA = −20 to +60°C, VDD = 2.7 to 5.5 V)

Resonator Recommended Circuit

Ceramic

Parameter

Conditions

MIN.

2.0

TYP.

MAX.

5.0

Unit

Oscillator frequency (f^X)^{Note 1}

V^DDoscillation voltage

range

MHz

V

SS0 X1

X2

resonator

Oscillation stabilization

time^{Note 2}

After V^DDreaches

oscillation voltage

range MIN.

4

ms

C1

C2

Oscillator frequency (f^X)^{Note 1}

2.0

5.0

MHz

V

SS0 X1

X2

Crystal

C1

C2

Oscillation stabilization

time^{Note 2}

V^DD= 4.5 to 5.5 V

V^DD= 2.7 to 5.5 V

10

30

5.0

ms

External

clock

X1 input frequency (f^X)^{Note 1}

2.0

85

MHz

X1

X2

X1 input high-/low-level width

(t^XH, t^XL)

250

ns

OPEN

Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for the instruction execution time.

2. Time required to stabilize oscillation after reset or STOP mode release. Use the resonator that

stabilizes oscillation within the oscillation wait time.

Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS0.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

2. When the main system clock is stopped and the device is operating on the subsystem

clock, wait until the oscillation stabilization time has been secured by the program before

switching back to the main system clock.

Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation

themselves or apply to the resonator manufacturer for evaluation.

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Subsystem Clock Oscillator Characteristics (TA = −20 to +60°C, VDD = 2.7 to 5.5 V)

Resonator Recommended Circuit

Crystal

Parameter

Conditions

MIN.

32

TYP.

MAX.

35

Unit

kHz

Oscillator frequency (f^XT)^{Note 1}

32.768

V

SS0 XT1 XT2

resonator

R

Oscillation stabilization

time^{Note 2}

V^DD= 4.5 to 5.5 V

V^DD= 2.7 to 5.5 V

1.2

2

s

C3

C4

10

35

s

External

clock

XT1 input frequency (f^XT)^{Note 1}

32

kHz

XT2

XT1

XT1 input high-/low-level

width (t^XTH, t^XTL)

14.3

15.6

µs

Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for the instruction execution time.

2. Time required to stabilize oscillation after V^DDreaches oscillation voltage range MIN. Use the

resonator that stabilizes oscillation within the oscillation wait time.

Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS0.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current

consumption, and is more prone to malfunction due to noise than the main system clock

oscillator. Particular care is therefore required with the wiring method when the subsystem

clock is used.

Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation

themselves or apply to the resonator manufacturer for evaluation.

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CHAPTER 18 ELECTRICAL SPECIFICATIONS

DC Characteristics (TA = −20 to +60°C, VDD = 2.7 to 5.5 V) (µPD789830) (1/2)

Parameter

Symbol

I^OH

Conditions

MIN.

TYP.

MAX.

−1

Unit

mA

V

Output current, high

Per pin

Total for all pins

Per pin

−15

Output current, low

Input voltage, high

I^OL

10

Total for all pins

80

V^IH1

V^IH2

V^IH3

V^IH4

V^IL1

V^IL2

V^IL3

VIL4

V^OH

P00 to P07, P10, P11, P23, P25, P50 to P57

RESET, P20 to P22, P26, P30 to 34

P24 (N-ch open drain)

0.7V^DD

0.8V^DD

0.7V^DD

V^DD−0.1

0

V^DD

V

12

V

X1, X2, XT1, XT2

V^DD

V

Input voltage, high

P00 to P07, P10, P11, P23, P25, P50 to P57

RESET, P20 to P22, P26, P30 to P34

P24 (N-ch open drain)

0.3V^DD

0.2V^DD

0.3V^DD

0.1

V

0

V

0

V

X1, X2, XT1, XT2

0

V

Output voltage, high

Output voltage, low

V^DD= 4.5 to 5.5 V, I^OH= −1 mA

I^OH= 2.7 to 5.5 V, I^OH= −100 µA

V^DD−1.0

V^DD−0.5

V

V^OL1

Pins other than P24

V^DD= 4.5 to 5.5 V.

1.0

0.5

1.0

0.4

V

I^OL= 10 mA

V^DD= 2.7 to 5.5 V,

V

I^OL= 400 µA

V^OL2

P24 (N-ch open drain)

V^DD= 4.5 to 5.5 V,

I^OL= 10 mA

V^DD= 2.7 to 5.5 V,

I^OL= 1.6 mA

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port

pins.

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CHAPTER 18 ELECTRICAL SPECIFICATIONS

DC Characteristics (TA = −20 to +60 °C, VDD = 2.7 to 5.5 V) (µPD789830) (2/2)

Parameter

Symbol

I^LIH1

Conditions

MIN.

TYP.

MAX.

3

Unit

Input leakage

current, high

V^IN= V^DD

P00 to P07, P10, P11, P20 to P23,

P25, P26, P30 to P34, P50 to P57,

RESET

µA

I^LIH2

I^LIH3

I^LIL1

X1, X2, XT1, XT2

20

−3

µA

V^IN= 12 V

V^IN= 0 V

P24 (N-ch open drain)

Input leakage

current, low

P00 to P07, P10, P11, P20 to P23,

P25, P26, P30 to P34, P50 to P57,

RESET, P24 (N-ch open drain),

except during read

I^LIL2

I^LIL3

I^LOH

X1, X2, XT1, XT2

−20

−30

3

µA

P24 (N-ch open drain), during read

Output leakage

current, high

V^OUT= V^DD

V^OUT= 0 V

Output leakage

current, low

I^LOL

−3

µA

kΩ

Software pull-up

resistor

R¹

V^IN= 0 V, P00 to P07, P10, P11, P30 to P34

50

100

200

V^DD= 5.0 V 10%^{Note 2}

5.0 MHz crystal

Power supply

current^{Note 1}

I^DD1

1.7

3.2

0.9

mA

V^DD= 3.0 V 10%^{Note 3}

oscillation

0.45

operating mode

V^DD= 5.0 V 10%^{Note 2}

I^DD2

I^DD3

I^DD4

I^DD5

5.0 MHz crystal

0.6

0.3

1.2

0.6

mA

V^DD= 3.0 V 10%^{Note 3}

oscillation HALT

mode

32.768 kHz crystal

oscillation

operating mode^{Note 4}

V^DD= 5.0 V 10%

V^DD= 3.0 V 10%

25

12

50

35

µA

32.768 kHz crystal V^DD= 5.0 V 10%

17

5

34

17

µA

oscillation HALT

mode^{Note 4}

V^DD= 3.0 V 10%

STOP mode

V^DD= 5.0 V 10%

V^DD= 3.0 V 10%

0.1

10

µA

0.05

5.0

Notes 1. Does not include the current when the LCD is operating (LCDON20 (bit 7 of LCD20 mode register

(LCDM20)) = 1, LIPS20 (bit 4 of LCDM20) = 1) and the port current (including the current flowing

through the on-chip pull-up resistors). For the current when the LCD is operating, refer to LCD

Operating Current in LCD Characteristics.

2. High-speed mode operation (when processor clock control register (PCC) is set to 00H)

3. Low-speed mode operation (when PCC is set to 02H)

4. When the main system clock operation is stopped

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port

pins.

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CHAPTER 18 ELECTRICAL SPECIFICATIONS

DC Characteristics (TA = −20 to +60°C, VDD = 2.7 to 5.5 V) (µPD78F9831) (1/2)

Parameter

Symbol

I^OH

Conditions

MIN.

TYP.

MAX.

−1

Unit

mA

Output current,

high

Per pin

Total for all pins

Per pin

−15

10

Output current, low

I^OL

Total for all pins

80

Input voltage, high

V^IH1

V^IH2

V^IH3

V^IH4

P00 to P07, P10 to P17, P23, P25, P50 to P57

RESET, P20 to P22, P26, P30 to P34, P40, P41

P24 (N-ch open drain)

0.7V^DD

V^DD

V

0.8V^DD

0.7V^DD

12

X1, X2, XT1, XT2

V^DD= 4.5 to 5.5 V

V^DD= 2.7 to 5.5 V

V^DD− 0.5

V^DD

V^DD− 0.1

V^DD

Input voltage, low

V^IL1

V^IL2

V^IL3

V^IL4

P00 to P07, P10 to P17, P23, P25, P50 to P57

RESET, P20 to P22, P26, P30 to P34, P40, P41

P24 (N-ch open drain)

0

0.3V^DD

0.2V^DD

0.3V^DD

0.4

0

X1, X2, XT1, XT2

V^DD= 4.5 to 5.5 V

V^DD= 2.7 to 5.5 V

V^DD= 4.5 to 5.5 V

V^DD= 2.7 to 5.5 V

0

0.1

Output voltage,

high

V^OH

I^OH= −1 mA

V^DD− 1.0

V^DD− 0.5

I^OH= −100 µA

Output voltage,

low

V^OL1

Pins other than the P24

4.5 < V^DD< 5.5 V,

I^OL= 10 mA

1.0

0.5

1.0

0.4

3

2.7 < V^DD< 4.5 V,

I^OL= 400 µA

V

V^OL2

P24 (N-ch open drain)

V^DD= 4.5 to 5.5 V,

I^OL= 10 mA

2.7 < V^DD< 4.5 V,

I^OL= 1.6 mA

V

Input leakage

current, high

I^LIH1

V^IN= V^DD

P00 to P07, P10 to

P17, P20 to P23, P25,

P26, P30 to P34, P40,

P41, P50 to P57,

RESET

µA

I^LIH2

I^LIH3

I^LIL1

X1, X2, XT1, XT2

20

−3

µA

V^IN= 12 V

V^IN= 0 V

P24 (N-ch open drain)

Input leakage

current, low

P00 to P07, P10 to

P17, P20 to P23, P25,

P26, P30 to P34, P40,

P41, P50 to P57,

RESET, P24 (When

an input instruction is

not executed)

I^LIL2

I^LIL3

X1, X2, XT1, XT2

−20

−30

µA

P24 (N-ch open drain)

When an input

instruction is executed

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port

pins.

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CHAPTER 18 ELECTRICAL SPECIFICATIONS

DC Characteristics (TA = −20 to +60°C, VDD = 2.7 to 5.5 V) (µPD78F9831) (2/2)

Parameter

Symbol

I^LOH

Conditions

MIN.

TYP.

MAX.

3

Unit

Output leakage

current, high

V^OUT= V^DD

V^OUT= 0 V

µA

Output leakage

current, low

I^LOL

-3

µA

kΩ

Software pull-up

resistor

R¹

V^IN= 0 V, P00 to P07, P10 to P17, P30 to P34

50

100

200

Power supply

current^{Note 1}

I^DD1

5.0 MHz crystal

oscillation operating

mode

V^DD= 5.0 V 10%^{Note 2}

V^DD= 3.0 V 10%^{Note 3}

5

3

10

6

MA

mA

I^DD2

5.0 MHz crystal

V^DD= 5.0 V 10%^{Note 2}

V^DD= 3.0 V 10%^{Note 3}

V^DD= 5.0 V 10%

0.8

0.4

120

1.6

0.8

240

mA

µA

oscillation HALT mode

I^DD3

32.768 kHz crystal

oscillation operating

mode^{Note 4}

V^DD= 3.0 V 10%

V^DD= 5.0 V 10%

80

25

160

55

µA

I^DD4

32.768 kHz crystal

oscillation HALT

mode^{Note 4}

V^DD= 3.0 V 10%

10

20

µA

I^DD5

STOP mode

V^DD= 5.0 V 10%

V^DD= 3.0 V 10%

0.1

10

µA

0.05

Notes 1. Does not include the current when the LCD is operating (LCDON20 = 1, LIPS20 = 1) and the port

current (including the current flowing through the on-chip pull-up resistors).

2. High-speed mode operation (when processor clock control register (PCC) is set to 00H)

3. Low-speed mode operation (when PCC is set to 02H)

4. When the main system clock operation is stopped

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port

pins.

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CHAPTER 18 ELECTRICAL SPECIFICATIONS

LCD Characteristics (TA = −20 to +60°C, VDD = 2.7 to 5.5 V)

Parameter

Symbol

V^LCD

Conditions

MIN.

3.5

TYP.

MAX.

5.5

Unit

V

LCD drive voltage

V^DD= V^LCD

VAON20 = 0

VAON20 = 1

2.7

5.5

V

Segment output

voltage^{Note 1}

V^ODS

When the output level is V^LC0

When the output level is V^LC2

When the output level is V^LC3

When the output level is V^LC0

When the output level is V^LC1

When the output level is V^LC4

V^LCn→ Sp, I^O= | 20 µA |

V^LCD

3/5V^LCD

2/5V^LCD

V^LCD

V

Common output

voltage^{Note 1}

V^ODC

V

4/5V^LCD

1/5V^LCD

5.0

V

Segment output on

resistance

R^SEG

R^COM

f^LCD

12.5

10.0

kΩ

Common output on

resistance

V^LCn→ COMq, I^O= | 20 µA |

4.0

kΩ

LCD input

frequency

VAON20 = 1

32

78.13

50

kHz

µA

VAON20 = 0

7.81

LCD operating

current^{Note 2}

I^LCD1

I^LCD2

I^LCD1

I^LCD2

V^DD= 5.0 V 10%, VAON20 = 0

25

13

30

17

V^DD= 3.0 V 10%, VAON20 = 1

V^DD= 5.0 V 10%, VAON20 = 0

V^DD= 3.0 V 10%, VAON20 = 1

30

65

40

µA

(µPD789830)

LCD operating

current^{Note 2}

(µPD78F9831)

Notes 1. Voltages when no load is applied

2. Total current flowing through the V^DD0pin (including the current flowing through the LCD divider

resistor)

When LCDON20 = 0 and LIPS20 = 0 (the display is turned off and the internal drive power is not

supplied), the power supply current is included in the power supply current I^DD5(STOP mode) in the

DC Characteristics.

Remark n = 0 to 4

p = 0 to 39

q = 0 to 15

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CHAPTER 18 ELECTRICAL SPECIFICATIONS

AC Characteristics

(1) Basic operation (TA = −20 to +60 °C, VDD = 2.7 to 5.5 V)

Parameter

Cycle time

Symbol

T^CY

Conditions

MIN.

0.4

TYP.

122

MAX.

4.0

Unit

Operating with main system clock

µs

(Min. instruction

execution time)

Operating with subsystem clock

114

125

µs

Interrupt input high-

/low-level width

t^INTH,

t^INTL

INTP0 to INTP2 (µPD789830)

INTP0 to INTP4 (µPD78F9831)

10

µs

RESET input low-

level width

t^RSL

TCY vs VDD (main system clock)

60

10

µ

4.0

Guaranteed

operation range

1.0

0.4

0.1

1

2

3

4

5

6

Supply voltage VDD [V]

(2) Serial interface (UART00) (TA = −20 to +60 °C, VDD = 2.7 to 5.5 V)

Parameter

Symbol

Conditions

Operation at f^X= 5.0 MHz

MIN.

TYP.

MAX.

Unit

bps

Transfer rate

78,125

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CHAPTER 18 ELECTRICAL SPECIFICATIONS

AC Timing Test Points (excluding X1, XT1 inputs)

0.8VDD

0.2VDD

0.8VDD

0.2VDD

Test points

Clock Timing

1/fX

t

XL

t

XH

V

IH4 (MIN.)

X1 input

V

IL4 (MAX.)

1/fXT

t

XTL

t

XTH

V

IH4 (MIN.)

XT1 input

V

IL4 (MAX.)

Interrupt Input Timing

t

INTL

t

INTH

INTR0 to INTP2 (

µ

PD789830)

INTP0 to INTP4 (

µ

PD78F9831)

RESET Input Timing

t

RSL

RESET

208

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CHAPTER 18 ELECTRICAL SPECIFICATIONS

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T = −20 to +60°C)

A

Parameter

Symbol

V^DDDR

Conditions

MIN.

1.8

TYP.

MAX.

5.5

Unit

V

Data retention power

supply voltage

Release signal set time

t^SREL

t^WAIT

0

µs

ms

Oscillation stabilization

wait time^{Note 1}

Release by RESET

Release by interrupt request

2¹⁵/f^X

Note 2

Notes 1. Oscillation stabilization wait time is a time for stopping the CPU operation to prevent the unstable

operation when the oscillation is started.

2. Selection of 2¹²/f^X, 2¹⁵/f^X, and 2¹⁷/f^Xis possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation

stabilization time select register (OSTS).

Remark f^X: Main system clock oscillation frequency

Data Retention Timing (STOP mode release by RESET)

Internal reset operation

HALT mode

STOP mode

Operating mode

Data retention mode

V

DD

V

DDDR

t

SREL

STOP instruction execution

RESET

t

WAIT

Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)

HALT mode

STOP mode

Operating mode

Data retention mode

V

DD

VDDDR

tSREL

STOP instruction execution

Standby release signal

(interrupt request)

t

WAIT

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User's Manual U13679EJ2V0UD

CHAPTER 18 ELECTRICAL SPECIFICATIONS

Flash Memory Write/Erase Characteristics (TA = 10 to 40 °C, VDD = 2.7 to 5.5 V)

Parameter

Symbol

f^X

Conditions

MIN.

2

TYP.

MAX.

5

Unit

MHz

mA

Operating frequency

Write current^Note

(V^DDpin)

I^DDW

When V^PPsupply voltage = V^PP1

13

5.0 MHz crystal oscillation operating mode

Write current^Note

(V^PPpin)

I^PPW

I^DDE

I^PPE

t^er

When V^PPsupply voltage = V^PP1

20

13

mA

Erase current^Note

(V^DDpin)

When V^PPsupply voltage = V^PP1

5.0 MHz crystal oscillation operating mode

Erase current^Note

(V^PPpin)

When V^PPsupply voltage = V^PP1

100

Erase time

20

s

Times

V

Write count

Erase/write are regarded as 1 cycle.

In normal operation

V^PPsupply voltage

V^PP0

V^PP1

0

0.2V^DD

10.3

During flash memory programming

9.7

10.0

V

Note The port current (including the current that flows to the on-chip pull-up resistors) is not included.

210

User's Manual U13679EJ2V0UD

CHAPTER 19 PACKAGE DRAWINGS

100-PIN PLASTIC LQFP (FINE PITCH) (14x14)

A

B

75

76

51

50

detail of lead end

S

C

D

R

Q

100

1

26

25

F

M

G

J

H

I

K

P

S

N

S

L

M

NOTE

Each lead centerline is located within 0.08 mm of

its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

A

B

C

D

F

16.00 0.20

14.00 0.20

16.00 0.20

1.00

G

1.00

+0.05

0.22

H

−0.04

I

J

0.08

0.50 (T.P.)

1.00 0.20

0.50 0.20

K

L

+0.03

0.17

M

−0.07

N

P

Q

0.08

1.40 0.05

0.10 0.05

+7°

3°

R

−3°

S

1.60 MAX.

S100GC-50-8EU, 8EA-2

211

User's Manual U13679EJ2V0UD

CHAPTER 20 RECOMMENDED SOLDERING CONDITIONS

The µPD78F9831 should be soldered and mounted under the following recommended conditions.

For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting

Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact an NEC sales

representative.

Table 20-1. Surface Mounting Soldering Conditions

µPD78F9831GC-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14)

Recommended Condition

Soldering Method

Infrared reflow

Soldering Conditions

Symbol

Package peak temperature: 235°C, Time: 30 seconds max.

(at 210°C or higher), Count: Twice or less

IR35-00-2

VPS

Package peak temperature: 215°C, Time: 40 seconds max.

(at 200°C or higher), Count: Twice or less

VP15-00-2

Partial heating

Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)

−

Caution Do not use different soldering methods together (except for partial heating).

212

User's Manual U13679EJ2V0UD

APPENDIX A DEVELOPMENT TOOLS

The following development tools are available for development of systems using the µPD789830 Subseries.

Figure A-1 shows development tools.

• Compatibility with PC98-NX Series

Unless stated otherwise, products which are supported for IBM PC/AT^TMand compatibles can also be used

with the PC98-NX Series. When using the PC98-NX Series, therefore, refer to the explanations for IBM PC/AT

and compatibles.

• Windows

Unless stated otherwise, "Windows" refers to the following operating systems.

• Windows 3.1

• Windows 95, 98, 2000

• Windows NT^TMVer. 4.0

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APPENDIX A DEVELOPMENT TOOLS

Figure A-1. Development Tools

Software package

·

Software package

Language processing software

Debugging software

·

Assembler package

C compiler package

Device file

·

Integrated debugger

System emulator

C compiler source file^{Note 1}

Control software

·

Project manager

(Windows version only)^{Note 2}

Host machine

(PC or EWS)

Interface adapter

Power supply unit

Flash memory writing tools

Flash programmer

In-circuit emulator

Emulation board

Flash memory

writing adapter

Flash memory

Emulation probe

Conversion socket or

conversion adapter

Target system

Notes 1. The C compiler source file is not included in the software package.

2. The project manager is included in the assembler package and is available only for Windows.

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User's Manual U13679EJ2V0UD

APPENDIX A DEVELOPMENT TOOLS

A.1 Software Package

SP78K0S

Various software tools for 78K/0S development are integrated in one package.

The following tools are included.

Software package

RA78K0S, CC78K0S, ID78K0-NS, SM78K0S, various device files

Part number: µS××××SP78K0S

Remark ×××× in the part number differs depending on the operating system to be used.

µS×××× SP78K0S

××××

AB17

BB17

Host Machine

PC-9800 series,

IBM PC/AT and compatibles

OS

Supply Medium

CD-ROM

Japanese Windows

English Windows

Note Also operates under the DOS environment

A.2 Language Processing Software

RA78K0S

Program that converts program written in mnemonic into object code that can be executed by

microcontroller.

Assembler package

In addition, automatic functions to generate symbol table and optimize branch instructions are also

provided.

Used in combination with a device file (DF789831) (sold separately).

The assembler package is a DOS-based application but may be used in the Windows environment

by using the Project Manager of Windows (included in the package).

Part number: µS××××RA78K0S

CC78K0S

Program that converts program written in C language into object codes that can be executed by

microcontroller.

C compiler package

Used in combination with an assembler package (RA78K0S) and device file (DF789831) (both sold

separately).

The C compiler package is a DOS-based application but may be used in the Windows environment

by using the Project Manager of Windows (included in the assembler package).

Part number: µS××××CC78K0S

DF789831^{Note 1}

Device file

File containing the information inherent to the device.

Used in combination with other tools (RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S) (all sold

separately).

Part number: µS××××DF789831

CC78K0S-L^{Note 2}

Source file of functions constituting object library included in C compiler package.

C compiler source file

Necessary for changing object library included in C compiler package according to customer's

specifications.

Since this is the source file, its working environment does not depend on any particular operating

system.

Part number: µS××××CC78K0S-L

Notes 1. DF789831 is a common file that can be used with RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S.

2. CC78K0S-L is not included in the software package (SP78K0S).

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APPENDIX A DEVELOPMENT TOOLS

Remark ×××× in the part number differs depending on the host machine and operating system to be used.

µS××××RA78K0S

µS××××CC78K0S

××××

AB13

Host Machine

PC-9800 series,

OS

Supply Media

3.5" 2HD FD

Japanese Windows

English Windows

Japanese Windows

English Windows

HP-UX^TM(Rel.10.10)

IBM PC/AT and compatibles

BB13

AB17

BB17

3P17

3K17

CD-ROM

HP9000 series 700^TM

SPARCstation^TM

SunOS^TM(Rel.4.1.1),

Solaris^TM(Rel.2.5.1)

µS××××DF789831

µS××××CC78K0S-L

××××

AB13

BB13

3P16

3K13

3K15

Host Machine

OS

Supply Medium

PC-9800 series,

Japanese Windows

English Windows

HP-UX (Rel.10.10)

3.5" 2HD FD

IBM PC/AT and compatibles

HP9000 series 700

SPARCstation

DAT

SunOS (Rel.4.1.1),

Solaris (Rel.2.5.1)

3.5" 2HD FD

1/4" CGMT

A.3 Control Software

Control software provided for an efficient user program development in the Windows

environment. The Project Manager allows a series of tasks required for user program

development to be performed, including starting the editor, building, and starting the

debugger.

Project Manager

The Project Manager is included in the assembler package (RA78K0S).

It cannot be used in an environment other than Windows.

216

User's Manual U13679EJ2V0UD

APPENDIX A DEVELOPMENT TOOLS

A.4 Flash Memory Writing Tools

Flashpro III

Flash programmer dedicated to microcontrollers incorporating flash memory.

(part number: FL-PR3, PG-FP3)

Flash writer

FA-100GC

Flash memory writing adapter. Used in connection with Flashpro III.

100-pin plastic LQFP

Flash memory writing adapter

Remark FL-PR3 and FA-100GC are products of Naito Densei Machida Mfg. Co., Ltd.

For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (+81-45-475-4191)

A.5 Debugging Tools (Hardware)

IE-78K0S-NS

In-circuit emulator for debugging hardware and software of application system using the

78K/0S Series. Supports an integrated debugger (ID78K0S-NS). Used in combination with

an AC adapter, emulation probe, and interface adapter for connecting the host machine.

In-circuit emulator

IE-78K0S-NS-A

In-circuit emulator with enhanced functions of the IE-78K0S-NS. The debug function is further

enhanced by adding a coverage function and enhancing the tracer and timer functions.

In-circuit emulator

IE-70000-MC-PS-B

AC adapter

Adapter for supplying power from a 100 to 240 VAC outlet.

IE-70000-98-IF-C

Interface adapter

Adapter required when using a PC-9800 series (except notebook type) as the host machine

(C bus supported).

IE-70000-CD-IF-A

PC card interface

PC card and interface cable required when using a notebook type PC as the host machine

(PCMICA socket supported).

IE-70000-PC-IF-C

Interface adapter

Adapter required when using an IBM PC/AT or compatible as the host machine (ISA bus

supported).

IE-70000-PCI-IF-A

Interface adapter

Adapter required when using a personal computer incorporating the PCI bus as the host

machine.

IE-789831-NS-EM1

Emulation board

Emulation board for emulating the peripheral hardware inherent to the device.

Used in combination with an in-circuit emulator.

NP-100GC

Cable for connecting the in-circuit emulator and target system.

Emulation probe

Used in combination with the TGC-100SDW when supporting a 100-pin plastic LQFP.

TGC-100SDW

Conversion adapter

Conversion adapter used to connect a target system board designed to allow mounting a 100-

pin plastic LQFP and the NP-100GC.

Remarks 1. NP-100GC is a product made by Naito Densei Machida Mfg. Co., Ltd.

For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (+81-45-475-4191)

2. The TGC-100SDW is a product made by TOKYO ELETECH CORPORATION.

For further information, contact: Daimaru Kogyo, Ltd.

Tokyo Electronics Department (TEL +81-3-3820-7112)

Osaka Electronics Department (TEL +81-6-6244-6672)

217

User's Manual U13679EJ2V0UD

APPENDIX A DEVELOPMENT TOOLS

A.6 Debugging Tools (Software)

ID78K0S-NS

This debugger supports the in-circuit emulators IE-78K0S-NS and IE-78K0S-NS-A for the

78K/0S Series. The ID78K0S-NS is Windows-based software.

Integrated debugger

It has improved C-compatible debugging functions and can display the results of tracing with the

source program using an integrating window function that associates the source program,

disassemble display, and memory display with the trace result.

Used in combination with a device file (DF789831) (sold separately).

Part number: µS××××ID78K0S-NS

SM78K0S

This is a system simulator for the 78K/0S Series. The SM78K0S is Windows-based software.

It can be used to debug the target system at C source level of assembler level while simulating

the operation of the target system on the host machine.

System simulator

Using SM78K0S, the logic and performance of the application can be verified independently of

hardware development. Therefore, the development efficiency can be enhanced and the

software quality can be improved.

Used in combination with a device file (DF789831) (sold separately).

Part number: µS××××SM78K0S

DF789831^Note

Device file

File containing the information inherent to the device.

Used in combination with other tools (RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S) (all sold

separately).

Part number: µS××××DF789831

Note DF789831 is a common file that can be used with RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S.

Remark ×××× in the part number differs depending on the operating system to be used and the supply medium.

µS××××ID78K0S-NS

µS××××SM78K0S

××××

AB13

Host Machine

PC-9800 series,

IBM PC/AT and compatibles

OS

Supply Medium

3.5" 2HD FD

Japanese Windows

English Windows

Japanese Windows

English Windows

BB13

AB17

BB17

CD-ROM

218

User's Manual U13679EJ2V0UD

APPENDIX A DEVELOPMENT TOOLS

A.7 Package Drawings of Conversion Adapter (TGC-100SDW)

Figure A-2. TGC-100SDW Package Drawings (for Reference) (Unit: mm)

TGC-100SDW (TQPACK100SD + TQSOCKET100SDW)

Package dimension (unit: mm)

A

B

N

L

M

O

X

C

T

F E D

H I J K

P Q R S

U

G

Y

Z

e

n

k

m

a

g

h

d

c

I

b

j

i

f

ITEM MILLIMETERS

INCHES

±.848

ITEM MILLIMETERS

INCHES

±.569

A

B

C

D

E

F

ꢀ1.55

±.5xꢀ4=1ꢀ

±.5

a

b

c

d

e

f

14.45

1.85±±.ꢀ5

3.5

±.±ꢀ±x±.945=±.47ꢀ

±.±ꢀ±

±.±73±±.±1±

±.138

±.5xꢀ4=1ꢀ

15.±

±.±ꢀ±x±.945=±.47ꢀ

±.591

ꢀ.±

±.±79

3.9

±.154

ꢀ1.55

±.848

±.ꢀ5

±.±1±

φ

1±.9

φ

±.177

G

H

I

3.55

±.14±

g

h

i

4.5

±.4ꢀ9

16.±

1.1ꢀ5±±.3

±~5°

5.9

±.63±

±.±44±±.±1ꢀ

±.±±±~±.197°

±.ꢀ3ꢀ

13.3

±.5ꢀ4

J

15.7

±.618

j

K

L

18.1

±.713

k

l

13.75

±.5xꢀ4=1ꢀ.±

1.1ꢀ5±±.3

1.1ꢀ5±±.ꢀ

7.5

±.541

±.8

±.±31

M

N

O

P

Q

R

S

T

±.±ꢀ±x±.945=±.47ꢀ

±.±44±±.±1ꢀ

±.±44±±.±±8

±.ꢀ95

m

n

ꢀ.4

±.±94

ꢀ.7

±.1±6

TGC-100SDW-G1E

1±.±

±.394

11.3

±.445

18.1

±.713

φ

±.197

5.±

U

V

W

X

Y

Z

5.±

±.197

φ

4- 1.3

4- ±.±51

1.8

±.±71

C ꢀ.±

C ±.±79

φ

±.9

±.3

±.±35

±.±1ꢀ

note: Product by TOKYO ELETECH CORPORATION.

219

User's Manual U13679EJ2V0UD

APPENDIX B REGISTER INDEX

B.1 Register Name Index (Alphabetic Order)

16-bit compare register 40 (CR40).........................................................................................................................97

8-bit compare register 00 (CR00).........................................................................................................................104

8-bit timer mode control register 00 (TMC00) ......................................................................................................105

8-bit timer counter 00 (TM00)...............................................................................................................................104

[A]

Alternate port function switching register (PF5) ...................................................................................................146

Asynchronous serial interface mode register 00 (ASIM00)..................................................................127, 131, 133

Asynchronous serial interface status register 00 (ASIS00)..........................................................................129, 134

[B]

[E]

Baud rate generator control register 00 (BRGC00)......................................................................................130, 135

External interrupt mode register 0 (INTM0)..........................................................................................................159

External interrupt mode register 1 (INTM1)..........................................................................................................160

[I]

Interrupt mask flag register 0 (MK0).....................................................................................................................158

Interrupt mask flag register 1 (MK1).....................................................................................................................158

Interrupt request flag register 0 (IF0)....................................................................................................................157

Interrupt request flag register 1 (IF1)....................................................................................................................157

[K]

[L]

Key return mode register 00 (KRM00) .................................................................................................................161

LCD20 clock selection register (LCDC20)............................................................................................................147

LCD20 mode register (LCDM20)..........................................................................................................................145

[O]

Oscillation stabilization time selection register (OSTS)........................................................................................171

[P]

PCL/BUZ control register 0 (PBS0)......................................................................................................................121

Port 0 (P0)..............................................................................................................................................................71

Port 1 (P1)........................................................................................................................................................72, 73

Port 2 (P2)..............................................................................................................................................................74

Port 3 (P3)..............................................................................................................................................................77

Port 4 (P4)..............................................................................................................................................................78

Port 5 (P5)..............................................................................................................................................................79

220

User's Manual U13679EJ2V0UD

APPENDIX B REGISTER INDEX

Port mode register 0 (PM0) ....................................................................................................................................80

Port mode register 1 (PM1) ....................................................................................................................................80

Port mode register 2 (PM2) ............................................................................................................................80, 122

Port mode register 3 (PM3) ....................................................................................................................................80

Port mode register 4 (PM4) ....................................................................................................................................80

Port mode register 5 (PM5) ....................................................................................................................................80

Processor clock control register (PCC) ..................................................................................................................86

Pull-up resistor option register 0 (PU0) ..................................................................................................................82

[R]

[S]

Reception buffer register 00 (RXB00) ..................................................................................................................126

Subclock control register (CSS) .............................................................................................................................88

Suboscillation mode register (SCKM).....................................................................................................................87

[T]

Timer 40 control register (TMC40) .........................................................................................................................98

Timer clock selection register 2 (TCL2)................................................................................................................116

Transmission shift register 00 (TXS00)................................................................................................................126

[W]

Watch timer mode control register (WTM)............................................................................................................111

Watchdog timer mode register (WDTM)...............................................................................................................117

221

User's Manual U13679EJ2V0UD

APPENDIX C REGISTER INDEX

B.2 Register Symbol Index (Alphabetic Order)

[A]

ASIM00:

ASIS00:

Asynchronous serial interface mode register 00 ..............................................................127, 131, 133

Asynchronous serial interface status register 00......................................................................129, 134

[B]

[C]

BRGC00: Baud rate generator control register 00....................................................................................130, 135

CR00:

CR40:

CSS:

8-bit compare register 00..................................................................................................................104

16-bit compare register 40..................................................................................................................97

Subclock control register ....................................................................................................................88

[I]

IF0:

Interrupt request flag register 0 ........................................................................................................157

Interrupt request flag register 1 ........................................................................................................157

External interrupt mode register 0 ....................................................................................................159

External interrupt mode register 1 ....................................................................................................160

IF1:

INTM0:

INTM1:

[K]

[L]

KRM00:

Key return mode register 00.............................................................................................................161

LCDC20: LCD20 clock selection register.........................................................................................................147

LCDM20: LCD20 mode register .......................................................................................................................145

[M]

MK0:

Interrupt mask flag register 0............................................................................................................158

Interrupt mask flag register 1............................................................................................................158

MK1:

[O]

OSTS:

Oscillation stabilization time selection register.................................................................................171

[P]

P0:

Port 0..................................................................................................................................................71

Port 1............................................................................................................................................72, 73

Port 2..................................................................................................................................................74

Port 3..................................................................................................................................................77

Port 4..................................................................................................................................................78

Port 5..................................................................................................................................................79

PCL/BUZ control register 0...............................................................................................................121

Processor clock control register .........................................................................................................86

Alternate port function switching register..........................................................................................146

Port mode register 0...........................................................................................................................80

Port mode register 1...........................................................................................................................80

Port mode register 2...................................................................................................................80, 122

Port mode register 3...........................................................................................................................80

P1:

P2:

P3:

P4:

P5:

PBS0:

PCC:

PF5:

PM0:

PM1:

PM2:

PM3:

222

User's Manual U13679EJ2V0UD

APPENDIX B REGISTER INDEX

PM4:

PM5:

PU0:

Port mode register 4 ...........................................................................................................................80

Port mode register 5 ...........................................................................................................................80

Pull-up resistor option register 0.........................................................................................................82

[R]

[S]

[T]

RXB00:

SCKM:

Reception buffer register 00 .............................................................................................................126

Suboscillation mode register ..............................................................................................................87

TCL2:

Timer clock selection register 2........................................................................................................116

8-bit timer counter 00........................................................................................................................104

8-bit timer mode control register 00..................................................................................................105

Timer 40 control register.....................................................................................................................98

Transmission shift register 00...........................................................................................................126

TM00:

TMC00:

TMC40:

TXS00:

[W]

WDTM:

WTM:

Watchdog timer mode register..........................................................................................................117

Watch timer mode control register....................................................................................................111

223

User's Manual U13679EJ2V0UD

APPENDIX C REVISION HISTORY

The following shows the revision history. “Chapter” refers to the chapters in the respective edition.

Edition

Description

Addition of table of timer outline

Chapter

CHAPTER 1 GENERAL

CHAPTER 2 PIN FUNCTIONS

2nd edition

Addition of description on V^PPpin processing

Modification of tables for types of pin I/O circuits and

recommended connection of unused pins

Addition of Note to description on suboscillation mode register

CHAPTER 5 CLOCK GENERATOR

CHAPTER 6 16-BIT TIMER 40

(SCKM)

Addition of Caution to description on 16-bit compare register

40 (CR40)

Addition of Caution to description on operation as interval timer

CHAPTER 7 8-BIT TIMER 00

Modification of Caution in watchdog timer mode register

CHAPTER 9 WATCHDOG TIMER

(WDTM)

Overall modification of descriptions on µPD78F9831

CHAPTER 16 µPD78F9831

Addition of electrical specifications

CHAPTER 18 ELECTRICAL

SPECIFICATIONS

Addition of package drawing

CHAPTER 19 PACKAGE DRAWINGS

Addition of recommended soldering conditions

CHAPTER 20 RECOMMENDED

SOLDERING CONDITIONS

Overall modification of descriptions on development tools

APPENDIX A DEVELOPMENT

TOOLS

Addition of revision history

APPENDIX C REVISION HISTORY

Deletion of APPENDIX B EMBEDDED SOFTWARE

−

224

User's Manual U13679EJ2V0UD

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CS 02.3


型号：	UPD789830
厂家：	ETC
描述：	UPD789830 Subseries User＇s Manual \| UM Including Electrical Characteristics[06/2002] UPD789830子系列用户手册\| UM包括电气特性[ 06/2002 ]\n 光电二极管
文件：	总225页 (文件大小：1482K)
中文：	中文翻译
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