UT1760A-GC_技术文档

UTI760A RTS Remote Terminal for Stores

Table I of MIL-STD-883, Method 5004, Class B, also

Standard Military Drawing available

FEATURES

❐ Complete MIL-STD-1760A Notice I through III

❐ Available in 68-pin pingrid array package

remote terminal interface

❐ 1K x 16 of on-chip static RAM for message data,

INTRODUCTION

completely accessible to host

The UT1760A RTS is a monolithic CMOS VLSI solution

totherequirementsofthedual-redundantMIL-STD-1553B

interface as speciﬁed by MIL-STD-1760A. Designed to

reduce cost and space in the mission stores interface, the

RTS integrates the remote terminal logic with a user-

conﬁgured 1K x 16 static RAM. In addition, the RTS has a

ﬂexible subsystem interface to permit use with most

processors or controllers.

❐ Self-test capability, including continuous loop-back

compare

❐ Programmable memory mapping via pointers for

efﬁcient use of internal memory, including buffering

multiple messages per subaddress

❐ RT-RT Terminal Address Compare

❐ Command word stored with incoming data for

enhanced data management

The RTS provides all protocol, data handling, error

checking, and memory control functions, as well as

comprehensive self-test capabilities. The RTS’s memory

meetsallofamissionstore’smessagestorageneedsthrough

user-deﬁned memory mapping. This memory-mapped

architecture allows multiple message buffering at

❐ User selectable RAM Busy (RBUSY) signal for slow

or fast processor interfacing

❐ Full military operating temperature range, -55°C to

+125°C, screened to the speciﬁc test methods listed in

RTA(4:0)

REMOTE TERMINAL

ADDRESS

MCSA(4:0)

CONTROL

INPUTS

MODE CODE/

SUBADDRESS

OUT

STATUS

OUTPUTS

COMMAND

RECOGNITION

CONTROL AND

ERROR LOGIC

DECODER

IN

1K X 16 RAM

ADDR(9:0)

OUT

MUX

PTR REGISTER

ENCODER

IN

12MHz

RESET

CLOCK AND RESET

LOGIC

DATA(15:0)

2MHz

Figure 1. UT1760A RTS Functional Block Diagram

RTS-1

Table of Contents

1.0 ARCHITECTURE AND OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.1 Memory Map and Host Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 RTS RAM Pointer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3 Internal Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.4 Mode Code and Subaddress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.5 MIL-STD-1760A Subaddress and Mode Code Deﬁnitions . . . . . . . . . . . . . . . 9

1.6 Terminal Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.7 Internal Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.8 Power-up and Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.9 Encoder and Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.10 RT-RT Transfer Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.11 Illegal Command Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

2.0 MEMORY MAP EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.0 PIN IDENTIFICATION AND DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.0 MAXIMUM AND RECOMMENDED OPERATING CONDITIONS22

5.0 DC ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

6.0 AC ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

7.0 PACKAGE OUTLINE DRAWING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

RTS-2

to its own internal RAM, it asserts the RBUSY signal to

alert the host. The RBUSY signal is programmable via the

internal Control Register to be asserted either 5.7ms or

2.7ms prior to the RTS needing access to its internal RAM.

1.0 ARCHITECTURE AND OPERATION

The UT1760A RTS is an interface device linking a MIL-

STD-1553serialdatabusandahostmicroprocessorsystem.

The RTS’s MIL-STD-1553B interface includes encoding/

decoding logic, error detection, command recognition, 1K

x 16 of SRAM, pointer registers, clock, and reset circuits.

Illegal subaddress circuitry makes the RTS MIL-STD-

1760A-speciﬁc.

The RTS stores MIL-STD-1760A messages in 1K x 16 of

on-chip RAM. For efﬁcient use of the 1K x 16 memory on

the RTS, the host programs a set of pointers to map where

the 1760A message is stored. The RTS uses the upper 64

words (address 3C0 (hex) through 3FF (hex)) as pointers.

The RTS provides pointers for all 30 receive subaddresses,

all 30 transmit subaddresses, and four mode code

commands with associated data words as deﬁned in

MIL-STD-1553B. The remaining 960 words of memory

contain receive, transmit, and mode code data in a

host-deﬁned structure.

1.1 Memory Map and Host Memory Interface

The host can access the 1K x 16 RAM memory like a

standard RAM device through the 10-bit address and 16-bit

data buses. The host uses the Chip Select (CS), Read/Write

(RD/WR), and Output Enable (OE) signals to control data

transfer to and from memory.When the RTS requires access

RTS Memory Map

000 (hex)

Message

Storage

Locations

3BF(hex)

15 MSB

0 LSB

XMIT VECTOR WORD MODE CODE (W/DATA)

3C0 (hex)

3C1 (hex)

RCV SUBADDRESS 01

Receive

Message

Pointers

(3C1 TO 3DE)

RCV SUBADDRESS 30

SYNCHRONIZE MODE CODE (W/DATA)

3DE (hex)

3DF (hex)

15 MSB

XMIT LAST COMMAND MODE CODE (W/DATA)

XMT SUBADDRESS 01

3E0 (hex)

3E1 (hex)

Transmit

Message

Pointers

(3E1 TO 3FE)

XMT SUBADDRESS 30

3FE (hex)

3FF (hex)

XMT BIT WORD MODE CODE (W/DATA)

15 MSB

Figure 2. RTS Memory Map

RTS-3

MESSAGE INDEX

15 (MSB)

MESSAGE DATA ADDRESS

10

9

0 (LSB)

Message Index:

Message Data Address:

Deﬁnes the maximum

messages buffered for the

given subaddress.

Indicates the starting memory

address for incoming message

storage.

Figure 3. Message Pointer Structure

1.2 RTS RAM Pointer Structure

TheTransmit Last Command Mode Code hasAddressField

boundary conditions for the location of command word

buffers. The host can allocate a maximum 63 sequential

locations following the Address Field starting address. For

proper operation, the Address Field must start on an I x 40

(hex) address boundary, where I is greater than or equal to

zero and less than or equal to 14. A list of valid Index and

Address Fields follows:

The RAM 16-bit pointers have a 6-bit index ﬁeld and a

10-bit address ﬁeld. The 6-bit index ﬁeld allows for the

storage of up to 64 messages per subaddress. A message

consists of the 1553 command word and its associated

data words.

The 16-bit pointer for Transmit Last Command Mode Code

is located at memory location 3E0 (hex). The Transmit Last

Command Mode Code pointer buffers up to 63 command

words. An example of command word storage follows:

I

Valid Index Fields

3F (hex) to 00 (hex)

Valid Address Fields

000 (hex) to 03F(hex)

040 (hex) to 07F (hex)

080 (hex) to 0BF(hex)

0C0 (hex) to 0FF (hex)

100 (hex) to 13F (hex)

140 (hex) to 17F (hex)

180 (hex) to 1BF (hex)

1C0 (hex) to 1FF (hex)

200 (hex) to 23F (hex)

240 (hex) to 27F (hex)

280 (hex) to 2BF (hex)

2C0 (hex) to 2FF (hex)

300 (hex) to 33F (hex)

340 (hex) to 37F (hex)

380 (hex) to 3BF (hex)

0

Example:

1

3E0 (hex) Contents = FC00 (hex)

11 1111 00 0000 0000

2

3

Address Field = 000 (hex)

Index Field = 3F (hex)

4

5

First command word storage location (3E0 = F801):

6

Address Field = 001 (hex)

Index Field = 3E (hex)

7

8

Sixty-third command word storage location

(3E0 = 003F):

9

10

11

12

13

14

Address Field = 03F (hex)

Index Field = 00 (hex)

Sixty-fourth command word storage location (3E0 = 003F)

(previous command word overwritten):

Address Field = 03F (hex)

Index Field = 00 (hex)

RTS-4

Subaddress/Mode Code

RAM Location

Subaddress/Mode Code

RAM Location

Transmit Vector Word Mode Code

3C0 (hex)

3C1 (hex)

3C2 (hex)

3C3 (hex)

3C4 (hex)

3C5 (hex)

3C6 (hex)

3C7 (hex)

3C8 (hex)

3C9 (hex)

3CA (hex)

3CB (hex)

3CC (hex)

3CD (hex)

3CE (hex)

3CF (hex)

3D0 (hex)

3D1 (hex)

3D2 (hex)

3D3 (hex)

3D4 (hex)

3D5 (hex)

3D6 (hex)

3D7 (hex)

3D8 (hex)

3D9 (hex)

3DA (hex)

3DB (hex)

3DC (hex)

3DD (hex)

3DE (hex)

3DF (hex)

Transmit Last Command Mode Code

3E0 (hex)

3E1 (hex)

3E2 (hex)

3E3 (hex)

3E4 (hex)

3E5 (hex)

3E6 (hex)

3E7 (hex)

3E8 (hex)

3E9 (hex)

3EA (hex)

3EB (hex)

3EC (hex)

3ED (hex)

3EE (hex)

3EF (hex)

3F0 (hex)

3F1 (hex)

3F2 (hex)

3F3 (hex)

3F4 (hex)

3F5 (hex)

3F6 (hex)

3F7 (hex)

3F8 (hex)

3F9 (hex)

3FA (hex)

3FB (hex)

3FC (hex)

3FD (hex)

3FE (hex)

3FF (hex)

Receive Subaddress

01

02

03

04

05

06

07

08

09

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

Transmit Subaddress

01

02

03

04

05

06

07

08

09

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

Synchronize w/Data Word Mode Code

Transmit Bit Word Mode Code

1.3 Internal Registers

enables the biphase inputs, recognizes broadcast

commands, selects Notice I and II or III, determines RAM

Busy(RBUSY)timing,selectsdisconnectorterminalactive

ﬂag, and puts the part in self-test mode. The Status Register

supplies operational status of the UT1760A RTS to the host.

These registers must be initialized before attempting RTS

operation. Internal registers can be accessed while RBUSY

is active.

The RTS uses two internal registers to allow the host to

control the RTS operation and monitor its status. The host

usestheControl(CTRL)signalalongwithChipSelect(CS),

Read/Write (RD/WR), and Output Enable (OE) to read the

16-bitStatusRegisterorwritetothe13-bitControlRegister.

No address data is needed to select a register. The Control

Register toggles bits in the MIL-STD-1553B status word,

RTS-5

Control Register (Write Only)

The 13-bit write-only Control Register manages the operation of the RTS. Write to the Control Register by applying a logic

one to OE, and a logic zero to CTRL, CS, and RD/WR. Data is loaded into the Control Register via I/O pins DATA(12:0).

Control register write must occur 50ns before the rising edge of COMSTR to latch data into the outgoing status word.

Bit

Number

Initial

Condition

Description

Bit 0

Bit 1

Bit 2

Bit 3

[1]

[0]

[1]

Channel A Enable. A logic 1 enables Channel A biphase inputs.

Channel B Enable. A logic 1 enables Channel B biphase inputs.

Terminal Flag. A logic 1 sets the Terminal Flag bit of the Status Word.

System Busy. A logic 1 sets the Busy bit of the Status Word and limits RTS access to the

memory. No data word can be retrieved or stored; command words will be stored.

Bit 4

Bit 5

[0]

Subsystem Busy. A logic 1 sets the Subsystem Flag bit of the Status Word.

Self-Test Channel Select. This bit selects which channel the self-test checks; a logic 1 selects

Channel A and a logic 0 selects Channel B.

Bit 6

[0]

Self-Test Enable. A logic 1 places the RTS in the internal self-test mode and inhibits normal

operation. Channels A and B should be disabled if self-test is chosen.

Bit 7

[0]

[1]

Service Request. A logic 1 sets the Service Request bit of the Status Word.

Instrumentation. A logic 1 sets the Instrumentation bit of the Status Word.

Broadcast Enable. A logic 1 enables the RTS to recognize broadcast commands.

Notice Select. A logic 1 enables Notice III operation; logic 0 enables Notice I or II operation.

Bit 8

Bit 9

Bit 10

Bit 11

DSCNCT/TERACT Pin Select. A logic 1 selects the “Disconnect” function; a logic 0 selects

the “Terminal Active” function.

Bit 12

[1]

RBUSY Time Select. A logic 1 selects a 5.7µs RBUSY alert; a logic 0 selects a 2.7µs

RBUSY alert.

[] - Values in parentheses indicate the initialized values of these bits.

CONTROL REGISTER (WRITE ONLY):

X

RBUSY PS NO

BCEN INS SRQ ITST ITCS SUBS BUSY TF CH B CH A

TS

TICE

EN

[1]

[0]

[1]

[0]

[1]

LSB

MSB

[ ] deﬁnes reset state

Figure 4a. Control Register

RTS-6

Status Register (Read Only):

The 16-bit read-only Status Register provides the RTS system status. Read the Status Register by applying a logic 0 to CTRL,

CS, and OE, and a logic 1 to RD/WR. The 16-bit contents of the Status Register are read from data I/O pins DATA(15:0).

Bit

Number

Initial

Condition

Description

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

[0]

MCSA0. The LSB of the mode code or subaddress as indicated by the logic state of bit 5.

MCSA1. Mode code or subaddress as indicated by the logic state of bit 5.

MCSA2. Mode code or subaddress as indicated by the logic state of bit 5.

MCSA3. Mode code or subaddress as indicated by the logic state of bit 5.

MCSA4. Mode code or subaddress as indicated by the logic state of bit 5.

MC/SA. A logic 1 indicates that bits 4 through 0 are the subaddress of the last command word,

and that the last command word was a normal transmit or receive command. A logic 0 indicates

that bits 4 through 0 are a mode code, and that the last command was a mode command.

Bit 6

Bit 7

Bit 8

Bit 9

[1]

Channel A/B. A logic 1 indicates that the most recent command arrived on Channel A; a logic 0

indicates that it arrived on Channel B.

Channel B Enabled. A logic 1 indicates that Channel B is available for both reception and

transmission.

Channel A Enabled. A logic 1 indicates that Channel A is available for both reception and

transmission.

Terminal Flag Enabled. A logic 1 indicates that the Bus Controller has not issued an Inhibit

Terminal Flag Mode Code. A logic 0 indicates that the Bus Controller, via the above mode

code, is overriding the host system’s ability to set the Terminal Flag bit of the status word.

Bit 10

Bit 11

Bit 12

[1]

[0]

Busy. A logic 1 indicates the Busy bit is set. This bit is reset when the System Busy bit in the

Control Register is reset.

Self-Test. A logic 1 indicates that the chip is in the internal self-test mode. This bit is reset

when the self-test is terminated.

TA Parity Error. A logic 1 indicates the wrong Terminal Address parity; it causes the biphase

inputs to be disabled. TA Parity Error results in the Message Error bit being set to a logic one,

and Channels A and B become disabled.

Bit 13

[0]

Message Error. A logic 1 indicates that a message error has occurred since the last Status Reg-

ister read. This bit is not reset until the Status Register has been examined. Message error con-

dition must be removed before reading the Status Register to reset the Message Error bit.

Bit 14

Bit 15

[0]

Valid Message. A logic 1 indicates that a valid message has been received since the last Status

Register read. This bit is not reset until the Status Register has been examined.

Terminal Active. A logic 1 indicates the device is executing a transmit or receive operation.

Same as TERACT output except active high. (Always TERACT; never DSCNCT.)

[] - Values in parentheses indicate the initialized values of these bits.

STATUS REGISTER (READ ONLY):

TERM VAL MESS TAPA

ACTV MESS ERR ERR

BUSY TFEN CH A CH B CHNL MC/ MCSAMCSAMCSA MCSA MCSA

SELF-

TEST

EN

A/B

SA

4

3

2

1

0

[0]

MSB

[0]

[1]

[0]

LSB

[ ] deﬁnes reset state

Figure 4b. Status Register

RTS-7

1.4 Mode Code and Subaddress

The UT1760A RTS provides two modes of illegal

will indicate whether the data on pins MCSA(4:0) is mode

code or subaddress information. Status Register bits 0

through 5 contain the same information as pins MCSA(4:0)

and MC/SA. The system designer can use signals

MCSA(4:0), MC/SA, BRDCST, RTRT, etc. to illegalize

mode codes, subaddresses, and other message formats

(broadcast and RT-to-RT) via the Illegal Command

(ILLCOM) input to the part.

subaddress decoding, one meeting MIL-STD-1760A

Notices I and II, and the other meeting MIL-STD-1760A

Notice III. In addition, the device has automatic internal

illegal command decoding for reserved MIL-STD-1553B

mode codes. These deﬁnitions are extracted from MIL-

STD-1760A and reviewed in section 1.5 of this document.

Upon command word validation and decode, status pins

MCSA(4:0) and MC/SA become valid. Status pin MC/SA

RTS MODE CODE HANDLING PROCEDURE

T/R

ModeCode

Function

Operation

2

0

10100

Selected Transmitter Shutdown

1. Command word stored

2. MERR pin asserted

3. MERR bit set in Status Register

4. Status word transmitted

0

Override Selected Transmitter

1. Command word stored

2. MERR pin asserted

3. MERR bit set in Status Register

4. Status word transmitted

10101

2

Shutdown

0

1

10001

00000

Synchronize (w/Data)

1. Command word stored

2. Data word stored

3. Status word transmitted

2

Dynamic Bus Control

1. Command word stored

2. MERR pin asserted

3. MERR bit set in Status Register

4. Status word transmitted

1

00001

00010

00011

00100

Synchronize

1. Command word stored

2. Status word transmitted

3

Transmit Status Word

1. Command word stored

2. Status word transmitted

1

Initiate Self-Test

1. Command word stored

2. Status word transmitted

Transmitter Shutdown

1. Command word stored

2. Alternate bus shutdown

3. Status word transmitted

1

00101

00110

00111

Override Transmitter Shutdown

Inhibit Terminal Flag Bit

Override Inhibit Terminal Flag

1. Command word stored

2. Alternate bus enabled

3. Status word transmitted

1. Command word stored

2. Terminal Flag bit set to zero and disabled

3. Status word transmitted

1. Command word stored

2. Terminal Flag bit enabled, but not set to logic one

3. Status word transmitted

1

01000

10010

10000

Reset Remote Terminal

1. Command word stored

2. Status word transmitted

Transmit Last Command

1. Status word transmitted

2. Last command word transmitted

3

Word

Transmit Vector Word

1. Command word stored

2. Status word transmitted

3. Data word transmitted

1

10011

Transmit BIT Word

1. Command word stored

2. Status word transmitted

3. Data word transmitted

Notes:

1. Further host interaction required for mode code operation.

2. Reserved mode code; A) MERR pin asserted, B) MESS ERR bit set, C) status word transmitted (ME bit set to logic one).

3. Status word not affected.

4. Undeﬁned mode codes are treated as reserved mode codes.

RTS-8

1.5 MIL-STD-1760A Subaddress and Mode Code Deﬁnitions

Table 1. Subaddress and Mode Code Deﬁnitions Per MIL-STD-1760A Notice I

Message Format

Subaddress Field

Binary (Decimal)

Description

Receive

Transmit

1

00000 (00)

00001 (01)

00010 (02)

00011 (03)

00100 (04)

00101 (05)

00110 (06)

00111 (07)

01000 (08)

01001 (09)

01010 (10)

01011 (11)

01100 (12)

01101 (13)

01110 (14)

01111 (15)

10000 (16)

10001 (17)

10010 (18)

10011 (19)

10100 (20)

10101 (21)

10110 (22)

10111 (23)

11000 (24)

11001 (25)

11010 (26)

11011 (27)

11100 (28)

11101 (29)

11110 (30)

11111 (31)

B.40.1.1.3

Mode Code Indicator

2

Reserved B.40.2.1

User Deﬁned

Reserved

Store Description

User Deﬁned

Reserved

User Deﬁned

Reserved

User Deﬁned

Reserved

User Deﬁned

Reserved

User Deﬁned

Reserved

User Deﬁned

Reserved

User Deﬁned

Reserved

User Deﬁned

Reserved

User Deﬁned

Reserved

User Deﬁned

Reserved

User Deﬁned

Reserved

Nuclear Weapon

User Deﬁned

Reserved

User Deﬁned

Reserved

User Deﬁned

Reserved

Nuclear Weapon

User Deﬁned

B.40.1.1.3

User Deﬁned

B.40.1.1.3

Mode Code Indicator

Notes:

1. Refer to section B.40.1.1.3 of the MIL-STD-1760A speciﬁcation for deﬁnition.

2. Refer to section B.40.2.1 of the MIL-STD-1760A speciﬁcation for deﬁnition.

3. Reserved subaddresses illegalized; Message Error bit and pin set; SW transmitted.

RTS-9

Table 2. Subaddress and Mode Code Deﬁnitions Per MIL-STD-1760A Notice II

Message Format

Subaddress Field

Binary (Decimal)

Description

Receive

1

Transmit

B.40.1.1.3

00000 (00)

00001 (01)

00010 (02)

00011 (03)

00100 (04)

00101 (05)

00110 (06)

00111 (07)

01000 (08)

01001 (09)

01010 (10)

01011 (11)

01100 (12)

01101 (13)

01110 (14)

01111 (15)

10000 (16)

10001 (17)

10010 (18)

10011 (19)

10100 (20)

10101 (21)

10110 (22)

10111 (23)

11000 (24)

11001 (25)

11010 (26)

11011 (27)

11100 (28)

11101 (29)

11110 (30)

11111 (31)

B.40.1.1.3

Mode Code Indicator

2

Reserved B.40.2.1

User Deﬁned

Reserved

Store Description

User Deﬁned

Reserved

User Deﬁned

Reserved

User Deﬁned

Reserved

User Deﬁned

Reserved

User Deﬁned

Reserved

User Deﬁned

Reserved

User Deﬁned

Reserved

User Deﬁned

Reserved

User Deﬁned

Reserved

User Deﬁned

Reserved

User Deﬁned

Reserved

Nuclear Weapon

User Deﬁned

Reserved

User Deﬁned

Reserved

User Deﬁned

Reserved

Nuclear Weapon

User Deﬁned

B.40.1.1.3

User Deﬁned

B.40.1.1.3

Mode Code Indicator

Notes:

1. Refer to section B.40.1.1.3 of the MIL-STD-1760A speciﬁcation for deﬁnition.

2. Refer to section B.40.2.1 of the MIL-STD-1760A speciﬁcation for deﬁnition.

3. Reserved subaddresses illegalized; Message Error bit and pin set; SW transmitted.

RTS-10

Table 3. Subaddress and Mode Code Deﬁnitions Per MIL-STD-1760A Notice III

Subaddress Field Message Format

Binary (Decimal)

Description

Receive

Transmit

1

00000 (00) B.40.1.1.3

B.40.1.1.3

Mode Code Indicator

2

00001 (01)

00010 (02)

00011 (03)

00100 (04)

00101 (05)

00110 (06)

00111 (07)

01000 (08)

01001 (09)

01010 (10)

01011 (11)

01100 (12)

01101 (13)

01110 (14)

01111 (15)

10000 (16)

10001 (17)

10010 (18)

10011 (19)

10100 (20)

10101 (21)

10110 (22)

10111 (23)

11000 (24)

11001 (25)

11010 (26)

11011 (27)

11100 (28)

11101 (29)

11110 (30)

11111 (31)

Reserved B.40.2.1

User Deﬁned

Reserved

Store Description

User Deﬁned

Reserved

Test Only

User Deﬁned

B.40.2.2.1

3

B.40.2.2.1

Mission Store Control/Monitor

Mass Data Transfer

User Deﬁned

B.40.1.5.8

4

B.40.1.1.5.8

User Deﬁned

5

6

B.40.2.2.4

B.40.2.2.5

Nuclear Weapon

User Deﬁned

B.40.2.2.4

User Deﬁned

B.40.2.2.5

Nuclear Weapon

User Deﬁned

B.40.1.1.3

User Deﬁned

B.40.1.1.3

Mode Code Indicator

Notes:

1. Refer to section B.40.1.1.3 of the MIL-STD-1760A speciﬁcation for deﬁnition.

2. Refer to section B.40.2.1 of the MIL-STD-1760A speciﬁcation for deﬁnition.

3. Refer to section B.40.2.2.1 of the MIL-STD-1760A speciﬁcation for deﬁnition.

4. Refer to section B.40.1.1.5.8 of the MIL-STD-1760A speciﬁcation for deﬁnition.

5. Refer to section B.40.2.2.4 of the MIL-STD-1760A speciﬁcation for deﬁnition.

6. Refer to section B.40.2.2.5 of the MIL-STD-1760A speciﬁcation for deﬁnition.

7. Reserved subaddresses illegalized; Message Error bit and pin set; SW transmitted.

RTS-11

1.6 Terminal Address

1.8 Power-up and Master Reset

The Terminal Address of the RTS is programmed via ﬁve

input pins: RTA(4:0) and RTPTY. Asserting MRST latches

the RTS’s TerminalAddress from pins RTA(4:0) and parity

bit RTPTY. The address and parity cannot change until the

next assertion of the MRST. The parity of the Terminal

Address is odd; input pin RTPTY is set to a logic state to

satisfy this requirement. A logic 1 on Status Register

bit 12 indicates incorrect Terminal Address parity. An

example follows:

After power-up, reset initializes the part with its biphase

ports enabled, latches the Terminal Address, selects Notice

III subaddress decoding, and turns on the busy option. The

device is ready to accept commands from the MIL-STD-

1553Bbus.Thebusyﬂagisassertedwhilethehostisloading

the message pointers and messages. After this task is

completed, the host removes the busy condition via a

Control Register write to the RTS. On power-up if the

terminal address parity (odd) is incorrect, the biphase inputs

are disabled and the message error pin (MERR) is asserted.

This condition can also be monitored via bit 12 of the Status

Register. The MERR pin is negated on reception of ﬁrst

valid command.

RTA(4:0) = 05 (hex) = 00101

RTPTY = 1 (hex) = 1

Sum of 1’s = 3 (odd), Status Register bit 12 = 0

RTA(4:0) = 04 (hex) = 00100

RTPTY = 0 (hex) = 0

1.9 Encoder and Decoder

Sum of 1’s = 1 (odd), Status Register bit 12 = 0

The RTS interfaces directly to a bus transmitter/ receiver via

the RTS Manchester II encoder/decoder. The UT1760A

RTS receives the command word from the MIL-STD-

1553B bus and processes it either by the primary or

secondarydecoder. Eachdecoderchecksforthepropersync

pulseandManchesterwaveform,edgeskew,correctnumber

of bits, and parity. If the command is a receive command,

the RTS processes each incoming data word for correct

format and checks the control logic for correct word count

and contiguous data. If an invalid message error is detected,

the message error pin is asserted, the RTS ceases processing

the remainder (if any) of the message, and it then suppresses

status word transmission. Upon command validation

recognition, the external status outputs are enabled.

Reception of illegal commands does not suppress status

word transmission.

RTA(4:0) = 04 (hex) = 00100

RTPTY = 1 (hex) = 1

Sum of 1’s = 2 (even), Status Register bit 12 = 1

The RTS checks the TerminalAddress and parity on Master

Reset. The state of the DSCNCT signal indicates the mated

status of the store. When all six Terminal Address pins

(RTA(4:0), RTPTY) go to a logic one, the DSCNCT pin is

asserted. To enable the disconnect function (DSCNCT pin)

bit 11 of the Control Register is set to a logic one. With

broadcast disabled, RTA (4:0) = 11111 operates as a normal

RT address.

1.7 Internal Self-Test

Setting bit 6 of the Control Register to a logic one enables

the internal self-test. Disable ChannelsA and B at this time

to prevent bus activity during self-test by setting bits 0 and

1 of the Control Register to a logic zero. Normal operation

is inhibited when internal self-test is enabled. The self-test

capability of the RTS is based on the fact that the MIL-STD-

1553B status word sync pulse is identical to the command

word sync pulse. Thus, if the status word from the encoder

is fed back to the decoder, the RTS will recognize the

incoming status word as a command word and thus cause

the RTS to transmit another status word. After the host

invokes self-test, the RTS self-test logic forces a status word

transmission even though the RTS has not received a valid

command. The status word is sent to decoder A or B

depending on the channel the host selected for self-test. The

self-test is controlled by the host periodically changing the

bit patterns in the status word being transmitted. Writing to

the Control Register bits 2, 3, 4, 7, 8, and 10 changes the

status word. Monitor the self-test by sampling either the

Status Register or the external status pins (i.e., Command

Strobe (COMSTR), Transmit/Receive (T/R)). For more

detailed explanation of internal self-test, consult UTMC

publication RTR/RTS Internal Self-Test Routine.

The RTS automatically compares the transmitted word

(encoder word) to the reﬂected decoder word by way of the

continuous loop-back feature. If the encoder word and

reﬂected word do not match, the transmitter error pin

(TXERR) is asserted. In addition to the loop-back compare

test, a timer precludes a transmission greater than 760µs by

the assertion of Fail-safe Timer (TIMERON). This timer is

reset upon receipt of another command. (RT-to-RT transfer

time-out = 57µs).

1.10 RT-RT Transfer Compare

The RT-to-RT TerminalAddress compare logic makes sure

that the incoming status word’s Terminal Address matches

the TerminalAddress of the transmitting RT speciﬁed in the

command word. An incorrect match results in setting the

message error bit and suppressing transmission of the

status word.

RTS-12

1.11 Illegal Command Decoding

2.0 MEMORY MAP EXAMPLE

The host has the option of asserting the ILLCOM pin to

illegalize a received command word. On receipt of an illegal

command, the RTS sets the Message Error bit in the status

word, sets the message error output, and sets the message

error latch in the Status Register.

Figures 5 and 6 illustrate the UT1760A RTS buffering three

receive command messages to Subaddress 4. The receive

message pointer for Subaddress 4 is located at 03C4 (hex)

in the 1K x 16 RAM. The 16-bit contents of location 03C4

(hex) point to the memory location where the ﬁrst receive

message is stored. The Address Field deﬁned as bits 0

through 9 of address 03C4 (hex) contain address

information. The Index Field deﬁned as bits 10 through 15

ofaddress03C4(hex)containthemessagebufferindex(i.e.,

number of messages buffered).

The following RTS outputs may be used to externally

decode an illegal command, Mode Code or Subaddress

indicator (MC/SA), Mode Code or Subaddress bus

MCSA(4:0), Command Strobe (COMSTR), Broadcast

(BRDCST), and Remote Terminal to Remote Terminal

transfer (RTRT) (see ﬁgure 21 on page 34.)

Figure 5 demonstrates the updating of the message pointer

aseachmessageisreceivedandstored.Thememorystorage

of these three messages is shown in ﬁgure 6.After receiving

the third message for Subaddress 4 (i.e., Index Field equals

zero) the Address Field of the message pointer is not

incremented. If the host does not update the receive

message pointer for Subaddress 4 before the next receive

command for Subaddress 4 is accepted, the third message

will be overwritten.

To illegalize a transmit command, the ILLCOM pin must

be asserted within 3.3µs after VALMSG goes to a logic 1 if

theRTSistorespondwiththeMessageErrorbitofthestatus

word at a logic 1. If the illegal command is mode code 2, 4,

5,6,7,or18,theILLCOMpinmustbeassertedwithin664ns

after Command Strobe (COMSTR) transitions to logic 0.

Asserting the ILLCOM pin within the 664ns inhibits the

modecodefunction. Formodecodeillegalization, assertthe

ILLCOM pin until the VALMSG signal is asserted.

Figures 7 and 8 show an example of multiple message

retrieval from Subaddress 16 upon reception of a MIL-STD-

1553Btransmitcommand.Themessagepointerfortransmit

Subaddress 16 is located at 03F0 (hex) in the 1K x 16 RAM.

The 16-bit contents of location 03F0 (hex) point to the

memory location where the ﬁrst message data words

are stored.

For an illegal receive command, the ILLCOM pin must be

asserted within 18.2µs after the COMSTR transitions to a

logic 0 in order to suppress data words from being stored.

Inaddition, theILLCOMpinmustbeatalogic1throughout

the reception of the message until VALMSG is asserted.

This does not apply to illegal transmit commands since the

status word is transmitted ﬁrst.

Figure 7 demonstrates the updating of the message pointer

as each message is received and stored. The data memory

for these three messages is shown in ﬁgure 8.

The above timing conditions also apply when the host

externally decodes an illegal broadcast command. The host

must remove the illegal command condition so that the next

command is not falsely decoded as illegal.

RTS-13

Example:

Remote terminal will receive and buffer three MIL-STD-1553 receive commands

of various word lengths to Subaddress 4.

MIL-STD-1553 Bus Activity:

CMD WORD #1 DW0 DW1 DW2 DW3

SA = 4

T/R = 0

WC = 4

CMD WORD #2 DW0 DW1

SA = 4

T/R = 0

WC = 2

CMD WORD #3 DW0 DW1 DW2 DW3

SA = 4

T/R = 0

WC = 4

Receive Subaddress 4;

data pointer at 03C4

(hex). (Initial condition)

INDEX = 0000 10

ADDRESS = 00 0100 0000

03C4 (hex)

0840 (hex)

After message #1,

4 data words plus

command word.

INDEX = 0000 01

ADDRESS = 00 0100 0101

0445 (hex)

0048 (hex)

After message #2,

2 data words plus

command word.

INDEX = 0000 00

ADDRESS = 00 0100 1000

After message #3,

4 data words plus

command word.

INDEX = 0000 00

ADDRESS = 00 0100 1000

Figure 5. RTS Message Handling

03C4 (hex)

0840 (hex)

COMMAND WORD #1

DATA WORD 0

040 (hex)

041 (hex)

042 (hex)

043 (hex)

044 (hex)

045 (hex)

046 (hex)

047 (hex)

048 (hex)

049 (hex)

04A (hex)

04B (hex)

04C (hex)

DATA WORD 1

DATA WORD 2

DATA WORD 3

0445 (hex)

0048 (hex)

03C4 (hex)

COMMAND WORD #2

DATA WORD 0

DATA WORD 1

COMMAND WORD #3

DATA WORD 0

DATA WORD 1

DATA WORD 2

0048 (hex)

DATA WORD 3

03C4 (hex)

Figure 6. Memory Storage Subaddress 4

RTS-14

Example:

Remote terminal will transmit and buffer three MIL-STD-1553 transmit commands

of various word lengths to Subaddress 16.

MIL-STD-1553 Bus Activity:

CMD WORD #1

DW3

SW DW0

DW1 DW2

SA = 16

T/R = 1

WC = 4

CMD WORD #2

DW1

SW SW0

SA = 16

T/R = 1

WC = 2

CMD WORD #3

SW DW0 DW1 DW2 DW3

SA = 16

T/R = 1

WC = 4

Transmit Subaddress 16;

data pointer at 03F0

03F0 (hex)

0830 (hex)

INDEX = 0000 10

ADDRESS = 00 0011 0000

(hex). (Initial condition)

After message #1,

4 data words.

0434 (hex)

0036 (hex)

INDEX = 0000 01

ADDRESS = 00 0011 0100

03F0 (hex)

After message #2,

2 data words.

INDEX = 0000 00

ADDRESS = 00 0011 0110

0036 (hex)

After message #3,

4 data words.

INDEX = 0000 00

ADDRESS = 00 0011 0110

Figure 7. RTS Message Handling

03F0(hex)

DATA WORD 0

DATA WORD 1

DATA WORD 2

DATA WORD 3

DATA WORD 0

DATA WORD 1

DATA WORD 0

DATA WORD 1

DATA WORD 2

DATA WORD 3

0830 (hex)

030 (hex)

031 (hex)

032 (hex)

033 (hex)

034 (hex)

035 (hex)

036 (hex)

037 (hex)

038 (hex)

039 (hex)

0434 (hex)

0036 (hex)

03F0 (hex)

030436(h(hexe)x)

03F0 (hex)

Note:

Example is valid only if message structure is known in advance.

Figure 8. Memory Storage Subaddress 16

RTS-15

3.0 PIN IDENTIFICATION AND DESCRIPTION

BIPHASE OUT

TAZ

TAO

ADDR0

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDRESS

BUS

A10

B10

J2

H1

H2

G1

G2

F1

E2

D1

D2

C1

ADDR(9:0)

TBZ

TBO

A9

B9

BIPHASE IN

RAZ

RAO

L7

K8

L6

RBZ

RBO

K7

TERMINAL

ADDRESS

RTA0

RTA1

RTA2

RTA3

RTA4

RTPTY

L5

K5

L4

K4

L3

K6

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9

DATA10

DATA11

DATA12

DATA13

DATA14

DATA15

DATA BUS

DATA(15:0)

L10

K10

K11

J10

J11

H10

H11

G10

F11

E10

E11

D10

D11

C10

MODE/CODE

SUBADDRESS

MCSA0

MCSA1

MCSA2

MCSA3

MCSA4

B2

A2

A3

B3

A4

UT1760A

RTS

STATUS

SIGNALS

MERR

A5

A6

B5

B6

B8

B1

A7

B4

B7

L8

C2

DSCNCT/TERACT

TXERR

TIMERON

COMSTR

MC/SA

C11

B11

BRDCST

T/R

V

F10

E1

DD

POWER

V

DD

RTRT

F2

V

GROUND

SS

VALMSG

RBUSY

G11

L2

A8

12MHZ

2MHZ

CLOCK

RESET

CONTROL

SIGNALS

CS

RD/WR

CTRL

K2

K1

J1

L9

K9

K3

MRST

OE

ILLCOM

Figure 9. UT1760A RTS Pin Description

RTS-16

Legend for TYPE and ACTIVE Fields:

TTO = Three-state TTL output

TTB = Three-state TTL bidirectional

AL = Active low

AH = Active high

[] - Value in parentheses indicates initial state of

these pins.

TI = TTL input

TUI = TTL input (pull-up)

TDI = TTL input (pull-down)

TO = TTL output

DATA BUS

NAME

PIN NUMBER

(PGA)

TYPE

ACTIVE

DESCRIPTION

DATA15

B11

C11

C10

D11

D10

E11

E10

F11

G10

H11

H10

J11

TTB

--

Bit 15 (MSB) of the bidirectional Data bus.

Bit 14 of the bidirectional Data bus.

Bit 13 of the bidirectional Data bus.

Bit 12 of the bidirectional Data bus.

Bit 11 of the bidirectional Data bus.

Bit 10 of the bidirectional Data bus.

Bit 9 of the bidirectional Data bus.

Bit 8 of the bidirectional Data bus.

Bit 7 of the bidirectional Data bus.

Bit 6 of the bidirectional Data bus.

Bit 5 of the bidirectional Data bus.

Bit 4 of the bidirectional Data bus.

Bit 3 of the bidirectional Data bus.

Bit 2 of the bidirectional Data bus.

Bit 1 of the bidirectional Data bus.

Bit 0 (LSB) of the bidirectional Data bus.

DATA14

DATA13

DATA12

DATA11

DATA10

DATA9

DATA8

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

J10

K11

K10

L10

ADDRESS BUS

NAME

PIN NUMBER

(PGA)

TYPE

ACTIVE

DESCRIPTION

ADDR9

ADDR8

ADDR7

ADDR6

ADDR5

ADDR4

ADDR3

ADDR2

ADDR1

ADDR0

C1

D2

D1

E2

F1

G2

G1

H2

H1

J2

TI

--

Bit 9 (MSB) of the Address bus.

Bit 8 of the Address bus.

Bit 7 of the Address bus.

Bit 6 of the Address bus.

Bit 5 of the Address bus.

Bit 4 of the Address bus.

Bit 3 of the Address bus.

Bit 2 of the Address bus.

Bit 1 of the Address bus.

Bit 0 (LSB) of the Address bus.

RTS-17

CONTROL INPUTS

NAME

PIN NUMBER

(PGA)

TYPE

ACTIVE

DESCRIPTION

CS

K2

TI

AL

Chip Select. The host processor uses the CS signal for

RTS Status Register reads, Control Register writes, or

host access to the RTS internal RAM.

RD/WR

K1

TI

--

Read/Write. The host processor uses a high level on this

input in conjunction with CS to read the RTS Status

Register or the RTS internal RAM. A low level on this

input is used in conjunction with CS to write to the RTS

Control Register or the RTS internal RAM.

CTRL

OE

J1

L9

K9

TI

AL

AH

Control. The host processor uses the active low CTRL

input signal in conjunction with CS and

RD/WR to access the RTS registers. A high level on this

input means access is to RTS internal RAM only.

Output Enable. The active low OE signal is used to

control the direction of data ﬂow from the RTS.

For OE = 1, the RTS Data bus is three-state; for

OE = 0, the RTS Data bus is active.

ILLCOM

TDI

Illegal Command. The host processor uses the

ILLCOM input to inform the RTS that the present

command is illegal.

RTS-18

STATUS OUTPUTS

NAME

PIN NUMBER

(PGA)

TYPE

ACTIVE

DESCRIPTION

MERR

[0]

A5

B5

B6

TO

AH

Message Error. The active high MERR output signals that

the Message Error bit in the Status Register has been set

due to receipt of an illegal command, or an error during

message sequence. MERR will reset to logic zero on the

receipt of the next valid command.

TXERR

[0]

TO

AH

AL

Transmission Error. The active high TXERR output is

asserted when the RTS detects an error in the reﬂected

word versus the transmitted word, using the continuous

loop-back compare feature. Reset on next COMSTR

assertion.

TIMERON

[1]

Fail-safe Timer. The TIMERON output pulses low for

760µs when the RTS begins transmitting (i.e., rising edge

of VALMSG) to provide a fail-safe timer meeting the

requirements of MIL-STD-1553B. This pulse is reset

when COMSTR goes low or during a Master Reset.

COMSTR

[1]

B8

A7

B7

TO

AL

AH

Command Strobe. COMSTR is an active low output of

500ns duration identifying receipt of a valid command.

BRDCST

[1]

Broadcast. BRDCST is an active low output that identiﬁes

receipt of a valid broadcast command.

RTRT

[0]

Remote Terminal to Remote Terminal. RTRT is an active

high output indicating that the RTS is processing a remote

terminal to remote terminal command.

DSCNCT or

TERACT

[X]

A6

TO

--

Disconnect or Terminal Active. Bit 11 of the Control

Register selects the mode of this dual-function pin. In the

“Disconnect” mode (bit 11 = 1), the active high DSCNCT

output is asserted when all six Terminal Address pins

(RTA0 - RTA4, RTPTY) go high, indicating a disconnect

condition. In the “Terminal Active” mode (bit 11 = 0), the

active low TERACT output is asserted at the beginning of

the RTS access to internal RAM for a given command and

negated after the last access for that command.

VALMSG

[0]

L8

C2

TO

AH

Valid Message. VALMSG is an active high output

indicating a valid message (including Broadcast) has

been received. VALMSG goes high prior to transmitting

the 1553 status word and is reset upon receipt of the

next command.

RBUSY

[0]

RTS Busy. RBUSY is asserted high while the RTS is

accessing its own internal RAM either to read or update

the pointers or to store or retrieve data words. RBUSY

becomes active either 2.7µs or 5.7µs before RTS requires

RAM access. This timing is controlled by Control Register

bit 12 (see section 1.3).

T/R

[0]

B4

TO

--

Transmit/Receive. A high level on this pin indicates a

transmit command message transfer is being or was

processed, while a low level indicates a receive command

message transfer is being or was processed.

RTS-19

MODE CODE/SUBADDRESS OUTPUTS

NAME

PIN NUMBER

(PGA)

TYPE

ACTIVE

DESCRIPTION

MC/SA

[0]

B1

TO

--

Mode Code/Subaddress Indicator. If MC/SA is low, it indi-

cates that the most recent command word is a mode code

command. If MC/SA is high, it indicates that the most

recent command word is for a subaddress. This output

indicates whether the mode code/subaddress ouputs (i.e.,

MCSA(4:0)) contain mode code or subaddress information.

MCSA0

[0]

B2

TO

--

Mode Code/Subaddress Output 0. If MC/SA is low, this pin

represents the least signiﬁcant bit of the most recent

command word (the LSB of the mode code). If MC/SA is

high, this pin represents the LSB of the subaddress.

MCSA1

[0]

A2

A3

B3

A4

TO

--

Mode Code/Subaddress Output 1.

Mode Code/Subaddress Output 2.

Mode Code/Subaddress Output 3.

MCSA2

[0]

MCSA3

[0]

MCSA4

[0]

Mode Code/Subaddress Output 4. If MC/SA is low, this pin

represents the most signiﬁcant bit of the mode code. If MC/

SA is high, this pin represents the MSB of the subaddress.

REMOTE TERMINAL ADDRESS INPUTS

NAME

PIN NUMBER

(PGA)

TYPE

ACTIVE

DESCRIPTION

RTA4

L3

K4

L4

K5

L5

K6

TUI

--

Remote Terminal Address bit 4 (MSB).

Remote Terminal Address bit 3.

Remote Terminal Address bit 2.

Remote Terminal Address bit 1.

Remote Terminal Address bit 0 (LSB).

RTA3

RTA2

RTA1

RTA0

RTPTY

Remote Terminal Address Parity. This input must provide

odd parity for the Remote Terminal Address.

RTS-20

1

BIPHASE INPUTS

NAME

PIN NUMBER

TYPE

TI

ACTIVE

DESCRIPTION

(PGA)

RAZ

RAO

RBZ

RBO

L7

--

Receiver - Channel A, Zero Input. Idle low Manchester

input form the 1553 bus receiver.

K8

L6

K7

TI

Receiver - Channel A, One Input. This input is the

complement of RAZ.

TI

Receiver - Channel B, Zero Input. Idle low Manchester

input from the 1553 bus receiver.

TI

Receiver - Channel B, One Input. This input is the

complement of RBZ.

Note:

1. For uniphase operation, tie RAZ (or RBZ) toV_DDand apply true uniphase input signal to RAO (or RBO).

BIPHASE OUTPUTS

NAME

PIN NUMBER

(PGA)

TYPE

ACTIVE

DESCRIPTION

TAZ

[0]

A10

TO

--

Transmitter - Channel A, Zero Output. This Manchester

encoded data output is connected to the 1553 bus

transmitter input. The output is idle low.

TAO

[0]

B10

A9

TO

--

Transmitter - Channel A, One Output. This output is the

complement of TAZ. The output is idle low.

TBZ

[0]

Transmitter - Channel B, Zero Output. This Manchester

encoded data output is connected to the 1553 bus

transmitter input. The output is idle low.

TBO

[0]

B9

TO

--

Transmitter - Channel B, One Output. This output is the

complement of TBZ. The output is idle low.

MASTER RESET AND CLOCK

NAME

MRST

PIN NUMBER

(PGA)

TYPE

ACTIVE

DESCRIPTION

K3

L2

A8

TUI

AL

Master Reset. Initializes all internal functions of the RTS.

MRST must be asserted 500ns before normal RTS

operation (500ns minimum). Does not reset RAM.

12MHz

2MHz

TI

--

12 MHz Input Clock. This is the RTS system clock that

requires an accuracy greater than 0.01% with a duty cycle

of 50% ± 10%.

TO

2MHz Clock Output. This is a 2MHz clock output

generated by the 12MHz input clock. This clock is

stopped when MRST is low.

RTS-21

POWER AND GROUND

NAME

PIN NUMBER

TYPE

ACTIVE

DESCRIPTION

(PGA)

V

F10

E1

PWR

--

+5 V Power. Power supply must be +5 V

DC

DD

DC

± 10%.

F2

G11

GND

--

Reference ground. Zero V logic ground.

SS

DC

4.0 OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS*

(referenced to V_SS

)

SYMBOL

PARAMETER

LIMITS

UNIT

V

DC supply voltage

-0.3 to +7.0

DD

IO

Voltage on any pin

-0.3 to V +0.3

V

DD

I

DC input current

±10

mA

°C

I

T

Storage temperature

Maximum power dissipation

-65 to +150

300

STG

1

P

mW

°C

D

T

Maximum junction temperature

+175

20

J

Θ

Thermal resistance, junction-to-case

°C/W

JC

Note:

1. Does not reﬂect the added P_Ddue to an output short-circuited.

*

Stressesoutsidethelistedabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thisisastressratingonly,

and functional operation of the device at these or any other conditions beyond limits indicated in the operational

sections of this speciﬁcation is not recommended. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

LIMITS

4.5 to 5.5

0 to V

UNIT

V

DC supply voltage

DC input voltage

Temperature range

Operating frequency

DD

V

IN

C

DD

T

-55 to +125

°C

F

12 ±.01%

MHz

O

RTS-22

5.0 DC ELECTRICAL CHARACTERISTICS

= 5.0V ± 10%; -55°C < T <+125°C)

V

DD

C

SYMBOL

PARAMETER

Low-level input voltage

High-level input voltage

CONDITION

MINIMUM MAXIMUM

UNIT

V

0.8

IL

2.0

V

IH

I

Input leakage current

TTL inputs

Inputs with pull-down resistors

Inputs with pull-up resistors

IN

V

= V or V

-1

110

-2000

1

2000

-110

µA

IN

DD

SS

= V

DD

SS

V

Low-level output voltage

High-level output voltage

I

= 3.2µA

0.4

V

OL

OH

= -400µA

2.4

-10

V

OH

I

Three-state output

leakage current

V

= V or V

SS

+10

µA

OZ

O

DD

1, 2

I

Short-circuit output current

V

= 5.5V, V = V

DD

90

mA

OS

DD

O

-90

= 5.5V, V = 0V

O

3

C

Input capacitance

ƒ = 1MHz @ 0V

ƒ = 12MHz, CL = 50pF

Note 5

10

15

20

50

1.5

pF

IN

3

Output capacitance

pF

OUT

IO

3

Bidirect I/O capacitance

pF

1, 4

I

Average operating current

mA

DD

QI

Quiescent current

DD

Notes:

1. Supplied as a design limit but not guaranteed or tested.

2. Not more than one output may be shorted at a time for a maximum duration of one second.

3. Measured only for initial qualiﬁcation, and after process or design changes that could affect input/output capacitance.

4. Includes current through input pull-ups. Instantaneous surge currents on the order of 1 ampere can occur during output switching.

Voltage supply should be adequately sized and decoupled to handle a large surge current.

5. All inputs with internal pull-ups or pull-downs should be left open circuit. All other inputs tied high or low.

BIT TIMES

1 2 3

4 5 6 7 8

5

9

10 11 12 13 14

5

15 16 17 18 19

5

20

1

COMMAND

WORD

P

T/R

DATA WORD COUNT/

MODE CODE

SYNC REMOTE TERMINAL

ADDRESS

SUBADDRESS/MODE

CODE

1

P

1

16

DATA WORD

DATA

SYNC

1

5

1

STATUS WORD

REMOTE TERMINAL

SYNC

RESERVED

ADDRESS

Figure 10. MIL-STD-1553B Word Formats

RTS-23

6.0 AC ELECTRICAL CHARACTERISTICS

(Over recommended operating conditions)

V

MIN

MAX

V

MIN

MAX

IH

IL

IH

IL

1

t

1

INPUT

t

b

a

c

V

MIN

MAX

IN-PHASE

OUTPUT

OH

2

V

OL

t

d

V

MIN

MAX

OH

OUT-OF-PHASE

OUTPUT

2

t

V

OL

t

e

V

MIN

MAX

OH

BUS

V

OL

t

f

t

g

t

h

SYMBOL

PARAMETER

↑

↓

↑

t

INPUT to response

a

b

c

↓

↑

↓

to response

INPUT

d

e

f

INPUT to data valid

↓

INPUT to high Z

↑

to high Z

INPUT

g

h

↑

INPUT to data valid

Notes:

1. Timing measurements made at (V_IHMIN + V_ILMAX)/2.

2. Timing measurements made at (V_OLMAX + V_OHMIN)/2.

3. Based on 50pf load.

4. Unless otherwise noted, allAC electrical characteristics are guaranteed by design or characterization.

Figure 11a. Typical Timing Measurements

5V

I

(source)

V

REF

3V

90%

REF

D

10%

50pF

0V

< 2ns

I

(sink)

REF

Input Pulses

Note:

50pF including scope probe and test socket

Figure 11b. AC Test Loads and Input Waveforms

RTS-24

12MHz

CS

t

12i

t

12j

t

12a

t

12f

CTRL

t

12b

RD/WR

ADDR(9:0)

12k

t

12c

12g

t

12d

t

12l

DATA(15:0)

OE

DATA VALID

t

1h

t

12e

t

12m

Figure 12. Microprocessor RAM Read

SYMBOL

PARAMETER

MIN

MAX

UNITS

1

10

--

ns

t

CTRL↑ set up wrt CS↓

12a

12b

12c

12d

12e

12f

RD/WR ↑ set up wrt CS↓

--

ADDR(9:0) Valid to CS↓ (Address Set up)

CS↓ to DATA(15:0) Valid

155

65

--

OE↓ to DATA(15:0) Don’t Care (Active)

CS↑ to CTRL Don’t Care

0

--

CS↑ to ADDR(9:0) Don’t Care

OE↑ to DATA(15:0) High Impedance

12g

12h

12i

--

40

5500

--

2

220

85

0

CS↓ to CS↑

CS↑ to CS↓

12j

--

CS↑ to RD/WR Don’t Care

12k

12l

3

25

65

--

CS↑ to DATA(15:0) Invalid

--

OE↓ to OE↑

12m

Notes:

1. “wrt” deﬁned as “with respect to.”

2. The maximum amount of time that CS can be held low is 5500ns if the user has selected the 5.7µs RBUSY option. For the 2.7µs

RBUSY option, the maximum CS low time is 2500ns.

3. Assumes OE is asserted.

RTS-25

12MHz

CS

t

13i

t

13j

t

13a

13b

13c

t

13k

CTRL

t

RD/WR

ADDR(9:0)

DATA(15:0)

OE

t

13f

t

13g

t

13d

VALID DATA

13h

t

13e

Figure 13. Microprocessor RAM Write

SYMBOL

PARAMETER

MIN

MAX

UNITS

10

0

--

ns

t

CTRL↑ set up wrt CS↓

13a

13b

13c

13d

13e

13f

RD/WR ↑ set up wrt CS↓

--

ADDR(9:0) Valid to CS↓ (Address set up)

CS↓ to DATA(15:0) Valid CS↓(DATA set up)

OE↓ to DATA(15:0) High Impedance

CS↑ to RD/WR Don’t Care

--

40

0

--

0

--

CS↑ to ADDR(9:0) Don’t Care

13g

13h

13i

20

180

85

0

--

CS↑ to DATA(15:0) Don’t Care (Hold-time)

1

5500

--

CS↓ to CS↑

CS↑ to CS↓

13j

--

CS↑ to CTRL Don’t Care

13k

Note:

1. The maximum amount of time that CS can be held low is 5500ns if the user has selected the 5.7µs RBUSY option. For the 2.7µs

RBUSY option, the maximum CS low time is 2500ns.

RTS-26

12MHz

CS

t

14c

t

14a

14b

t

14e

CTRL

RD/WR

t

14f

t

14h

DATA(15:0)

VALID DATA

t

14d

OE

t

14g

Figure 14. Control Register Write

SYMBOL

PARAMETER

MIN

MAX

UNITS

0

--

ns

t

CTRL↓ set up wrt CS↓

RD/WR ↓ set up wrt CS↓

14a

14b

14c

14d

14e

14f

1

50

0

5500

--

CS↓ to CS↑

CS↑ to DATA(15:0) Don’t Care (Hold-time)

CS↑ to CTRL Don’t Care

0

--

0

--

CS↑ to RD/WR Don’t Care

40

0

--

OE↑ to Data(15:0) High Impedance

DATA (15:0) Valid to CS↓ (DATA set up)

14g

14h

--

Note:

1. The maximum amount of time that CS can be held low is 5500ns if the user has selected the 5.7µs RBUSY option. For the 2.7µs

RBUSY option, the maximum CS low time is 2500ns.

RTS-27

12MHz

CS

t

15b

t

15a

15c

t

15e

CTRL

RD/WR

t

15f

t

15d

t

15j

VALID DATA

DATA(15:0)

t

15h

t

15g

t

15i

OE

Figure 15. Status Register Read

SYMBOL

PARAMETER

MIN

MAX

UNITS

0

65

0

--

5500

--

ns

t

CTRL↓ set up wrt CS↓

15a

15b

15c

15d

15e

15f

1

CS↓ to CS↑

RD/WR↑ set up wrt CS↓

--

65

--

CS↓ to DATA(15:0) Valid

5

CS↑ to CTRL Don’t Care

5

--

CS↑ to RD/WR Don’t Care

OE↓ to DATA(15:0) Don’t Care (Active)

OE↑ to DATA(15:0) High Impedance

OE↓ to OE↑

--

65

40

--

15g

15h

15i

--

65

25

--

CS↓ to DATA(15:0) Don’t Care (Active)

15j

Note:

1. The maximum amount of time thatCS can be held low is 5500ns if the user has selected the 5.7µs RBUSY option. For the 2.7µs RBUSY

option, the maximum CS low time is 2500ns.

RTS-28

VALMSG

TIMERON

t

16a

t

16c

A/B

BIPHASE

OUTPUT ZERO

t

16b

COMSTR

ILLCOM

t

16d

t

16g

t

16f

16e

Figure 16. RT Fail-Safe Timer Signal Relationships

SYMBOL

PARAMETER

MIN

MAX

UNITS

0

1.2

727.3

--

35

--

ns

µs

ns

µs

ns

µs

ns

t

VALMSG↑ before TIMERON↓

TIMERON↓ before ﬁrst BIPHASE OUT O↑

TIMERON low pulse width (time-out)

COMSTR↓ to TIMERON↑

16a

16b

16c

16d

16e

16f

727.4

25

--

3.3

664

18.2

--

VALMSG↑ to ILLCOM↑

1

--

COMSTR↓ to ILLCOM↑

2

--

COMSTR↓ to ILLCOM↑

16f

3

500

ILLCOM↑ to ILLCOM↓

16g

Notes:

1. Mode code 2, 4, 5, 6, 7, or 18 received.

2. To suppress data word storage.

3. For transmit command illegalization.

RTS-29

12MHz

CS COMMAND WORD

P

1

BIPHASE IN

t

17a

MC/SA

and MCSA(4:0)

t

17b

17c

t

17l

COMSTR

t

17d

17e

BRDCST

T/R

t

17f

17g

t

17h

17i

VALMSG

t

17j

t

17k

MERR

Note:

1. Measured from the mid-bit parity crossing.

Figure 17. Status Output Timing

SYMBOL

PARAMETER

MIN

MAX

UNITS

4

0

2.1

0

14

2.8

17

ns

µs

ns

µs

ns

µs

ns

µs

ns

µs

ns

t

12Mhz↑ to MC/SA Valid

Command Word to MC/SA Valid

12MHz↑ to COMSTR↓

17a

17b

3

4

17c

17d

17e

17f

17g

17h

17i

3

3.2

0

3.7

32

Command Word to COMSTR↓

4

12MHz↑ to BRDCST↓

3

2.6

0

3.2

57

Command Word to BRDCST↓

12MHz↑ to T/R Valid

3

2.2

0

2.7

32

Command Word toT/R Valid

12MHz↑ to VALMSG↑

1,2,3

6.2

0

6.7

37

Command Word toVALMSG↑

12MHz↑ to MERR↑

17j

17k

17l

485

500

COMSTR↓ TO COMSTR↑

Notes:

1. Receive last data word to Valid Message active (VALMSG↑).

2. Transmit command word to Valid Message active (VALMSG↑).

3. Command word measured from mid-bit crossing.

4. Guaranteed by test.

RTS-30

12MHz

CS COMMAND WORD

P

t

18a

BIPHASE IN

t

18i

RBUSY

t

18h

t

18b

18c

TERACT

t

18d

t

18e

RTRT

18f

t

18g

MRST

Note:

1. Measured from mid-bit parity crossing.

Figure 18. Status Output Timing

PARAMETER MIN

SYMBOL

MAX

UNITS

--

3.2

0

37

3.8

37

3.7

32

22

--

ns

µs

ns

µs

ns

µs

ns

µs

ns

t

12MHz↑ to RBUSY↑

18a

18b

3

Command Word toRBUSY↑

12MHz↑ to TERACT↓

2

18c

18d

18e

18f

1,3

3.1

0

Command Word to TERACT↓

12MHz↑ to RTRT↑

2

3

21.0

500

--

Command Word to RTRT↑

MRST↓ to MRST↑

18g

5.5

8.5

--

RBUSY↑ to RBUSY↓ (2.7µs)

(5.7µs)

t

18h

18i

--

3.10

240

RBUSY↓ to RBUSY↑ (2.7µs)

(5.7µs)

--

Notes:

1. TERACT enabled via Control Register.

2. Guaranteed by test.

3. Command word measured from mid-bit crossing

RTS-31

BIPHASE IN

DS DATA WORD

P

DS DATA WORD

CS COMMAND WORD

COMSTR

T/R

RBUSY

1

2

3

TERACT

SS STATUS WORD

P

BIPHASE OUT

VALMSG

Notes:

1. Burst of 5 DMAs: read command pointer, store command word, update command pointer, read data word pointer, store

command word.

2. Burst of 1 DMA: store data word.

3. Burst of 2 DMAs: store data word, update data word pointer.

4. Approximately 560ns per DMA access.

Figure 19a. Receive Command with Two Data Words

CS COMMAND WORD

P

BIPHASE IN

COMSTR

T/R

RBUSY

1

2

3

TERACT

BIPHASE OUT

SS STATUS WORD

P

DS DATA WORD

P

DS DATA WORD

P

VALMSG

CS = Command sync

SS = Status sync

DS = Data sync

P = Parity

Notes:

1. Burst of 4 DMAs: read command pointer, store command word, update command pointer, read data word pointer.

2. Burst of 1 DMA: read data word.

3. Burst of 2 DMAs: read data word, update data word pointer.

4. Approximately 560ns per DMA access.

Figure 19b. Transmit Command with Two Data Words

RTS-32

ADDR(9:0)

DATA(15:0)

CONTROL

HOST

SUBSYSTEM

UT1760A

RTS

UT63M125

1553 TRANSCEIVER

1553 BUS A

1553 BUS B

Figure 20a. RTS General System Diagram (Idle low interface)

RAO

RXOUT

RAZ

CHANNEL A

TXINHB

CHANNEL A

TXIN

TAO

TAZ

UTMC

63M125

RTS

RBO

RBZ

RXOUT

CHANNEL B

TXINHB

CHANNEL B

TBO

TBZ

TXIN

TIMERON

Figure 20b. RTS Transceiver Interface Diagram

RTS-33

MC/SA

MCSA0

MCSA1

ILLEGAL

COMMAND

DECODER

MCSA2

MCSA3

MCSA4

RTS

COMSTR

BRDCST

T/R

RTRT

ILLCOM

Figure 21. Mode Code/Subaddress Illegalization Circuit

7.0 PACKAGE OUTLINE DRAWING

RTS-34

L

K

J

L10

L2

K2

J2

L3

K3

L4

K4

L5

K5

L6

K6

L7

K7

L8

K8

L9

K9

K10 K11

K1

J1

J10

H10

G10

J11

H11

G11

F11

E11

D11

C11

B11

H

H2

G2

H1

G1

G

F

F2

E2

D2

C2

B2

A2

F10

E10

D10

C10

B10

F1

E1

E

D

D1

C1

B1

C

B

A

B3

A3

B4

A4

B5

A5

B6

A6

B7

A7

B8

A8

B9

A9

A10

10

1

2

3

4

5

6

7

8

9

11

C1 ADDR9

C2 RBUSY

C10 DATA13

C11 DATA14

A2 MCSA1

A3 MCSA2

A4 MCSA4

A5 MERR

A6 TERACT or

DSCNCT

G1 ADDR3

G2 ADDR4

G10 DATA7

K1 RD/WR

K2 CS

K3 MRST

K4 RTA3

K5 RTA1

K6 RTPTY

K7 RBO

G11

V

SS

D1 ADDR7

D2 ADDR8

D10 DATA11

D11 DATA12

H1 ADDR1

H2 ADDR2

H10 DATA5

H11 DATA6

A7 BRDCST

A8 2MHz

A9 TBZ

K8 RAO

K9 ILLCOM

K10 DATA1

K11 DATA2

A10 TAZ

E1

V

DD

J1

J2

CTRL

ADDR0

B1 MC/SA

B2 MCSA0

B3 MCSA3

B4 T/R

E2 ADDR6

E10 DATA9

E11 DATA10

L2

L3

L4

L5

L6

L7

L8

12MHz

RTA4

RTA2

RTA0

RBZ

B5 TXERR

B6 TIMERON

B7 RTRT

F1

ADDR5

RAZ

VALMSG

B8 COMSTR

Figure 22. UT1760A RTS Pingrid Array Conﬁguration (Bottom View)

RTS-35


型号：	UT1760A-GC
厂家：	ETC
描述：	Telecommunication IC 电信IC\n 电信
文件：	总48页 (文件大小：1043K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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