UT22VP10E-15UCC [ETC]
Fuse-Programmable PLD ; 保险丝可编程PLD\n
| 型号： | UT22VP10E-15UCC |
| 厂家： | 
ETC |
| 描述： | Fuse-Programmable PLD
|
| 文件： | 总19页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Standard Products
UT22VP10 Universal RADPALTM
Data Sheet
November 2000
FEATURES
q High speed Universal RADPAL
q Radiation-hardened process and design; total dose irradia-
-
t
: 15.5ns, 20ns, 25ns maximum
tion testing to MIL-STD-883, Method 1019
PD
-
-
-
Total dose: 1.0E6 rads(Si)
-
f
: 33MHz maximum external frequency
MAX1
2
Upset threshold 50 MeV-cm /mg (min)
-
-
Supported by industry-standard programmer
Amorphous silicon anti-fuse
2
Latchup immune(LET>109 MeV-cm /mg)
q QML Q & V compliant
q Packaging options:
q Asynchronous and synchronous RADPAL operation
-
-
Synchronous PRESET
Asynchronous RESET
-
-
-
24-pin 100-mil center DIP (0.300 x 1.2)
24-lead flatpack (.45 x .64)
28-lead quad-flatpack (.45 x .45)
q Up to 22 input and 10 output drivers may be configured
-
-
CMOS & TTL-compatible input and output levels
Three-state output drivers
q Standard Military Drawing 5962-94754 available
q Variable product terms, 8 to 16 per output
q 10 user-programmable output macrocells
-
-
-
Registered or combinatorial operation
Output driver polarity control selectable
Two feedback paths available
13
11
10
9
8
7
6
5
4
3
2
1
12
VSS
Reset
PROGRAMMABLE ARRAY LOGIC
(132 X 44)
8
10
12
14
16
16
14
12
10
8
Preset
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
CP
VDD
14
15
16
17
18
19
20
21
22
23
24
Figure 1. Block Diagram
PRODUCT DESCRIPTION
QUAD-FLATPACK PIN CONFIGURATION
The UT22VP10 RADPAL is a fuse programmable logic array
device. The familiar sum-of-products (AND-OR) logic struc-
ture is complemented with a programmable macrocell. The
UT22VP10 is available in 24-pin DIP, 24-lead flatpack, and
28-lead quad-flatpack package offerings providing up to 22
inputs and 10 outputs. Amorphous silicon anti-fuse technology
provides the programming of each output. The user specifies
whether each of the potential outputs is registered or combina-
torial. Output polarity is also individually selected, allowing for
greater flexibility for output configuration. A unique output en-
able function allows the user to configure bidirectional I/O on
an individual basis.
I
I
CK/I VDD VDD I/O0 I/O1
4
3
2
1
28 27 26
25
I
I
5
6
7
8
I/O2
I/O3
I/O4
VSS
24
23
22
I
VSS
21
20
19
I
I
I
9
I/O5
I/O6
I/O7
10
11
The UT22VP10 architecture implements variable sum terms
providing8to16producttermstooutputs. Thisfeatureprovides
the user with increased logic function flexibility. Other features
include common synchronous preset and asynchronous reset.
These features eliminate the need for performing the initializa-
tion function.
12 13 14 15 16 17 18
I
I
VSS VSS
I
I/O9 I/O8
The UT22VP10 provides a device with the flexibility to imple-
ment logic functions in the 500 to 800 gate complexity. The
flexible architecture supports the implementation of logic func-
tions requiring up to 21 inputs and only a single output or down
to 12 inputs and 10 outputs. Development and programming
support for the UT22VP10 is provided by DATA I/O.
PIN NAMES
CK/I
Clock/Data Input
Data Input
I
I/O
Data Input/Output
Power
V
DD
DIP & FLATPACK PIN CONFIGURATION
V
Ground
SS
FUNCTION DESCRIPTION
1
2
24
23
CK/I
I
VDD
I/O0
The UT22VP10 RADPAL implements logic functions as sum-
of-products expressions in a one-time programmable-AND/
fixed-OR logic array. User-defined functions are created by
programming the connections of input signals into the array.
User-configurable output structures in the form of I/O macro-
cells further increase logic flexibility.
3
22
21
20
19
18
17
16
15
14
13
I
I
I
I
I
I
I
I
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I
4
5
6
7
8
9
10
11
12
I
VSS
2
1, 2, 3
Table 1. Macrocell Configuration Table
C
C
C
0
Output Type
Polarity
Feedback
2
1
0
0
0
Registered
Registered
Active LOW
Active HIGH
Active LOW
Active HIGH
Active LOW
Active HIGH
Registered
Registered
I/O
0
X
X
1
0
1
1
0
0
1
0
1
0
1
Combinatorial
Combinatorial
Registered
I/O
I/O
1
Registered
I/O
Notes:
1. 0 equals programmed low or programmed.
2. 1 equals programmed high or unprogrammed.
3. X equals don’t care.
a Don’t Care state exists and that term will always be a logical
one.
OVERVIEW
The UT22VP10 RADPAL architecture (see figure 1) has 12 ded-
icated inputs and 10 I/Os to provide up to 22 inputs and 10
outputs for creating logic functions. At the core of the device
is a one-time programmable anti-fuse AND array that drives a
fixed OR array. With this structure, the UT22VP10 can imple-
ment up to 10 sum-of-products logic expressions.
PRODUCT TERMS
The UT22VP10 provides 120 product terms that drive the 10
OR functions. The 120 product terms connect to the outputs in
two groups of 8, 10, 12, 14, and 16 to form logical sums.
MACROCELL ARCHITECTURE
Associated with each of the 10 OR functions is a macrocell
which is independently programmed to one of six different con-
figurations. The one-time programmable macro cells allow
each I/O to create sequential or combinatorial logic functions
with either Active-High or Active-Low polarity.
The output macrocell provides complete control over the archi-
tecture of each output. Configuring each output independently
permits users to tailor the configuration of the UT22VP10 to
meet design requirements.
Each I/O macrocell (see figure 2) consists of a D flip-flop and
two signal-select multiplexers. Three configuration select bits
controlling the multiplexers determine the configuration of
each UT22VP10 macrocell (see table 1). The configuration se-
lect bits determine output polarity, output type (registered or
combinatorial) and input feedback type (registered or I/O). See
figure 3 for equivalent circuits for the macrocell configurations.
LOGIC ARRAY
The one-time programmable AND array of the UT22VP10
RADPAL is formed by input lines intersecting product terms.
The input lines and product terms are used as follows:
44 input lines:
• 24 input lines carry the true and complement of the signals
applied to the input pins
OUTPUT FUNCTIONS
• 20 lines carry the true and complement values of feedback
or input signals from the 10 I/Os
The signal from the OR array may be fed directly to the output
pin (combinatorial function) or latched in the D flip-flop (reg-
istered function). The D flip-flop latches data on the rising edge
of the clock. When the synchronous preset term is satisfied, the
Q output of the D flip-flop output will be set logical one at the
next rising edge of the clock input. Satisfying the asynchronous
clear term sets Q logical zero, regardless of the clock state. If
both terms are satisfied simultaneously, the clear will override
the preset.
132 product terms:
• 120 product terms (arranged in 2 groups of 8, 10, 12, 14, and
16) used to form logic sums
• 10 output enable terms (one for each I/O)
• 1 global synchronous preset term
• 1 global asynchronous reset term
At each input-line/product-term intersection there is an anti-
fuse cell which determines whether or not there is a logical
connection at that intersection. A product term which is con-
nected to both the true and complement of an input signal will
always be logical zero, and thus will not effect the OR function
that it drives. When there are no connections on a product term
3
OUTPUT
SELECT
MUX
AR
D
Q
Q
C1 C0
CK
SP
INPUT/
FEEDBACK
MUX
C1 C2
C1
C0
C2
Figure 2. Macrocell
OUTPUT POLARITY
BIDIRECTIONAL I/O
Each macrocell can be configured to implement Active-High
or Active-Low logic. Programmable polarity eliminates the
need for external inverters.
The feedback signal is taken from the I/O pin when the macro-
cell implements a combinatorial function (C = 1) or a regis-
1
tered function (C = 1, C = 0). In this case, the pin can be used
2
1
as a dedicated input, a dedicated output, or a bidirectional I/O.
OUTPUT ENABLE
POWER-ON RESET
The output of each I/O macrocell can be enabled or disabled
under the control a programmable output enable product term.
The output signal is propagated to the I/O pin when the logical
conditions programmed on the output enable term are satisfied.
Otherwise, the output buffer is driven to the high-impedance
state.
To ease system initialization, all D flip-flops will power-up to
a reset condition and the Q output will be low. The actual output
of the UT22VP10 will depend on the programmed output po-
larity. The reset delay time is 5ms maximum. See the Power-up
Reset section for a more descriptive list of POR requirements.
The output enable term allows the I/O pin to function as a ded-
icated input, dedicated output, or bidirectional I/O. When every
connection is unprogrammed, the output enable product term
permanently enables the output buffer and yields a dedicated
output. If every connection is programmed, the enable term is
logically low and the I/O functions as a dedicated input.
ANTI-FUSE SECURITY
The UT22VP10 provides a security bit that prevents unautho-
rized reading or copying of designs programmed into the de-
vice. The security bit is set by the PLD programmer at the con-
clusion of the programming cycle. Once the security bit is set
it is no longer possible to verify (read) or program the
UT22VP10. NOTE: UTMC does not recommend using the
UT22VP10 unless the security fuse has been programmed.
The security bit must be blown to ensure proper function-
ality of the UT22VP10.
REGISTER FEEDBACK
The feedback signal to the AND array is taken from the Q output
when the I/O macrocell implements a registered function
(C = 0, C = 0).
2
1
4
AR
D
Q
Q
CK
SP
Registered Feedback, Registered, Active-Low Output (C = 0, C = 0, C = 0)
2
1
0
AR
D
Q
Q
CK
SP
Registered Feedback, Registered, Active-High Output (C = 0, C = 0, C = 1)
2
1
0
I/O Feedback, Combinatorial, Active-Low Output (C = X, C = 1, C = 0)
2
1
0
Figure 3. Macrocell Configuration (continued on next page)
5
I/O Feedback, Combinatorial, Active-High Output (C = X, C = 1, C = 1)
2
1
0
AR
D
Q
Q
CK
SP
I/O Feedback, Registered, Active-Low Output (C = 1, C = 0, C = 0)
2
1
0
AR
D
Q
Q
CK
SP
I/O Feedback, Registered, Active-High Output (C = 1, C = 0, C = 1)
2
1
0
Figure 3. Macrocell Configuration
6
1
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
LIMIT
UNITS
V
Supply voltage
-0.3 to 7.0
V
DD
2
Input voltage any pin
-0.3 to +7.0
V
V
I/O
T
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 10 seconds)
Thermal resistance junction to case
DC input current
-65 to +150
+175
+300
20
°C
°C
STG
T
J
T
°C
S
Q
°C/W
mA
W
JC
I
±10
I
3
Maximum power dissipation
1.6
P
D
I
Output sink current
12
mA
O
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the
device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2. Minimum voltage is -0.6VDD which may undershoot to -2.0VDD for pulses of less than 20ns. Maximum output pin voltage is VDD +0.75VDD which may
overshoot to +7.0VDD for pulses of less than 20ns.
3. (ICC max + IOS) 5.5V.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMIT
UNITS
1
Supply voltage
4.5 to 5.5
V
V
DD
V
Input voltage any pin
Temperature range
0 to V
V
IN
DD
T
-55 to + 125
°C
C
Notes:
1. See page 12 for minimum VDD requirements at power-up.
7
1, 7
DC ELECTRICAL CHARACTERISTICS
2
3,
(V
= 5.0V ±10%; V = 0V -55°C < T < +125°C)
SS C
DD
SYMBOL
PARAMETER
Low-level input voltage
CONDITION
MINIMUM
MAXIMUM
UNIT
V
TTL
--
.8
V
IL
V
High-level input voltage
Low-level input voltage
High-level input voltage
Low-level output voltage
High-level output voltage
Low-level output voltage
High-level output voltage
Input leakage current
TTL
2.2
--
--
V
V
IH
V
CMOS
CMOS
.3*V
--
IL
IH
DD
V
.7*V
V
DD
V
V
V
V
I
I
I
I
I
= 12.0mA, V = 4.5V (TTL)
.4
V
OL
OH
OL
OH
IN
OL
OH
OL
OH
DD
= -12.0mA, V = 4.5V (TTL)
2.4
--
--
V
DD
= 200mA, V = 4.5V (CMOS)
V
+0.05
--
V
DD
SS
= -200mA, V = 4.5V (CMOS)
V
-0.05
DD
V
DD
V
= V and V
SS
-10
-10
10
10
mA
mA
IN
DD
I
Three-stateoutputleakage V = V and V , V = 5.5V
OZ
O
DD
SS
DD
current
4,5
Short-circuit output cur-
rent
V
V
= 5.5V, V = V
DD
-160
160
mA
DD
DD
O
I
OS
= 5.5V, V = 0V
O
5,6
5,6
Input capacitance
=1MHz @0V
=1MHz @0V
--
--
--
15
15
pF
pF
C
IN
Bidirectional capacitance
C
I/O
5
Supply current: Output
three-state, worst-case pat-
tern programmed,
V
= 5.5V
120
mA
I
DD
DD
=f
MAX1
I
Supply current:
Unprogrammed
V
= 5.5V
--
25
mA
DDQ
DD
Notes:
1. All specifications valid for radiation dose < 1E6 rads(Si).
2. See page 12 for minimum VDD requirements at power-up.
3. Maximum allowable relative shift equals 50mV.
4. Duration not to exceed 1 second, one output at a time.
5. Tested initially and after any design or process changes that affect that parameter and, therefore, shall be guaranteed to the limit specified.
6. All pins not being tested are to be open.
7. CMOS levels only tested on CMOS devices. TTL levels only tested on TTL devices.
8
1,2
AC CHARACTERISTICS READ CYCLE (Post-Radiation)
3
(V
= 5.0V ±10%; -55°C < T < +125°C)
C
DD
22VP10-15.5
22VP10-20
MIN MAX
22VP10-25
MIN MAX
SYMBOL
PARAMETER
UNIT
MIN
MAX
4,5,6
Input to output propagation delay
Input to output enable delay
Input to output disable delay
Clock to output delay
15.5
20
25
ns
ns
ns
ns
ns
t
PD
4
23
23
15
24
23
23
15
24
25
25
15
28
t
t
EA
4
ER
4,6
t
CO
4
Clock to combinatorial output delay via internal
registered feedback
t
CO2
4,6
Input or feedback setup time
Input or feedback hold time
15
15
18
ns
ns
t
S
4,6
4
2
2
2
t
H
External clock period (t + t )
30
12
30
12
33
14
ns
t
CO
S
P
4
Clock width, clock high time, clock low time
External maximum frequency (1/(t + t ))
ns
t
WH, WL
4,6
4,6
4,6
33
42
32
13
33
42
32
13
30
36
32
13
MHz
MHz
MHz
ns
CO
S
f
f
f
MAX1
MAX2
Data path maximum frequency (1/(t
+ t ))
WL
WH
Internal feedback maximum frequency (1/(t + t ))
CO
CF
MAX3
4
Register clock to feedback input
Asynchronous reset width
t
CF
4
20
20
20
20
25
25
ns
t
AW
4
Asynchronous reset recovery time
Input to asynchronous reset
Synchronous preset recovery time
Power up reset time
ns
t
AR
4
20
20
25
ns
t
AP
4,6
20
20
25
ns
t
SPR
4,6
PR
1.0
1.0
1.0
ms
t
Notes:
1. Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E6 rads(Si).
2. Guaranteed by characterization.
3. See page 12 for minimum VDD requirements for power-up.
4. Tested initially and after any design or process changes that affect.
5. Device 22VP10-15 tested at -55°C, +25°C and +50°C. At 125°C, tested to 20ns limit.
6. Tested on Programmed Test Ring only.
9
INPUT OR
BIDIRECTIONAL
INPUT OR
BIDIRECTIONAL
VT
INPUT
VT
tS
INPUT
tH
tPD
CLOCK
VT
tCO
COMBINATIONAL
OUTPUT
VT
REGISTERED
OUTPUT
VT
tp
Combinatorial Output
Registered Output
INPUT OR
BIDIRECTIONAL
tWH
VT
INPUT
tER
tEA
VT
OUTPUT
VT
tWL
Clock Width
Combinatorial Output
(V - 0.5V, V + 0.5V)
OH
OL
tAW
INPUT ASSERTING
ASYNCHRONOUS
RESET
INPUT ASSERTING
SYNCHRONOUS
PRESET
VT
VT
tH
tAP
tS
tSPR
CLOCK
REGISTERED
OUTPUT
VT
VT
VT
tCO
tAR
CLOCK
REGISTERED
OUTPUT
VT
VT
Asynchronous Reset
Synchronous Preset
1,2,3
Notes:
1. VT = 1.5V.
Figure 4. AC Electrical
2. Input pulse amplitude 0V to 3.0V.
3. Input rise and fall times 3ns maximum.
10
CLK
CLK
PRODUCT
TERMS
D
Q
Q
PRODUCT
TERMS
D
Q
Q
REGISTER
REGISTER
1
tCF
PRODUCT
TERMS
OUTPUT
PRODUCT
TERMS
CLK
D
OUTPUT
Q
REGISTER
Clock to Combinatorial Output (t
)
CO2
Note:
1. tCF defined as the propagation delay from Q to D register input.
1
+ t
f
; Internal Feedback
MAX3
t
CO
CF
Figure 5. Signal Paths
11
POWER-UP RESET
4. Following reset, the clock input must not be driven from
LOW to HIGH until all applicable input and feedback setup
times are met.
The power-up reset feature ensures that all flip-flops will be
reset to LOW after the device has been powered up. The output
state will depend on the programmed pattern. This feature is
valuable in simplifying state machine initialization. See figure
6 for a timing diagram. Due to the synchronous operation of the
5. The power-up voltage must meet the minimum V require-
DD
ments described by the following device dependent and tem-
perature dependent equations:
power-up reset and the wide range of ways V can rise to its
DD
SMD Device types 01, 02, 03, 04, 08
CMOS and TTL
CMOS
steady state, the following five conditions are required to ensure
a valid power-up reset.
o
V
=4.61V -0.0090*( C)
DD
SMD Device types 05, 06, 07
o
V
=4.41 -0.0090* ( C)
1. The voltage supplied to the V pin(s) must be equal to 0V
DD
DD
Note: The minimum V requirement above is not applicable
if the UT22VP10 application is purely combinatorial (i.e. no
registered outputs).
prior to the intended power-up sequence.
DD
2. The voltage on V must rise from 0V to 1V at a rate of
DD
0.1V/s or faster.
3. The V rise must be continuously increasing with respect
DD
to time, through 3V, and monotonic thereafter.
VDD
VDD min
VDD
tPR
REGISTERED
ACTIVE-LOW
OUTPUT
tS
CLOCK
tWL
Figure 6. Power-Up Reset Waveform
RADIATION HARDNESS
The UT22VP10 RADPAL incorporates special design and layout features which allow operation in high-level radiation environments.
UTMC has developed special low-temperature processing techniques designed to enhance the total-dose radiation hardness of both
the gate oxide and the field oxide while maintaining the circuit density and reliability. For transient radiation hardness and latchup
immunity, UTMC builds radiation-hardened products on epitaxial wafers using an advanced twin-tub CMOS process.
1
RADIATION HARDNESS DESIGN SPECIFICATIONS
PARAMETER
CONDITION
+25°C per MIL-STD-883 Method 1019
-55°C to +125°C
MINIMUM
1.0E6
UNIT
Total Dose
rads(Si)
2
LET Threshold
Neutron Fluence
50
MeV-cm /mg
2
1MeV equivalent
1.0E14
n/cm
Note:
1. The RADPAL will not latchup during radiation exposure under recommended operating conditions.
12
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