UT62257C [ETC]
ASYNCHRONOUS STATIC RAM- High Speed ; 异步静态RAM-高速\n
| 型号： | UT62257C |
| 厂家： | 
ETC |
| 描述： | ASYNCHRONOUS STATIC RAM- High Speed
|
| 文件： | 总12页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UTRON
UT62257C
32K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
REVISION HISTORY
REVISION
DESCRIPTION
DATE
Preliminary Rev. 0.1 Original.
Jun 7,2001
Jul 19,2001
Rev. 1.0
1.TRUTH TABLE
2.DC ELECTRICAL CHARACTERISTICS
Add order information for lead free product
Rev. 1.1
May15,2003
UTRON TECHNOLOGY INC.
P80062
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
UTRON
UT62257C
32K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
FEATURES
GENERAL DESCRIPTION
ꢀ Access time : 35/70ns (max.)
ꢀ Low power consumption:
Operating : 40 mA (typical.)
Standby : 3mA (typical) normal
2uA (typical) L-version
The UT62257C is a 262,144-bit low power CMOS
static random access memory organized as 32,768
words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
1uA (typical) LL-version
The UT62257C is designed for high-speed and low
ꢀ Single 5V power supply
ꢀ All inputs and outputs are TTL compatible
ꢀ Fully static operation
、
power application. With 2 chip controls (
CE2 ), it
CE
is easy to design memory systems with power-down
and capacity expansion in the application circuits. It
is particularly well suited for battery back-up
nonvolatile memory application.
ꢀ Three state outputs
ꢀ Data retention voltage : 2V (min.)
ꢀ Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
The UT62257C operates from a single 5V power
supply and all inputs and outputs are fully TTL
compatible.
28-pin 8mmx13.4mm STSOP
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
Vcc
A14
A12
A7
1
28
27
32K X 8
MEMORY
ARRAY
A0-A14
DECODER
2
3
W
E
26
25
A13
A8
4
A6
Vcc
Vss
A5
5
6
24
23
A9
A4
A11
7
22
21
A3
CE2
A10
8
9
A2
I/O DATA
CIRCUIT
20
19
A1
CE
I/O1-I/O8
COLUMN I/O
A0
10
11
I/O8
I/O7
I/O6
I/O5
I/O4
18
17
16
15
I/O1
I/O2
I/O3
Vss
12
13
14
CE
PDIP/SOP
CONTROL
CIRCUIT
CE2
WE
A10
1
28
27
CE2
A11
2
3
CE
I/O8
I/O7
26
25
A9
A8
4
A13
WE
Vcc
5
6
24
23
I/O6
PIN DESCRIPTION
I/O5
I/O4
7
8
9
22
21
SYMBOL
DESCRIPTION
A14
A12
A7
Vss
I/O3
I/O2
I/O1
A0
UT62257C
A0 - A14
Address Inputs
20
19
I/O1 - I/O8
Data Inputs/Outputs
10
11
18
17
16
15
A6
Chip Enable Inputs
、
CE2
CE
12
13
14
A5
Write Enable Input
Power Supply
Ground
WE
VCC
VSS
A4
A1
A3
A2
STSOP
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80062
2
UTRON
UT62257C
32K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to VSS
Operating Temperature
SYMBOL
VTERM
TA
RATING
-0.5 to +7.0
0 to +70
-65 to +150
1
UNIT
V
℃
℃
Storage Temperature
TSTG
Power Dissipation
PD
W
mA
℃
DC Output Current
IOUT
50
Soldering Temperature (under 10 sec)
Tsolder
260
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
I/O OPERATION
SUPPLY CURRENT
CE2
X
L
H
H
CE
H
X
L
L
WE
X
X
H
L
Standby
High - Z
High - Z
DOUT
ISB, ISB1
ISB, ISB1
ICC, ICC1, ICC2
ICC, ICC1, ICC2
Read
Write
DIN
Note: H = VIH, L=VIL, X = Don't care.
℃
℃
DC ELECTRICAL CHARACTERISTICS (VCC = 5V±10%, TA = 0 to 70 )
PARAMETER
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage
Current
SYMBOL TEST CONDITION
MIN.
2.2
- 0.5
- 1
- 1
TYP.
MAX. UNIT
*1
VIH
-
-
-
-
VCC+0.5
V
V
*2
VIL
0.8
1
≦
≦
≦
VCC
ILI
ILO
VSS
VSS
VIN
A
µ
µ
≦
VI/O
VCC
1
A
=VIH or CE2 = VIL
CE
Output High Voltage
Output Low Voltage
Operating Power
Supply Current
VOH
VOL
ICC
IOH= - 1mA
2.4
-
-
40
30
-
V
V
mA
mA
IOL= 4mA
-
-
-
0.4
50
40
Cycle time=Min., II/O = 0mA ,
- 35
- 70
=VIL , CE2 = VIH
CE
ICC1
ICC2
Cycle time=1µs,100%duty,II/O=0mA,
= 0.2V ; CE2 = VCC-0.2V ,
-
-
-
-
10
mA
CE
other pins at 0.2V or VCC-0.2V
Cycle time=500ns,100%duty,II/O=0mA,
= 0.2V ; CE2 = VCC-0.2V ,
-
20
mA
CE
other pins at 0.2V or VCC-0.2V
Standby Power
Supply Current
ISB
normal
1
10
5
mA
mA
=VIH or CE2 = VIL
CE
CE
ISB1
0.3
≧
VCC-0.2V
≧
CE2 VCC-0.2V
ISB
-L/-LL
-L
-
-
-
3
mA
=VIH or CE2 = VIL
CE
CE
ISB1
-
2
1
100
40
A
A
µ
≧
VCC-0.2V
≧
CE2 VCC-0.2V
-LL
µ
Notes:
1. Overshoot : Vcc+2.0v for pulse width less than 10ns.
2. Undershoot : Vss-2.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON TECHNOLOGY INC.
P80062
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
UTRON
UT62257C
32K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
℃
CAPACITANCE (TA=25 , f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
MIN.
-
-
MAX
8
10
UNIT
pF
pF
CIN
CI/O
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
5ns
1.5V
CL = 100pF, IOH/IOL = -1mA/4mA
℃
℃
AC ELECTRICAL CHARACTERISTICS (VCC = 5V±10% , TA = 0 to 70 )
(1) READ CYCLE
PARAMETER
SYMBOL
UT62257C-35
MIN. MAX.
35
UT62257C-70
UNIT
MIN.
MAX.
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
-
70
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
10
5
-
35
35
25
-
70
70
35
-
-
10
5
-
-
5
-
-
25
25
-
35
35
-
-
5
(2) WRITE CYCLE
PARAMETER
SYMBOL
UT62257C-35
MIN. MAX.
35
UT62257C-70
UNIT
MIN.
MAX.
Write Cycle Time
tWC
tAW
tCW
tAS
tWP
tWR
tDW
tDH
-
70
60
60
0
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z
30
30
0
-
-
-
-
25
0
-
-
50
0
-
-
20
0
-
-
30
0
-
-
tOW*
tWHZ*
5
-
5
-
-
15
-
25
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
P80062
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
4
UTRON
UT62257C
32K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC
Address
tAA
tOH
tOH
Previous data valid
Dout
Data Valid
READ CYCLE 2 (
and CE2 Controlled) (1,3,4,5)
CE
tRC
Address
CE
tAA
tACE
CE2
tCHZ
tOH
tCLZ
Dout
High-Z
High-Z
Data Valid
Notes :
1.
is high for read cycle.
WE
2.Device is continuously selected
=low, CE2=high.
CE
3.Address must be valid prior to or coincident with
=low, CE2=high; otherwise tAA is the limiting parameter.
±
CE
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL=5pF. Transition is measured 500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ
.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80062
5
UTRON
UT62257C
32K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
WRITE CYCLE 1 (
Controlled) (1,2,3,5,6)
WE
tWC
Address
CE
tAW
tCW
CE2
tAS
tWP
tWR
WE
tWHZ
(4)
tOW
High-Z
Dout
Din
(4)
tDW
tDH
Data Valid
WRITE CYCLE 2 (
and CE2 Controlled) (1,2,5,6)
CE
tWC
Address
CE
tAW
tWR
tAS
tCW
CE2
tWP
WE
tWHZ
High-Z
(4)
Dout
Din
tDW
tDH
Data Valid
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80062
6
UTRON
UT62257C
32K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
Notes :
1.
,
must be high or CE2 must be low during all address transitions.
WE CE
2.A write occurs during the overlap of a low
, high CE2, low
.
WE
CE
3. During a
bus.
controlled write cycle, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed on the
WE
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the low transition and CE2 high transition occurs simultaneously with or after low transition, the outputs remain in a high
CE
impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
WE
±
℃
℃
DATA RETENTION CHARACTERISTICS (TA = 0 to 70 )
PARAMETER
Vcc for Data Retention
SYMBOL TEST CONDITION
VDR
MIN.
2.0
TYP.
-
MAX.
5.5
UNIT
V
≧
VCC-0.2V
CE
or CE2 ≤ 0.2V
Data Retention Current
IDR
tCDR
tR
- L
- LL
-
-
1
0.5
50
20
Vcc=3V, CE2 ≤ 0.2V
A
A
µ
µ
≧
or
VCC-0.2V
CE
Chip Disable to Data
Retention Time
Recovery Time
See Data Retention
Waveforms (below)
0
-
-
ns
tRC*
-
-
ns
tRC* = Read Cycle Time
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (
controlled)
CE
≧
VDR 2V
VCC
CE
Vcc(min.)
Vcc(min.)
tCDR
tR
≧
CE
VCC-0.2V
VIH
VIH
Low Vcc Data Retention Waveform (2) (CE2 controlled)
≧
VDR 2V
VCC
VCC(min.)
VCC(min.)
t
CDR
t
R
≦
CE2
0.2V
CE2
VIL
VIL
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80062
7
UTRON
UT62257C
32K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
PACKAGE OUTLINE DIMENSION
28 pin 600 mil PDIP Package Outline Dimension
UNIT
INCH(BASE)
SYMBOL
MM(REF)
A1
A2
B
0.010(MIN)
0.254(MIN)
±
3.810 0.254
±
0.457 0.127
±
0.150 0.001
±
0.018 0.005
c
±
±
0.254 0.102
0.010 0.004
D
±
±
37.084 0.127
1.460 0.005
E
±
±
0.600 0.010
15.240 0.254
e
0.100 (TYP)
2.540(TYP)
eB
L
±
±
16.256 0.762
±
3.302 0.254
0o~15o
0.640 0.03
±
0.130 0.010
0o~15o
θ
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80062
8
UTRON
UT62257C
32K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
28 pin 330 mil SOP Package Outline Dimension
UNIT
INCH(BASE)
SYMBOL
MM(REF)
A
A1
A2
b
0.112 (MAX)
0.004(MIN)
2.845 (MAX)
0.102(MIN)
±
±
0.098 0.005
2.489 0.127
0.016 (TYP)
0.010 (TYP)
0.406(TYP)
0.254(TYP)
c
D
±
±
18.110 0.127
0.713 0.005
E
±
±
8.407 0.127
0.331 0.005
E1
e
±
±
0.465 0.012
11.811 0.305
0.050 (TYP)
1.270(TYP)
L
±
±
1.0255 0.203
0.0404 0.008
L1
S
y
θ
±
±
0.067 0.008
1.702 0.203
0.047 (MAX)
0.003(MAX)
1.194 (MAX)
0.076(MAX)
o
o
10o
0
10o
∼
∼
0
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80062
9
UTRON
UT62257C
32K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
28 pin 8x13.4mm STSOP Package Outline Dimension
HD
c
L
1
28
14
15
"A"
y
Seating Plane
D
14
15
0
SEATING PLANE
1
28
L1
"A" DATAIL VIEW
UNIT
INCH(BASE)
0.047 (MAX)
MM(REF)
SYMBOL
A
A1
A2
D
1.20 (MAX)
±
±
0.10 0.05
±
1.00 0.05
±
11.800 0.100
0.004 0.002
±
0.039 0.002
±
0.465 0.004
±
±
E
0.315 0.004
8.000 0.100
e
0.022 (TYP)
0.55 (TYP)
±
±
13.40 0.20.
HD
L1
y
0.528 0.008
±
±
0.0315 0.004
0.003 (MAX)
0.80 0.10
0.076 (MAX)
o
o
Θ
∼
∼
0
5o
0
5o
UTRON TECHNOLOGY INC.
P80062
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
10
UTRON
UT62257C
32K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
ORDERING INFORMATION
PART NO.
ACCESS TIME
STANDBY CURRENT
PACKAGE
28 PIN PDIP
(ns)
70
70
70
35
35
35
70
70
70
35
35
70
70
(µA)
5 mA
UT62257CPC-70
UT62257CPC-70L
UT62257CPC-70LL
UT62257CSC-35
UT62257CSC-35L
UT62257CSC-35LL
UT62257CSC-70
UT62257CSC-70L
UT62257CSC-70LL
UT62257CLS-35L
UT62257CLS-35LL
UT62257CLS-70L
UT62257CLS-70LL
28 PIN PDIP
28 PIN PDIP
28 PIN SOP
28 PIN SOP
28 PIN SOP
28 PIN SOP
28 PIN SOP
28 PIN SOP
28 PIN STSOP
28 PIN STSOP
28 PIN STSOP
28 PIN STSOP
100
40
A
A
µ
µ
5 mA
100
A
µ
40
A
µ
5 mA
100
A
µ
40
100
50
A
µ
A
µ
A
µ
100
40
A
A
µ
µ
ORDERING INFORMATION (for lead free product)
PART NO.
ACCESS TIME
STANDBY CURRENT
PACKAGE
(ns)
(µA)
UT62257CPCL-70
UT62257CPCL-70L
UT62257CPCL-70LL
UT62257CSCL-35
UT62257CSCL-35L
UT62257CSCL-35LL
UT62257CSCL-70
UT62257CSCL-70L
UT62257CSCL-70LL
UT62257CLSL-35L
UT62257CLSL-35LL
UT62257CLSL-70L
UT62257CLSL-70LL
70
70
5 mA
28 PIN PDIP
28 PIN PDIP
28 PIN PDIP
28 PIN SOP
28 PIN SOP
28 PIN SOP
28 PIN SOP
28 PIN SOP
28 PIN SOP
28 PIN STSOP
28 PIN STSOP
28 PIN STSOP
28 PIN STSOP
100
40
A
A
µ
µ
70
35
35
35
70
70
70
35
35
70
70
5 mA
100
A
µ
40
A
µ
5 mA
100
A
µ
40
100
50
A
µ
A
µ
A
µ
100
40
A
A
µ
µ
UTRON TECHNOLOGY INC.
P80062
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
11
UTRON
UT62257C
32K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
THIS PAGE IS LEFT BLANK INTENTIONALLY.
UTRON TECHNOLOGY INC.
P80062
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
12
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