UT6264CSCL-70LE [ETC]
8K X 8 BIT LOW POWER CMOS SRAM;
| 型号： | UT6264CSCL-70LE |
| 厂家： | 
ETC |
| 描述： | 8K X 8 BIT LOW POWER CMOS SRAM 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总10页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UTRON
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
FEATURES
The UT6264C is a 65,536-bit low power CMOS
static random access memory organized as 8,192
words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
Access time : 35/70ns (max.)
ꢀ
Low power consumption :
ꢀ
Operating : 45/30 mA (typ.)
CMOS Standby : 2mA (typ.) normal
2 µA (typ.) L-version
Easy memory expansion is provided by using two
chip enable input.(
,CE2) ,and supports low
CE1
1 µA (typ.) LL-version
data retention voltage for battery back-up
operation with low data retention current.
Single 4.5V~5.5V power supply
ꢀ
Operating temperature :
ꢀ
℃
℃
Commercial : 0 ~70
The UT6264C operates from a single 4.5V~5.5V
power supply and all inputs and outputs are fully
TTL compatible.
All inputs and outputs TTL compatible
Fully static operation
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Three state outputs
Data retention voltage : 2V (min.)
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
PIN CONFIGURATION
Vcc
WE
NC
A12
A7
1
28
27
FUNCTIONAL BLOCK DIAGRAM
2
3
26
25
CE2
A8
×
4
8K
8
A6
A0-A12
DECODER
MEMORY
ARRAY
A5
5
6
24
23
A9
A4
A11
Vcc
Vss
7
8
9
22
21
A3
OE
A10
A2
20
19
CE1
I/O8
I/O7
I/O6
I/O5
I/O4
A1
A0
10
11
I/O DATA
CIRCUIT
I/O1-I/O8
COLUMN I/O
18
17
16
15
I/O1
I/O2
I/O3
Vss
12
13
14
CE1
CE2
OE
PDIP/SOP
CONTROL
CIRCUIT
WE
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0 - A12
Address Inputs
I/O1 - I/O8
Data Inputs/Outputs
Chip Enable Inputs
Write Enable Input
Output Enable Input
,CE2
CE1
WE
OE
VCC
VSS
NC
Power Supply
Ground
No connection
GENERAL DESCRIPTION
UTRON TECHNOLOGY INC.
P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
UTRON
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
SYMBOL
VTERM
TA
RATING
-0.5 to +7.0
0 to +70
UNIT
V
Terminal Voltage with Respect to VSS
Operating Temperature
Storage Temperature
Commercial
℃
TSTG
-65 to +150
℃
W
Power Dissipation
PD
1
DC Output Current
IOUT
50
260
mA
℃
Soldering Temperature (under 10 sec)
Tsolder
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
CE2
I/O OPERATION
SUPPLY CURRENT
CE1
H
OE
X
WE
X
Standby
Standby
Output Disable
Read
X
High - Z
High - Z
High - Z
DOUT
ISB, ISB1
X
L
X
X
ISB, ISB1
L
H
H
H
H
L
H
Icc,Icc1,Icc2
Icc,Icc1,Icc2
Icc,Icc1,Icc2
L
H
Write
L
X
L
DIN
note: H = VIH, L=VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS (VCC = 4.5V~5.5V, TA = 0℃to 70℃)
PARAMETER
Power Voltage
SYMBOL TEST CONDITION
MIN. TYP. MAX. UNIT
Vcc
VIH
VIL
4.5
2.2
5.0
5.5
VCC+0.5
0.8
V
V
V
Input High Voltage
Input Low Voltage
Input Leakage Current
-
-
-
- 0.5
- 1
A
µ
ILI
≦
≦
1
VSS VIN VCC
≦
≦
VSS VI/O VCC;
=VIH;or CE2=VIL;
CE1
= VIL
A
µ
Output Leakage Current
ILO
- 1
-
1
or
= VIH ;or
OE
WE
Output High Voltage
Output Low Voltage
VOH
VOL
IOH = - 1mA
IOL = 4mA
2.4
-
-
-
V
-
0.4
V
- 35
- 70
-
45
60
mA
Cycle time=Min,II/O = 0mA;
ICC
= VIL , CE2= VIH
-
-
30
45
30
mA
CE1
Cycle time=1us; II/O = 0mA ;
Operating Power
Supply Current
Icc1
=0.2V; CE2=Vcc-0.2V;
CE1
20
mA
other pins at 0.2V or Vcc-0.2V
Cycle time=500ns;II/O = 0mA;
=0.2V; CE2=Vcc-0.2V;
CE1
Icc2
ISB
-
10
15
mA
other pins at 0.2V or Vcc-0.2V
Normal
- L/- LL
Normal
- L
-
-
-
-
-
1
0.3
2
10
3
mA
mA
mA
= VIH or CE2= VIL
CE1
Standby Current (TTL)
5
≧
VCC-0.2V ;
CE1
A
µ
2
100
50
Standby Current (CMOS)
ISB1
≦
or CE2 0.2V;
A
µ
- LL
1
other pins at 0.2V or Vcc-0.2V
UTRON TECHNOLOGY INC.
P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
UTRON
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
℃
CAPACITANCE (TA=25 , f=1.0MHz)
PARAMETER
SYMBOL
CIN
MIN.
MAX
8
10
UNIT
pF
pF
Input Capacitance
Input/Output Capacitance
-
-
CI/O
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
5ns
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
1.5V
CL = 100pF, IOH/IOL = -1mA/4mA
℃
℃
AC ELECTRICAL CHARACTERISTICS (VCC = 4.5V~5.5V, TA = 0 to 70
)
(1) READ CYCLE
UT6264C-35
UT6264C-70
PARAMETER
SYMBOL
UNIT
MIN.
MAX.
MIN.
MAX.
Read Cycle Time
tRC
35
-
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tAA
-
35
35
25
-
-
70
70
35
-
Chip Enable Access Time
tACE1, tACE2
-
-
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
tOE
tCLZ1*, tCLZ2*
tOLZ*
tCHZ1*, tCHZ2*
-
-
10
5
-
10
5
-
-
-
25
25
-
35
35
-
tOHZ*
-
-
tOH
5
5
(2) WRITE CYCLE
PARAMETER
UT6264C-35
UT6264C-70
SYMBOL
UNIT
MIN.
35
30
30
0
MAX.
MIN.
70
60
60
0
MAX.
Write Cycle Time
tWC
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
tAW
-
-
tCW1, tCW2
-
-
tAS
-
-
Write Pulse Width
Write Recovery Time
tWP
25
0
-
50
0
-
tWR
-
-
Data to Write Time Overlap
Data Hold from End of Write-Time
Output Active from End of Write
Write to Output in High-Z
tDW
20
0
-
30
0
-
tDH
-
-
tOW*
5
-
5
-
tWHZ*
-
15
-
25
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
UTRON
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2,4)
tRC
Address
tAA
tOH
tOH
DOUT
Data Valid
(
, CE2 and
Controlled) (1,3,5,6)
READ CYCLE 2
CE1
OE
t
RC
Address
CE1
t
AA
t
t
ACE1
CE2
OE
ACE2
t
CHZ1
CHZ2
t
OE
t
OHZ
t CLZ1
t
t
OH
CLZ2 t OLZ
t
Dout
HIGH-Z
HIGH-Z
Data Valid
Notes :
1.
2. Device is continuously selected
is HIGH for a read cycle.
WE
,
=VIL and CE2=VIH.
OE CE1
3. Address must be valid prior to or coincident with
low
and CE2 high transition; otherwise tAA is the limiting parameter.
CE1
4.
5.
is low.
OE
±
t
CLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2 and tOHZ are specified with CL=5pF. Transition is measured 500mV from steady state.
6. At any given temperature and voltage condition, tCHZ1 is less than tCLZ1, tCHZ2 is less than tCLZ2, tOHZ is less than tOLZ.
UTRON TECHNOLOGY INC.
P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
UTRON
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
WRITE CYCLE 1 (
Controlled) (1,2,3,5,6)
WE
t
WC
Address
t
AW
CE1
CE2
t
CW1
CW2
t
t
WR
t
AS
t
WP
WE
t
WHZ
t
OW
High-Z
Dout
Din
(4)
(4)
t
DW
t
DH
Data Valid
WRITE CYCLE 2 (
and CE2 Controlled) (1,2,5)
CE1
t
WC
Address
t
AW
CW1
CE1
CE2
WE
t
AS
t
t
WR
t
CW2
t
WP
t
WHZ
High-Z
Dout
t
DH
t
DW
Din
Data Valid
Notes :
1.
or
must be HIGH or CE2 must be LOW during all address transitions.
CE1
WE
2. A write occurs during the overlap of a low
, a high CE2 and a low
.
CE1
WE
LOW, tWP must be greater than tWHZ+tDW to allow the I/O drivers to turn off
OE
3. During a
controlled with write cycle with
WE
and data to be placed on the bus.
4. During this period, I/O pins are in the output state, and input singals must not be applied.
5. If the
LOW transition occurs simultaneously with or after
LOW transition, the outputs remain in a high Impedance state.
CE1
WE
±
6.
t
OW and tWHZ are specified with CL=5pF. Transition is measured 500mV from steady state.
UTRON TECHNOLOGY INC.
P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
UTRON
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
℃
℃
DATA RETENTION CHARACTERISTICS (TA = 0 to 70
)
PARAMETER
SYMBOL
TEST CONDITION
MIN. TYP. MAX. UNIT
Vcc for Data Retention
≧
VDR
V
CC-0.2V or CE2 ≤ 0.2V
2.0
-
1
5.5
50
20
V
CE1
Vcc=2V
CE1
Data Retention Current
-L
-LL
-
-
µA
µA
IDR
≧
0.5
V
CC-0.2V or CE2 ≤ 0.2V
Chip Disable to Data
Retention Time
See Data RetentionWaveforms
tCDR
tR
0
-
-
-
-
ns
ns
(below)
Recovery Time
tRC*
tRC* = Read Cycle Time
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (
controlled)
CE1
Data Retention Mode
≧
V
DR
2V
V
CC
Vcc
Vcc
t
R
t
CDR
≧
CE1
V
CC-0.2V
CE1
V
IH
V
IH
Low Vcc Data Retention Waveform (2) (CE2 controlled)
Data Retention Mode
≧
V
DR
2V
V
CC
Vcc
Vcc
t
R
t
CDR
≦
CE2 0.2V
CE2
V
IL
V
IL
UTRON TECHNOLOGY INC.
P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
6
UTRON
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
PACKAGE OUTLINE DIMENSION
28 pin 600 mil PDIP Package Outline Dimension
UNIT
INCH(BASE)
MM(REF)
SYMBAOL1
0.010 (MIN)
0.254 (MIN)
`
±
±
A2
0.150 0.005 3.810 0.127
B
B1
c
0.020 (MAX)
0.055 (MAX)
0.012 (MAX)
0.508(MAX)
1.397(MAX)
0.304 (MAX)
D
1.430 (MAX) 36.322 (MAX)
E
0.625 (MAX)
0.52 (MAX)
0.100 (TYP)
0.6 (TYP)
15.87 (MAX)
13.208 (MAX)
2.540(TYP)
15.24 (TYP)
4.572(MAX)
1.524 (MAX)
2.032(MAX)
15o(MAX)
E1
e
eB
L
0.180(MAX)
0.06 (MAX)
0.08(MAX)
15o(MAX)
S
Q1
Θ
UTRON TECHNOLOGY INC.
P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
7
UTRON
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
28 pin 330 mil SOP Package Outline Dimension
UNIT
INCH(REF)
MM(BASE)
SYMBOL
A
0.112(max)
0.004(MIN)
0.098±0.005
0.016(TYP)
0.010(TYP)
0.713±0.005
0.331±0.005
0.465±0.012
0.050(TYP)
0.0404±0.008
0.067±0.008
0.047(MAX)
0.003(MAX)
0°~10°
2.845(max)
0.102(MIN)
A1
A2
b
2.489±0.127
0.406(TYP)
0.254(TYP)
18.110±0.127
8.407±0.127
11.811±0.305
1.270(TYP)
1.0255±0.203
1.702±0.203
1.194(MAX)
0.076(MAX)
0°~10°
c
D
E
E1
e
L
L1
S
y
θ
UTRON TECHNOLOGY INC.
P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
8
UTRON
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
ORDERING INFORMATION
ACCESS TIME
STANDBY CURRENT
PACKAGE
PART NO.
(ns)
35
35
35
70
70
70
35
35
35
70
70
70
(µA) (TYP.)
UT6264CPC-35
UT6264CPC-35L
UT6264CPC-35LL
UT6264CPC-70
UT6264CPC-70L
UT6264CPC-70LL
UT6264CSC-35
UT6264CSC-35L
UT6264CSC-35LL
UT6264CSC-70
UT6264CSC-70L
UT6264CSC-70LL
2mA
28 PIN PDIP
28 PIN PDIP
28 PIN PDIP
28 PIN PDIP
28 PIN PDIP
28 PIN PDIP
28 PIN SOP
28 PIN SOP
28 PIN SOP
28 PIN SOP
28 PIN SOP
28 PIN SOP
2 A
µ
1 A
µ
2mA
2 A
µ
1 A
µ
2mA
2 A
µ
1 A
µ
2mA
2 A
µ
1 A
µ
UTRON TECHNOLOGY INC.
P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
9
UTRON
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
REVISION HISTORY
REVISION
DESCRIPTION
DATE
Preliminary Rev. 0.1 Original.
May 3 ,2001
Jun.4,2001
Jan 15,2002
Rev. 1.0
Rev. 1.1
The timeing waveforms add CE2 control pin.
1. Revised package outline dimension.
2. Revised waveform.
UTRON TECHNOLOGY INC.
P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
10
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