UT62L1024PC-35L中文资料_数据手册_规格书



UTRON

UT62L1024

Rev. 1.7

128K X 8 BIT LOW POWER CMOS SRAM

FEATURES

GENERAL DESCRIPTION

Access time : 35/55/70ns (max.)

The UT62L1024 is a 1,048,576-bit low power

CMOS static random access memory organized

as 131,072 words by 8 bits. It is fabricated using

high performance, high reliability CMOS

technology.

Low power consumption :

Operating : 40/35/30 mA (typical)

Standby : 2.5µA (typical) L-version

0.5µA (typical) LL-version

Power supply range : 2.7V to 3.6V

Easy memory expansion is provided by using

All inputs and outputs TTL compatible

Fully static operation

two chip enable input.(

,CE2) It is

CE1

Three state outputs

particularly well suited for battery back-up

nonvolatile memory application.

Data retention voltage : 2V (min.)

Package : 32-pin 600 mil PDIP

32-pin 450 mil SOP

The UT62L1024 operates from a single 2.7V~

3.6V power supply and all inputs and outputs

are fully TTL compatible.

32-pin 8x20 mm TSOP-1

32-pin 8x13.4 mm STSOP

FUNCTIONAL BLOCK DIAGRAM

×

2048 512

A0-A16

DECODER

MEMORY

ARRAY

Vcc

Vss

I/O DATA

CIRCUIT

I/O1-I/O8

COLUMN I/O

CE1

CE2

OE

CONTROL

CIRCUIT

WE

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

UTRON

UT62L1024

Rev. 1.7

128K X 8 BIT LOW POWER CMOS SRAM

PIN CONFIGURATION

NC

Vcc

A15

1

32

31

A11

1

2

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

OE

A10

A16

2

A9

A8

CE2

A14

A12

3

4

30

29

3

CE1

I/O8

A13

4

WE

A13

A8

I/O7

I/O6

I/O5

I/O4

Vss

I/O3

I/O2

I/O1

A0

5

28

27

26

25

24

23

22

21

20

19

18

17

A7

A6

WE

CE2

6

A15

Vcc

NC

A16

A14

A12

A7

7

A5

A4

A9

7

8

A11

8

UT62L1024

9

A3

9

OE

A10

10

11

12

13

14

15

16

A2

10

11

A1

CE1

I/O8

A0

12

13

14

15

16

I/O1

I/O2

I/O3

Vss

I/O7

I/O6

I/O5

I/O4

A6

A1

A2

A3

A5

A4

PDIP / SOP

TSOP-I/STSOP

PIN DESCRIPTION

SYMBOL

A0 - A16

I/O1 - I/O8

DESCRIPTION

Address Inputs

Data Inputs/Outputs

Chip enable 1,2 Inputs

,CE2

CE1

Write Enable Input

Output Enable Input

WE

OE

V_CC

V_SS

NC

Power Supply

Ground

No Connection

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

UTRON

UT62L1024

Rev. 1.7

128K X 8 BIT LOW POWER CMOS SRAM

ABSOLUTE MAXIMUM RATINGS*

PARAMETER

SYMBOL

V_TERM

T_A

RATING

-0.5 to +4.6

0 to +70

UNIT

V

Terminal Voltage with Respect to Vss

Operating Temperature

℃

Storage Temperature

T_STG

P_D

-65 to +150

℃

W

Power Dissipation

1

DC Output Current

I_OUT

T_solder

50

260

mA

℃

Soldering Temperature (under 10 sec)

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect

device reliability.

TRUTH TABLE

MODE

I/O OPERATION

SUPPLY CURRENT

CE2

X

L

H

WE

CE1

OE

X

Standby

H

X

H

L

High - Z

High -Z

High - Z

D_OUT

I_SB,I_SB1

I_{CC ,}I_CC1

Standby

Output Disable

Read

X

L

X

H

L

I_{CC , CC1}

I

Write

X

D_IN

I_{CC ,}I_CC1

Note: H = V_IH, L=V_IL, X = Don't care.

℃

(V_CC= 2.7V~3.6V, Ta = 0 to +70

℃

DC ELECTRICAL CHARACTERISTICS

)

PARAMETER

SYMBOL TEST CONDITION

MIN. TYP. MAX. UNIT

Input High Voltage

Input Low Voltage

Input Leakage Current

V_IH

V_IL

I_IL

2.0

- 0.5

- 1

-

V_CC+0.5

V

µ

0.6

1

≦

A

V_SSV_INV_CC

Output Leakage Current I_OL

≦

V_SSV_I/OV_CC

=V_IHor CE2 = V_ILor

A

µ

CE1

- 1

-

1

= V_IHor

= V_IL

WE

OE

Output High Voltage

Output Low Voltage

Average Operating

Power Supply Courrent

V_OH

V_OL

I_CC

I_OH= - 1mA

2.2

-

V

I_OL= 4mA

-

0.4

60

V

Cycle time =Min. 100% Duty,

35

55

70

40

mA

=V_IL, CE2 = V_IH,

CE1

I_I/O= 0mA

Cycle time = 1 s, 100% Duty,

-

35

30

50

40

I_CC1

µ

-

5

mA

≦

≧

.

0.2V,CE2 V_CC-0.2V,

CE1

I

CE1

_I/O= 0mA

Standby Power

Supply Current

I_SB

I_SB1

-

1.0

mA

=V_IHor CE2 = V_IL

100

20*

40

≧

V_CC-0.2V or

A

µ

- L

2.5

≦

.CE2 0.2V

-

A

µ

-

0.5

LL

10*

℃

*Those parameters are for reference only under 50

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

UTRON

UT62L1024

Rev. 1.7

128K X 8 BIT LOW POWER CMOS SRAM

℃

(Ta=25 , f=1.0MHz)

CAPACITANCE

PARAMETER

SYMBOL

C_IN

MIN.

MAX.

UNIT

pF

Input Capacitance

6

8

-

Input/Output Capacitance

C_I/O

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels

0.4V to 2.4V

Input Rise and Fall Times

Input and Output Timing Reference Levels

Output Load

5ns

1.5V

C_L=50pF, I_OH/I_OL=-1mA/2mA

℃

(V_CC= 2.7V~3.6V , Ta = 0 to +70

℃

AC ELECTRICAL CHARACTERISTICS

)

(1) READ CYCLE

UT62L1024-35 UT62L1024-55 UT62L1024-70

MIN. MAX. MIN. MAX. MIN. MAX.

PARAMETER

SYMBOL

UNIT

Read Cycle Time

t_RC

35

-

55

-

70

-

ns

Address Access Time

t_AA

35

25

-

55

30

-

70

35

-

Chip Enable Access Time

Output Enable Access Time

Chip Enable to Output in Low-Z

t_ACE1, t_ACE2

-

t_OE

-

t_CLZ1*, t_CLZ2

*

10

5

-

10

5

-

10

5

-

Output Enable to Output in Low-Z t_OLZ

*

-

Chip Disable to Output in High-Z

t_CHZ1*, t_CHZ2

*

25

-

30

-

35

-

Output Disable to Output in High-Z t_OHZ

*

-

Output Hold from Address Change t_OH

5

(2) WRITE CYCLE

UT62L1024-35

UT62L1024-70

MAX. MIN. MAX.

UT62L1024-55

PARAMETER

SYMBOL

UNIT

MIN.

35

30

0

MAX. MIN.

Write Cycle Time

t_WC

-

55

50

0

-

70

60

0

-

ns

Address Valid to End of Write

Chip Enable to End of Write

Address Set-up Time

Write Pulse Width

t_AW

t_CW1, t_CW2

-

t_AS

-

t_WP

25

0

-

40

0

-

45

0

-

Write Recovery Time

Data to Write Time Overlap

t_WR

-

t_DW

20

0

-

25

0

-

30

0

-

Data Hold from End of Write-Time t_DH

-

Output Active from End of Write

Write to Output in High-Z

t_OW

*

5

-

5

-

5

-

t_WHZ

*

-

15

-

20

-

25

*These parameters are guaranteed by device characterization, but not production tested.

UTRON TECHNOLOGY INC.

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

UTRON

UT62L1024

Rev. 1.7

128K X 8 BIT LOW POWER CMOS SRAM

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) _(1,2,4)

t_RC

Address

t_AA

t_OH

DOUT

Data Valid

READ CYCLE 2 (

, CE2 and

Controlled) _(1,3,5,6)

CE1

OE

t

RC

Address

CE1

t

AA

t

ACE1

CE2

OE

ACE2

t

CHZ1

CHZ2

t

OE

t

OHZ

t

t ^CLZ1

t

OH

^CLZ2t ^OLZ

t

Dout

HIGH-Z

Data Valid

Notes :

1.

2. Device is continuously selected

is HIGH for a read cycle.

WE

,

=V_ILand CE2=V_IH.

OE CE1

3. Address must be valid prior to or coincident with

low

and CE2 high transition; otherwise t_AAis the limiting parameter.

CE1

4.

is low.

OE

±

5. t_CLZ1, t_CLZ2, t_OLZ, t_CHZ1, t_CHZ2and t_OHZare specified with C_L=5pF. Transition is measured 500mV from steady state.

6. At any given temperature and voltage condition, t_CHZ1is less than t_CLZ1, t_CHZ2is less than t_CLZ2, t_OHZis less than t_OLZ.

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

UTRON

UT62L1024

Rev. 1.7

128K X 8 BIT LOW POWER CMOS SRAM

WRITE CYCLE 1 (

Controlled) _(1,2,3,5)

WE

t

WC

Address

t

AW

CE1

CE2

t

CW1

t

CW2

t

WR

t

AS

t

WP

WE

t

WHZ

t

OW

High-Z

Dout

Din

(4)

t

DW

t

DH

Data Valid

WRITE CYCLE 2 (

and CE2 Controlled) _(1,2,5)

CE1

t

WC

Address

t

AW

CW1

CE1

CE2

WE

t

AS

t

WR

t

CW2

t

WP

t

WHZ

High-Z

Dout

t

DH

t

DW

Din

Data Valid

Notes :

1.

or

must be HIGH or CE2 must be LOW during all address transitions.

CE1

WE

2. A write occurs during the overlap of a low

, a high CE2 and a low

.

CE1

WE

LOW, t_WPmust be greater than t_WHZ+t_DWto allow the I/O drivers to turn

OE

3. During a

controlled with write cycle with

WE

off and data to be placed on the bus.

4. During this period, I/O pins are in the output state, and input singals must not be applied.

4. If the

LOW transition occurs simultaneously with or after

LOW transition, the outputs remain in a high Impedance

CE1

WE

state.

±

6. t_OWand t_WHZare specified with C_L=5pF. Transition is measured 500mV from steady state.

UTRON TECHNOLOGY INC.

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

UTRON

UT62L1024

Rev. 1.7

128K X 8 BIT LOW POWER CMOS SRAM

℃

DATA RETENTION CHARACTERISTICS

(Ta = 0 to +70

)

PARAMETER

SYMBOL TEST CONDITION

V_DR

MIN. TYP. MAX. UNIT

Vcc for Data Retention

2.0

-

3.3

V

≧

V_CC-0.2V or

CE1

CE2 ≤ 0.2V

Data Retention Current

I_DR

Vcc=2V

- L

-

40

20*

20

5*

-

µA

1

- LL

≧

V

_CC-0.2V or

CE1

0.5

-

CE2 ≤ 0.2V

Chip Disable to Data

Retention Time

t_CDR

t_R

See Data Retention

Waveforms (below)

0

ns

Recovery Time

t_RC*

-

t_RC* = Read Cycle Time

℃

*Those parameters are for reference only under 50

DATA RETENTION WAVEFORM

Date Retention Mode

V_CC

2.7V

t_R

V_DR≧2.0V

t_CDR

CE1

V_IH

V_SS

≧V_CC-0.2V

CE1

CE2

V_IL

CE2 ≤ 0.2V

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

UTRON

UT62L1024

Rev. 1.7

128K X 8 BIT LOW POWER CMOS SRAM

PACKAGE OUTLINE DIMENSION

32 pin 600 mil PDIP Package Outline Dimension

UNIT

INCH(BASE)

MM(REF)

^SYMBA^OL1

A2

B

0.010 (MIN)

0.254 (MIN)

±

0.150 0.005 3.810 0.127

±

0.018 0.005 0.457 0.127

A

±

0.050 0.005 1.270 0.127

B1

c

D

E

E1

e

eB

L

±

0.010 0.004 0.254 0.102

±

1.650 0.005 41.910 0.127

±

0.600 0.010 15.240 0.254

±

0.544 0.004 13.818 0.102

0.100 (TYP)

2.540 (TYP)

±

0.640 0.020 16.256 0.508

±

0.130 0.010 3.302 0.254

±

0.075 0.010 1.905 0.254

S

Q1

±

0.070 0.005 1.778 0.127

Note:

1. D/E1/S DIMENSION DO NOT INCLUDE MOLD FLASH.

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

UTRON

UT62L1024

Rev. 1.7

128K X 8 BIT LOW POWER CMOS SRAM

32 pin 450mil SOP Package Outline Dimension

UNIT

INCH(BASE)

SYMBOL

MM(REF)

A

A1

A2

b

0.118 (MAX)

0.004(MIN)

0.111(MAX)

0.016(TYP)

0.008(TYP)

0.817(MAX)

±

2.997 (MAX)

0.102(MIN)

2.82(MAX)

0.406(TYP)

0.203(TYP)

20.75(MAX)

±

c

D

E

0.445 0.005 11.303 0.127

±

E1

e

0.555 0.012 14.097 0.305

A

0.050(TYP)

1.270(TYP)

±

L

0.0347 0.008 0.881 0.203

±

L1

S

0.055 0.008 1.397 0.203

0.026(MAX)

0.004(MAX)

0^o-10^o

0.066 (MAX)

0.101(MAX)

0^o-10^o

y

C

Θ

UTRON TECHNOLOGY INC.

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

UTRON

UT62L1024

Rev. 1.7

128K X 8 BIT LOW POWER CMOS SRAM

32 pin TSOP-I Package Outline Dimension

UNIT

INCH(BASE)

MM(REF)

SYMBOL

A

0.047 (MAX)

1.20 (MAX)

±

0.004 0.002

0.10 0.05

A1

A2

C

±

0.039 0.002

1.00 0.05

0.008 + 0.002

- 0.001

0.20 + 0.05

-0.03

E

b

c

D

E

e

HD

L

0.005 (TYP)

±

0.127 (TYP)

±

0.724 0.004 18.40 0.10

±

0.315 0.004

8.00 0.10

0.020 (TYP)

0.50 (TYP)

±

0.787 0.008 20.00 0.20

±

0.0197 0.004 0.50 0.10

±

0.0315 0.004 0.08 0.10

L1

y

0.003 (MAX) 0.076 (MAX)

H

B

o

Θ

〜

0

5

0

5

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

UTRON

UT62L1024

Rev. 1.7

128K X 8 BIT LOW POWER CMOS SRAM

32 pin 8mm x 13.4mm STSOP Package Outline Dimension

HD

c

L

°

12 (2x)

32

1

17

16

"A"

y

Seating Plane

D

°

12 (2X)

16

17

GAUGE PLANE

0

SEATING PLANE

L

°

12 (2X)

L1

"A" DATAIL VIEW

1

32

UNIT

INCH(BASE)

MM(REF)

SYMBOL

A

0.049 (MAX)

1.25 (MAX)

±

0.005 0.002 0.130 0.05

A1

±

0.039 0.002

1.00 0.05

A2

b

±

0.008 0.01

0.20 0.025

c

0.005 (TYP)

0.127 (TYP)

±

0.465 0.004 11.80 0.10

D

±

0.315 0.004

8.00 0.10

E

e

0.020 (TYP)

0.50 (TYP)

±

0.528 0.008 13.40 0.20.

HD

L

±

0.0197 0.004 0.50 0.10

±

0.0315 0.004

0.8 0.10

L1

y

0.003 (MAX)

0.076 (MAX)

c

o

Θ

〜

0

5

0

5

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

UTRON

UT62L1024

Rev. 1.7

128K X 8 BIT LOW POWER CMOS SRAM

ORDERING INFORMATION

PART NO.

ACCESS TIME

STANDBY CURRENT

PACKAGE

(ns)

35

55

70

35

55

70

35

55

70

35

55

70

℃

(µA) (max) Ta = 50

UT62L1024PC-35L

UT62L1024PC-35LL

UT62L1024PC-55L

UT62L1024PC-55LL

UT62L1024PC-70L

UT62L1024PC-70LL

UT62L1024SC-35L

UT62L1024SC-35LL

UT62L1024SC-55L

UT62L1024SC-55LL

UT62L1024SC-70L

UT62L1024SC-70LL

UT62L1024LC-35L

UT62L1024LC-35LL

UT62L1024LC-55L

UT62L1024LC-55LL

UT62L1024LC-70L

UT62L1024LC-70LL

UT62L1024LS-35L

UT62L1024LS-35LL

UT62L1024LS-55L

UT62L1024LS-55LL

UT62L1024LS-70L

UT62L1024LS-70LL

20

10

20

10

20

10

20

10

20

10

20

10

20

10

20

10

20

10

20

10

20

10

20

10

32 PIN PDIP

32 PIN SOP

32 PIN TSOP-I

32 PIN STSOP

UTRON TECHNOLOGY INC.

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TEL: 886-3-5777882 FAX: 886-3-5777919

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

UTRON

UT62L1024

Rev. 1.7

128K X 8 BIT LOW POWER CMOS SRAM

REVISION HISTORY

REVISION

DESCRIPTION

DATE

Rev. 1.0

Rev. 1.1

Original.

128Kx 8 Low Voltage CMOS SRAM TN8106 body

降為：

Jun. 01. 1997

Apr. 05. 2000

之

已作

fine

將

、

tunings,

I

SB1

0.5uA(LL) 2uA(L) Vcc range 3.0V~3.6V

Rev. 1.2

Rev. 1.3

Rev. 1.4

Rev. 1.5

Rev. 1.6

Add STSOP-I Package

Modify the format of power consumption

Add speed : -55ns

Aug. 29. 2000

Sep. 01. 2000

Dec. 01. 2000

Mar. 15. 2001

Jun. 26. 2001

Vcc min 3.1→2.7V

1. The symbols CE1# ,OE# & WE# are revised as

,

&

.

CE1 OE WE

2. Add Icc value of 55ns range(access time) .

3. V_OHis revised as 2.2V.

4. I_SB1is revised as 100µs.

Rev. 1.7

Revised 32 pin 8mmx13.4mm STSOP Package Outline

Dimension.

Nov. 26. 2001

UTRON TECHNOLOGY INC.

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

UTRON

UT62L1024

Rev. 1.7

128K X 8 BIT LOW POWER CMOS SRAM

THIS PAGE IS LEFT BLANK INTENTIONALLY.

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型号	制造商	描述	价格	文档
UT62L1024PC-35LL	ETC	128K X 8 BIT LOW POWER CMOS SRAM	获取价格
UT62L1024PC-55L	ETC	128K X 8 BIT LOW POWER CMOS SRAM	获取价格
UT62L1024PC-55LL	ETC	128K X 8 BIT LOW POWER CMOS SRAM	获取价格
UT62L1024PC-70L	ETC	128K X 8 BIT LOW POWER CMOS SRAM	获取价格
UT62L1024PC-70LL	ETC	128K X 8 BIT LOW POWER CMOS SRAM	获取价格
UT62L1024SC-35L	ETC	128K X 8 BIT LOW POWER CMOS SRAM	获取价格
UT62L1024SC-35LL	ETC	128K X 8 BIT LOW POWER CMOS SRAM	获取价格
UT62L1024SC-55L	ETC	128K X 8 BIT LOW POWER CMOS SRAM	获取价格
UT62L1024SC-55LL	ETC	128K X 8 BIT LOW POWER CMOS SRAM	获取价格
UT62L1024SC-70L	ETC	128K X 8 BIT LOW POWER CMOS SRAM	获取价格

UT62L1024PC-35L

UT62L1024PC-35L 概述

UT62L1024PC-35L 数据手册

UT62L1024PC-35L 相关器件

UT62L1024PC-35L 相关文章

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