UT62L25716 [ETC]
ASYNCHRONOUS STATIC RAM- High Speed ; 异步静态RAM-高速\n
| 型号： | UT62L25716 |
| 厂家： | 
ETC |
| 描述： | ASYNCHRONOUS STATIC RAM- High Speed
|
| 文件： | 总13页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UTRON
UT62L25716
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.3
REVISION HISTORY
REVISION
Preliminary Rev. 0.5
DESCRIPTION
Draft Date
Mar, 2001
Original.
Rev.1.0
1.Separate Industrial and Commercial SPEC.
2.New waveforms.
Jul. 12,2001
3.Add access time 55ns range.
4.The symbols CE1# and OE# and WE# are revised as.
and
CE1
and
.
WE
OE
Rev.1.1
1.Revised access time ꢀ55/70/100ns
-Rev 1.0: 55ns(max) for Vcc=3.0V~3.6V
70/100 ns(max) for Vcc=2.7V~3.6V
Nov. 8. 2002
2.Revised “SYMBOL” : ꢀ
CE1 CE
3.Revised ABSOLUTE MAXIMUM RATINGS
- VTERM : -0.3 to 4.6 ꢀ-0.5 to 4.6V
- PD : 1.0~1.5 ꢀ1W
- IOUT : 50ꢀ20mA
4.Revised DC CHARACTERISTICS
- VIH : 2.0ꢀ2.2V
5.Revised AC CHARACTERISTICS
- tOH & tBLZ : 5ꢀ10ns
6.Revised 48-pin TFBGA package outline dimension：
-ball diameter : 0.3mm ꢀ0.35mm
Rev.1.2
1. Revised Standby current (LL-Version) : 3uA(typ)ꢀ2uA(typ)
Dec 03,2002
2. Revised operating current (Iccmax) : 45/35/25mAꢀ40/30/25mA
3. Revised DC CHARACTERISTICS :
a. Operating Power Supply Current (Icc)
55ns (max) : 45ꢀ40mA
70ns (typ) : 25ꢀ20mA, 70ns (max) : 35ꢀ30mA
100ns (Typ) : 20ꢀ16mA
b. Standby current(CMOS) :
LL-version (typ) : 3ꢀ2uA, 25ꢀ20uA
Rev.1.3
1. Revised VOH(Typ) : NAꢀ2.7V
May 06.2003
2. Add VIH(max)=VCC+2.0V for pulse width less than 10ns.
VIL(min)=VSS-2.0V for pulse width less than 10ns.
3. Add order information for lead free product
UTRON TECHNOLOGY INC.
P80047
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
UTRON
UT62L25716
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.3
FEATURES
GENERAL DESCRIPTION
ꢁ Fast access time : 55/70/100 ns
ꢁ CMOS low power operating
Operating current : 40/30/25 (Icc max.)
Standby current : 20uA (typ.) L-version
2uA (typ.) LL-version
The UT62L25716 is a 4,194,304-bit low power
CMOS static random access memory organized as
262,144 words by 16 bits.
The UT62L25716 operates from a single 2.7V ~
3.6V power supply and all inputs and outputs are
fully TTL compatible.
ꢁ Single 2.7V~3.6V power supply
ꢁ Operating temperature:
℃
℃
Commercial : 0 ~70
The UT62L25716 is designed for low power system
applications. It is particularly well suited for use in
high-density low power system applications.
℃
℃
Extended : -20 ~80
ꢁ All TTL compatible inputs and outputs
ꢁ Fully static operation
ꢁ Three state outputs
ꢁ Data retention voltage:1.5V (min.)
ꢁ Data byte control :
(I/O1~I/O8)
LB
(I/O9~I/O16)
UB
ꢁ Package : 48-pin 6mm × 8mm TFBGA
FUNCTIONAL BLOCK DIAGRAM
256K X 16
A0-A17
DECODER
MEMORY
ARRAY
Vcc
Vss
I/O1-I/O8
Lower Byte
I/O DATA
CIRCUIT
COLUMN I/O
I/O9-I/O16
Upper Byte
CE2
CE
OE
WE
LB
CONTROL
CIRCUIT
UB
UTRON TECHNOLOGY INC.
P80047
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
UTRON
UT62L25716
Rev. 1.3
256K X 16 BIT LOW POWER CMOS SRAM
PIN CONFIGURATION
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0 - A17
I/O1 - I/O16 Data Inputs/Outputs
Address Inputs
A
OE
UB
LB
A0
A3
A1
A4
A2
CE2
I/O1
I/O3
Vcc
Vss
I/O7
I/O8
NC
B
C
D
E
F
Chip Enable Input
Write Enable Input
Output Enable Input
Lower-byte Control
Upper-byte Control
, CE2
CE
I/O9
CE
WE
OE
LB
I/O10 I/O11
A5
A6
I/O2
I/O4
I/O5
I/O6
WE
A11
Vss
Vcc
I/O12
I/O13
A17
NC
A14
A12
A9
A7
A16
A15
A13
A10
UB
VCC
VSS
NC
Power Supply
Ground
No Connection
I/O15 I/O14
G
H
I/O16
NC
NC
A8
1
2
3
4
5
6
TFBGA
TRUTH TABLE
MODE
I/O OPERATION
SUPPLY
CURRENT
CE2
OE
UB
CE
WE
LB
I/O1-I/O8
I/O9-I/O16
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z
DOUT
H
X
X
L
L
L
L
L
L
L
L
X
L
X
X
X
H
H
L
L
L
X
X
X
X
X
X
H
H
H
H
H
L
X
X
H
L
X
L
H
L
L
H
L
X
X
H
X
L
H
L
L
High – Z
High – Z
High – Z
High – Z
High – Z
DOUT
Standby
ISB, ISB1
X
H
H
H
H
H
H
H
H
Output Disable
Read
ICC,ICC1,ICC2
ICC,ICC1,ICC2
High – Z
DOUT
DOUT
H
L
L
DIN
High – Z
DIN
High – Z
DIN
DIN
Write
L
L
ICC,ICC1,ICC2
Note: H = VIH, L=VIL, X = Don't care.
UTRON TECHNOLOGY INC.
P80047
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
UTRON
UT62L25716
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.3
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to VSS
SYMBOL
VTERM
TA
RATING
-0.5 to 4.6
0 to 70
-20 to 80
-65 to 150
1
UNIT
V
℃
Commercial
Extended
Operating Temperature
℃
TA
℃
Storage Temperature
Power Dissipation
DC Output Current
TSTG
PD
W
mA
℃
IOUT
50
Soldering Temperature (under 10 secs)
Tsolder
260
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
℃
℃
℃
℃
DC ELECTRICAL CHARACTERISTICS
(VCC = 2.7V~3.6V, TA = 0 to 70 / -20 to 80 (E))
PARAMETER
SYMBOL TEST CONDITION
MIN. TYP. MAX. UNIT
Power Voltage
Input High Voltage
VCC
2.7 3.0
3.6
VCC+0.3
V
V
V
＊
1
2.2
-0.2
- 1
-
-
-
-
VIH
＊
2
Input Low Voltage
0.6
1
VIL
ILI
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
≦
≦
A
µ
VSS VIN VCC
ILO
≦
≦
- 1
1
-
0.4
40
30
25
A
µ
VSS VI/O VCC; Output Disable
VOH
VOL
IOH= -1mA
IOL= 2.1mA
Cycle time=min, 100%duty
2.2 2.7
V
V
mA
mA
mA
-
-
-
-
-
55
70
30
20
16
Operating Power
Supply Current
ICC
I/O=0mA,
=V
IL
CE
100
Tcycle=
1 s
µ
Tcycle=
500ns
≦
100%duty,I =0mA,
0.2V,
CE
I/O
ICC1
-
-
4
8
5
mA
Average Operation
Current
other pins at 0.2V or Vcc-0.2V
ICC2
ISB
10
mA
mA
Standby Current (TTL)
-
-
-
0.3
20
2
0.5
80
20
=VIH, other pins =VIL or VIH
CE
CE
-L
-LL
A
A
µ
=V -0.2V
CC
Standby Current (CMOS) ISB1
other pins at 0.2V or Vcc-0.2V
µ
Notes:
1. Overshoot : Vcc+2.0v for pulse width less than 10ns.
2. Undershoot : Vss-2.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON TECHNOLOGY INC.
P80047
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
4
UTRON
UT62L25716
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.3
℃
CAPACITANCE
(TA=25 , f=1.0MHz)
PARAMETER
Input Capacitance
SYMBOL
CIN
MIN.
-
-
MAX
6
8
UNIT
pF
pF
Input/Output Capacitance
Note : These parameters are guaranteed by device characterization, but not production tested.
CI/O
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
5ns
1.5V
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
CL = 30pF, IOH/IOL = -1mA/2.1mA
℃
℃
℃
℃
AC ELECTRICAL CHARACTERISTICS
(VCC =2.7V~3.6V, TA =0 to 70 / -20 to 80 (E))
(1) READ CYCLE
UT62L25716-55 UT62L25716-70 UT62L25716-100
PARAMETER
SYMBOL
UNIT
MIN.
55
-
-
-
10
5
-
-
10
-
MAX.
-
55
55
30
-
MIN.
70
-
-
-
10
5
-
-
10
-
MAX.
-
70
70
35
-
MIN.
100
-
-
-
10
5
-
-
10
-
MAX.
-
100
100
50
-
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
20
20
-
25
25
-
30
30
-
tBA
55
70
100
,
Access Time
LB UB
tBHZ
tBLZ
-
25
-
-
30
-
-
40
-
ns
ns
,
to High-Z Output
to Low-Z Output
LB UB
10
10
10
,
LB UB
(2) WRITE CYCLE
PARAMETER
UT62L25716-55 UT62L25716-70 UT62L25716-100
SYMBOL
UNIT
MIN.
55
50
50
0
MAX.
MIN.
70
60
60
0
MAX.
MIN.
100
80
80
0
MAX.
Write Cycle Time
tWC
tAW
tCW
tAS
tWP
tWR
tDW
tDH
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z
-
-
-
45
0
-
-
55
0
-
-
70
0
-
-
25
0
-
-
30
0
-
-
40
0
-
-
tOW*
tWHZ*
tBW
5
-
5
-
5
-
-
45
30
-
-
60
30
-
-
80
40
-
,
Valid to End of Write
LB UB
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
P80047
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
5
UTRON
UT62L25716
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.3
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled)
(1,2)
tRC
Address
tAA
tOH
tOH
Previous data valid
Dout
Data Valid
READ CYCLE 2 (
and CE2 and
Controlled)
tRC
(1,3,4,5)
CE
OE
Address
CE
tAA
tACE
CE2
tBA
LB , UB
OE
tBHZ
tCHZ
tBLZ
tOE
tCLZ
tOLZ
tOHZ
tOH
Dout
High-Z
High-Z
Data Valid
Notes :
1.
is high for read cycle.
WE
2.Device is continuously selected
=low,
=low, CE2=high,
CE
or
LB UB
=low.
or
OE
3.Address must be valid prior to or coincident with
parameter.
=low, CE2=high,
=low transition; otherwise tAA is the limiting
CE
LB UB
±
4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL=5pF. Transition is measured 500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ, tBHZ is less than tBLZ, tOHZ is less than tOLZ
.
UTRON TECHNOLOGY INC.
P80047
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
6
UTRON
UT62L25716
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.3
WRITE CYCLE 1 (
Controlled)
(1,2,3,5,6)
WE
tWC
Address
CE
tAW
tCW
CE2
tAS
tWP
tWR
WE
tBW
LB , UB
tWHZ
(4)
tOW
tDH
High-Z
Dout
Din
(4)
tDW
Data Valid
WRITE CYCLE 2 (
and CE2 Controlled)
(1,2,5,6)
CE
tWC
Address
tAW
CE
tWR
tAS
tCW
CE2
WE
tWP
tBW
LB , UB
tWHZ
High-Z
(4)
Dout
Din
tDW
tDH
Data Valid
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80047
7
UTRON
UT62L25716
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.3
WRITE CYCLE 3 (
,
Controlled)
(1,2,5,6)
LB UB
tWC
Address
tAW
CE
CE2
tAS
tCW
tWR
tWP
WE
tBW
LB , UB
Dout
Din
tWHZ
High-Z
tDW
tDH
Data Valid
Notes :
1.
,
,
,
must be high or CE2 must be low during all address transitions.
WE CE LB UB
2.A write occurs during the overlap of a low
, high CE2, low
,
or
=low.
CE
OE
WE LB UB
3.During a
controlled write cycle with
low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be
WE
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the low transition and CE2 high transition occurs simultaneously with or after
,
,
low transition, the outputs remain in a
WE
CE LB UB
high impedance state.
±
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
UTRON TECHNOLOGY INC.
P80047
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
8
UTRON
UT62L25716
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.3
℃
℃
℃
℃
DATA RETENTION CHARACTERISTICS
(TA = 0 to 70 / -20 to 80 (E))
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX. UNIT
Vcc for Data Retention
VDR
1.5
-
3.6
V
≧
≦
CC-0.2V or CE2 0.2V
V
CE
Vcc=1.5V
Data Retention Current
IDR
- L
-
-
1
0.5
50
20
A
µ
µ
- LL
A
≧
VCC-0.2V
CE
≦
or CE2 0.2V
Chip Disable to Data
Retention Time
Recovery Time
tCDR
tR
See Data Retention
Waveforms (below)
0
5
-
-
-
-
ms
ms
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (
controlled)
CE
≧
VDR
1.5V
VCC
Vcc(min.)
Vcc(min.)
tCDR
tR
≧
CE
VCC-0.2V
VIH
VIH
CE
Low Vcc Data Retention Waveform (2) (CE2 controlled)
≧
≦
VDR
1.5V
0.2V
VCC
VCC(min.)
VCC(min.)
tCDR
tR
CE2
CE2
VIL
VIL
Low Vcc Data Retention Waveform (3) (
,
controlled)
LB UB
VDR ≧ 1.5V
VCC
Vcc(min.)
Vcc(min.)
t
CDR
t
R
LB,UB ≧ VCC-0.2V
VIH
VIH
LB,UB
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80047
9
UTRON
UT62L25716
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.3
PACKAGE OUTLINE DIMENSION
48 pin 6.0mmX8.0mm TFBGA Package Outline Dimension
UTRON TECHNOLOGY INC.
P80047
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
10
UTRON
UT62L25716
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.3
ORDERING INFORMATION
COMMERCIAL TEMPERATURE
PART NO.
ACCESS TIME
STANDBY CURRENT
PACKAGE
( ns )
( µA) typ.
UT62L25716BS-55L
UT62L25716BS-55LL
UT62L25716BS-70L
UT62L25716BS-70LL
UT62L25716BS-100L
UT62L25716BS-100LL
55
55
70
70
100
100
20
2
20
2
20
2
48 PIN BGA
48 PIN BGA
48 PIN BGA
48 PIN BGA
48 PIN BGA
48 PIN BGA
EXTENDED TEMPERATURE
PART NO.
ACCESS TIME
(ns)
STANDBY CURRENT
PACKAGE
( µA) typ.
UT62L25716BS-55LE
UT62L25716BS-55LLE
UT62L25716BS-70LE
UT62L25716BS-70LLE
UT62L25716BS-100LE
UT62L25716BS-100LLE
55
55
70
70
100
100
20
2
20
2
20
2
48 PIN BGA
48 PIN BGA
48 PIN BGA
48 PIN BGA
48 PIN BGA
48 PIN BGA
UTRON TECHNOLOGY INC.
P80047
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
11
UTRON
UT62L25716
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.3
ORDERING INFORMATION (for lead free product)
COMMERCIAL TEMPERATURE
PART NO.
ACCESS TIME
STANDBY CURRENT
PACKAGE
( ns )
( µA) typ.
UT62L25716BSL-55L
UT62L25716BSL-55LL
UT62L25716BSL-70L
UT62L25716BSL-70LL
UT62L25716BSL-100L
UT62L25716BSL-100LL
55
55
70
70
100
100
20
2
20
2
20
2
48 PIN BGA
48 PIN BGA
48 PIN BGA
48 PIN BGA
48 PIN BGA
48 PIN BGA
EXTENDED TEMPERATURE
PART NO.
ACCESS TIME
STANDBY CURRENT
PACKAGE
(ns)
( µA) typ.
UT62L25716BSL-55LE
UT62L25716BSL-55LLE
UT62L25716BSL-70LE
UT62L25716BSL-70LLE
UT62L25716BSL-100LE
UT62L25716BSL-100LLE
55
55
70
70
100
100
20
2
20
2
20
2
48 PIN BGA
48 PIN BGA
48 PIN BGA
48 PIN BGA
48 PIN BGA
48 PIN BGA
UTRON TECHNOLOGY INC.
P80047
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
12
UTRON
UT62L25716
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.3
THIS PAGE IS LEFT BLANK INTENTIONALLY.
UTRON TECHNOLOGY INC.
P80047
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
13
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