V53C1256164VBUT8I [ETC]
256Mbit MOBILE SDRAM 2.5 VOLT FBGA PACKAGE 16M X 16; 的256Mbit移动SDRAM 2.5伏FBGA封装16M ×16
| 型号： | V53C1256164VBUT8I |
| 厂家： | 
ETC |
| 描述： | 256Mbit MOBILE SDRAM 2.5 VOLT FBGA PACKAGE 16M X 16 |
| 文件： | 总46页 (文件大小：561K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
V55C2256164VB
256Mbit MOBILE SDRAM
2.5 VOLT FBGA PACKAGE 16M X 16
7
8PC
10
100MHz
10 ns
7 ns
System Frequency (fCK
Clock Cycle Time (tCK3
)
143 MHz
7 ns
125 MHz
8 ns
)
Clock Access Time (tAC3) CAS Latency = 3
Clock Access Time (tAC2) CAS Latency = 2
Clock Access Time (tAC1) CAS Latency = 1
5.4 ns
6 ns
6 ns
6 ns
8 ns
19 ns
19 ns
22 ns
■ Programmable Power Reduction Feature by par-
tial array activation during Self-Refresh
■ Operating Temperature Range
Commercial (0°C to 70°C)
Features
■ 4 banks x 4Mbit x 16 organization
■ High speed data transfer rates up to 143 MHz
■ Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
Industrial (-40°C to +85°C)
■ Single Pulsed RAS Interface
■ Data Mask for Read/Write Control
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency:1, 2, 3
■ Programmable Wrap Sequence: Sequential or
Interleave
■ Programmable Burst Length:
1, 2, 4, 8, Full page for Sequential Type
1, 2, 4, 8 for Interleave Type
■ Multiple Burst Read with Single Write Operation
■ Automatic and Controlled Precharge Command
■ Random Column Address every CLK (1-N Rule)
■ Power Down Mode and Clock Suspend Mode
■ Deep Power Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 8192 cycles/64 ms
■ Available in 54-ball FBGA, with 9x6 ball array
with 3 depupulated rows, 13x8 mm and 54 pin
TSOP II
■ VDD=2.5V, VDDQ=1.8V
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Temperature
C/T
7
•
8PC
10
Mark
0°C to 70°C
•
•
•
•
•
•
Commercial
Extended
-40°C to 85°C
•
V55C2256164VB Rev. 1.0 April 2005
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ProMOS TECHNOLOGIES
V55C2256164VB
Part Number Information
V
5 5
C
2
2 5 6 1 6
4
V
B
T
7
ORGANIZATION
ProMOS
& REFRESH
OTHER
16Mx16, 8K : 25616
PC
: CL2
TYPE
DRAM
SDRAM
BLANK: CL3
53
54
55
TEMPERATURE
BLNK: 0 - 70C
MOBILE SDRAM
-40 - 85C
I :
E :
-40 - 125C
CMOS
BANKS
SPEED
VOLTAGE
3 : 3.3 V
2 : 2.5 V
1 : 1.8 V
2 : 2 BANKS
I/O
10 : 100MHz
8 : 125MHz:
75 : 133MHz
7 : 143MHz
6 : 166MHz
5 : 200MHz
4 : 4 BANKS
8 : 8 BANKS
V: LVTTL
REV LEVEL
A: 1st
B: 2nd
C: 3rd
D: 4th
PACKAGE
LEAD PLATING
T
LEAD FREE GREEN
PACKAGE DESC.
TSOP
E
F
I
S
C
J
60-Ball FBGA
54-Ball FBGA
BGA
SPECIAL FEATURE
G
K
L: STANDARD LOW POWER
U: ULTRA LOW POWER
B
H
M
TI
SI
TS
SS
TE
SF
Die-Stacked TSOP
Die-Stacked FBGA
V55C2256164VB Rev. 1.0 April 2005
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ProMOS TECHNOLOGIES
V55C2256164VB
Description Pkg.
FBGA
Pin Count
C
54
Pin Configuration for x16 devices:
1
2
3
7
8
9
VSS DQ15 VSSQ
DQ14 DQ13 VDDQ
DQ12 DQ11 VSSQ
DQ10 DQ9 VDDQ
DQ8 NC VSS
UDQM CLK CKE
A
B
C
D
E
F
VDDQ DQ0 VDD
VSSQ DQ2 DQ1
VDDQ DQ4 DQ3
VSSQ DQ6 DQ5
VDD LDQM DQ7
CAS RAS WE
A12 A11
A9
A6
A4
G
H
J
BA0 BA1
CS
A10
VDD
A8
A7
A5
A0
A3
A1
A2
VSS
< Top-view >
V55C2256164VB Rev.1.0 April 2005
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ProMOS TECHNOLOGIES
V55C2256164VB
Description Pkg.
TSOP-II
Pin Count
T
54
54 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
Pin Names
CLK
Clock Input
CKE
Clock Enable
V
I/O
CCQ
NC
I/O
1
2
3
4
5
6
7
8
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
CC
1
CS
Chip Select
I/O
V
8
SSQ
RAS
Row Address Strobe
Column Address Strobe
Write Enable
V
NC
CAS
I/O
V
2
7
CCQ
V
SSQ
NC
WE
NC
I/O
CCQ
NC
I/O
V
3
6
SSQ
A0–A12
BA0, BA1
I/O1–I/O16
LDQM, UDQM
VCC
Address Inputs
Bank Select
V
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
NC
I/O
I/O
V
4
5
CCQ
Data Input/Output
Data Mask
V
SSQ
NC
NC
V
NC
WE
CAS
RAS
CS
BA0
BA1
V
SS
CC
NC
Power (+3.3V)
Ground
DQM
CLK
CKE
A12
VSS
VCCQ
VSSQ
Power for I/O’s (+3.3V)
Ground for I/O’s
Not connected
A
A
A
A
A
A
A
V
11
9
8
7
6
5
4
SS
A
10
NC
A
0
A
1
A
2
A
3
CC
V
356804V-01
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V55C2256164VB
Description
The V55C2256164VB is a four bank Synchronous DRAM organized as 4 banks x 4Mbit x 16. The
V55C2256164VB achieves high speed data transfer rates up to 143 MHz by employing a chip architecture
that prefetches multiple bits and then synchronizes the output data to a system clock.
All of the control, address, data input and output circuits are synchronized with the positive edge of an ex-
ternally supplied clock.
Operating the four memory banks in an interleaved fashion allows random access operation to occur at
higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 143 MHz is
possible depending on burst length, CAS latency and speed grade of the device.
Signal Pin Description
Pin
Type
Signal Polarity
Function
CLK
Input
Pulse
Positive
Edge
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
clock.
CKE
CS
Input
Input
Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode or the Self Refresh mode.
Pulse Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
RAS,CAS
WE
Input
Input
Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
A0 - A12
Level
—
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends from the SDRAM organization:
• 8M x 16 SDRAM CA0–CA8.
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are
used to define which bank to precharge.
BA0,
BA1
Input
Level
Level
—
—
Selects which bank is to be active.
DQx
Input
Data Input/Output pins operate in the same manner as on conventional DRAMs.
Output
LDQM
UDQM
Input
Pulse Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sam-
pled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a word mask by allowing input data to be written if it is low but blocks the write operation
if DQM is high.
VCC, VSS Supply
Power and ground for the input buffers and the core logic.
VCCQ
VSSQ
Supply
—
—
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
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V55C2256164VB
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the
positive edge of the clock. The following list shows the thruth table for the operation commands.
Device
State
CKE CKE
A0-9,
BS0
BS1
Operation
Row Activate
n-1
n
X
X
X
X
X
X
X
X
X
X
H
L
CS
L
RAS CAS WE DQM A11 A10
Idle3
Active3
Active3
Active3
Active3
Any
H
L
H
H
H
H
L
H
L
H
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
V
V
V
V
V
X
X
V
X
X
X
X
V
L
V
V
V
V
V
V
X
V
X
X
X
X
Read
H
L
Read w/Autoprecharge
Write
H
L
L
H
L
H
L
L
Write with Autoprecharge
Row Precharge
Precharge All
H
L
L
L
H
L
H
L
H
H
L
L
Any
H
L
L
L
H
V
X
X
X
X
Mode Register Set
No Operation
Idle
H
L
L
L
Any
H
L
H
X
L
H
X
L
H
X
H
H
X
X
X
X
X
L
Device Deselect
Auto Refresh
Any
H
H
L
Idle
H
Self Refresh Entry
Self Refresh Exit
Idle
H
L
L
L
Idle
H
L
X
H
X
H
X
H
X
H
X
H
X
H
(Self Refr.)
L
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
Power Down Entry
Power Down Exit
Idle
Active4
H
L
Any
H
L
(Power
Down)
H
Data Write/Output Enable
Data Write/Output Disable
Deep Pwoer Down Entry
Deep Pwoer Down Exit
Active
Active
Idle
H
H
H
L
X
X
L
X
X
L
X
X
H
X
X
X
H
X
X
X
L
L
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
Deep power-
Down
H
X
X
Notes:
1. V = Valid , x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands
are provided.
3. These are state of bank designated by BS0, BS1 signals.
4. Power Down Mode can not entry in the burst cycle.
5. After Deep Power Down mode exit a full new initialization of memory device is mandatory
V55C2256164VB Rev. 1.0 April 2005
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V55C2256164VB
rameters to be set as shown in the previous table.
Power On and Initialization
The default power on state of the mode register is
supplier specific and may be undefined. The
following power on and initialization sequence
guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM,
the Synchronous DRAM must be powered up and
initialized in a predefined manner. During power on,
all VCC and VCCQ pins must be built up
simultaneously to the specified voltage when the
input signals are held in the “NOP” state. The power
on voltage must not exceed VCC+0.3V on any of
the input pins or VCC supplies. The CLK signal
must be started at the same time. After power on,
an initial pause of 200 µs is required followed by a
precharge of both banks using the precharge
command. To prevent data contention on the DQ
bus during power on, it is required that the DQM and
CKE pins be held high during the initial pause
period. Once all banks have been precharged, the
Mode Register and Low Power Mode Register Set
Command must be issued to initialize the Mode
Register. A minimum of two Auto Refresh cycles
(CBR) are also required.These may be done before
or after programming the Mode Register. Failure to
follow these steps may lead to unpredictable start-
up modes.
Low Power Mode Register
The Low Power Mode Register controls functions
beyond those controlled by the Mode Register.
These additional functions are unique to the Low-
Power DRM and includes a Refresh Period field
(TCR) for temperature compensated self-refresh
and a Partial-Array Self-Refresh field (PAS). The
PASR field is used to specify whether only one
quarter (bank 0), one half (bank 0+1) or all banks of
the SDRAM array are enabled. Disabled banks will
not be refreshed in Self-Refresh mode and written
data will be lost. When only bank 0 is selected, it’s
possible to partially select only half or mone quarter
of bank 0. The TCR field has four entries to set Re-
fresh Period during self-refresh depending on the
case temperature of the Low power RAM. It’s re-
quired during the initialization seuqence and can be
modified when the part id idle.
Read and Write Operation
When RAS is low and both CAS and WE are high
at the positive edge of the clock, a RAS cycle starts.
According to address data, a word line of the select-
ed bank is activated and all of sense amplifiers as-
sociated to the wordline are set. A CAS cycle is
triggered by setting RAS high and CAS low at a
clock timing after a necessary delay, t
, from the
Programming the Mode Register
RCD
The Mode register designates the operation
mode at the read or write cycle. This register is di-
vided into 4 fields. A Burst Length Field to set the
length of the burst, an Addressing Selection bit to
program the column access sequence in a burst cy-
cle (interleaved or sequential), a CAS Latency Field
to set the access time at clock cycle and a Opera-
tion mode field to differentiate between normal op-
eration (Burst read and burst Write) and a special
Burst Read and Single Write mode. The mode set
operation must be done before any activate com-
mand after the initial power up. Any content of the
mode register can be altered by re-executing the
mode set command. All banks must be in pre-
charged state and CKE must be high at least one
clock before the mode set operation. After the mode
register is set, a Standby or NOP command is re-
quired. Low signals of RAS, CAS, and WE at the
positive edge of the clock activate the mode set op-
eration. Address input data at this timing defines pa-
RAS timing. WE is used to define either a read
(WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access
modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 125 MHz
data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation,
i.e., one of 1, 2, 4, 8. Column addresses are seg-
mented by the burst length and serial data accesses
are done within this boundary. The first column ad-
dress to be accessed is supplied at the CAS timing
and the subsequent addresses are generated auto-
matically by the programmed burst length and its
sequence. For example, in a burst length of 8 with
interleave sequence, if the first address is ‘2’, then
the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and
5.
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V55C2256164VB
Address Input for Mode Set (Mode Register Operation)
A12 ...
A7
BA1 BA0
Address Bus (Ax)
A6 A5 A4 A3 A2 A1 A0
CAS Latency BT Burst Length
Operation Mode
Mode Register
Burst Type
Operation Mode
BA1 BA0 A12 A11 A10 A9 A8 A7
A3
0
Type
Mode
Sequential
Interleave
Burst Read/Burst
Write
0
0
0
0
0
0
0
0
0
0
0
0
1
Burst Read/Single
Write
0
1
0
0
Burst Length
CAS Latency
Length
A6
0
A5
0
A4
Latency
Reserve
1
A2
A1
A0
Sequential Interleave
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
1
2
0
0
0
1
2
4
4
0
1
3
8
8
1
0
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Full page
Reserve
Reserve
Reserve
Reserve
1
0
1
1
1
1
Similar to the page mode of conventional
DRAM’s, burst read or write accesses on any col-
umn address are possible once the RAS cycle
with an operation change from a read to a write is
possible by exploiting DQM to avoid bus contention.
When two or more banks are activated
sequentially, interleaved bank read or write
operations are possible. With the programmed
burst length, alternate access and precharge
operations on two or more banks can realize fast
serial data access modes among many different
pages. Once two or more banks are activated,
column to column interleave operation can be done
between different pages.
latches the sense amplifiers. The maximum t
or
RAS
the refresh interval time limits the number of random
column accesses. A new burst access can be done
even before the previous burst ends. The interrupt
operation at every clock cycles is supported. When
the previous burst is interrupted, the remaining ad-
dresses are overridden by the new address with the
full burst length. An interrupt which accompanies
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V55C2256164VB
Low Power Mode Register Table
BA1 BA0
A12 to A5
A4 A3 A2 A1 A0 Address Bus (Ax)
1*)
0*)
all have to be set to "0"
TCR
PASR
Mode Register
Self-Refresh:
Temperature-Compensated
A4
0
A3
0
Max case temp
70OC
45OC
15OC
85OC
0
1
1
1
0
1
Partial-Array Self Refresh:
banks to be self-refreshed
A1 A0
A2
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
all banks
1/2 array (BA1=0)
1/4 array (BA1=0, BA0=0)
Reserved
0
0
0
1
Reserved
1
1/8 array (BA1=BA0=0, A11=0)
1
1/16 array (BA1=BA0=0,
A11=A10=0)
1
1
1
Reserved
*)BA1 and BA0 must be 1, 0 to select the Extended Mode Register (Vs. the Mode Register)
The Low Power Mode Register must be set during the initialization sequence. Once the device is operational, the
Low Power Mode Register set can be issued anytime when the part is idle.
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V55C2256164VB
Burst Length and Sequence:
Burst Starting Address Sequential Burst Addressing
Interleave Burst Addressing
Length
(A2 A1 A0)
(decimal)
(decimal)
2
xx0
xx1
0, 1
1, 0
0, 1
1, 0
4
8
x00
x01
x10
x11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
Full Page
nnn
Cn, Cn+1, Cn+2
Not supported
a data mask function for writes. When DQM is acti-
vated, the write operation at the next clock is prohib-
Refresh Mode
SDRAM has two refresh modes, Auto Refresh
and Self Refresh. Auto Refresh is similar to the CAS
-before-RAS refresh of conventional DRAMs. All of
banks must be precharged before applying any re-
fresh mode. An on-chip address counter increments
the word and the bank addresses and no bank infor-
mation is required for both refresh modes.
The chip enters the Auto Refresh mode, when
RAS and CAS are held low and CKE and WE are
held high at a clock timing. The mode restores word
line after the refresh and no external precharge
command is necessary. A minimum tRC time is re-
quired between two automatic refreshes in a burst
refresh mode. The same rule applies to any access
command after the automatic refresh operation.
The chip has an on-chip timer and the Self Re-
fresh mode is available. It enters the mode when
RAS, CAS, and CKE are low and WE is high at a
clock timing. All of external control signals including
the clock are disabled. Returning CKE to high en-
ables the clock and initiates the refresh exit opera-
ited (DQM Write Mask Latency t
= zero clocks).
DQW
Power Down
In order to reduce standby power consumption, a
power down mode is available. All banks must be
precharged and the necessary Precharge delay
(trp) must occur before the SDRAM can enter the
Power Down mode. Once the Power Down mode is
initiated by holding CKE low, all of the receiver cir-
cuits except CLK and CKE are gated off. The Power
Down mode does not perform any refresh opera-
tions, therefore the device can’t remain in Power
Down mode longer than the Refresh period (tref) of
the device. Exit from this mode is performed by tak-
ing CKE “high”. One clock delay is required for
mode entry and exit.
Auto Precharge
Two methods are available to precharge
SDRAMs. In an automatic precharge mode, the
CAS timing accepts one extra address, CA10, to
determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command
is issued, the Read with Auto-Precharge function
is initiated. The SDRAM automatically enters the
precharge operation one clock before the last data
out for CAS latencies 2, two clocks for CAS laten-
cies 3 and three clocks for CAS latencies 4. If CA10
is high when a Write Command is issued, the Write
tion. After the exit command, at least one t delay
is required prior to any access command.
RC
DQM Function
DQM has two functions for data I/O read and
write operations. During reads, when it turns to
“high” at a clock timing, data outputs are disabled
and become high impedance after two clock delay
(DQM Data Disable Latency t
). It also provides
DQZ
V55C2256164VB Rev. 1.0 April 2005
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ProMOS TECHNOLOGIES
V55C2256164VB
with Auto-Precharge function is initiated. The
SDRAM automatically enters the precharge opera-
Burst Termination
Once a burst read or write operation has been ini-
tiated, there are several methods in which to termi-
nate the burst operation prematurely. These
methods include using another Read or Write Com-
mand to interrupt an existing burst operation, use a
Precharge Command to interrupt a burst cycle and
close the active bank, or using the Burst Stop Com-
mand to terminate the existing burst operation but
leave the bank open for future Read or Write Com-
mands to the same page of the active bank. When
interrupting a burst with another Read or Write
Command care must be taken to avoid I/O conten-
tion. The Burst Stop Command, however, has the
fewest restrictions making it the easiest method to
use when terminating a burst operation before it has
been completed. If a Burst Stop command is issued
during a burst write operation, then any residual
data from the burst write cycle will be ignored. Data
that is presented on the I/O pins before the Burst
Stop Command is registered will be written to the
memory.
tion a time delay equal to t
after the last data in.
(Write recovery time)
WR
Precharge Command
There is also a separate precharge command
available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge
operation. Three address bits, BA0, BA1 and A10
are used to define banks as shown in the following
list. The precharge command can be imposed one
clock before the last data out for CAS latency = 2,
two clocks before the last data out for CAS latency
= 3. Writes require a time delay twr from the last
data out to apply the precharge command.
Bank Selection by Address Bits:
A10 BA0 BA1
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
Bank 0
Bank 1
Bank 2
Bank 3
all Banks
Deep Power Down Mode
TheDeep Power Down mode is an unique functi
on with very low standby currents. All internal volat
ge generators inside the RAM are stopped and all
memory data is lost in this mode. To enter the Deep
Power Down mode all banks must be precharged.
Recommended Operation and Characteristics
T = 0 to 70 °C(Commercial)/-40 to 85 °C(Extended); V = 0 V; V = 2.5 V,V
= 1.8V
A
SS
CC
CCQ
Limit Values
Parameter
Symbol
VCC
min.
max.
2.9
Unit
V
Notes
Supply voltage
2.3
1.65
I/O Supply Voltage
VCCQ
VIH
2.9
V
1, 2
1, 2
1, 2
Input high voltage
0.8xVCCQ
– 0.3
Vcc+0.3
0.3
V
Input low voltage
VIL
V
Output high voltage (IOUT = – 4.0 mA)
Output low voltage (IOUT = 4.0 mA)
VOH
VOL
VCCQ-0.2
–
–
V
0.4
V
Input leakage current, any input
II(L)
– 5
5
µA
(0 V < VIN < 3.6 V, all other inputs = 0 V)
Output leakage current
IO(L)
– 5
5
µA
(DQ is disabled, 0 V < VOUT < VCC
)
Note:
1. All voltages are referenced to VSS
2. IH may overshoot to VCC + 0.8 V for pulse width of < 4ns with 2.5V. VIL may undershoot to -0.8 V for pulse width < 4.0 ns with
2.5V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
.
V
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Absolute Maximum Ratings*
Operating temperature range (commercial)0 to 70 °C
Operating temperature range (extended) -25 to 85 °C
Storage temperature range ............... -55 to 150 °C
Input/output voltage ..................-0.3 to (V +0.3) V
CC
Power supply voltage ..........................-0.3 to 3.6 V
Power dissipation .......................................... 0.7 W
Data out current (short circuit) ...................... 50 mA
*Note:
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Operating Currents T = 0 to 70 °C(Commercial)/-40 to 85 °C(Extended);
A
V
= 0 V; V = 2.5 V,V
= 1.8V(Recommended Operating Conditions unless otherwise noted)
CCQ
SS
CC
Max.
-8PC
100
Symbol Parameter & Test Condition
ICC1 Operating Current
-7
10
Unit
Note
1 bank operation
110
90
mA
7
tRC = tRCMIN., tRC = tCKMIN.
Active-precharge command cy-
cling, without Burst Operation
ICC2P Precharge Standby Current
tCK = min.
CK = Infinity
0.5
0.5
0.5
0.5
0.5
0.5
mA
mA
7
7
in Power Down Mode
ICC2PS
t
CS =VIH, CKE≤ VIL(max)
ICC2N Precharge Standby Current
tCK = min.
CK = Infinity
20
5
20
5
20
5
mA
mA
in Non-Power Down Mode
ICC2NS
t
CS =VIH, CKE≥ VIL(max)
ICC3N No Operating Current
CKE ≥ VIH(MIN.)
25
5
25
5
25
5
mA
mA
mA
tCK = min, CS = VIH(min)
bank ; active state ( 4 banks)
ICC3P
ICC4
CKE ≤ VIL(MAX.)
(Power down mode)
Burst Operating Current
110
90
70
7,8
7
t
CK = min
Read/Write command cycling
ICC5
ICC7
Auto Refresh Current
165
10
155
10
150
10
mA
uA
tCK = min
Auto Refresh command cycling
Deep Power down Current
Notes:
7. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and
RC. Input signals are changed one time during tCK
t
.
8. These parameter depend on output loading. Specified values are obtained with output open.
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Temperature Compensated/Partial Array Self-Refresh Currents
Parameter & Test Condition
Extended Mode
Register M[4:3]
Tcase[ C]
Symb.
Max.
Unit
O
85OC max
70OC max
45OC max
15OC max
85OC max
70OCmax
45OC max
15OCmax
85OC max
70OC max
45OC max
15OC max
85OC max
70OC max
45OC max
15OC max
85OC max
70OC max
45OC max
15OC max
900
600
500
400
600
500
400
350
450
420
350
300
400
350
310
290
350
320
295
280
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
ICC6
Self Refresh Current
Self refresh Mode
CKE=0.2V, tck=infinity,
full array activations, all banks
ICC6
ICC6
ICC6
ICC6
Self Refresh Current
Self refresh Mode
CKE=0.2V, tck=infinity,
1/2 array activations, Bank 0+1
Self Refresh Current
Self refresh Mode
CKE=0.2V, tck=infinity,
1/4 array activations, Bank 0
Self Refresh Current
Self refresh Mode
CKE=0.2V, tck=infinity,
1/8 array activations, Bank 0
Self Refresh Current
Self refresh Mode
CKE=0.2V, tck=infinity,
1/16 array activations, Bank 0
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AC Characteristics 1,2, 3
T = 0 to 70 °C(Commercial)/-40 to 85 °C(Extended);V = 0 V; V = 2.5 V,V = 1.8V, tT=1 ns
A
SS
CC
CCQ
Limit Values
-8PC
-10
-7
Min. Max.
#
Symbol Parameter
Min.
Max.
Min.
Max.
Unit
Note
Clock and Clock Enable
1
2
3
tCK
tCK
tAC
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
CAS Latency = 1
7
–
–
–
8
–
–
–
10
12
25
–
–
–
ns
ns
ns
10
20
10
20
Clock Frequency
CAS Latency = 3
CAS Latency = 2
CAS Latency = 1
–
–
–
143
100
50
–
–
–
125
100
50
–
–
–
100
83
MHz
MHz
MHz
40
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
2, 4
–
_
_
5.4
6
–
_
_
6
6
–
_
_
7
8
ns
ns
ns
CAS Latency = 1
19
19
22
4
5
6
tCH
tCL
tT
Clock High Pulse Width
Clock Low Pulse Width
Transition Tim
2.5
2.5
0.3
–
–
3
3
–
–
3
3
–
–
ns
ns
ns
1.2
0.5
10
0.5
10
Setup and Hold Times
7
8
tIS
tIH
Input Setup Time
1.5
0.8
1.5
0.8
14
0
–
–
–
–
–
7
2
1
–
–
–
–
–
8
2.5
1
–
–
–
–
–
8
ns
ns
ns
ns
ns
ns
5
5
5
5
Input Hold Time
9
tCKS
tCKH
tRSC
tSB
Input Setup Time
2
2.5
1
10
11
12
CKE Hold Time
1
Mode Register Set-up Time
Power Down Mode Entry Time
16
0
20
0
Common Parameters
13
14
15
16
17
tRCD
tRP
tRAS
tRC
Row to Column Delay Time
Row Precharge Time
Row Active Time
15
15
42
60
14
–
20
20
45
60
16
–
–
20
20
50
70
20
–
–
ns
ns
ns
ns
ns
6
6
6
6
6
–
100K
–
100k
–
100k
–
Row Cycle Time
tRRD
Activate(a) to Activate(b) Command
Period
–
–
–
18
tCCD
CAS(a) to CAS(b) Command Period
1
–
1
–
1
–
CLK
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AC Characteristics (Cont’d)
Limit Values
-8PC
-10
-7
#
Symbol Parameter
Min. Max.
Min.
Max.
Min.
Max.
Unit
Note
Refresh Cycle
19
20
tREF
Refresh Period (8192 cycles)
Self Refresh Exit Time
—
64
—
64
—
64
ms
tSREX
1
—
1
—
1
—
CLK
Read Cycle
21
22
23
24
tOH
tLZ
Data Out Hold Time
3
1
3
–
–
–
7
2
3
1
3
–
–
–
7
2
3
1
3
–
–
–
7
2
ns
ns
2
7
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
tHZ
ns
tDQZ
CLK
Write Cycle
25
26
tWR
Write Recovery Time
1
0
–
–
1
0
–
–
1
0
–
–
CLK
CLK
tDQW
DQM Write Mask Latency
Notes for AC Parameters:
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests are referenced to the 0.9V crossover point for VCCQ=1.8V components. The transition time is mea-
sured between V and V . All AC measurements assume t = 1ns with the AC output load circuit shown in
IH
IL
T
Figure 1.
tCK
VIH
VIL
CLK
+ 1.4 V
t
T
tCS
tCH
50 Ohm
1.4V
COMMAND
Z=50 Ohm
I/O
tAC
tAC
tLZ
50 pF
tOH
1.4V
OUTPUT
tHZ
Figure 1.
4. If clock rising time is longer than 1 ns, a time (t /2 – 0.5) ns has to be added to this parameter.
T
5. If t is longer than 1 ns, a time (t – 1) ns has to be added to this parameter.
T
T
6. These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as
follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.
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Timing Diagrams
1. Bank Activate Command Cycle
2. Burst Read Operation
3. Read Interrupted by a Read
4. Read to Write Interval
4.1 Read to Write Interval
4.2 Minimum Read to Write Interval
4.3 Non-Minimum Read to Write Interval
5. Burst Write Operation
6. Write and Read Interrupt
6.1 Write Interrupted by a Write
6.2 Write Interrupted by Read
7. Burst Write & Read with Auto-Precharge
7.1 Burst Write with Auto-Precharge
7.2 Burst Read with Auto-Precharge
8. Burst Termination
8.1 Termination of a Burst Write Operation
8.2 Termination of a Burst Write Operation
9. AC- Parameters
9.1 AC Parameters for a Write Timing
9.2 AC Parameters for a Read Timing
10. Mode Register Set
11. Power on Sequence and Auto Refresh (CBR)
12. Power Down Mode
13. Self Refresh (Entry and Exit)
14. Auto Refresh (CBR)
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Timing Diagrams (Cont’d)
15. Random Column Read ( Page within same Bank)
15.1 CAS Latency = 2
15.2 CAS Latency = 3
16. Random Column Write ( Page within same Bank)
16.1 CAS Latency = 2
16.2 CAS Latency = 3
17. Random Row Read ( Interleaving Banks) with Precharge
17.1 CAS Latency = 2
17.2 CAS Latency = 3
18. Random Row Write ( Interleaving Banks) with Precharge
18.1 CAS Latency = 2
18.2 CAS Latency = 3
19. Precharge Termination of a Burst
19.1 CAS Latency = 2
19.2 CAS Latency = 3
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1. Bank Activate Command Cycle
(CAS latency = 3)
T0
T1
T
T
T
T
T
CLK
. . . . . . . . . .
Bank A
Row Addr.
Bank A
Col. Addr.
Bank A
Row Addr.
Bank B
Row Addr.
. . . . . . . . . .
ADDRESS
tRCD
tRRD
Write A
with Auto
Precharge
Bank B
Activate
Bank A
Activate
Bank A
Activate
. . . . . . . . . .
NOP
NOP
NOP
COMMAND
: “H” or “L”
tRC
2. Burst Read Operation
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
DOUT A0
DOUT A1
DOUT A0
DOUT A2
DOUT A1
DOUT A3
DOUT A2
t
CK2, I/O’s
CAS latency = 3
DOUT A3
t
CK3, I/O’s
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3. Read Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
DOUT A0
DOUT B0
DOUT A0
DOUT B1
DOUT B0
DOUT B2
DOUT B1
DOUT B3
DOUT B2
t
CK2, I/O’s
CAS latency = 3
DOUT B3
t
CK3, I/O’s
4.1 Read to Write Interval
(Burst Length = 4, CAS latency = 3)
T0 T1 T2
T3
T4
T5
T6
T7
T8
CLK
Minimum delay between the Read and Write Commands = 4+1 = 5 cycles
tDQW
DQM
tDQZ
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
NOP
NOP
COMMAND
I/O’s
DIN B
0
DIN B
1
DIN B
2
DOUT A
0
Must be Hi-Z before
the Write Command
: “H” or “L”
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4.2 Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
tDQW
DQM
tDQZ
1 Clk Interval
READ A
BANK A
ACTIVATE
NOP
NOP
WRITE A
NOP
NOP
NOP
NOP
COMMAND
Must be Hi-Z before
the Write Command
CAS latency = 2
DIN A
DIN A
DIN A
DIN A
3
0
1
2
tCK2, I/O’s
: “H” or “L”
4.3 Non-Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
tDQW
DQM
tDQZ
NOP
READ A
NOP
NOP
READ A
NOP
WRITE B
NOP
NOP
COMMAND
CAS latency = 2
DOUT A
DOUT A
DOUT A
DIN B
DIN B
DIN B
DIN B
DIN B
DIN B
0
1
0
1
2
tCK1, I/O’s
Must be Hi-Z before
the Write Command
CAS latency = 3
0
0
1
2
tCK2, I/O’s
: “H” or “L”
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5. Burst Write Operation
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
I/O’s
DIN A
0
don’t care
DIN A
DIN A
DIN A
3
1
2
The first data element and the Write
are registered on the same clock edge.
Extra data is ignored after
termination of a Burst.
6.1 Write Interrupted by a Write
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
WRITE A
WRITE B
DIN B0
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
I/O’s
1 Clk Interval
DIN A0
DIN B1
DIN B2
DIN B3
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6.2 Write Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
WRITE A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
don’t care
don’t care
DIN A
0
DOUT B
0
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
1
2
3
t
CK2, I/O’s
CAS latency = 3
DIN A
0
don’t care
DOUT B
3
0
1
2
tCK3, I/O’s
Input data must be removed from the I/O’s at least one clock
cycle before the Read dataAPpears on the outputs to avoid
data contention.
7. Burst Write with Auto-Precharge
Burst Length = 2, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
BANK A
ACTIVE
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Auto-Precharge
tRP
tWR
CAS latency = 2
DIN A
DIN A
0
1
I/O’s
*
tWR
tRP
CAS latency = 3
DIN A
DIN A
1
0
I/O’s
Begin Autoprecharge
*
Bank can be reactivated after trp
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7.2 Burst Read with Auto-Precharge
Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
READ A
COMMAND
t
RP
CAS latency = 2
*
DOUT A
DOUT A
DOUT A
DOUT A
t
0
1
2
3
t
CK2, I/O’s
RP
CAS latency = 3
*
DOUT A
DOUT A
DOUT A
DOUT A
3
0
1
2
tCK3, I/O’s
Begin Autoprecharge
*
Bank can be reactivated after t
RP
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8.1 Termination of a Burst Read Operation
(CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Burst
Stop
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
DOUT A0
DOUT A1
DOUT A0
DOUT A2
DOUT A1
DOUT A3
DOUT A2
t
CK2, I/O’s
CAS latency = 3
DOUT A3
t
CK3, I/O’s
8.2 Termination of a Burst Write Operation
(CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Burst
Stop
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2,3
don’t care
DIN A
0
DIN A
DIN A
2
1
I/O’s
Input data for the Write is masked.
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\)
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\)
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\)
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\)
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ProMOS TECHNOLOGIES
V55C2256164VB
V55C2256164VB Rev. 1.0 April 2005
38
ProMOS TECHNOLOGIES
V55C2256164VB
V55C2256164VB Rev. 1.0 April 2005
39
ProMOS TECHNOLOGIES
V55C2256164VB
V55C2256164VB Rev. 1.0 April 2005
40
ProMOS TECHNOLOGIES
V55C2256164VB
V55C2256164VB Rev. 1.0 April 2005
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ProMOS TECHNOLOGIES
V55C2256164VB
Deep Power Down Mode Entry
CLK
CKE
CS
WE
CAS
RAS
Addr.
DQM
DQ
input
DQ
output
High-Z
t RP
Precharge Command
Deep Power Down Entry
Deep Power Down Mode
Normal Mode
The deep power down mode has to be maintained for a minimum of 100µs.
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ProMOS TECHNOLOGIES
V55C2256164VB
Deep Power Down Exit
The deep power down mode is exited by asserting CKE high. After the exit, the following sequence is needed to
enter a new command:
1. Maintain NOP input conditions for a minimum of 200 µs
2. Issue precharge commands for all banks of the device
3. Issue eight or more autorefresh commands
4. Issue a mode register set command to initialize the mode register
5. Issue an extended mode register set command to initialize the extende mode register
CLK
CK E
CS
RAS
CAS
WE
200
s
tRP
tRC
Deep Power Down
exit
All banks
precharge
Auto
refresh
Auto
refresh
Mode
Register Mode
Set
Extended
New
Command
Register Accepted
Set
Here
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ProMOS TECHNOLOGIES
V55C2256164VB
Package Diagram
54-Pin Plastic TSOP-II (400 mil)
0.047 [1.20] MAX
+0.004
0.006
0.15
0.04 0.002
[1 0.05]
0.400 0.005
[10.16 0.13]
-0.002
+0.01
-0.05
.004 [0.1]
0.006 [0.15] MAX
0.024 0.008
[0.60 .020]
0.031
[0.80]
0.463 0.008
[11.76 0.20]
+0.002
M
54x
0.016
0.40
.008 [0.2]
-0.004
+0.05
-0.10
54
28
Index Marking
1
27
1
0.881 -0.01
[22.38 -0.25]
1
Does not include plastic or metal protrusion of 0.15 max. per side
Unit in inches [mm]
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ProMOS TECHNOLOGIES
V55C2256164VB
FBGA-BOC package 54 BGA package with 3 depop. rows
Units (mm)
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ProMOS TECHNOLOGIES
WORLDWIDE OFFICES
V55C2256164VB
SALES OFFICES:
JAPAN
TAIWAN(Hsinchu)
NO. 19 LI HSIN ROAD
SCIENCE BASED IND. PARK
HSIN CHU, TAIWAN, R.O.C.
PHONE: 886-3-566-3952
FAX: 886-3-578-6028
USA(West)
ONZE 1852 BUILDING 6F
2-14-6 SHINTOMI, CHUO-KU
TOKYO 104-0041
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
PHONE: 81-3-3537-1400
FAX: 81-3-3537-1402
TAIWAN(Taipei)
USA(East)
7F, NO. 102 MIN-CHUAN E. ROAD
SEC. 3, Taipei, Taiwan, R.O.C
PHONE: 886-2-2545-1213
FAX: 886-2-2545-1209
25 Creekside Road
Hopewell Jct, NY 12533
PHONE:845-223-1689
FAX:845-223-1684
© Copyright ,ProMOS TECHNOLOGY.
Printed in U.S.A.
The information in this document is subject to change without
notice.
ProMOS TECH subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. ProMOS TECH does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
ProMOS TECH makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of ProMOS TECH.
V55C2256164VB Rev. 1.0 April 2005
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