VMX51C900-25-PG [ETC]
Versa Mix 8051 MCU with LCD Controller and ADC; 反之亦然混合8051单片机LCD控制器和ADC型号: | VMX51C900-25-PG |
厂家: | ETC |
描述: | Versa Mix 8051 MCU with LCD Controller and ADC |
文件: | 总55页 (文件大小:2404K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
VMX51C900
Datasheet
Rev 1.2
Versa Mix 8051 MCU with LCD Controller and ADC
Overview
Features
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80C51/80C52 pin compatible
8KB on-chip Flash memory
The VMX51C900 is an 8-bit microcontroller with 8KB of
Flash memory, 256 bytes of RAM and based on the
architecture of the standard 80C51 microcontroller.
256 Bytes on-chip data RAM
4 8-bit I/O ports and 1 4-bit I/O port
4-Channel, 8-bit A/D Converter
LCD Driver: 14-Segment x 4-Common
2-PWM Outputs
UART serial port
3 16-bit Timers/Counters
Watchdog Timer
BCD arithmetic + 8-bit Unsigned Multiply and Division
2 levels of Interrupt Priority and nested Interrupts
Power saving modes
Low EMI (ALE disable)
Code protection function
Operates at a clock frequency of up to 25MHz
Industrial Temperature range (-40°C to +85°C)
5V version available
The VMX51C900 includes extra features such as a 4
Channel 8-bit A/D Converter, 2 PWM outputs and 14
segment x 4 common LCD driver. The VMX51C900
hardware features make it a versatile and cost-effective
controller for a wide range of embedded applications.
The Flash memory can be programmed using a parallel
programmer available from Ramtron. Support is also
available from 3rd party commercial programmer
manufacturers.
The VMX51C900 is available in PLCC-44, QFP-44 and
DIP-40 packages and operates over the industrial
temperature range.
FIGURE 2: VMX51C900 PLCC-44 AND QFP-44 PIN OUT DIAGRAMS
FIGURE 1: VMX51C900 BLOCK DIAGRAM
8051
PROCESSOR
ADDRESS/
DATA BUS
6
40
7
39
PWMB/P1.5
P1.6
P0.4/AD4/LCDSEG9
P0.5/AD5/LCDSEG8
P0.6/AD6/LCDSEG7
P0.7/AD7/LCDSEG6
#EA
8KB
FLASH
P1.7
PORT 0
8
8
8
8
4
RES
RXD/P3.0
P4.3
VMX51C900
PLCC-44
P4.1
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
ADCIN0/T0/P3.4
ADCIN1/T1/P3.5
ALE/LCDSEG5
256 Bytes of
RAM
PORT 1
PORT 2
PORT 3
PORT 4
#PSEN/LCDSEG4
P2.7/A15/LCDSEG3
P2.6/A14/LCDSEG2
P2.5/A13/LCDSEG1
17
29
UART
Serial port
18
28
POWER
CONTROL
2 INTERRUPT
INPUTS
TIMER 0
TIMER 1
TIMER 2
WATCHDOG
TIMER
RESET
PWM
2
14 segments
8 bit A/D
LCD Driver
4
Channel
Converter
(4 Inputs)
4
Commons
Ramtron International Corporation
1850 Ramtron Drive Colorado Springs
Colorado, USA, 80921
http://www.ramtron.com
MCU customer service: 1-800-943-4625, 1-514-871-2447, ext. 208
1-800-545-FRAM, 1-719-481-7000
?
?
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page 1 of 55
VMX51C900
A9
LCDCOM2
P2.2
A10
LCDCOM3
P2.3
O
-
I/O
O
-
I/O
O
-
Bit 9 of Ext. Memory Address
LCD Driver Common 2
Bit 2 of Port 2
Bit 10 of Ext. Memory Address
LCD Driver Common 3
Bit 3 of Port 2 &
26
27
28
29
30
33
23
22
A11
LCDSEG0
Bit 11 of Ext. Memory Address
LCD Segment 0
34
LCDSEG10/AD3/P0.3
P2.4/A12/LCDSEG0
P2.3/A11/LCDCOM3
P2.2/A10/LCDCOM2
P2.1/A9/LCDCOM1
P2.0/A8/LCDCOM0
LCDSEG11/AD2/P0.2
LCDSEG12/AD1/P0.1
LCDSEG13/AD0/P0.0
VDD
P2.4
A12
LCDSEG1
P2.5
A13
LCDSEG2
P2.6
A14
I/O
O
-
I/O
O
-
Bit 4 of Port 2
Bit 12 of Ext. Memory Address
LCD Segment 1
Bit 5 of Port 2
Bit 13 of External Memory Address
LCD Segment 2
VMX51C900
QFP-44
P4.2
P4.0
VSS
PWM0/T2/P1.0
T2EX/P1.1
PWMA/P1.2
P1.3
XTAL1
XTAL2
P3.7/#RD/ADCIN3
P3.6/#WR/ADCIN2
P1.4
44
12
11
1
I/O
O
Bit 6 of Port 2
Bit 14 of External Memory Address
Pin Descriptions for PLCC-44
TABLE 1: PIN DESCRIPTIONS FOR PLCC-44
PLCC
- 44
Name
I/O
Function
PLCC
- 44
1
Name
I/O
Function
Bit 2 of Port 4
LCDSEG3
P2.7
A15
LCDSEG4
#PSEN
LCDSEG5
ALE
-
LCD Segment 3
Bit 7 of Port 2
Bit 15 of External Memory Address
LCD Segment 4
Program Store Enable
LCD Segment 5
Address Latch Enable
Bit 1 of Port 4
External Access
P4.2
I/O
I
I/O
I
I/O
I/O
O
I/O
I/O
O
31
I/O
O
-
O
-
O
I/O
I
T2
Timer 2 Clock Out
Bit 0 of Port 1
Timer 2 Control
Bit 1 of Port 1
Bit 2 of Port 1
PWM Channel A
Bit 3 of Port 1
Bit 4 of Port 1
PWM Channel B
Bit 5 of Port 1
2
3
4
P1.0
T2EX
P1.1
P1.2
PWMA
P1.3
P1.4
PWMB
P1.5
P1.6
P1.7
32
33
34
35
P4.1
#EA
5
6
LCDSEG6
P0.7
AD7
LCDSEG7
P0.6
AD6
LCDSEG8
P0.5
AD5
LCDSEG9
P0.4
AD4
LCDSEG10
P0.3
AD3
LCDSEG11
P0.2
AD2
LCDSEG12
P0. 1
AD1
LCDSEG13
P0.0
AD0
-
LCD Segment 6
Bit 7 Of Port 0
Data/Address Bit 7 of Ext. Memory
LCD Segment 7
Bit 6 of Port 0
Data/Address Bit 6 of Ext. Memory
LCD Segment 8
Bit 5 of Port 0
Data/Address Bit 5 of Ext. Memory
LCD Segment 9
Bit 4 of Port 0
Data/Address Bit 4 of Ext. Memory
LCD Segment 10
Bit 3 Of Port 0
Data/Address Bit 3 of Ext. Memory
LCD Segment 11
Bit 2 of Port 0
Data/Address Bit 2 of Ext. Memory
LCD Segment 12
Bit 1 of Port 0 & Data
Address Bit 1 of Ext. Memory
LCD Segment 13
Bit 0 Of Port 0 & Data
Address Bit 0 of Ext. Memory
5V supply
36
37
38
39
40
41
42
I/O
I/O
-
I/O
I/O
-
I/O
I/O
-
I/O
I/O
-
I/O
I/O
-
I/O
I/O
-
I/O
I/O
-
I/O
I/O
-
7
I/O
I/O
I/O
I
8
9
10
Bit 6 of Port 1
Bit 7 of Port 1
Reset
RES
RXD
P3.0
P4.3
TXD
P3.1
#INT0
P3.2
#INT1
P3.3
ADCIN0
T0
I
Receive Data
11
12
13
I/O
I/O
O
I/O
I
I/O
I
I/O
Ain
I
I/O
Ain
I
I/O
Ain
O
I/O
Ain
O
I/O
O
Bit 0 of Port 3
Bit 3 of Port 4
Transmit Data &
Bit 1 of Port 3
External Interrupt 0
Bit 2 of Port 3
External Interrupt 1
Bit 3 of Port 3
ADC input 0
Timer 0
Bit 4 of Port 3
ADC input 1
Timer 1 & 3
Bit 5 of Port
14
15
16
17
18
19
P3.4
ADCIN1
T1
P3.5
ADCIN2
#WR
P3.6
ADCIN3
#RD
ADC input 2
Ext. Memory Write
Bit 6 of Port 3
ADC input 3
Ext. Memory Read
Bit 7 of Port 3
Oscillator/Crystal Output
Oscillator/Crystal In
Ground
Bit 0 of Port 4
LCD Driver Common 0
Bit 0 of Port 2
Bit 8 of Ext. Memory Address
LCD Driver Common 1
Bit 1 of Port 2
43
44
VDD
P3.7
20
21
22
23
XTAL2
XTAL1
VSS
P4.0
LCDCOM0
P2.0
A8
LCDCOM1
P2.1
I
-
I/O
-
I/O
O
24
25
-
I/O
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VMX51C900
6
40
7
39
PWMB/P1.5
P0.4/AD4/LCDSEG9
P0.5/AD5/LCDSEG8
P0.6/AD6/LCDSEG7
P0.7/AD7/LCDSEG6
#EA
P1.6
P1.7
RES
RXD/P3.0
P4.3
VMX51C900
PLCC-44
P4.1
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
ADCIN0/T0/P3.4
ADCIN1/T1/P3.5
ALE/LCDSEG5
#PSEN/LCDSEG4
P2.7/A15/LCDSEG3
P2.6/A14/LCDSEG2
P2.5/A13/LCDSEG1
17
29
18
28
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VMX51C900
Pin Descriptions for QFP-44
TABLE 2: PIN DESCRIPTIONS FOR QFP-44
Name
P4.1
#EA
LCDSEG6
P0.7
AD7
LCDSEG7
P0.6
AD6
LCDSEG8
P0.5
AD5
LCDSEG9
P0.4
AD4
LCDSEG10
P0.3
AD3
LCDSEG11
P0.2
AD2
LCDSEG12
P0. 1
AD1
LCDSEG13
P0.0
AD0
VDD
P4.2
T2
P1.0
T2EX
P1.1
I/O
Function
Bit 1 of Port 4
External Access
LCD Segment 6
Bit 7 Of Port 0
Data/Address Bit 7 of Ext. Memory
LCD Segment 7
Bit 6 of Port 0
Data/Address Bit 6 of Ext. Memory
LCD Segment 8
Bit 5 of Port 0
Data/Address Bit 5 of Ext. Memory
LCD Segment 9
Bit 4 of Port 0
Data/Address Bit 4 of Ext. Memory
LCD Segment 10
Bit 3 Of Port 0
Data/Address Bit 3 of Ext. Memory
LCD Segment 11
Bit 2 of Port 0
Data/Address Bit 2 of Ext. Memory
LCD Segment 12
Bit 1 of Port 0 & Data
Address Bit 1 of Ext. Memory
LCD Segment 13
Bit 0 Of Port 0 & Data
Address Bit 0 of Ext. Memory
5V supply
Bit 2 of Port 4
Timer 2 Clock Out
Bit 0 of Port 1
Timer 2 Control
Bit 1 of Port 1
Bit 2 of Port 1
PWM Channel A
PLCC
- 44
28
PLCC
- 44
Name
I/O
Function
PWM Channel B
Bit 5 of Port 1
Bit 6 of Port 1
Bit 7 of Port 1
Reset
I/O
I
-
I/O
I/O
-
I/O
I/O
-
I/O
I/O
-
I/O
I/O
-
I/O
I/O
-
I/O
I/O
-
I/O
I/O
-
I/O
I/O
-
I/O
I
I/O
I
I/O
I/O
O
I/O
I/O
PWMB
P1.5
P1.6
P1.7
O
1
29
I/O
I/O
I/O
I
2
3
4
30
31
32
33
34
35
36
37
RES
RXD
P3.0
P4.3
TXD
P3.1
#INT0
P3.2
#INT1
P3.3
ADCIN0
T0
P3.4
ADCIN1
T1
P3.5
ADCIN2
#WR
P3.6
ADCIN3
#RD
I
Receive Data
Bit 0 of Port 3
Bit 3 of Port 4
Transmit Data &
Bit 1 of Port 3
External Interrupt 0
Bit 2 of Port 3
External Interrupt 1
Bit 3 of Port 3
ADC input 0
Timer 0
Bit 4 of Port 3
ADC input 1
Timer 1 & 3
Bit 5 of Port
ADC input 2
Ext. Memory Write
Bit 6 of Port 3
ADC input 3
Ext. Memory Read
Bit 7 of Port 3
Oscillator/Crystal Output
Oscillator/Crystal In
Ground
Bit 0 of Port 4
LCD Driver Common 0
Bit 0 of Port 2
Bit 8 of Ext. Memory Address
LCD Driver Common 1
Bit 1 of Port 2
Bit 9 of Ext. Memory Address
LCD Driver Common 2
Bit 2 of Port 2
Bit 10 of Ext. Memory Address
LCD Driver Common 3
Bit 3 of Port 2 &
Bit 11 of Ext. Memory Address
LCD Segment 0
Bit 4 of Port 2
Bit 12 of Ext. Memory Address
LCD Segment 1
Bit 5 of Port 2
Bit 13 of External Memory Address
LCD Segment 2
Bit 6 of Port 2
Bit 14 of External Memory Address
LCD Segment 3
Bit 7 of Port 2
Bit 15 of External Memory Address
LCD Segment 4
5
6
7
I/O
I/O
O
I/O
I
I/O
I
I/O
Ain
I
I/O
Ain
I
I/O
Ain
O
I/O
Ain
O
I/O
O
8
9
10
11
12
13
P3.7
38
39
14
15
16
17
XTAL2
XTAL1
VSS
P4.0
LCDCOM0
P2.0
A8
LCDCOM1
P2.1
A9
LCDCOM2
P2.2
A10
LCDCOM3
P2.3
A11
LCDSEG0
I
-
40
41
42
I/O
-
I/O
O
18
19
20
21
22
23
24
25
P1.2
PWMA
P1.3
-
43
44
Bit 3 of Port 1
Bit 4 of Port 1
I/O
O
-
I/O
O
-
I/O
O
-
I/O
O
-
I/O
O
-
I/O
O
-
I/O
O
-
O
-
P1.4
P2.4
A12
LCDSEG1
P2.5
A13
LCDSEG2
P2.6
A14
LCDSEG3
P2.7
A15
33
23
34
22
LCDSEG10/AD3/P0.3
LCDSEG11/AD2/P0.2
LCDSEG12/AD1/P0.1
P2.4/A12/LCDSEG0
P2.3/A11/LCDCOM3
P2.2/A10/LCDCOM2
LCDSEG13/AD0/P0.0
VDD
P2.1/A9/LCDCOM1
P2.0/A8/LCDCOM0
VMX51C900
QFP-44
P4.2
P4.0
PWM0/T2/P1.0
VSS
T2EX/P1.1
PWMA/P1.2
P1.3
XTAL1
XTAL2
P3.7/#RD/ADCIN3
P3.6/#WR/ADCIN2
P1.4
44
12
11
1
LCDSEG4
#PSEN
LCDSEG5
ALE
26
27
Program Store Enable
LCD Segment 5
Address Latch Enable
O
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VMX51C900
DIP-40 Pin Descriptions
PLCC
- 44
Name
I/O
Function
LCD Segment 3
Bit 7 of Port 2
Bit 15 of External Memory Address
LCD Segment 4
Program Store Enable
LCD Segment 5
Address Latch Enable
External Access
LCD Segment 6
Bit 7 Of Port 0
Data/Address Bit 7 of Ext. Memory
LCD Segment 7
Bit 6 of Port 0
Data/Address Bit 6 of Ext. Memory
LCD Segment 8
Bit 5 of Port 0
Data/Address Bit 5 of Ext. Memory
LCD Segment 9
Bit 4 of Port 0
Data/Address Bit 4 of Ext. Memory
LCD Segment 10
Bit 3 Of Port 0
LCDSEG3
P2.7
A15
LCDSEG4
#PSEN
LCDSEG5
ALE
#EA
LCDSEG6
P0.7
AD7
LCDSEG7
P0.6
AD6
LCDSEG8
P0.5
AD5
LCDSEG9
P0.4
AD4
LCDSEG10
P0.3
AD3
LCDSEG11
P0.2
-
TABLE 3: VMX51C900 PIN DESCRIPTIONS FOR DIP40 PACKAGE
DIP -
28
29
I/O
O
-
O
-
O
I
-
Name
I/O
Function
40
T2
P1.0
T2EX
P1.1
P1.2
PWMA
P1.3
P1.4
PWMB
P1.5
P1.6
I
Timer 2 Clock Out
Bit 0 of Port 1
Timer 2 Control
Bit 1 of Port 1
Bit 2 of Port 1
PWM Channel A
Bit 3 of Port 1
Bit 4 of Port 1
PWM Channel B
Bit 5 of Port 1
1
30
31
I/O
I
I/O
I/O
O
I/O
I/O
O
I/O
I/O
I/O
I
2
3
32
33
34
35
36
37
38
I/O
I/O
-
I/O
I/O
-
I/O
I/O
-
I/O
I/O
-
I/O
I/O
-
I/O
I/O
-
I/O
I/O
-
I/O
I/O
-
4
5
6
7
8
9
Bit 6 of Port 1
Bit 7 of Port 1
Reset
P1.7
RES
RXD
P3.0
TXD
P3.1
#INT0
P3.2
#INT1
P3.3
ADCIN0
T0
P3.4
ADCIN1
T1
P3.5
ADCIN2
#WR
P3.6
ADCIN3
#RD
I
Receive Data
Bit 0 of Port 3
Transmit Data &
Bit 1 of Port 3
External Interrupt 0
Bit 2 of Port 3
External Interrupt 1
Bit 3 of Port 3
ADC input 0
Timer 0
Bit 4 of Port 3
ADC input 1
Timer 1 & 3
Bit 5 of Port
ADC input 2
Ext. Memory Write
Bit 6 of Port 3
ADC input 3
Ext. Memory Read
Bit 7 of Port 3
Oscillator/Crystal Output
Oscillator/Crystal In
Ground
10
11
12
13
I/O
O
I/O
I
I/O
I
I/O
Ain
I
I/O
Ain
I
I/O
Ain
O
I/O
Ain
O
I/O
O
Data/Address Bit 3 of Ext. Memory
LCD Segment 11
Bit 2 of Port 0
Data/Address Bit 2 of Ext. Memory
LCD Segment 12
Bit 1 of Port 0 & Data
Address Bit 1 of Ext. Memory
LCD Segment 13
AD2
LCDSEG12
P0. 1
AD1
LCDSEG13
P0.0
14
15
16
17
39
40
Bit 0 Of Port 0 & Data
Address Bit 0 of Ext. Memory
5V supply
AD0
VDD
P3.7
18
19
20
XTAL2
XTAL1
VSS
T2 / P1.0
T2EX / P1.1
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
I
-
2
P0.0 / AD0 / LCDSEG13
P0.1 / AD1 / LCDSEG12
P0.2 / AD2 / LCDSEG11
P0.3 / AD3 / LCDSEG10
P0.4 / AD4 / LCDSEG9
P0.5 / AD5 / LCDSEG8
P0.6 / AD6 / LCDSEG7
P0.7 / AD7 / LCDSEG6
#EA / VPP
PWMA / P1.2
P1.3
3
LCDCOM0
P2.0
A8
LCDCOM1
P2.1
A9
LCDCOM2
P2.2
A10
LCDCOM3
P2.3
A11
-
LCD Driver Common 0
Bit 0 of Port 2
Bit 8 of Ext. Memory Address
LCD Driver Common 1
Bit 1 of Port 2
Bit 9 of Ext. Memory Address
LCD Driver Common 2
Bit 2 of Port 2
Bit 10 of Ext. Memory Address
LCD Driver Common 3
Bit 3 of Port 2 &
Bit 11 of Ext. Memory Address
LCD Segment 0
Bit 4 of Port 2
Bit 12 of Ext. Memory Address
LCD Segment 1
Bit 5 of Port 2
Bit 13 of External Memory Address
LCD Segment 2
Bit 6 of Port 2
4
21
22
23
24
25
26
27
I/O
O
-
I/O
O
-
I/O
O
-
I/O
O
-
I/O
O
-
I/O
O
-
P1.4
5
PWMB / P1.5
P1.6
6
7
P1.7
8
RESET
9
VMX51C900
DIP-40
RXD / P3.0
TXD / P3.1
#INT0 / P3.2
#INT1 / P3.3
ADCIN0 / T0 / P3.4
ADCIN1 / T1 / P3.5
ADCIN2 / #WR / P3.6
ADCIN3 / #RD / P3.7
XTAL2
10
11
12
13
14
15
16
17
18
19
20
ALE / LCDSEG5
PSEN / LCDSEG4
P2.7 / A15 / LCDSEG3
P2.6 / A14 / LCDSEG2
P2.5 / A13 / LCDSEG1
P2.4 / A12 / LCDSEG0
P2.3 / A11 / LCDCOM3
P2.2 / A10 / LCDCOM2
P2.1 / A9 / LCDCOM1
P2.0 / A8 / LCDCOM0
LCDSEG0
P2.4
A12
LCDSEG1
P2.5
A13
LCDSEG2
P2.6
A14
XTAL1
VSS
I/O
O
Bit 14 of External Memory Address
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VMX51C900
Instruction Set
Size
(bytes)
Instr.
Cycles
Op
Code
Mnemonic
Description
Boolean Instruction
CLR C
CLR bit
SETB C
SETB bit
CPL C
The following tables describe the instruction set of the
VMX51C900. The instructions are function and binary code
compatible with industry standard 8051s.
Clear Carry bit
Clear bit
Set Carry bit to 1
Set bit to 1
Complement Carry bit
Complement bit
Logical AND between Carry and bit
Logical AND between Carry and not bit
Logical ORL between Carry and bit
Logical ORL between Carry and not bit
Copy bit value into Carry
Copy Carry value into Bit
1
2
1
2
1
2
2
2
2
2
2
2
1
1
1
1
1
1
2
2
2
2
1
2
C3h
C2h
D3h
D2h
B3h
B2h
82h
A0h,B0h
72h
A0h
TABLE 4: LEGEND FOR INSTRUCTION SET TABLE
CPL bit
Symbol
A
Function
Accumulator
ANL C,bit
ANL C,#bit
ORL C,bit
ORL C,#bit
MOV C,bit
MOV bit,C
Data Transfer Instructions
MOV A, Rn
MOV A, direct
MOV A, @Ri
MOV A, #data
MOV Rn, A
MOV Rn, direct
MOV Rn, #data
MOV direct, A
MOV direct, Rn
MOV direct, direct
MOV direct, @Ri
MOV direct, #data
MOV @Ri, A
MOV @Ri, direct
MOV @Ri, #data
MOV DPTR, #data
MOVC A, @A+DPTR
Rn
Register R0-R7
Direct
@Ri
rel
Internal register address
Internal register pointed to by R0 or R1 (except MOVX)
Two's complement offset byte
Direct bit address
A2h
92h
bit
#data
#data 16
addr 16
addr 11
8-bit constant
16-bit constant
16-bit destination address
11-bit destination address
Move register to A
Move direct byte to A
Move data memory to A
Move immediate to A
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
1
1
1
1
2
1
1
2
2
2
2
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
E8h-Efh
E5h
E6h,E7h
74h
F8h-FFh
A8h-AFh
78h-7Fh
F5h
88h-8Fh
85h
86h,87h
75h
F6h,F7h
A6h,A7h
76h-77h
90h
93h
83h
E2h,E3h
E0h
F2h,F3h
F0h
C0h
D0h
C8h-CFh
C5h
C6h,C7h
D6h,D7h
Move A to register
TABLE 5: VRS570/VRS580 INSTRUCTION SET
Move direct byte to register
Move immediate to register
Move A to direct byte
Move register to direct byte
Move direct byte to direct byte
Move data memory to direct byte
Move immediate to direct byte
Move A to data memory
Move direct byte to data memory
Move immediate to data memory
Move immediate to data pointer
Move code byte relative DPTR to A
Move code byte relative PC to A
Move external data (A8) to A
Move external data (A16) to A
Move A to external data (A8)
Move A to external data (A16)
Push direct byte onto stack
Pop direct byte from stack
Exchange A and register
Size
(bytes)
Instr.
Cycles
Op-
Code
Mnemonic
Description
Arithmetic instructions
ADD A, Rn
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
SUBB A, Rn
SUBB A, direct
SUBB A, @Ri
SUBB A, #data
INC A
INC Rn
INC direct
INC @Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
INC DPTR
MUL AB
Add register to A
Add direct byte to A
Add data memory to A
Add immediate to A
Add register to A with carry
Add direct byte to A with carry
Add data memory to A with carry
Add immediate to A with carry
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract data mem from A with borrow
Subtract immediate from A with borrow
Increment A
Increment register
Increment direct byte
Increment data memory
Decrement A
Decrement register
Decrement direct byte
Decrement data memory
Increment data pointer
Multiply A by B
Divide A by B
Decimal adjust A
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
4
1
28h-2Fh
25h
26h,27h
24h
38h-3Fh
35h
36h,37h
34h
98h-9Fh
95h
96h-97h
94h
04h
08h-0Fh
05h
06h, 07h
14h
18h-1Fh
15h
16h,17h
A3h
A4h
MOVC A, @A+PC
MOVX A, @Ri
MOVX A, @DPTR
MOVX @Ri, A
MOVX @DPTR, A
PUSH direct
POP direct
XCH A, Rn
XCH A, direct
XCH A, @Ri
XCHD A, @Ri
Branching Instructions
Exchange A and direct byte
Exchange A and data memory
Exchange A and data memory nibble
11h,31h,
51h,71h,
91h,B1h,
D1h,F1h
12h
22h
32h
01h,21h,
41h,61h,
81h,A1h,
C1h,E1h
02h
80h
40h
50h
20h
30h
10h
73h
60h
70h
B5h
ACALL addr 11
Absolute call to subroutine
2
2
DIV AB
DA A
84h
D4h
LCALL addr 16
RET
RETI
Long call to subroutine
Return from subroutine
Return from interrupt
3
1
1
2
2
2
Logical Instructions
ANL A, Rn
ANL A, direct
ANL A, @Ri
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, Rn
ORL A, direct
ORL A, @Ri
ORL A, #data
ORL direct, A
ORL direct, #data
XRL A, Rn
XRL A, direct
XRL A, @Ri
XRL A, #data
XRL direct, A
XRL direct, #data
CLR A
AND register to A
AND direct byte to A
AND data memory to A
AND immediate to A
AND A to direct byte
AND immediate data to direct byte
OR register to A
OR direct byte to A
OR data memory to A
OR immediate to A
OR A to direct byte
OR immediate data to direct byte
Exclusive-OR register to A
Exclusive-OR direct byte to A
Exclusive-OR data memory to A
Exclusive-OR immediate to A
Exclusive-OR A to direct byte
Exclusive-OR immediate to direct byte
Clear A
Compliment A
Swap nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
58h-5Fh
55h
56-57h
54h
52h
53h
48h-4Fh
45h
46h,47h
44h
42h
43h
68h-6Fh
65h
66h,67h
64h
62h
63h
E4h
F4h
C4h
23h
AJMP addr 11
Absolute jump unconditional
2
2
LJMP addr 16
SJMP rel
JC rel
JNC rel
JB bit, rel
JNB bit, rel
JBC bit,rel
JMP @A+DPTR
JZ rel
Long jump unconditional
Short jump (relative address)
Jump on carry = 1
Jump on carry = 0
Jump on direct bit = 1
3
2
2
2
3
3
3
1
2
2
3
3
3
3
2
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Jump on direct bit = 0
Jump on direct bit = 1 and clear
Jump indirect relative DPTR
Jump on accumulator = 0
Jump on accumulator 1= 0
Compare A, direct JNE relative
Compare A, immediate JNE relative
Compare reg, immediate JNE relative
Compare ind, immediate JNE relative
Decrement register, JNZ relative
Decrement direct byte, JNZ relative
JNZ rel
CJNE A, direct, rel
CJNE A, #d, rel
CJNE Rn, #d, rel
CJNE @Ri, #d, rel
DJNZ Rn, rel
DJNZ direct, rel
B4h
B8h-BFh
B6h,B7h
D8h-DFh
D5h
CPL A
SWAP A
RL A
RLC A
RR A
RRC A
Miscellaneous Instruction
NOP No operation
1
1
00h,A5h
33h
03h
13h
Rn:
@Ri:
Any of the register R0 to R7
Indirect addressing using Register R0 or R1
Rotate A right through carry
#data: immediate Data provided with Instruction
#data16: Immediate data included with instruction
bit:
rel:
address at the bit level
relative address to Program counter from +127 to –128
Addr11: 11-bit address range
Addr16: 16-bit address range
#d:
Immediate Data supplied with instruction
_______________________________________________________________________________________________
www.ramtron.com page 6 of 55
VMX51C900
Special Function Registers (SFR)
Addresses 80h to FFh of the SFR address space can be accessed in direct addressing mode only. The following table
lists the VMX51C900 special function registers.
TABLE 6: SPECIAL FUNCTION REGISTERS (SFR)
Reset
read
Value
SFR
Register
SFR
Adrs
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P0
SP
DPL
DPH
Reserved
PCON
TCON
TMOD
TL0
80h
81h
82h
83h
84h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Fh
A0h
A3h
A4h
A8h
A9h
AAh
ACh
B0h
B3h
B8h
B9h
BFh
C8h
CAh
CBh
CCh
CDh
D0h
D3h
D8h
DFh
E0h
E1h
E2h
E3h
E4h
E5h
E6h
E7h
F0h
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
11111111b
00000111b
00000000b
00000000b
10000100b
00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
11111111b
10010111b
00000000b
10000000b
00000000b
00000000b
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SMOD
TF1
GATE1
-
-
-
GF1
IE1
GATE0
GF0
IT1
C/T0
-
-
-
-
PDOWN
IE0
T0M1
-
IDLE
IT0
T0M0
-
-
-
-
-
ADCDATA0
P1.0
WDTKEY0
RI
TR1
C/T1
-
-
-
-
TF0
T1M1
-
-
-
-
ADCCLK1
ADCDATA5
P1.5
WDTKEY5
SM2
TR0
T1M0
-
-
-
-
-
-
-
-
-
-
-
-
TL1
TH0
TH1
-
-
-
ADCCTRL
ADCDATA
P1
WDTKEY
SCON
SBUF
P0IOCTRL
P1IOCTRL
P2IOCTRL
P3IOCTRL
WDTCTRL
P2
PWMACTRL
PWMA
IEN0
ADCEND
ADCDATA7
P1.7
WDTKEY7
SM0
ADCCONT
ADCDATA6
P1.6
WDTKEY6
SM1
-
LCDSEG7
PWMBE
ADCCLK0
ADCDATA4 ADCDATA3
P1.4
WDTKEY4
REN
ADCCH1
ADCCH0
ADCDATA2
P1.2
WDTKEY2
RB8
-
LCDSEG11
-
ADCDATA1
P1.1
WDTKEY1
TI
P1.3
WDTKEY3
TB8
-
-
-
-
-
-
LCDSEG10
LCDSEG12
LCDSEG13
LCDSEG6
LCDSEG8
LCDSEG9
PWMAE
LCDCOM2
LCDSEG3
ADCIEN3
WDTE
P2.7
LCDSEG2
ADCIEN2
LCDSEG1
ADCIEN1
WDTCLR
P2.5
LCDSEG0
ADCIEN0
LCDCOM3
LCDCOM1
-
WDTPS1
P2.1
PWMACK1 PWMACK0 00000000b
NPA.1
ET0
-
-
NP4.1
P3.1
PWMB.1
PT0
LCDCOM0 00000000b
-
-
-
00000000b
00000000b
11111111b
-
-
-
P2.3
-
PWMA.0
ET1
ADCIE
ADCIF
PWMD4.0
P3.3
PWMB.3
PT1
WDTPS2
P2.2
WDTPS0
P2.0
P2.6
-
PWMA.3
P2.4
-
PWMA.1
-
-
-
PWMA.4
PWMA.2
ET2
NPA.2
EX1
NPA.0
EX0
00000000b
00000000b
00000000b
00000000b
10101100b
11111111b
00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000001b
EA
-
-
-
-
-
ES
-
-
IEN1
IF1
PWMD4
P3
PWMB
IP
-
-
-
-
-
-
PWMD4.4
P3.7
PWMB.7
PWMD4.3
P3.6
PWMB.6
PWMD4.2
P3.5
PWMB.5
PT2
PWMD4.1
P3.4
PWMB.4
NP4.2
P3.2
PWMB.2
PX1
NP4.0
P3.0
PWMB.0
PX0
-
-
-
-
-
PS
-
-
IP1
-
-
ADCIP
-
EXEN2
-
-
-
-
-
-
SYSCON
T2CON
RCAP2L
RCAP2H
TL2
TH2
PSW
PWMBCTRL
P4
LCDCTRL
ACC
LCDBUF0
LCDBUF1
LCDBUF2
LCDBUF3
LCDBUF4
LCDBUF5
LCDBUF6
B
WDR
TF2
-
-
-
ALEI
CP/RL2
EXF2
RCLK
TCLK
TR2
C/T2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CY
-
-
AC
-
-
F0
-
-
RS1
RS0
OV
-
P
-
-
-
-
P4.3
-
PWMBRES PWMBCK1 PWMBCK0 00000000b
P4.2
LCDCLK2
P4.1
LCDCLK1
P4.0
LCDCLK0
00001111b
00000000b
11100000b
11100001b
11100010b
11100011b
11100100b
11100101b
11100110b
1100111b
LCDON
LCDEN
LCDPRI
-
-
-
-
-
-
-
-
SEG0_COM3
SEG0_COM2
SEG0_COM1
SEG0_COM0
SEG1_COM3
SEG1_COM2
SEG1_COM1
SEG1_COM0
SEG2_COM3
SEG4_COM3
SEG6_COM3
SEG8_COM3
SEG10_COM3
SEG12_COM3
SEG2_COM2
SEG4_COM2
SEG6_COM2
SEG8_COM2
SEG10_COM2
SEG12_COM2
SEG2_COM1
SEG4_COM1
SEG6_COM1
SEG8_COM1
SEG10_COM1
SEG12_COM1
SEG2_COM0
SEG4_COM0
SEG6_COM0
SEG8_COM0
SEG10_COM0
SEG12_COM0
SEG3_COM3
SEG5_COM3
SEG7_COM3
SEG9_COM3
SEG11_COM3
SEG13_COM3
SEG3_COM2
SEG5_COM2
SEG7_COM2
SEG9_COM2
SEG11_COM2
SEG13_COM2
SEG3_COM1
SEG5_COM1
SEG7_COM1
SEG9_COM1
SEG11_COM1
SEG13_COM1
SEG3_COM0
SEG5_COM0
SEG7_COM0
SEG9_COM0
SEG11_COM0
SEG13_COM0
-
-
-
-
-
-
-
-
00000000b
______________________________________________________________________________________________
www.ramtron.com page 7 of 55
VMX51C900
VMX51C900 Program Memory
RS1
RS0
Active Bank
Address
00h-07h
08h-0Fh
10h-17h
18-1Fh
0
0
1
1
0
1
0
1
0
1
2
3
The VMX51C900 includes 8KB of on-chip Program
Flash memory which can be programmed using a
parallel programmer.
The System Control Register
Data Pointer
System control is enabled by the SYSCON register.
The SYSCON register is used to monitor whether the
system has been reset due to overflow of the
watchdog timer and to inhibit activity on the ALE pin
when the VMX51C900 executes code from the internal
program memory.
The VMX51C900 has one 16-bit data pointer. The
DPTR is accessed through two SFR addresses: DPL is
located at address 82h and DPH is located at address
83h.
TABLE 7: SYSTEM CONTROL REGISTER (SYSCON) – SFR BFH
Data Memory
7
6
5
4
3
2
1
0
The VMX51C900 includes 256 bytes of RAM
configured as the standard internal memory structure
of a 8052.
WDR
Unused
ALEI
Bit
Mnemonic Description
7
WDR
This is the Watchdog Timer reset bit. It will
be set to 1 when the reset signal generated
by WDT overflows.
FIGURE 1: VMX51C900 DATA MEMORY STRUCTURE
FF
FF
Upper 128 bytes
(Can only be accessed in indirect
addressing mode)
SFR
(Can only be accessed in direct
addressing mode)
6:1
0
Unused
ALEI
-
80
7F
ALE output inhibit bit, which is used to
reduce EMI.
Lower 128 bytes
(Can be accessed in indirect and
direct addressing mode)
80
00
Lower 128 Bytes (00h to 7Fh, Bank 0 & Bank 1)
Reduced EMI Function
The lower 128 bytes of data memory (from 00h to 7Fh)
is summarized as follows:
The VMX51C900 can be set up to reduce EMI
(electromagnetic interference) emissions by setting bit
0 (ALEI) of the SYSCON register to 1. This function will
inhibit the Fosc/6Hz clock signal output on the ALE pin.
o
o
Address range 00h to 7Fh can be accessed in
direct and indirect addressing modes
Address range 00h to 1Fh includes the R0-R7
register area
Program Status Word Register
o
o
Address range 20h to 2Fh is bit addressable
Address range 30h to 7Fh is not bit
addressable and can be used as general-
purpose storage
The PSW register is a bit addressable register that
contains the status flags (CY, AC, OV, P), user flag
(F0) and register bank select bits (RS1, RS0) of the
8051 processor.
Upper 128 Bytes (80h to FFh, Bank 2 & Bank 3)
TABLE 8: PROGRAM STATUS WORD REGISTER (PSW) - SFR DOH
The upper 128 bytes of the data memory (80h to FFh)
can be accessed using indirect addressing or by using
bank mapping in direct addressing mode.
7
CY
6
AC
5
F0
4
RS1
3
RS0
2
OV
1
-
0
P
Bit
Mnemonic Description
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
-
Carry Bit
Auxiliary Carry Bit from bit 3 to 4.
User definer flag
R0-R7 Registers bank select bit 0
R0-R7 Registers bank select bit 1
Overflow flag
Stack Pointer
The stack pointer (SP) register is located at SFR
address 81h. The SP value corresponds to the
address of the last data item written to the processor
stack. When data is put on the stack, the SP value is
incremented.
-
P
Parity flag
______________________________________________________________________________________________
www.ramtron.com page 8 of 55
VMX51C900
The SP’s default value at reset is 07h. The SP can be
programmed to point anywhere in the 00h to FFh RAM
memory range.
exit a Power Down mode is to perform a hardware
reset.
The SMOD bit of the PCON register controls the
oscillator divisor applied to Timer1 when used as a
baud rate generator for the UART. Setting this bit to 1
doubles the frequency of the UART’s baud rate
generator.
Each time a function call is performed or an interrupt is
serviced, the 16-bit return address (2 bytes) is stored
onto the stack. Data can also be placed manually on
the stack by using the PUSH and POP instructions.
Description of Power Control Register
The VMX51C900 provides two power saving modes:
Idle and Power Down, which are controlled by the
PDOWN and IDLE bits of the PCON register at
address 87h.
TABLE 9: POWER CONTROL REGISTER (PCON) - SFR 87H
7
6:4
3
2
1
0
SMOD
GF1
GF0
PDOWN
IDLE
Bit
Mnemonic Description
7
SMOD
1: Double the baud rate of the serial port
frequency that was generated by Timer 1.
0: Normal serial port baud rate generated by
Timer 1.
6
5
4
3
2
1
0
GF1
GF0
PDOWN
IDLE
General Purpose Flag
General Purpose Flag
Power Down mode control bit
Idle mode control bit
The Idle mode is useful in applications that require
reduced power consumption. When in Idle mode, the
processor clock is stopped, but the peripherals
continue running. The contents of the RAM, I/O state
and SFR registers are maintained and the timer,
external interrupts and UARTs are left operational.
Since only the processor clock stops, normal operating
power will be cut to about half. The processor will
awaken if an external event triggering an interrupt
occurs.
In Power Down mode, the VMX51C900 oscillator and
peripherals, including the watchdog timer, are
disabled. The contents of the RAM and the SFR
registers, however, are maintained.
When in Power Down mode, the VMX51C900 current
consumption drops to about 100uA. The only way to
______________________________________________________________________________________________
www.ramtron.com page 9 of 55
VMX51C900
Each I/O may be used independently as a logical
input or output. When configured as an input, the
corresponding bit register must be high. This would
correspond to #Q=0 in the above figure.
Input/Output Ports
The VMX51C900 has 36 I/O lines grouped into four 8-
bit and one 4-bit I/O port(s). These I/Os can be
individually configured as inputs or outputs.
The transistor would be off (open-circuited) and the
current would flow from VCC to the pin, generating a
logical high at the output.
With the exception of the P0 I/Os, which are of the
open drain type, each I/O consists of a transistor
connected to ground and a dynamic pull-up resistor
comprised of a combination of transistors.
The VMX51C900 I/O ports P1, P2, P3 and P4 are
considered “quasi bi-directional” because of the pull-up
resistance (even though the I/O’s are configured as
inputs). As such, a small current is likely to flow from
the VMX51C900 I/O’s pull-up resistors to the driving
circuit when the inputs are driven low.
Writing a 0 into a given I/O port bit register will activate
the transistor connected to ground. This will bring the
I/O to a logic low level.
Writing a 1 into a given I/O port bit register deactivates
the transistor between the pin and ground. In this case,
an internal weak pull-up resistor will bring the pin to a
high level (except on Port 0 which is open-drain
based).
Structure of Port 0
The internal structure of P0 is shown in the following
figure. As opposed to the other ports, P0 is truly bi-
directional. In other words, when used as an input, it is
considered to be in a floating logical state (high
impedance state). This arises from the absence of the
internal pull-up resistance. The pull-up resistance is
actually replaced by a transistor that is only used when
the port is configured to access the external
memory/data bus (EA=0).
To use a given I/O as an input, a 1 must be written into
its associated port register bit. By default, upon reset
all the I/Os are configured as inputs. Note that the
VMX51C900 I/O ports are not designed to source
current.
Structure of the P1, P2, P3 and P4 Ports
When used as an I/O port, P0 acts as an open drain
port and the use of an external pull-up resistor is likely
to be required for some applications.
The following figure describes the general structure of
the P1, P2, P3 and P4 port I/Os. For these ports, the
output stage consists of transistor X1 and additional
transistors configured as pull-ups. Note that the figure
below does not show the intermediary logic that
connects the register output with the output stage
because this logic varies with the auxiliary function of
each port.
FIGURE 3: PORT P0’S PARTICULAR STRUCTURE
Address A0/A7
Read Register
Control
FIGURE 2: GENERAL STRUCTURE OF THE OUTPUT STAGE OF P1, P2, P3 AND P4
Vcc
Read Register
Q
Internal Bus
Vcc
IC Pin
D Flip-Flop
X1
Write to
Register
Q
Pull-up
Network
Q
Internal Bus
IC Pin
D Flip-Flop
Read Pin
Write to
Register
X1
Q
Read Pin
Alternately, P0 can be configured as the low byte (AD0
through AD7) of the address/data bus when the
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VMX51C900
VMX51C900 EA pin is held at 0V during reset, or
when a MOVX instruction is executed.
Port P0 and P2 as Address and Data Bus
The output stage may receive data from two sources:
The P0 register located at address 80h controls the
individual pin direction when configured as an I/O. The
·
·
The outputs of register P0 or the bus address
itself multiplexed with the data bus for P0
P0 register is bit-addressable.
TABLE 10: PORT 0 REGISTER (P0) - SFR 80H
7
6
5
4
3
2
1
0
The outputs of the P2 register or the high byte
(A8 through A15) of the bus address for the P2
port
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
Bit
7
6
5
4
3
2
1
0
Mnemonic Description
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
For each bit of the P0 register correspond
to an I/O line:
FIGURE 4: P2 PORT STRUCTURE
Read Register
0: Output transistor pull the line to 0V
1: The output transistor is blocked so the
pull-up brings the I/O to 5V.
Vcc
Address
Pull-up
Network
Q
Q
Internal Bus
IC Pin
D Flip-Flop
Write to
Register
X1
Control
Port 2
Port P2 is very similar to Port1 and Port3, the
difference being that the alternate function of P2 is to
act as the upper address bus (A8-A15) when the EA
line of the VMX51C900 is held low at reset time or
when a MOVX instruction is executed.
Read Pin
When the ports are used as an address or data bus,
the special function registers P0 and P2 are
disconnected from the output stage, the 8 bits of the
P0 register are forced to 1 and the contents of the P2
register remains constant.
Like the P1, P2 and P3 registers, the P2 register is bit-
addressable.
TABLE 11: PORT 2 REGISTER (P2) - SFR A0H
Port 1
7
6
5
4
3
2
1
0
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
The P1 register controls the direction of the Port 1 I/O
pins. Writing a 1 to the corresponding bit configures
the port as an output. This presents a logic 1 to the
corresponding I/O pin or allows the I/O pin to be used
as an input. Writing a 0 activates the output “pull-
down” transistor, which will force the corresponding I/O
line to a logic low.
Bit
7
6
5
4
3
2
1
0
Mnemonic Description
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
For each bit of the P2 register correspond
to an I/O line:
0: Output transistor pull the line to 0V
1: The output transistor is blocked so the
pull-up brings the I/O to 5V.
TABLE 12: PORT 1 REGISTER (P2) - SFR 90H
7
6
5
4
3
2
1
0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
Bit
7
6
5
4
3
2
1
0
Mnemonic Description
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
For each bit of the P1 register correspond
to an I/O line:
0: Output transistor pulls the line to 0V
1: The output transistor is blocked so the
pull-up brings the I/O to 5V
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VMX51C900
TABLE 13: PORT 3 REGISTER (P3) - SFR B0H
Auxiliary Port 1 Functions
7
6
5
4
3
2
1
0
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
The Port 1 I/O pins are shared with the PWMA &
PWMB outputs, the Timer2 EXT and the T2 input (see
following table).
Bit
7
6
5
4
3
2
1
0
Mnemonic Description
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
Each bit of the P3 register corresponds to
an I/O line:
Pin
Mnemonic Function
0: Output transistor pulls the line to 0V
1: Output transistor is blocked so the pull-
up brings the I/O to 5V
P1.0 T2
P1.1 T2EX
Timer 2 Counter input
Timer2 Auxiliary input
P1.2
PWMA output
To configure P3 pins as inputs or use
alternate P3 functions, the corresponding
bit must be set to 1
PWMA
P1.3
P1.4
P1.5 PWMB
P1.6
PWMB output
The following table describes the auxiliary functions of
the Port 3 I/O pins.
P1.7
TABLE 14: P3 AUXILIARY FUNCTION TABLE
Pin
Mnemonic
Function
P3.0
RXD
Serial Port:
Receive data in asynchronous mode
Input and output data in synchronous
mode
Auxiliary P3 Port Functions
P3.1
TXD
Serial Port:
Transmit data in asynchronous mode
Output clock value in synchronous mode
External Interrupt 0
Timer 0 Control Input
External Interrupt 1
The Port 3 I/O pins are shared with the UART
interface, the INT0 and INT1 interrupts, the Timer0 and
Timer1 inputs and the #WR and #RD lines when
external memory access is performed.
P3.2
P3.3
INT0
INT1
Timer 1 Control Input
P3.4
P3.5
P3.6
T0
T1
Timer 0 Counter Input
Timer 1 Counter Input
Write signal for external memory
To maintain the correct line functionality in auxiliary
function mode, the P3 register Q output must be held
stable at 1. This is achieved by setting the
corresponding P3 bit to 1.
WR
RD
P3.7
Read signal for external memory
FIGURE 5: P3 PORT STRUCTURE
Auxiliary
Function: Output
Read Register
Vcc
IC Pin
X1
Q
Internal Bus
D Flip-Flop
Write to
Register
Q
Read Pin
Auxiliary
Function: Input
The P3 register controls the P3 pin operation.
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VMX51C900
TABLE 16: LIST OF INSTRUCTIONS THAT READ AND MODIFY THE PORT USING REGISTER
VALUES
Port 4
Instruction Function
Port 4 consists of four pins and its SFR (P4) address is
0D8H.
ANL
ORL
XRL
JBC
CPL
INC
Logical AND ex: ANL P0, A
Logical OR ex: ORL P2, #01110000B
Exclusive OR ex: XRL P1, A
Jump if the bit of the port is set to 0
Complement one bit of the port
Increment the port register by 1
Decrement the port register by 1
Decrement by 1 and jump if the result
is not equal to 0
TABLE 15: PORT 4 (P4) - SFR D8H
7
6
5
4
3
2
1
0
Unused
P4.3
P4.2
P4.1
P4.0
Bit
Mnemonic Description
DEC
DJNZ
7
6
5
4
3
2
1
0
Unused
Unused
Unused
Unused
P4.3
P4.2
P4.1
P4.0
-
-
-
-
MOV P.,C
CLR P.x
Copy the held bit C to the port
Set the port bit to 0
Used to output the setting to pins P4.3,
P4.2, P4.1, P4.0 respectively.
SETB P.x
Set the port bit to 1
Software Particulars Concerning the Ports
Port Operation Timing
Writing to a Port (Output)
Some instructions allow the user to read the logic state
of the output pin, while others allow the user to read
the contents of the associated port register. These
instructions are called read-modify-write instructions. A
list of these instructions may be found in the table
below.
When an operation results in a modification of the
contents in a port register, the new value is placed at
the output of the D flip-flop during the last machine
cycle that the instruction needed to execute.
Upon execution of these instructions, the contents of
the port register (at least 1 bit) is modified. The other
read instructions take the present state of the input into
account. For example, the instruction ANL P3, #01h
obtains the value in the P3 register; performs the
desired logic operation with the constant 01h and
recopies the result into the P3 register. When users
want to take the present state of the inputs into
account, they must first read these states and perform
an AND operation of the value read and the constant
(see following example).
Reading a Port (Input)
In order to be sampled, the signal duration present on
the I/O inputs must be longer than Fosc/12.
MOV A, P3; State of the inputs in the accumulator
ANL A, #01; AND operation between P3 and 01h
When the port is used as an output, the register
contains information on the state of the output pins.
Measuring the state of an output directly on the pin is
inaccurate because the electrical level depends mostly
on the type of charge that is applied to it. The functions
shown below take the value of the register rather than
that of the pin.
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VMX51C900
I/O Port Drive Capability
The maximum allowable continuous current that the
device can sink on an I/O port is defined in the
following table.
Maximum sink current on one given I/O
Maximum total sink current for P0
10mA
26mA
Maximum total sink current for P1, 2, 3,4 15mA
Maximum total sink current on all I/O 71mA
It is not recommended to exceed the sink current
outlined in the above table. Doing so will likely result in
the low-level output voltage exceeding device
specifications and in turn affect device reliability.
The VMX51C900 I/O ports are not designed to source
current.
Timers
The VMX51C900 includes three 16-bit timers: Timer0,
Timer1 and Timer2.
The timers can operate in two modes:
·
·
Event counting mode
Timer mode
When operating in event counting mode, the counter is
incremented each time an external event, such as a
transition in the logical state of the timer input (T0, T1,
T2 input), is detected. When operating in timer mode,
the counter is incremented by the microcontroller’s
system clock (Fosc/12) or by a divided version of it.
Timer0 and Timer1
Timers0 and 1 have four modes of operation. These
modes allow the user to change the size of the
counting register or to authorize an automatic reload
when encountering a specific value. Timer1 can also
be used as a baud rate generator to generate
communication frequencies for the serial interface.
Timer0 and Timer1 are configured by the TMOD and
TCON registers.
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VMX51C900
TABLE 17: TIMER MODE CONTROL REGISTER (TMOD) – SFR 89H
7
6
C/T1
5
T1M1
4
T1M0
3
2
C/T0
1
T0M1
0
T0M0
GATE1
GATE0
Bit
Mnemonic Description
7
GATE1
C/T1
1: Enables external gate control (pin INT1 for
Counter 1). When INT1 is high, and TRx bit is
set (see TCON register), a counter is
incremented every falling edge on the T1IN
input pin
Selects timer or counter operation (Timer 1).
1 = A counter operation is performed
0 = The corresponding register will function
as a timer
6
Selects the operating mode of
Timer/Counter 1
5
4
3
T1M1
T1M0
GATE0
If set, enables external gate control (pin INT0
for Counter 0). When INT0 is high, and TRx
bit is set (see TCON register), a counter is
incremented every falling edge on the T0IN
input pin
Selects timer or counter operation (Timer 0).
1 = A counter operation is performed
0 = The corresponding register will function
as a timer
2
C/T0
Selects the operating mode of
Timer/Counter 0
1
0
T0M1
T0M0
The table below summarizes the four operating modes
of timers 0 and 1. The timer operating mode is
selected by the T1M1/T1M0 and T0M1/T0M0 bits of
the TMOD register.
TABLE 18: TIMER/COUNTER MODE DESCRIPTION SUMMARY
M1 M0 Mode Function
0
0
1
0
1
0
Mode 0
Mode 1
Mode 2
13-bit Counter
16-bit Counter
8-bit auto-reload Counter/Timer. The reload
value is kept in TH0 or TH1, while TL0 or TL1
is incremented every machine cycle. When TLx
overflows, the value of THx is copied to TLx.
If Timer 1 M1 and M0 bits are set to 1, Timer 1
stops.
1
1
Mode 3
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VMX51C900
Timer0 /Timer1 Counter/Timer Functions
TABLE 19: TIMER 0 AND 1 CONTROL REGISTER (TCON) –SFR 88H
7
TF1
6
TR1
5
TF0
4
TR0
3
IE1
2
IT1
1
IE0
0
IT0
Timing Function
When either Timer 0 or 1 is configured to operate as a
timer, its value is automatically incremented at every
system cycle. In the event of an overflow, the overflow
flag is set and the counter is set to zero. The overflow
flags (TF0 and TF1) are located in the TCON register.
Bit
7
Mnemonic Description
TF1
Timer 1 Overflow Flag. Set by hardware on
Timer/Counter overflow. Cleared by
hardware on Timer/Counter overflow.
Cleared by hardware when processor
vectors to interrupt routine.
6
TR1
TF0
Timer 1 Run Control Bit. Set/cleared by
software to turn Timer/Counter on or off.
Timer 0 Overflow Flag. Set by hardware on
Timer/Counter overflow. Cleared by
hardware when processor vectors to
interrupt routine.
Timer 0 Run Control Bit. Set/cleared by
software to turn Timer/Counter on or off.
Interrupt Edge Flag. Set by hardware when
external interrupt edge is detected. Cleared
when interrupt processed.
Interrupt 1 Type Control Bit. Set/cleared by
software to specify falling edge/low level
triggered external interrupts.
Interrupt 0 Edge Flag. Set by hardware
when external interrupt edge is detected.
Cleared when interrupt processed.
Interrupt 0 Type control bit. Set/cleared by
software to specify falling edge/low level
triggered external interrupts.
The TR0 and TR1 bits of the TCON register gate the
corresponding timer operation. . In order for the timer
to run, the corresponding TRx bit must be set to 1.
5
The IT0 and IT1 bits of the TCON register control the
event that will trigger an external interrupt as follows:
4
3
TR0
IE1
IT0 = 0: The INT0, if enabled, occurs if a low level is
present on P3.2
2
1
0
IT1
IE0
IT0
IT0 = 1: The INT0, if enabled, occurs if a high to low
transition is detected on P3.2
IT1 = 0: The INT1, if enabled, occurs if a low level is
present on P3.3
IT1 = 1: The INT1, if enabled, occurs if a high to low
transition is detected on P3.3
Counting Function
The IE0 and IE1 bits of the TCON register are external
flags which indicate that a transition has been detected
on the INT0 and INT1 interrupt pins, respectively.
When operating as a counter, the timer register is
incremented at every falling edge of the T0 and T1
signals located at the input of the timers.
If the external interrupt is configured as edge sensitive,
the corresponding IE0 and IE1 flags are automatically
cleared when the corresponding interrupt is serviced.
When the sampling circuit detects a high immediately
followed by a low in the following machine cycle, the
counter is incremented. Two system cycles are
required to detect and record an event. In order to be
properly sampled, the counting frequency should be
reduced by a factor of 24 (24 times less than the
oscillator’s frequency).
If the external interrupt is configured as level sensitive,
the corresponding flag must be cleared by the
software.
Timer0/Timer1 Operating Modes
The user may change the operating mode via the M1
and M0 bits of the TMOD SFR.
Mode 0
A schematic representation of this mode of operation is
presented in the figure below. In Mode 0, the Timer
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VMX51C900
operates as 13-bit counter made up of 5 LSBs from the
TLx register and the 8 upper bits coming from the THx
register. When an overflow causes the value of the
register to roll over to 0, the TFx interrupt signal goes
to 1. The count value is validated as soon as TRx goes
to 1 and the GATE bit is 0, or when INTx is 1.
FIGURE 7: TIMER/COUNTER 1 MODE 2: 8-BIT AUTOMATIC RELOAD
Fosc
÷12
C/T1 / C/T0 = 1
C/T1 / C/T0 = 1
TL1 / TL0
0
1
0
7
Control
T1 / T0 Pin
Reload
FIGURE 6: TIMER/COUNTER 1 MODE 0: 13-BIT COUNTER
0
7
TH1 / TH0
TF1 / TF0
TR1 / TR0
GATE1 / GATE0
÷12
Fosc
INT
TL1 / TL0
0
1
C/T1 / C/T0 =0
C/T1 / CT0 =1
INT1 / INT0 pin
0
4
7
CLK
Mode 0
Mode 1
Control
T1/T0 pin
TR1/TR0
Mode 3
In Mode 3, Timer 1 is blocked as if its’ control bit, TR1,
was set to 0. In this mode, Timer 0’s registers TL0 and
TH0 are configured as two separate 8-bit counters.
The TL0 counter uses Timer 0’s control bits (C/T,
GATE, TR0, INT0, TF0), the TH0 counter is held in
Timer Mode (counting machine cycles) and gains
control over TR1 and TF1 from Timer 1. At this point,
TH0 controls the Timer 1 interrupt.
TH1 / TH0
GATE1 /
GATE0
0
7
INT1 /
INT0 pin
TF1 /
TF0
INT
Mode 1
Mode 1 is almost identical to Mode 0, with the
difference being that in Mode 1, the counter/timer uses
the full 16-bits of the Timer.
FIGURE 8: TIMER/COUNTER 0 MODE 3
TH0
0
7
CLK
Mode 2
Control
In this Mode, the register of the Timer is configured as
an 8-bit auto-re-loadable Counter/Timer. In Mode 2,
the TLx is used as the counter. In the event of a
counter overflow, the TFx flag is set to 1 and the value
contained in THx, which is preset by software, is
reloaded into the TLx counter. The value of THx
remains unchanged.
TF1
INTERRUPT
TR1
Fosc
÷12
TL0
0
1
C/T =0
C/T =1
0
7
CLK
Control
T0PIN
TF0
INTERRUPT
TR0
GATE
INT0 PIN
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VMX51C900
Capture/Reload Select.
0
Timer 2
1: Capture of Timer 2 value into RCAP2H,
RCAP2L is performed if EXEN2=1 and a
negative transitions occurs on the T2EX
pin. The capture mode requires RCLK and
TCLK to be 0.
CP/RL2
Timer 2 of the VMX51C900 is a 16-bit Timer/Counter
and is similar to Timers 0 and 1 in that it can operate
either as an event counter or as a timer. This is
controlled by the C/T2 bit in the T2CON special
function register. Timer 2 has three operating modes -
Auto-Load, Capture and Baud Rate Generator. These
modes are selected via the T2CON SFR The following
table describes T2CON special function register bits.
0: Auto-reload reloads will occur either with
Timer 2 overflows or negative transitions at
T2EX when EXEN2=1. When either RCK
=1 or TCLK =1, this bit is ignored and the
timer is forced to auto-reload on Timer 2
overflow.
The Timer 2 mode selection bits and their function are
described in the following table.
TABLE 20: TIMER 2 CONTROL REGISTER (T2CON) –SFR C8H
7
TF2
6
EXF2
5
4
3
2
TR2
1
C/T2
0
RCLK
TCLK
EXEN2
CP/RL2
TABLE 21: TIMER 2 MODE SELECTION BITS
CP/RL2
0
RCLK + TCLK
0
TR2 MODE
Bit
7
Mnemonic Description
Timer 2 Overflow Flag: Set by an overflow
of Timer 2 and must be cleared by
software. TF2 will not be set when either
RCLK =1 or TCLK =1.
TF2
16-bit Auto-
1
1
Reload Mode
16-bit Capture
Mode
0
1
Timer 2 external flag change in state occurs
when either a capture or reload is caused
by a negative transition on T2EX and
EXEN2=1. When Timer 2 is enabled,
EXF=1 will cause the CPU to Vector to the
Timer 2 interrupt routine. Note that EXF2
must be cleared by software.
6
EXF2
Baud Rate
Generator Mode
Timer 2 stops
1
X
X
1
0
X
The details of each mode are described below.
Serial Port Receive Clock Source.
1: Causes Serial Port to use Timer 2
overflow pulses for its receive clock in
modes 1 and 3.
5
4
3
RCLK
TCLK
Timer 2 Capture Mode
In Capture Mode, the EXEN2 bit of the T2CON register
controls whether an external transition on the T2EX pin
will trigger capture of the timer value.
0: Causes Timer 1 overflow to be used for
the Serial Port receive clock.
Serial Port Transmit Clock.
1: Causes Serial Port to use Timer 2
overflow pulses for its transmit clock in
modes 1 and 3.
When EXEN2 = 0, Timer 2 acts as a 16-bit timer or
counter, which, upon overflowing, will set the TF2 bit
(Timer 2 overflow bit). This overflow can be used to
generate an interrupt
0: Causes Timer 1 overflow to be used for
the Serial Port transmit clock.
Timer 2 External Mode Enable.
1: Allows a capture or reload to occur as a
result of a negative transition on T2EX if
Timer 2 is not being used to clock the Serial
Port.
EXEN2
FIGURE 9: TIMER 2 IN CAPTURE MODE
FOSC
÷12
0
1
TIMER
TL2
TH2
0: Causes Timer 2 to ignore events at
T2EX.
0
0
7
7
0
0
7
7
C/T2
COUNTER
Start/Stop Control for Timer 2.
1: Start Timer 2
2
1
TR2
T2 pin
RCAP2L
RCAP2H
0: Stop Timer 2
TR2
Timer or Counter Select (Timer 2)
1: External event counter falling edge
triggered.
TF2
C/T2
T2EX pin
EXF2
0: Internal Timer (OSC/12)
EXEN2
Timer 2
Interrupt
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VMX51C900
When EXEN2 = 1, the above still applies, however, in
addition, it is possible to allow a 1 to 0 transition at the
T2EX input to cause the current value stored in the
Timer 2 registers (TL2 and TH2) to be captured into
the RCAP2L and RCAP2H registers. Furthermore, the
transition at T2EX causes bit EXF2 in T2CON to be
set, and EXF2, like TF2, can generate an interrupt.
Note that both EXF2 and TF2 share the same interrupt
vector.
Timer 2 Auto-Reload Mode
In this mode, there are also two options controlled by
the EXEN2 bit in the T2CON register.
If EXEN2 = 0, when Timer 2 rolls over, it not only sets
TF2, but also causes the Timer 2 registers to be
reloaded with the 16-bit value in the RCAP2L and
RCAP2H registers previously initialised. In this mode,
Timer 2 can be used as a baud rate generator source
for the serial port.
If EXEN2=1, Timer 2 still performs the above
operation, however, additionally, a 1 to 0 transition at
the external T2EX input will also trigger an anticipated
reload of Timer 2 with the value stored in RCAP2L,
RCAP2H and set EXF2.
FIGURE 10: TIMER 2 IN AUTO-RELOAD MODE
FOSC
÷12
0
1
TIMER
TL2
TH2
0
0
7
7
0
0
7
7
C/T2
COUNTER
T2 pin
RCAP2L
RCAP2H
TR2
TF2
T2EX pin
EXF2
EXEN2
Timer 2
Interrupt
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VMX51C900
UART Control Register
Timer 2 Baud Rate Generator Mode
The SCON (serial port control) register contains
control and status information, and includes the 9th
data bit for transmit/receive (TB8/RB8 if required),
mode selection bits and serial port interrupt bits (TI
and RI).
Timer 2 can be configured as a UART baud rate
generator. This mode is activated when RCLK is set to
1 and/or TCLK is set to 1. This mode will be described
in the serial port section.
FIGURE 11: TIMER 2 IN AUTOMATIC BAUD GENERATOR MODE
TABLE 22: SERIAL PORT CONTROL REGISTER (SCON) – SFR 98H
7
SM0
6
SM1
5
SM2
4
REN
3
TB8
2
RB8
1
TI
0
RI
FOSC
÷2
0
1
TIMER
TL2
TH2
0
0
7
0
0
7
7
Bit
Mnemonic Description
C/T2
7
SM0
SM1
SM2
Bit to select mode of operation (see table
below)
Bit to select mode of operation (see table
below)
Multiprocessor communication is possible
in Modes 2 and 3.
COUNTER
T2 pin
7
6
RCAP2L
RCAP2H
TR2
1
0
TX Clock
RX Clock
÷16
÷16
TCLK
1
0
5
0
1
Timer 1 Overflow
÷2
RCLK
SMOD
In Modes 2 or 3 if SM2 is set to 1, RI will
not be activated if the received 9th data bit
(RB8) is 0.
Timer
Interrupt
Request
2
T2EX pin
EXF2
EXEN2
In Mode 1, if SM2 = 1 then RI will not be
activated if a valid stop bit was not
received.
Serial Reception Enable Bit
This bit must be set by software and
cleared by software.
UART Serial Port
4
REN
The serial port on the VMX51C900 can operate in full
duplex; in other words, it can transmit and receive data
simultaneously. Different communication speeds can
be configured for transmission and reception by
assigning one timer for transmission and another for
reception.
1: Serial reception enabled
0: Serial reception disabled
9th data bit transmitted in Modes 2 and 3
This bit must be set by software and
cleared by software.
3
2
TB8
RB8
9th data bit received in Modes 2 and 3.
In Mode 1, if SM2 = 0, RB8 is the stop bit
that was received.
In Mode 0, this bit is not used.
This bit must be cleared by software.
Transmission Interrupt flag.
The VMX51C900 serial port includes a double
buffering feature, such that the serial port can begin
reception of a byte even if the processor has not
retrieved the last byte from the receive register.
However, if the previously received byte has not been
read by the time reception of the next byte is complete,
the byte present in the receive buffer will be lost.
1
0
TI
Automatically set to 1 when:
· The 8th bit has been sent in Mode 0.
· Automatically set to 1 when the stop bit
has been sent in the other modes.
This bit must be cleared by software.
Reception Interrupt flag
The SBUF register provides access to the transmit and
receive registers of the serial port. Reading from the
SBUF register will access the receive register, while a
write to the SBUF loads the transmit register.
RI
Automatically set to 1 when:
· The 8th bit has been received in Mode 0.
· Automatically set to 1 when the stop bit
has been sent in the other modes (see
SM2 exception).
This bit must be cleared by software.
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VMX51C900
TABLE 23: SERIAL PORT MODES OF OPERATION
UART Transmission in Mode 0
SM0
0
0
SM1
0
1
Mode
Description
Baud Rate
Fosc/12
Variable
Fosc/64 or
Fosc/32
0
1
2
Shift Register
8-bit UART
9-bit UART
Any instruction that uses SBUF as a destination
register may initiate a transmission. The “write to
SBUF” signal also loads a 1 into the 9 position of the
transmit shift register and informs the TX control block
to begin a transmission. The internal timing is such that
one full machine cycle will elapse between a write to
SBUF instruction and the activation of SEND.
1
0
th
1
1
3
9-bit UART
Variable
UART Operating Modes
The VMX51C900’s serial port can operate in four
modes. In all four modes, a transmission is initiated by
an instruction that uses the SBUF register as a
destination register. In Mode 0, reception is initiated by
setting RI to 0 and REN to 1. An incoming Start bit
initiates reception in the other modes, provided that
REN is set to 1. The following section describes the
four modes.
The SEND signal enables the output of the shift
register to the alternate output function line of P3.0 and
enables SHIFT CLOCK to the alternate output function
line of P3.1.
At every machine cycle in which SEND is active, the
contents of the transmit shift register are shifted to the
right by one position.
Zeros come in from the left as data bits shift out to the
right. The TX control block sends its final shift and de-
activates SEND while setting T1 after one condition is
fulfilled. When the MSB of the data byte is at the
output position of the shift register; the 1 that was
initially loaded into the 9th position is just to the left of
the MSB; and all positions to the left of that contain
zeros. Once these conditions are met, the de-
activation of SEND and the setting of T1 occurs at T1
of the 10th machine cycle after the “write to SBUF”
pulse.
UART Operation in Mode 0
In Mode 0, serial data exits and enters through the
RXD pin. TXD is used to output the shift clock. The
signal is composed of 8 data bits starting with the LSB.
The baud rate in this mode is 1/12 the oscillator
frequency.
FIGURE 12: SERIAL PORT MODE 0 BLOCK DIAGRAM
Internal Bus
1
Write to
SBUF
UART Reception in Mode 0
Q
S
D
SBUF
RXD P3.0
Shift
CLK
When REN and R1 are set to 1 and 0, respectively,
reception is initiated. The bits 11111110 are written to
the receive shift register at the end of the next machine
cycle by the RX control unit. In the following phase, the
RX control unit will activate RECEIVE.
ZERO DETECTOR
Shift
Clock
TXD P3.1
Shift
Start
TX Control Unit
TX Clock
Send
Fosc/12
TI
Serial Port
Interrupt
RI
RX Clock
Receive
RX Control Unit
The contents of the receive shift register are shifted
one position to the left at the end of every machine
cycle during which RECEIVE is active. The value that
comes in from the right is the value that was sampled
at the P3.0 pin.
RI
REN
Start Shift
1
1
1
1
1
1
1
0
RXD P3.0
Input Function
RXD P3.0
Shift Register
READ SBUF
SBUF
1’s are shifted out to the left as data bits are shifted in
from the right. The RX control block is flagged to do
one last shift and load SBUF when the 0 that was
initially loaded into the rightmost position arrives at the
leftmost position in the shift register.
Internal Bus
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VMX51C900
UART Operation in Mode 1
UART Transmission in Mode 1
Transmission in this mode is initiated by any
instruction that makes use of SBUF as a destination
register. The 9th bit position of the transmit shift register
is loaded by the “write to SBUF” signal. This event also
flags/informs the TX Control Unit that a transmission
has been requested.
In Mode 1 operation, 10 bits are transmitted (through
TXD) or received (through RXD). The transactions are
composed of: a Start bit (Low); 8 data bits (LSB first)
and one Stop bit (high). The reception is completed
once the Stop bit sets the RB8 flag in the SCON
register. Either Timer 1 or Timer 2 controls the baud
rate in this mode.
It is after the next rollover in the divide-by-16 counter
when transmission actually begins. It follows that the
bit times are synchronized to the divide-by-16 counter
and not to the “write to SBUF” signal.
The following diagram shows the serial port structure
when configured in Mode 1.
FIGURE 13: SERIAL PORT MODE 1 AND 3 BLOCK DIAGRAM
Internal Bus
When a transmission begins, it places the start bit at
TXD. Data transmission is activated one bit time later.
This activation enables the output bit of the transmit
shift register to TXD. One bit time after that, the first
shift pulse occurs.
1
Write to
SBUF
Timer 1
Overflow
Q
S
D
SBUF
TXD
In this Mode, zeros are clocked in from the left as data
bits are shifted out to the right. When the most
significant bit of the data byte is at the output position
of the shift register, the 1 that was initially loaded into
the 9th position is to the immediate left of the MSB, and
all positions to the left of that contain zeros. This
condition flags the TX Control Unit to shift one more
time.
CLK
Timer 2
Overflow
ZERO DETECTOR
÷2
0
1
Shift
Start
Data
SMOD
0
0
1
TX Control Unit
TCLK
TX Clock
÷16
Send
÷16
TI
1
RCLK
Serial Port
Interrupt
RX Clock
RI
Load
SBUF
RX Control Unit
1-0 Transition
Detector
Start
SHIFT
UART Reception in Mode 1
Bit
Detector
9-Bit Shift Register
Shift
RXD
A one to zero transition at pin RXD will initiate
reception. It is for this reason that RXD is sampled at a
rate of 16 multiplied by the baud rate that has been
established. When a transition is detected, 1FFh is
written into the input shift register and the divide-by-16
counter is immediately reset. The divide-by-16 counter
is reset in order to align its rollovers with the
boundaries of the incoming bit times.
LOAD SBUF
SBUF
READ SBUF
Internal Bus
In total, there are 16 states in the counter. During the
7th, 8th and 9th counter states of each bit time; the bit
detector samples the value of RXD. The accepted
value is the value that was seen in at least two of the
three samples. The purpose of doing this is for noise
rejection. If the value accepted during the first bit time
is not zero, the receive circuits are reset and the unit
goes back to searching for another one to zero
transition. All false start bits are rejected by doing this.
If the start bit is valid, it is shifted into the input shift
register, and the reception of the rest of the frame will
proceed.
For a receive operation, the data bits come in from the
right as 1’s shift out on the left. As soon as the start bit
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VMX51C900
arrives at the leftmost position in the shift register, (9-
bit register), it tells the UART’s receive controller block
to perform one last shift operation: to set RI and to load
SBUF and RB8. The signal to load SBUF and RB8,
and to set RI, will be generated if, and only if, the
following conditions are met at the time the final shift
pulse is generated:
FIGURE 14: SERIAL PORT MODE 2 BLOCK DIAGRAM
Internal Bus
1
Write to
SBUF
Q
S
D
SBUF
Fosc/2
÷2
TXD
o
o
Either SM2 = 0 or the received stop bit = 1
RI = 0
CLK
ZERO DETECTOR
0
1
If both conditions are met, the stop bit goes into RB8,
the 8 data bits go into SBUF, and RI is activated. If one
of these conditions is not met, the received frame is
completely lost. At this time, whether the above
conditions are met or not, the unit goes back to
searching for a one to zero transition in RXD.
Shift
Data
Send
Stop
Start
SMOD
TX Control Unit
TX Clock
÷16
TI
÷16
Serial Port
Interrupt
Sample
RI
RX Clock
Control
Load
SBUF
RX Control Unit
1-0 Transition
Detector
Start
SHIFT
UART Operation in Mode 2
Bit
Detector
9-Bit Shift Register
Shift
RXD
In Mode 2 a total of 11 bits are transmitted (through
TXD) or received (through RXD). The transactions are
composed of: a Start bit (Low), 8 data bits (LSB first), a
programmable 9th data bit, and one Stop bit (High).
LOAD SBUF
SBUF
READ SBUF
For transmission, the 9th data bit comes from the TB8
bit of SCON. For example, the parity bit P in the PSW
could be moved into TB8.
Internal Bus
th
In the case of receive, the 9 data bit is automatically
written into RB8 of the SCON register.
In Mode 2, the baud rate is programmable to either
1/32 or 1/64 the oscillator frequency.
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VMX51C900
UART Operation in Mode 3
UART in Mode 2 and 3: Additional Information
In Mode 3, 11 bits are transmitted (through TXD) or
received (through RXD). The transactions are
composed of: a Start bit (Low), 8 data bits (LSB first), a
programmable 9th data bit, and one Stop bit (High).
As mentioned previously, for an operation in Modes 2
and 3, 11 bits are transmitted (through TXD) or
received (through RXD). The signal comprises: a
logical low Start bit, 8 data bits (LSB first), a
programmable 9th data bit, and one logical high Stop
bit.
Mode 3 is identical to Mode 2 in all respects but one:
the baud rate. Either Timer 1 or Timer 2 generates the
baud rate in Mode 3.
On transmit, (TB8 in SCON) can be assigned the value
th
of 0 or 1. On receive; the 9 data bit goes into RB8 in
SCON. The baud rate is programmable to either 1/32
or 1/64 the oscillator frequency in Mode 2. Mode 3 may
have a variable baud rate generated from either Timer
1 or Timer 2 depending on the states of TCLK and
RCLK.
FIGURE 15: SERIAL PORT MODE 3 BLOCK DIAGRAM
Internal Bus
1
Write to
SBUF
UART Transmission in Mode 2 and Mode 3
Timer 1
Overflow
Q
S
D
SBUF
TXD
CLK
The transmission is initiated by any instruction that
makes use of SBUF as the destination register. The 9th
bit position of the transmit shift register is loaded by the
“write to SBUF” signal. This event also informs the
UART transmission control unit that a transmission has
been requested. After the next rollover in the divide-by-
16 counter, a transmission actually starts at the
beginning of the machine cycle. It follows that the bit
times are synchronized to the divide-by-16 counter and
not to the “write to SBUF” signal, as in the previous
mode.
Timer 2
Overflow
ZERO DETECTOR
÷2
0
1
Shift
Start
Data
SMOD
0
0
1
TX Control Unit
TCLK
TX Clock
÷16
Send
÷16
TI
1
RCLK
Serial Port
Interrupt
RI
SAMPLE
RX Clock
Start
Load
SBUF
RX Control Unit
1-0 Transition
Detector
SHIFT
Bit
Detector
9-Bit Shift Register
Shift
RXD
LOAD SBUF
Transmissions begin when the SEND signal is
activated, which places the Start bit on TXD pin. Data
is activated one bit time later. This activation enables
the output bit of the transmit shift register to the TXD
pin. The first shift pulse occurs one bit time after that.
SBUF
READ SBUF
Internal Bus
The first shift clocks a Stop bit (1) into the 9th bit
position of the shift register on TXD. Thereafter, only
zeros are clocked in. Thus, as data bits shift out to the
right, zeros are clocked in from the left. When TB8 is at
the output position of the shift register, the stop bit is
just to the left of TB8, and all positions to the left of that
contain zeros. This condition signals to the TX control
unit to shift one more time and set TI, while
deactivating SEND. This occurs at the 11th divide-by-
16 rollover after “write to SBUF”.
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VMX51C900
UART Baud Rates
UART Reception in Mode 2 and Mode 3
In Mode 0, the baud rate is fixed and is represented by
the following formula:
One to zero transitions on the RXD pin initiate
reception. It is for this reason that RXD is sampled at a
rate of 16 multiplied by the baud rate that has been
established.
When a transition is detected, the 1FFh is written into
the input shift register and the divide-by-16 counter is
immediately reset.
Mode 0 Baud Rate = Oscillator Frequency
12
In Mode 2, the baud rate depends on the value of the
SMOD bit in the PCON SFR. From the formula below,
we can see that if SMOD = 0 (which is the value on
reset), the baud rate is 1/32 the oscillator frequency.
During the 7th, 8th and 9th counter states of each bit
time; the bit detector samples the value of RXD. The
accepted value is the value that was seen in at least
two of the three samples. If the value accepted during
the first bit time is not zero, the receive circuits are
reset and the unit goes back to searching for another
one to zero transition. If the start bit is valid, it is shifted
into the input shift register, and the reception of the
rest of the frame will proceed.
Mode 2 Baud Rate = 2SMOD x (Oscillator Frequency)
64
For a receive operation, the data bits come in from the
right as 1’s shift out on the left. As soon as the start bit
arrives at the leftmost position in the shift register (9-bit
register), it tells the RX control block to do one more
shift, to set RI, and to load SBUF and RB8. The signal
to set RI and to load SBUF and RB8 will be generated
if, and only if, the following conditions are satisfied at
the instance when the final shift pulse is generated:
The Timer 1 and/or Timer 2 overflow rate determines
the baud rates in modes 1 and 3.
Generating UART Baud Rate with Timer 1
When Timer 1 functions as a baud rate generator, the
baud rate in modes 1 and 3 are determined by the
Timer 1 overflow rate.
-
-
Either SM2 = 0 or the received 9th bit equal 1
RI = 0
Mode 1,3 Baud Rate = 2SMODx Timer 1 Overflow Rate
32
If both conditions are met, the 9th data bit received
goes into RB8, and the first 8 data bits go into SBUF. If
one of these conditions is not met, the received frame
is completely lost. One bit time later, whether the
above conditions are met or not, the unit goes back to
searching for a one to zero transition at the RXD input.
Please note that the value of the received stop bit is
unrelated to SBUF, RB8 or RI.
Timer 1 must be configured as an 8-bit timer (TL1) with
auto-reload with TH1 value when an overflow occurs
(Mode 2). In this application, the Timer 1 interrupt
should be disabled.
The following two formulas can be used to calculate
the baud rate and the reload value to be written into
the TH1 register.
Mode 1,3 Baud Rate =
2SMODx Fosc
32 x 12(256 – TH1)
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VMX51C900
The value to write into the TH1 register is defined by
the following formula:
The following formula can be used to calculate the
baud rate in modes 1 and 3 using Timer2:
Modes 1, 3 Baud Rate =
Oscillator Frequency
32x[65536 – (RCAP2H, RCAP2L)]
TH1 = 256 -
2SMODx Fosc
32 x 12x (Baud Rate)
Generating UART Baud Rates with Timer 2
The formula below is used to define the reload value to
write into the RCAP2h, RCAP2L registers to achieve a
given baud rate.
Timer 2 is often preferred to generate the baud rate, as
it can be easily configured to operate as a 16-bit timer
with auto-reload. This enables much better resolution
than using Timer 1 in 8-bit auto-reload mode.
(RCAP2H, RCAP2L) = 65536 -
Fosc
32x[Baud Rate]
The baud rate using Timer 2 is defined as:
Mode 1,3 Baud Rate = Timer 2 Overflow Rate
16
In the above formula, RCAP2H and RCAP2L are the
content of RCAP2H and RCAP2L taken as a 16-bit
unsigned integer.
The timer can be configured as either a timer or a
counter in any of its three running modes. In typical
applications, it is configured as a timer (C/T2 is set to
0).
Note that a rollover in TH2 does not set TF2 and will
not generate an interrupt. Therefore, the Timer 2
interrupt does not have to be disabled when Timer 2 is
configured in baud rate generator mode. Furthermore,
when Timer 2 is operating as a UART baud rate
generator (TR2 is set to 1), the user should not try to
perform read or write operations to the TH2 or TL2 and
RCAP2H, RCAP2L registers.
To make the Timer 2 operate as a baud rate generator,
the TCLK and RCLK bits of the T2CON register must
be set to 1.
The baud rate generator mode is similar to the auto-
reload mode in that an overflow in TH2 causes the
Timer 2 registers to be reloaded with the 16-bit value in
registers RCAP2H and RCAP2L, which are preset by
software. However, when Timer 2 is configured as a
baud rate generator, its clock source is Osc/2.
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VMX51C900
Timer 1 Reload Value in Modes 1 & 3 for UART Baud Rate
The following table provides examples of the Timer 1, 8-bit reload value when used as a UART baud rate generator
and the SMOD bit of the PCON register is set to 1.
22.184MHz
16.000MHz
14.745MHz
12.000MHz
11.059MHz
8.000MHz
3.57MHz
115200bps
57600bps
38400bps
31250bps
19200bps
9600bps
2400bps
1200bps
300bps
FFh
Feh
FDh
-
FAh
F4h
D0h
A0h
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FFh
-
-
FDh
FAh
E8h
D0h
40h
FEh
-
FEh
-
-
E6h
CCh
30h
FCh
F8h
E0h
C0h
00h
DDh
BBh
-
DDh
75h
C2h
Timer 2 Reload Value in Modes 1 & 3 for UART Baud Rate
The following table contains examples of [RCAP2H, RCAP2L] reload values for Timer 2 when T2 is configured as
baud rate generator for the VMX51C900 UART.
22.184MHz
FFFDh
FFFAh
FFF4h
FFEEh
FFEAh
FFDCh
FFB8h
FEE0h
FDC0h
F700h
16.000MHz
-
14.745MHz
FFFEh
FFFCh
FFF8h
FFF4h
FFF1h
FFE8h
FFD0h
FF40h
FE80h
FA00h
12.000MHz
11.059MHz
-
8.000MHz
3.57MHz
230400bps
115200bps
57600bps
38400bps
31250bps
19200bps
9600bps
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FFFDh
FFFAh
FFF7h
FFF5h
FFEEh
FFDCh
FF70h
FEE0h
FB80h
FFF3h
FFF0h
FFE6h
FFCCh
FF30h
FE5Fh
F97Dh
FFF4h
-
FFD9h
FF64h
FEC7h
FB1Eh
FFF8h
FFF3h
FFE6h
FF98h
FF30h
FCBEh
-
2400bps
1200bps
300bps
FFD1h
FFA3h
FE8Bh
UART initialization in Mode 3 using Timer 1
UART initialization in Mode 3, using Timer 2
;*** INTIALIZE THE UART @ 9600BPS, Fosc=11.0592MHz
;*** INTIALIZE THE UART @57600BPS, Fosc=11.0592MHz
INISER0T1I: MOV A,T2CON
ANL A,#11001111B
MOV T2CON,A
;RETRIEVE CURRENT VALUE OF T2CON
;RCLK & TCLK BIT = 0 -> TO USE TIMER1
;BAUD RATE GENERATOR SOURCE FOR UART
;SET THE SMOD BIT TO 1
;CONFIG TIMER1 AT 8BIT WITH AUTO-RELOAD
;CALCULATE THE TIMER 1 RELOAD VALUE
;TH1 = [(2^SMOD) * Fosc] / (32 * 12 * Fcomm)
;TH1 FOR 9600BPS @ 11.059MHz = FAh
;CONFIG SCON_0 MODE_1
INISER0T2I: MOV SCON,#05Ah
;CONFIG SCON_0 MODE_1,
;CALCULATE RELOAD VALUE WITH T2
;RCAP2H,RCAP2L = 65536 - [ Fosc / (32*Fcomm)]
MOV PCON,#80H
MOV TL1,#0FAH
MOV TH1,#0FAH
MOV RCAP2H,#0FFh ;RELOAD VALUE 57600bps, 11.059MHz =FFFAh
MOV RCAP2L,#0DCh
;
MOV T2CON,#034h
;SERIAL PORT0, TIMER2 RELOAD START
MOV SCON,#05Ah
MOV TMOD,#00100000B ;CONFIG TIMER 1 IN MODE 2, 8BIT
; + AUTO RELOAD
MOV TCON,#01000000B ;START TIMER1
CLR SCON.0
CLR SCON.1
;CLEAR UART RX, TX FLAGS
CLR SCON.0
CLR SCON.1
;CLEAR UART RX, TX FLAGS
MOV SBUF,#DATA
;SEND ONE BYTE ON THE SERIAL PORT
MOV SBUF,#DATA
;SEND ONE BYTE ON THE SERIAL PORT
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VMX51C900
PWM outputs
TABLE 25: PWMA DATA REGISTER (PWMA) – SFR A4H
7
6
5
4
The VMX51C900 includes 2 PWM outputs, PWMA and
PWMB.
PWMA.4
PWMA.3
PWMA.2
PWMA.1
3
2
1
0
PWMA.0
NPA.2
NPA.1
NPA.0
PWM Registers - Port1 Configuration Register
Bit
7:4
Mnemonic
PWMA[4:0]
Description
Contents of PWM Data
The VMX51C900 PWM outputs are shared with
Inserts Narrow Pulses in a 8-PWM-Cycle
Frame
Port1’s I/Os.
To activate the PWM output, the
3:0
NPA[3:0]
corresponding bit in the P1IOCTRL register must be
set.
The table below displays the number of narrow pulses
generated in an 8-cycle frame versus the NPA number.
TABLE 24: PORT1 I/O CONTROL REGISTER (P1IOCTRL, 9BH)
7
-
6
5
-
4
-
NPA[2:0]
Number of Narrow Pulses inserted in
PWMBE
an 8-cycle frame
000
001
010
011
100
101
110
111
1
2
3
4
5
6
7
8
3
-
2
1
-
0
-
PWMAE
Bit
7
6
5:3
2
1:0
Mnemonic
Description
PWMBE
PWMB output enabled when set to 1
-
PWMAE
-
PWMA output enabled when set to 1
-
PWMA Control Register
The table below describes the PWMA control register
which is used to control the frequency at which the
PWMA operates.
Description of PWMA Function
The PWMA channel is controlled by two SFR registers;
one for the PWM data and the other to control the
PWMA input clock, PWMACK.
TABLE 26: PWMCONTROL REGISTER (PWMACTRL) – SFR A3H
7
6
5
4
3
2
1
0
PWMACK1
PWMACK0
Unused
PWMA Data Register
Bit
7:2
1
Mnemonic
Unused
PWMACK1
PWMACK0
Description
-
Input Clock Frequency Divider Bit 1
Input Clock Frequency Divider Bit 0
The PWMA data register is composed of two parts:
the upper 5 bits, which control the duty cycle of the
PWM output and the remaining 3 bits, which control
the narrow pulse generator (NPA), The NPA generates
narrow pulses among the PWMA 8-cycle frames. The
number of pulses generated in the frame cycle
corresponds to the values defined in the NPA bits. The
insertion of narrow pulses in the PWM frame cycles
enables a PWM resolution equivalent to 8 bits.
0
The following table shows the relationship between the
values of PWMACK1/PWMACK0 and the value of the
divider. Numerical values of the corresponding
frequencies are also provided.
PWMACK1 PWMACK0
Divider
PWM clock,
Fosc=20MHz
10MHz
5MHz
2.5MHz
1.25MHz
The following table describes the PWMA data register.
The PWMA.x bits determine the duty cycle of the
PWMA output waveform. The NPAx bits will generate
narrow pulses in the 8-cycle PWM frame.
0
0
1
1
0
1
0
1
2
4
8
16
The following formulas can be used to calculate the
PWMA output frequency and the PWMA frame rate.
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VMX51C900
PWMA Clock =
Fosc
2(PWMACTRL [1:0] +1)
PWMA Frame =
Fosc
32 x 2(PWMACTRL [1:0] +1)
Example of PWM Timing Diagram
The following provides an example the PWMA configuration.
If Fosc = 20MHz, PWMACTRL = #02H, then PWMA clock = 20MHz/2^(2+1) = 20MHz/8 = 2.5MHz. PWMA output cycle
frame frequency = (20MHz/2^(2+1))/32 = 78.1 kHz
MOV PWMACTRL,#02H
MOV PWMA #82H
MOV P1IOCTRL, #04H
; PWMA Clock = Fosc/8
; PWMA[4:0]=10h (=20T high, 12T low), NPA[2:0] = 2
; Enable P1.2 as PWMA output pin
FIGURE 16: PWMA TIMING DIAGRAM
1st Cycle
frame
2nd Cycle
frame
3rd Cycle
frame
4th Cycle
frame
5th Cycle
frame
6th Cycle
frame
7th Cycle
frame
8th Cycle
frame
32T
32T
32T
32T
32T
32T
32T
32T
20
20
20
20
20
20
20
20
1T
1T
(Narrow pulse inserted by NPA[2:0]=2)
PWMA clock= 1/T= Fosc / 2^(PWMACK+1)
The PWMA output cycle frame frequency = PWMA clock/32 = [Fosc/2^(PWMACK+1)]/32
.
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VMX51C900
PWMB Function Description
The following formula is used to calculate the PWMB
output frequency:
The VMX51C900 PWMB can operate as an 8-bit PWM
or as a 5-bit PWM. Unlike the PWMA, when the PWMB
is configured to operate in 5-bit resolution, there are no
narrow pulses generated in the PWM frame cycle.
PWMB Clock =
Fosc
2(PWMBCK [1:0] +4)
The PWMB channel is controlled by two SFR registers
PWMB Data & PWMB Control). These registers are
used to control the resolution and input clock division
factor.
The
following
table
provides
examples
of
PWMB Data Register
PWMBCK[1:0] bit values versus output frequency
when a 20MHz oscillator is used:
The following table describes the PWMB data register
which is used to control the duty cycle of the PWM
output waveform.
PWMBK1 PWMBCK0
Divider
PWMB clock,
Fosc=20MHz
1.25MHz
0
0
1
1
0
1
0
1
16
32
When the PWMB is configured to operate in 5-bit
resolution (see below) only the 5 LSBs of the PWMB
register are used.
625 KHz
64
312.5KHz
128
156.2KHz
TABLE 27: PWMB DATA REGISTER (PWMB) – SFR B3HH
The following figure describes the relationship between
the PWMB duty cycle vs. the PWMB data register
contents and the PWMBRES bit value.
7
6
5
4
PWMB.7
PWMB.6
PWMB.5
PWMB.4
3
2
1
0
PWMB.3
PWMB.2
PWMB.1
PWMB.0
FIGURE 17: PWMB TIMING DIAGRAM EXAMPLES
Bit
7:0
Mnemonic
PWMB[7:0]
Description
PWM duty cycle control
PWMBRES = 1
32T
8
PWMB = 8
PWMB Control Register
32T
The following table describes the PWMB control
register.
16
PWMB = 16
PWMBRES = 0
256T
256T
TABLE 28: PWMB CONTROL REGISTER (PWMBCTRL) – SFR D3H
PWMB = 64
64
7
6
5
4
3
2
1
0
PWMBRES
PWMBCK1
PWMBCK0
PWMB = 128
128
Bit
[7:3]
2
Mnemonic
Unused
PWMBRES
Description
-
0: Set PWMB resolution to 8-bit
1: Set PWMB resolution to 5-bit
1
0
PWMBCK1
PWMBCK0
Input Clock Frequency Divider Bit 1
Input Clock Frequency Divider Bit 0
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VMX51C900
The configuration and use of the VMX51C900 A/D
Converter involves the following steps:
Analog-to-Digital Converter (ADC)
The VMX51C900 includes a 4-channel, 8-bit A/D
converter. ADC inputs are shared with I/O ports P3.4
to P3.7. The ADC derives its reference from the supply
voltage.
·
·
·
·
Activate the ADC Input
Set the ADC Control Register
Set the ADC Interrupts (if required)
Collect the ADC Data
FIGURE 18: ADC SRUCTURE
The VMX51C900 ADC shares its inputs with the upper
nibble of Port 3. Writing a 1 into a given ADCIENx bit
VDD
P3.4
of
the
P3IOCTRL
register
configures
the
P3.4 / ADCIN0
ADCIN0
corresponding I/O pins as ADC inputs. When the
ADCIENx bit remains at 0, the P3 pins can be used as
general purpose I/Os.
P3.5
P3.5 / ADCIN1
ADCIN1
ADCDATA(7:0)
P3.6
ADC
ADCLK(1:0)
P3.6 / ADCIN2
ADCIN2
ADCCONT
When the Port 3 pins are configured as ADC inputs,
writing to the corresponding P3 register bits will not
affect device operation, while reading these port pins
will return the port register values.
P3.7
ADCEND
P3.7 / ADCIN3
ADCIN3
ADCCH(1:0)
ADCIEN(3:0)
The ADC binary output represents the ratio of the
analog voltage at its input vs. the VMX51C900 supply
as shown in the following figure:
TABLE 29: PORT3 CONFIGURATION REGISTER (P3IOCTRL, 9DH)
7
6
5
4
ADCIEN3
ADCIEN2
ADCIEN1
ADCIEN0
3
-
2
-
1
-
0
-
FIGURE 19: ADC OUTPUT VS. ANALOG VOLTAGE PRESENT AT ITS INPUTS
Bit
7
Mnemonic
Description
ADC Input 3 Enable
0 = P3.7 I/O
1 = ADC input 3
ADC Input 2 Enable
0 = P3.6 I/O
1 = ADC input 2
ADC Input 1 Enable
0 = P3.5 I/O
1 = ADC input 1
ADC Input 0 Enable
0 = P3.4 I/O
1 = ADC input 0
Unused
OUTPUT
CODE
1111_1111
1111_1110
1111_1101
ADCIEN3
ADCIEN2
ADCIEN1
ADCIEN0
-
1111_1100
1 LSB = VDD / 256
6
5
0000_0011
0000_0010
0000_0001
0000_0000
4
VDD
0V
3:0
The following formula is used to calculate the ADC
conversion result based on input and supply voltages.
ADCresult = Vin
Vsupply
* 256
When the ADC input voltage exceeds the supply
voltage, the ADC conversion result will saturate at
0FFh.
When the voltage is lower than the
VMX51C900’s ground reference, the ADC conversion
result will remain at 00h.
Configuring the VMX51C900 ADC
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VMX51C900
The ADCCLTR register sets the ADC clock speed
value, selects the analog channel which the conversion
is to be performed on and defines whether the ADC
will perform a single or continuous conversion of the
selected channel.
Bits 3 and 2 of the ADCCTRL register control the ADC
input on which the conversion will be performed.
ADCCH1
ADCCH0
ADC input channel
ADCIN0
0
0
1
1
0
1
0
1
ADCIN1
TABLE 30:ADC CONTROL REGISTER ADCCTRL (8EH)
ADCIN2
7
6
5
4
ADCIN3
ADCEND
ADCCONT
ADCCLK[1:0]
The ADCDATA register is a read-only register which
receives the ADC conversion result.
3
2
1
-
0
-
ADCCH[1:0]
Bit
7
Mnemonic
ADCEND
Description
ADC End of conversion bit
Get set to 1 when the ADC conversion
completes. It is cleared when the
ADCCTRL is written and when the
ADCDATA Register is read.
ADC Continuous conversion Bit
1 = ADC run in continuous and the
ADCDATA is refreshed after each
conversion is performed on the selected
channel.
TABLE 31:ADC DATA REGISTER ADCDATA(8FH)
7
6
5
4
3
2
1
0
ADCDATA[7:0]
Bit
7:0
Mnemonic
ADCDATA
Description
ADC data register
6
ADC Conversion Time
ADCCONT
ADC conversion requires 20 ADC clock cycles. The
conversion rate can be calculated as follows:
0 = ADC conversion is performed once
ADC Clock prescaler
(see Table below)
ADC Channel select
(See table below)
5:4
3:2
1:0
ADCCLK[1:0]
ADCCH[1:0]
-
ADC Conv Rate = Fadc clock
20
-
ADC Conv Rate =
Fosc
20*2(ADCCLK[1:0] + 3)
The ADCEND bit is used to monitor the status of the
ADC conversion process. At the end of a conversion,
the ADCEND flag is set. Writing to the ADCCTRL
register or reading the ADCDATA register
automatically clears the ADCEND bit.
VMX51C900 ADC Initialization and Use
The following is an example of how to configure the
VMX51C900 and use the ADC to read channel 0 in
continuous mode using the ADC interrupt to retrieve
the conversion result.
When set to 1, the ADCCONT bit of the ADCCTRL
register configures the ADC to perform continuous
conversions on the selected ADC input channel and
refreshes the ADCDATA register when the conversion
is complete.
(…)
;*** INITIALIZE THE A/D CONVERTER
MOV P3CON,#10000000B
;CONFIG P3.7 -> ADCIN3
MOV ADCCTRL,#0001110B
;CONFIG ADCCTRL
;7 ADCEND = 0
In order for the ADC to operate properly, a 500KHz to
2.5MHz clock must be fed into the VMX51C900 ADC.
The ADC clock is derived from the VMX51C900’s
oscillator and the division factor is controlled by the
ADCCLK1 and ADCCLK0 bits of the ADCCTRL
register (see following table).
;6 ADCCONT = SINGLE CONV.
;5:4 ADCCLK = Fosc/16
;3:2 ADCCH = ADCIN3
;1:0 UNUSED
; Fosc = 11.059MHz CONV=34.5KHz
;WAIT FOR ADC CONVERSION TO
;COMPLETE
WAITADC: MOV A,ADCCTRL
ANL A,#80H
JZ
WAITADC
MOV BINL,ADCDATA
;RETRIEVE ADC DATA
(…)
ADCCLK1 ADCCLK0
ADC_CLK
Fosc / 8*
Fosc / 16
Fosc / 32
Fosc / 64
0
0
1
1
0
1
0
1
*Use this Fosc division factor below 20MHz
Operating the ADC with a clock outside of the 500KHz
to 2.5MHz frequency range may lead to an ADC
malfunction.
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VMX51C900
Configuring the LCD Driver
Integrated LCD Driver
The initialization of the LCD driver is performed using
The VMX51C900 features an on-chip LCD driver
designed to drive custom LCD panels in consumer,
medical and industrial systems.
the
LCDCTRL,
P0IOCTRL,
P2IOCTRL
and
LCDBUF[6:0] registers.
The LCD driver outputs are multiplexed with regular
VMX51C900 I/Os. For this reason, the I/Os required
for LCD operation must be configured for the LCD
driver mode. This is done by setting the corresponding
bits of the P0IOCTRL and P2IOCTRL registers to 1
and, if required, setting the LCDPRI bit of the
LCDCTRL register.
The LCD driver is set up to drive a 14-segment x 4
common LCD panel, without the need for external
components.
Once configured, the LCD driver operates
independently of the processor and generates the
appropriate signals to display the data saved in the
LCD buffer (LCDBUFx) registers, which are accessible
via the SFR registers.
TABLE 32: PORT 0 I/O CONTROL REGISTER (P0IOCTRL, 9AH)
7
6
5
4
LCDSEG6
LCDSEG7
LCDSEG8
LCDSEG9
The VMX51C900 LCD driver works on 1/4 duty and
1/3 bias. When activated, LCD driver power
consumption is about 0.88mA (1.2uA when de-
activated).
3
2
1
0
LCDSEG10
LCDSEG11
LCDSEG12
LCDSEG13
Bit
7
6
5
4
3
2
1
0
Mnemonic
Description
LCDSEG6
LCDSEG7
LCDSEG8
LCDSEG9
LCDSEG10
LCDSEG11
LCDSEG12
LCDSEG13
1= Assign P0.7 to LCD Seg. 6 driver
1= Assign P0.6 to LCD Seg. 7 driver
1= Assign P0.5 to LCD Seg. 8 driver
1= Assign P0.4 to LCD Seg. 9 driver
1= Assign P0.3 to LCD Seg. 10 driver
1= Assign P0.2 to LCD Seg. 11 driver
1= Assign P0.1 to LCD Seg. 12 driver
1= Assign P0.0 to LCD Seg. 13 driver
Timing Chart of LCD Driver Output
The 14-segment and the 4-common drivers are 4-level
outputs that switch between VDD, V1, V2 and VSS
LCD driver voltage levels.
The LCD segment/common states are stored into six
SFRs called LCDBUFx registers. Each LCDBUFx
register controls the state of two LCD segments for
each time-slot activated by the LCDCOMx lines. The
following diagram shows a typical LCD driver output
timing diagram:.
TABLE 33: PORT 2 I/O CONTROL REGISTER (P2IOCTRL, 9CH)
7
6
5
4
LCDSEG3
LCDSEG2
LCDSEG1
LCDSEG0-
FIGURE 20: LCD DRIVER OUTPUT TIMING DIAGRAM
3
2
1
0
LCDCOM3
LCDCOM2
LCDCOM1
LCDCOM0
Bit
7
6
5
4
3
2
1
0
Mnemonic
Description
LCDSEG3
LCDSEG2
LCDSEG1
LCDSEG0
LCDCOM3
LCDCOM2
LCDCOM1
LCDCOM0
1= Assign P2.7 to LCD Seg. 3 driver
1= Assign P2.6 to LCD Seg. 2 driver
1= Assign P2.6 to LCD Seg. 1 driver
1= Assign P2.6 to LCD Seg. 0 driver
1= Assign P2.6 to LCD Com. 3 driver
1= Assign P2.6 to LCD Com. 2 driver
1= Assign P2.6 to LCD Com. 1 driver
1= Assign P2.6 to LCD Com. 0 driver
The LCD is activated by setting the LCDEN bit of the
LCDCTRL register.
The LCDON bit of the LCDCTRL serves to turn the
display ON so that the contents in the LCDBUFx
registers are sent to the display.
When the LCDPRI bit is set to 1, the VMX51C900
PSEN and ALE pins are assigned as the LCDSEG4
and LCDSEG5 lines, respectively.
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VMX51C900
TABLE 34: LCD CONTROL REGISTER (LCDCTRL, DFH)
needs to be active during the LCDCOM1 time-slot,
then both bits 5 and 6 of the LCDBUF0 register must
be set.
7
6
5
4
-
LCDON
LCDEN
LCDPRI
3
-
2
1
0
The
following
tables
describe
the
LCD
LCDCLK2
LCDCLK1
LCDCLK0
segment/common combinations controlled by the
LCDBUFx registers..
Bit
Mnemonic
LCDON
Description
7
6
5
1 = LCD Display is ON
0 = LCD Display is OFF
1 = LCD is enabled
TABLE 35: LCD BUFFER REGISTER 0 (LCDBUF0, E1H)
LCDEN
LCDPRI
7
6
5
4
0 = LCD is disabled
SEG0_COM3
SEG0_COM2
SEG0_COM1
SEG0_COM0
1 = Give priority of LCD operation on
#PSEN/LCDSEG4 and
ALE/LCDSEG5 pins
Unused
3
2
1
0
4:3
2:0
-
SEG1_COM3
SEG1_COM2
SEG1_COM1
SEG1_COM0
LCDCLK[2:0]
LCD prescaler select
Bit
Mnemonic
Description
7
SEG0_COM3 If set to 1, the LCDSEG0 will be ON
during LCDCOM3 time slot
SEG0_COM2 If set to 1, the LCDSEG0 will be ON
during LCDCOM2 time slot
SEG0_COM1 If set to 1, the LCDSEG0 will be ON
during LCDCOM1 time slot
SEG0_COM0 If set to 1, the LCDSEG0 will be ON
during LCDCOM0 time slot
SEG1_COM3 If set to 1, the LCDSEG1 will be ON
during LCDCOM3 time slot
SEG1_COM2 If set to 1, the LCDSEG1 will be ON
during LCDCOM2 time slot
SEG1_COM1 If set to 1, the LCDSEG1 will be ON
during LCDCOM1 time slot
SEG1_COM0 If set to 1, the LCDSEG1 will be ON
during LCDCOM0 time slot
The LCD driver clock can be adjusted to meet the
driving speed requirements of the LCD display. The
LCDCLK[2:0] bits of the LCDCTRL register are used to
define the LCD driver clock prescaler value as follows:
6
5
4
3
2
1
0
LCDCLK[2:0]
000
LCD Clock prescaler value
1
2
001
010
4
011
8
100
101
110
111
16
32
64
128
The LCD clock speed can be calculated using the
following formula.
FCLK_LCD
=
Fosc
2 * 32 * LCDCLK[2:0]
The LCD frame frequency is defined as follows:
FLCD_Frame = FCLKLCD / 256
The typical range of FFrame is:
1026HZ ~ 8HZ at 16MHz (Fosc = 8MHz)
The six LCDBUFx registers contain the mapping of the
LCDSEGxx/LCDCOMx segment state. To activate a
given segment (ON) during one of the four time-slots in
each frame, the bit corresponding to the
segment/common must be set to 1.
For example, to activate the LCDSEG 0 during the
second time-slot (controlled by LCDCOM2), bit 6 of the
LCDBUF0 must be set to 1. If the LCDSEG 0 also
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VMX51C900
TABLE 36: LCD BUFFER REGISTER 1 (LCDBUF1, E2H)
TABLE 38: LCD BUFFER REGISTER 3 (LCDBUF3, E4H)
7
6
5
4
7
6
5
4
SEG2_COM3
SEG2_COM2
SEG2_COM1
SEG2_COM0
SEG6_COM3
SEG6_COM2
SEG6_COM1
SEG6_COM0
3
2
1
0
3
2
1
0
SEG3_COM3
SEG3_COM2
SEG3_COM1
SEG3_COM0
SEG7_COM3
SEG7_COM2
SEG7_COM1
SEG7_COM0
Bit
7
Mnemonic
Description
Bit
7
Mnemonic
Description
SEG2_COM3 If set to 1, the LCDSEG2 will be ON
during LCDCOM3 time slot
SEG2_COM2 If set to 1, the LCDSEG2 will be ON
during LCDCOM2 time slot
SEG2_COM1 If set to 1, the LCDSEG2 will be ON
during LCDCOM1 time slot
SEG2_COM0 If set to 1, the LCDSEG2 will be ON
during LCDCOM0 time slot
SEG3_COM3 If set to 1, the LCDSEG3 will be ON
during LCDCOM3 time slot
SEG3_COM2 If set to 1, the LCDSEG3 will be ON
during LCDCOM2 time slot
SEG3_COM1 If set to 1, the LCDSEG3 will be ON
during LCDCOM1 time slot
SEG3_COM0 If set to 1, the LCDSEG3 will be ON
during LCDCOM0 time slot
SEG6_COM3 If set to 1, the LCDSEG6 will be ON
during LCDCOM3 time slot
SEG6_COM2 If set to 1, the LCDSEG6 will be ON
during LCDCOM2 time slot
SEG6_COM1 If set to 1, the LCDSEG6 will be ON
during LCDCOM1 time slot
SEG6_COM0 If set to 1, the LCDSEG6 will be ON
during LCDCOM0 time slot
SEG7_COM3 If set to 1, the LCDSEG7 will be ON
during LCDCOM3 time slot
SEG7_COM2 If set to 1, the LCDSEG7 will be ON
during LCDCOM2 time slot
SEG7_COM1 If set to 1, the LCDSEG7 will be ON
during LCDCOM1 time slot
SEG7_COM0 If set to 1, the LCDSEG7 will be ON
during LCDCOM0 time slot
6
5
4
3
2
1
0
6
5
4
3
2
1
0
TABLE 37: LCD BUFFER REGISTER 2 (LCDBUF2, E3H)
TABLE 39: LCD BUFFER REGISTER 4 (LCDBUF4, E5H)
7
6
5
4
7
6
5
4
SEG4_COM3
SEG4_COM2
SEG4_COM1
SEG4_COM0
SEG8_COM3
SEG8_COM2
SEG8_COM1
SEG8_COM0
3
2
1
0
3
2
1
0
SEG5_COM3
SEG5_COM2
SEG5_COM1
SEG5_COM0
SEG9_COM3
SEG9_COM2
SEG9_COM1
SEG9_COM0
Bit
7
Mnemonic
Description
Bit
7
Mnemonic
Description
SEG4_COM3 If set to 1, the LCDSEG4 will be ON
during LCDCOM3 time slot
SEG4_COM2 If set to 1, the LCDSEG4 will be ON
during LCDCOM2 time slot
SEG4_COM1 If set to 1, the LCDSEG4 will be ON
during LCDCOM1 time slot
SEG4_COM0 If set to 1, the LCDSEG4 will be ON
during LCDCOM0 time slot
SEG5_COM3 If set to 1, the LCDSEG5 will be ON
during LCDCOM3 time slot
SEG5_COM2 If set to 1, the LCDSEG5 will be ON
during LCDCOM2 time slot
SEG5_COM1 If set to 1, the LCDSEG5 will be ON
during LCDCOM1 time slot
SEG5_COM0 If set to 1, the LCDSEG5 will be ON
during LCDCOM0 time slot
SEG8_COM3 If set to 1, the LCDSEG8 will be ON
during LCDCOM3 time slot
SEG8_COM2 If set to 1, the LCDSEG8 will be ON
during LCDCOM2 time slot
SEG8_COM1 If set to 1, the LCDSEG8 will be ON
during LCDCOM1 time slot
SEG8_COM0 If set to 1, the LCDSEG8 will be ON
during LCDCOM0 time slot
SEG9_COM3 If set to 1, the LCDSEG9 will be ON
during LCDCOM3 time slot
SEG9_COM2 If set to 1, the LCDSEG9 will be ON
during LCDCOM2 time slot
SEG9_COM1 If set to 1, the LCDSEG9 will be ON
during LCDCOM1 time slot
SEG9_COM0 If set to 1, the LCDSEG9 will be ON
during LCDCOM0 time slot
6
5
4
3
2
1
0
6
5
4
3
2
1
0
______________________________________________________________________________________________
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VMX51C900
TABLE 40: LCD BUFFER REGISTER 5 (LCDBUF5, E6H)
Table 41: LCD Buffer Register 6 (LCDBUF6, E7h)
7
6
5
4
7
6
5
4
SEG10_COM3
SEG10_COM2
SEG10_COM1
SEG10_COM0
SEG12_COM3
SEG12_COM2
SEG12_COM1
SEG12_COM0
3
2
1
0
3
2
1
0
SEG11_COM3
SEG11_COM2
SEG11_COM1
SEG11_COM0
SEG13_COM3
SEG13_COM2
SEG13_COM1
SEG13_COM0
Bit
7
Mnemonic
Description
If set to 1, the LCDSEG10 will be ON
during LCDCOM3 time slot
If set to 1, the LCDSEG10 will be ON
during LCDCOM2 time slot
If set to 1, the LCDSEG10 will be ON
during LCDCOM1 time slot
If set to 1, the LCDSEG10 will be ON
during LCDCOM0 time slot
If set to 1, the LCDSEG11 will be ON
during LCDCOM3 time slot
If set to 1, the LCDSEG11 will be ON
during LCDCOM2 time slot
If set to 1, the LCDSEG11 will be ON
during LCDCOM1 time slot
Bit
7
Mnemonic
Description
If set to 1, the LCDSEG12 will be ON
during LCDCOM3 time slot
If set to 1, the LCDSEG12 will be ON
during LCDCOM2 time slot
If set to 1, the LCDSEG12 will be ON
during LCDCOM1 time slot
If set to 1, the LCDSEG12 will be ON
during LCDCOM0 time slot
If set to 1, the LCDSEG13 will be ON
during LCDCOM3 time slot
If set to 1, the LCDSEG13 will be ON
during LCDCOM2 time slot
If set to 1, the LCDSEG13 will be ON
during LCDCOM1 time slot
SEG10_COM3
SEG10_COM2
SEG10_COM1
SEG10_COM0
SEG11_COM3
SEG11_COM2
SEG11_COM1
SEG11_COM0
SEG12_COM3
SEG12_COM2
SEG12_COM1
SEG12_COM0
SEG13_COM3
SEG13_COM2
SEG13_COM1
SEG13_COM0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
If set to 1, the LCDSEG11 will be ON
during LCDCOM0 time slot
If set to 1, the LCDSEG13ill be ON
during LCDCOM0 time slot
VMX51C900 LCD Driver Example Program
The following program example show the basic steps
required to initialize and use the VMX51C900 LCD
driver.
;** LCD DRIVER INITIALISATION
MOV P0IOCTRL,#0FFH
MOV P2IOCTRL,#0FFH
;Assign I/O pin to LCD driver
MOV LCDCON,#11100110B
;LCD_ON=1
;LCD_EN =1 -> ENABLE
;SEG = 1
;BIT3, BIT4 = UNUSED
;LS[2:0] = 110 -> PRESCALER = 64
;**LCD SEGMENTS CONFIGURATION
MOV LCDBUF0,#00010010B
;LCDSEG0 is ON during COM0
;&
LCDSEG1
is
ON
during
;LCDCOM1 period
MOV LCDBUF1,#01000000B
MOV LCDBUF2,#11111111B
MOV LCDBUF6,#00000010B
;LCDSEG2 is ON during LCDCOM2
;period
;LCDSEG4 & LCDSEG5 are always
;ON
(…)
;LCDSEG13 is ON during LCDCOM1
______________________________________________________________________________________________
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VMX51C900
The following table provides a condensed view of the LCD Segment/LCD Common control vs. LCDBUFx registers.
LCDCOM3
Bit7
LCDCOM2
Bit6
LCDCOM1
Bit5
LCDCOM0
Bit4
LCDCOM3
Bit3
LCDCOM2
Bit2
LCDCOM1
Bit1
LCDCOM0
Bit0
Mnemonic
Address
LCDBUF0 E1H
LCDBUF1 E2H
LCDBUF2 E3H
LCDBUF3 E4H
LCDBUF4 E5H
LCDBUF5 E6H
LCDBUF6 E7H
LCDSEG0
LCDSEG2
LCDSEG4
LCDSEG6
LCDSEG8
LCDSEG10
LCDSEG12
LCDSEG0
LCDSEG2
LCDSEG4
LCDSEG6
LCDSEG8
LCDSEG10
LCDSEG12
LCDSEG0
LCDSEG2
LCDSEG4
LCDSEG6
LCDSEG8
LCDSEG10
LCDSEG12
LCDSEG0
LCDSEG2
LCDSEG4
LCDSEG6
LCDSEG8
LCDSEG10
LCDSEG12
LCDSEG1
LCDSEG3
LCDSEG5
LCDSEG7
LCDSEG9
LCDSEG11
LCDSEG13
LCDSEG1
LCDSEG3
LCDSEG5
LCDSEG7
LCDSEG9
LCDSEG11
LCDSEG13
LCDSEG1
LCDSEG3
LCDSEG5
LCDSEG7
LCDSEG9
LCDSEG11
LCDSEG13
LCDSEG1
LCDSEG3
LCDSEG5
LCDSEG7
LCDSEG9
LCDSEG11
LCDSEG13
Interrupts
The following figure provides a pictorial description of
the various interrupts on the VMX51C900:
The VMX51C900 has nine interrupts (10 if the WDT is
included) and eight interrupt vectors (including reset)
used for handling. The interrupts are enabled via the
IE register (see following table).
FIGURE 21: INTERRUPT SOURCES
INT0
IT0
IE0
TABLE 42: IEN0INTERRUPT ENABLE REGISTER –SFR A8H
7
EA
6
-
5
ET2
4
ES
3
ET1
2
EX1
1
ET0
0
EX0
TF0
Bit
Mnemonic Description
7
EA
Disables All Interrupts
0: no interrupt acknowledgment
INT1
IT1
IE1
INTERRUPT
SOURCES
1: Each interrupt source is individually
enabled or disabled by setting or clearing
its enable bit.
TF1
6
5
4
3
2
1
0
-
Reserved
Timer 2 Interrupt Enable Bit
TI
ET2
ES
ET1
EX1
ET0
EX0
RI
Serial Port Interrupt Enable Bit
Timer 1 Interrupt Enable Bit
External Interrupt 1 Enable Bit
Timer 0 Interrupt Enable Bit
External Interrupt 0 Enable Bit
TF2
EXF2
ADC
Interrupt Vectors
TABLE 43: IEN1INTERRUPT ENABLE REGISTER 1–SFR A9H
7
-
6
-
5
-
4
-
3
2
1
-
0
-
The following table specifies each interrupt source, its
flag and its vector address.
ADCIE
-
Bit
Mnemonic Description
TABLE 44: INTERRUPT VECTOR ADDRESS
7:4
3
2:0
-
-
ADCIE
-
ADC Interru[pt Enable
-
Interrupt Source
Flag
Vector
Address
0000h*
0003h
RESET (+ WDT)
INT0
WDR
IE0
Timer 0
INT1
TF0
IE1
000Bh
0013h
Timer 1
Serial Port
Timer 2
TF1
001Bh
0023h
002Bh
004Bh
RI+TI
TF2+EXF2
ADCIF
ADC Interrupt
______________________________________________________________________________________________
www.ramtron.com page 37 of 55
VMX51C900
sources that do not have their corresponding IP or IP1
bit set to 1.
Execution of an Interrupt
When the processor receives an interrupt request, an
automatic jump to the desired subroutine occurs. This
jump is similar to executing a branch to a subroutine
instruction: the processor automatically saves the
address of the next instruction on the stack. An internal
flag is set to indicate that an interrupt is taking place,
and then the jump instruction is executed. An interrupt
subroutine must always end with the RETI instruction.
This instruction allows the processor to retrieve the
return address placed on the stack and update the
internal flags of the interrupt controller.
The IP and IP1 register structures are represented in
the following tables:
TABLE 46: IP INTERRUPT PRIORITY REGISTER –SFR B8H
7
-
6
-
5
PT2
4
PS
3
PT1
2
PX1
1
PT0
0
PX0
Bit
Mnemonic Description
7
6
-
-
Gives Timer 2 Interrupt Higher Priority
5
4
3
2
1
0
PT2
PS
PT1
PX1
PT0
PX0
Gives Serial Port Interrupt Higher Priority
Gives Timer 1 Interrupt Higher Priority
Gives INT1 Interrupt Higher Priority
Gives Timer 0 Interrupt Higher Priority
Gives INT0 Interrupt Higher Priority
Interrupt Enable and Interrupt Priority
When the VMX51C900 is reset, the IEN0 and IEN1
registers are cleared, disabling all the interrupts. The
corresponding bits in the IEN0 and IEN1 registers must
be set to enable the interrupts.
TABLE 47: IP1 INTERRUPT PRIORITY REGISTER 1 –SFR B9H
7
-
6
-
5
-
4
-
3
2
1
-
0
-
The IEN0 register is part of the bit addressable internal
RAM. Therefore, each bit can be individually modified
in one instruction without having to modify the other
bits of the register. The IEN1 register that controls the
ADC interrupt is not bit addressable. In order to enable
the ADC interrupt, a direct write must be performed in
the IEN1 register to set the ADCIE bit to 1.
ADCIP
-
Bit
7:4
Mnemonic Description
-
Gives ADC Interrupt Higher Priority
3
ADCIP
-
2:0
External Interrupts
All interrupts can be inhibited by clearing the EA bit of
the IEN0 register.
The VMX51C900 has two external interrupt inputs
(INT0 and INT1). These interrupt lines are shared with
P3.2 and P3.3.
The priority in which the interrupts are serviced is
displayed in the following table:
TABLE 45: INTERRUPT PRIORITY
The IE0 and IE1 bits of the TCON register are external
flags that detect a low level or high-to-low transition on
the INT0, INT1 interrupt pins respectively. These flags
are automatically cleared when the corresponding
interrupt is serviced.
Interrupt Source
RESET + WDT (Highest Priority)
IE0
TF0
IE1
TF1
RI+TI
TF2+EXF2
Bits IT0 and IT1 of the TCON register determine
whether the external interrupts are level or edge
sensitive.
ADCIP (Lowest Priority)
IT0 = 0: The INT0, if enabled, occurs if a low level is
present on P3.2
Modifying the Order of Priority
IT0 = 1: The INT0, if enabled, occurs if a high-to-low
transition is detected on P3.2
The VMX51C900 allows the user to modify the natural
priority of the interrupts by programming the
corresponding bits in the IP (interrupt priority) register.
When any bit in this register is set to 1, it gives the
corresponding source priority over interrupts from
IT1 = 0: The INT1, if enabled, occurs if a low level is
present on P3.3
______________________________________________________________________________________________
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VMX51C900
IT1 = 1: The INT1, if enabled, occurs if a high-to-low
transition is detected on P3.3
Serial Port Interrupt
The serial port can generate an interrupt upon byte
reception or when byte transmission is completed.
Both conditions share the same interrupt vector and it
is up to the user-developed interrupt service routine
software to determine what caused the interrupt by
examining the serial interrupt flags RI and TI.
The state of the external interrupt, when enabled, can
be monitored using flags IE0 and IE1 of the TCON
register that are set when the interrupt condition
occurs.
In cases where the interrupt is configured as edge
triggered, the associated flag is automatically cleared
when the interrupt is serviced. If the interrupt is
configured as level sensitive, the interrupt flag must be
cleared by the software.
Note that neither of these flags are cleared by the
hardware upon execution of the interrupt service
routine. The flags must be cleared by the software.
Timer0 and Timer1 Interrupts
Both Timer0 and Timer1 can be configured to generate
an interrupt when a rollover of the timer/counter occurs
(exception is Timer 0 in Mode 3).
The TF0 and TF1 flags serve to monitor timer overflow
occurring intimers 0 and 1. These interrupt flags are
automatically cleared when the interrupt is serviced.
Timer 2 interrupt
A Timer 2 interrupt can occur if the TF2 and/or EXF2
flags are set to 1 and if the Timer 2 interrupt is
enabled. The TF2 flag is set when a rollover of the
Timer 2 counter/timer occurs. The EXF2 flag can be
set by a 1 to 0 transition on the T2EX pin by the
software.
Note that neither flag is cleared by the hardware upon
execution of the interrupt service routine. The service
routine may have to determine whether it was TF2 or
EXF2 that generated the interrupt. These flag bits will
have to be cleared by the software.
Every bit that generates interrupts can either be
cleared or set by the software, yielding the same result
as when the operation is done by the hardware. In
other words, pending interrupts can be cancelled and
interrupts can be generated by the software.
______________________________________________________________________________________________
www.ramtron.com page 39 of 55
VMX51C900
When the ADC interrupt is authorized and
a
ADC Interrupt
conversion is completed, the ACDIF flag of the IF1
register will be set to 1. Once the ADC interrupt routine
is executed, the ADCIF will be automatically cleared.
Like other peripherals on the VMX51C900, the A/D
converter can generate an interrupt to the processor
once the conversion is completed. The interrupt vector
associated with the A/D converter is 04Bh.
TABLE 50: INTERRUPT FLAG REGISTER (IF1, AAH)
7
-
6
-
5
-
4
-
The IP1, IEN1 and IFI special function registers control
the ADC interrupt.
3
2
-
1
-
0
-
ADCIF
To activate the ADC interrupt, the ADCIE bit of the
IEN1 register must be set, as well as the general
interrupt bit, EA bit 7 of the IEN0 register.
Bit
7:4
3
Mnemonic
Description
Unused
-
ADCIF
ADC Interrupt Flag
Will be set to 1 if ADC interrupt
TABLE 48: INTERRUPT ENABLE REGISTER (IEN1, A9H)
occurred. Cleared automatically when
the interrupt is serviced.
Unused
7
-
6
-
5
-
4
-
2:0
-
3
2
-
1
-
0
-
ADCIE
ADC Initialization & Use (by Interrupt)
Bit
7:4
3
Mnemonic
Description
Unused
ADC Interrupt Enable
0 = ADC interrupt Disabled
1 = ADC interrupt Enabled
Unused
The following code example demonstrates the basic
steps for configuring the VMX51C900 A/D converter
and use the ADC interrupt to retrieve conversion
results. The ADCEND bit of the ADCCTRL register can
be used to monitor when the A/D conversion process
is terminated.
-
ADCIE
2:0
-
By default, the ADC interrupt is set to low priority.
However, setting the ADCIP bit of the IP1 register will
give the ADC higher priority.
;*** RESET VECTOR
ORG 0000H
LJMP START
;*** ADC INTERRUPT JUMP VECTOR ***
ORG 04BH
TABLE 49: INTERRUPT PRIORITY REGISTER (IP1, B9H)
LJMP IRQADC
;JUMP TO ADC INTERRUPT ROUTINE
7
-
6
-
5
-
4
-
;*** MAIN PROGRAM START ***
ORG 0100H
START:
MOV SP,#0C0H
;INITIALISE STACK POINTER
3
2
-
1
-
0
-
ADCIP
;*** INITIALIZE THE A/D CONVERTER
MOV P3IOCTRL,#01000000B
MOV ADCCTRL,#01001000B
;CONFIG P3.6 -> ADCIN2
;CONFIG ADCCTRL
;7 ADCEND = 0
;6 ADCCONT = CONT CONV.
;5:4 ADCCLK = Fosc/8
;3:2 ADCCH = ADCI2
;1:0 UNUSED
;WITH Fosc = 11.059MHz
;CONV RATE 69.1KHz
Bit
7:4
3
Mnemonic
Description
Unused
ADC Interrupt Priority
0 = ADC interrupt is Low Priority
1 = ADC interrupt is High Priority
Unused
ADCGO:
-
ADCIP
2:0
-
MOV ADCVALUE,#00H
MOV IEN1,#00001000B
SETB EA
;ENABLE ADC INTERRUPT
;ENABLE GENERAL INTERRUPTS
(…)
;***************************
;* ADC INTERRUPT
;***************************
IRQADC:
MOV ADCVALUE,ADCDATA
;RETRIEVE ADCDATA
RETI
______________________________________________________________________________________________
www.ramtron.com page 40 of 55
VMX51C900
Once the WDT is enabled, the user software must
clear it periodically. If the WDT is not cleared, its
overflow will trigger a reset of the VMX51C900.
The Watchdog Timer
The VMX51C900 watchdog timer (WDT) is a 16-bit
free-running counter operating from an independent
250KHz internal RC oscillator. An overflow of the WDT
counter will reset the processor.
TABLE 52: WATCH DOG TIMER REGISTERS: WDTCTRL – SFR 9FH
7
6
5
4
3
2
1
0
WDT
CLR
WDT
PS2
WDT
PS1
WDT
PS0
WDTE
Unused
Unused
The WDT is a useful safety measure for systems that
are susceptible to noise, power glitches and other
conditions that could cause the software to go into
infinite dead loops or runaways. The WDT provides the
user software with a recovery mechanism from
abnormal software conditions.
Bit
7
6
5
[4:3]
2
1
Mnemonic
WDTE
Unused
WDTCLR
Unused
WDTPS2
WDTPS1
WDTPS0
Description
Watchdog Timer Enable Bit
-
Watchdog Timer Counter Clear Bit
-
Clock Source Divider Bit 2
Clock Source Divider Bit 1
Clock Source Divider Bit 0
0
Watchdog Timer Registers
The WDT timeout delay can be adjusted by configuring
the clock divider input for the WDT time base source
The configuration and use of the VMX51C900
watchdog timer is handled by three registers:
WDTKEY, WDTCTRL and SYSCON.
clock.
To
select
the
divider
value,
the
[WDTPS2~WDTPS0] bits of the watchdog timer
control register should be set accordingly.
The WDTKEY register ensures that the watchdog timer
is not inadvertently reset in case of program
malfunction.
The following table indicates the approximate timeout
periods for different values of the WDTPSx bits of the
watchdog timer register.
The WDTCTRL register is by default configured as a
read-only register. To modify its contents, two
consecutive write operations to the WDTKEY register
must be performed as follows:
TABLE 53: TIMEOUT PERIOD AT
WDTPS [2:0]
000
WDT Period
2.048ms
MOV WDTKEY,#01Eh
MOV WDTKEY,#0E1h
001
4.096ms
010
8.192ms
011
16.384ms
32.768ms
65.536ms
131.072ms
262.144ms
Once the configuration or WDT reset operation is
complete, the WDTCTRL register can be restored to
read-only by writing the following sequence into the
WDTKEY register:
100
101
110
111
MOV WDTKEY,#0E1h
MOV WDTKEY,#01Eh
To enable the WDT, bit 7 (WDTE) of the WDTCTRL
register must be set to 1. The 16-bit counter will then
begin counting from the 250KHz oscillator divided,
according to the value of the WDTPS2~WDTPS0 bits.
TABLE 51: WATCH DOG TIMER KEY REGISTER: WDTKEY – SFR 97H
7
6
5
4
3
2
1
0
WDTKEY7:0
The WDT is cleared by setting the WDTCLR bit of the
WDTCTRL to 1. This will clear the contents of the 16-
bit counter and force it to restart.
Bit
7:0
Mnemonic
WDTKEY
Description
Watchdog Key
If the WDT overflows, the processor will be reset, the
WDR bit (7) of the SYSCON register will be set to 1
and the WDTE bit will be cleared to 0. The user should
check the WDR bit if an unexpected reset has taken
place.
______________________________________________________________________________________________
www.ramtron.com page 41 of 55
VMX51C900
TABLE 54: WATCH DOG TIMER REGISTER-SYSTEM CONTROL REGISTER (SYSCON)–SFR
BFH
WDTRESET: NOP
MOV A,PORTVAL
CPL
;IF THE WDT CAUSE THE RESET INIT PORTVAL
;TOGGLE P1 VALUE
A
7
6
5
4
3
2
1
0
MOV PORTVAL,A
MOV P1,A
WDR
Unused
ALEI
;*** SEQUENCE TO CLEAR THE WATCHDOG TIMER (SAME AS CONFIG)
Bit
7
[6:1]
0
Mnemonic
WDR
Unused
ALEI
Description
Watch Dog Timer Reset Bit
-
1: Enable Electromagnetic Interference
Reducer
0: Disable Electromagnetic Interference
Reducer
LOOP:
;MOV WDTKEY,#01EH ;UNLOCK THE WDTCTRL REG ACCESS IN
;WRITING MODE
;MOV WDTKEY,#0E1H
;MOV WDTCTRL,#10100010B
;CONFIG THE WDT TIMER
;BIT 7 - WDTEN=1 WDT ENABLE
;BIT 6 - UNUSED
;BIT 5 - WDTCLR=1 WDT CLEAR
;BIT 4:3 - UNUSED
;BIT 2:0 - WDTCLK=010 - WDT TIMEOUT = 8mS
;MOV WDTKEY,#0E1H ;LOCK THE WDTCTRL ACCESS IN WRITING
;MOV WDTKEY,#01EH
WDT initialization Example
(…)
LJMP LOOP
The following program example shows the WDT
initialization sequence and the routine to periodically
clear it.
;*** VARIABLE DEFINITION ***
CPTR
PORTVAL EQU
EQU
020H
00H
;*** PROGRAM START HERE ****
ORG 0000h
LJMP START
;*** MAIN PROGRAM START ***
ORG 0100h
;*** CHECK IF RESET WAS CAUSED BY THE WATCHDOG TIMER
START:
MOV A,SYSCON
ANL A,#80H
JNZ WDTRESET
;WDT BIT SET -> WE GOT A WDT RESET
INITWDT:
MOV WDTKEY,#01EH ;UNLOCK THE WDTCTRL REG ACCESS IN
MOV WDTKEY,#0E1H ;WRITING MODE
MOV WDTCTRL,#10000010B ;CONFIG THE WATCHDOG TIMER
;BIT 7 - WDTEN=1 WATCHDOG TIMER ENABLE
;BIT 6 - UNUSED
;BIT 5 - WDTCLR=1 WATCHDOG CLEAR
;BIT 4:3 - UNUSED
;BIT 2:0 - WDTCLK=010 - WDT TIMEOUT = 8mS
MOV WDTKEY,#0E1H ;LOCK THE WDTCTRL ACCESS IN WRITING
MOV WDTKEY,#01EH
MOV PORTVAL,#00H ;INIT PORT VALUE TO 00H
______________________________________________________________________________________________
www.ramtron.com page 42 of 55
VMX51C900
the technical literature provided with any crystal or
ceramic resonator or contact the manufacturer to
select the appropriate values for external components.
Crystal Configuration
The crystal connected to the VMX51C900 oscillator
input should be of a parallel type, operating in
fundamental mode.
FIGURE 22: CRYSTAL CONFIGURATION
The following table shows the recommended value of
the capacitors and feedback resistors used at different
operating frequencies.
XTAL1
XTAL
VMX51C900 Crystal configuration
VMX51C900
XTAL
C1
C2
3MHz
30 pF
30 pF
open
6MHz
30 pF
30 pF
open
12MHz
30 pF
30 pF
open
R
R
XTAL2
XTAL
C1
C2
16MHz
30 pF
30 pF
open
20MHz
22 pF
22 pF
open
25MHz
15 pF
15 pF
62KO
C1
C2
R
Note: Oscillator circuits may differ with various crystals
or ceramic resonators of higher oscillation frequency.
Crystals or ceramic resonator characteristics vary from
one manufacturer to the other. The user should review
______________________________________________________________________________________________
www.ramtron.com page 43 of 55
VMX51C900
Operating Conditions
TABLE 55: OPERATING CONDITIONS
Symbol
TA
TS
VCC5
Fosc
Description
Min.
-40
-55
4.5
3.0
Typ.
25
25
5.0
-
Max.
+85
155
5.5
Unit
ºC
ºC
V
MHz
Remarks
Ambient temperature under bias
Operating temperature
Storage temperature
Supply voltage
Oscillator Frequency
25
DC Characteristics
TABLE 56: DC CHARACTERISTICS
Symbol Parameter
Valid
Port 0,1,2,3,4,#EA
RES, XTAL1
Port 0,1,2,3,4,#EA
RES, XTAL1
Port 0, ALE, #PSEN
Port 1,2,3,4
Min.
-0.5
0
Max.
1.0
0.8
VCC+0.5
Unit
V
V
V
V
V
V
V
Test Conditions
VCC=5V
VCC=5V
VCC=5V
VCC=5V
IOL=3.2mA
IOL=1.6mA
IOH=-800uA
VIL1
Input Low Voltage
VIL2
Input Low Voltage
Input High Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
VIH1
VI H2
VOL1
VOL2
2.0
70% VCC VCC+0.5
0.4
0.4
2.4
VOH1
Output High Voltage
Port 0
90%VCC
2.4
V
V
V
IOH=-80uA
IOH=-60uA
IOH=-10uA
Port
1,2,3,4,ALE,#PSEN
VOH2
IIL
Output High Voltage
90% VCC
Logical 0 Input Current
Port 1,2,4, P3.0-P3.3
Port 1,2,3,4,P3.0-P3.3
Port 0, #EA
-50
-650
10
uA
Vin=0.45V
Logical Transition
Current
uA
Vin=2.0V
ITL
ILI
Input Leakage Current
uA
0.45V<Vin< 5V
R RES Reset Pull-down
Resistance
RES
18
90
10
Kohm
C-10
Pin Capacitance
pF
Fre=1 MHz, Ta=25°C
20
10
100
mA
mA
uA
Active mode, 16MHz
Idle mode, 16MHz
Power down mode
ICC
Power Supply Current
VDD
FIGURE 23: ICC ACTIVE MODE TEST CIRCUIT
FIGURE 24: ICC IDLE MODE TEST CIRCUIT
Vcc
Vcc
Vcc
Icc
Icc
VCC
VCC
8
RST
8
PO
EA
PO
EA
RST
VMX51C900
XTAL2
VMX51C900
(NC)
(NC)
XTAL2
XTAL1
VSS
Clock Signal
XTAL1
VSS
Clock Signal
______________________________________________________________________________________________
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VMX51C900
AC Characteristics
TABLE 57: AC CHARACTERISTICS
Fosc 16
Variable Fosc
Valid
Symbol
T LHLL
T AVLL
T LLAX
T LLIV
T LLPL
T PLPH
T PLIV
Parameter
ALE Pulse Width
Cycle
Unit
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Min.
Type Max.
Min.
Type
Max.
RD/WRT 115
RD/WRT 43
RD/WRT 53
RD
2xT - 10
T - 20
T - 10
Address Valid to ALE Low
Address Hold after ALE Low
ALE Low to Valid Instruction In
ALE Low to #PSEN low
#PSEN Pulse Width
#PSEN Low to Valid Instruction In
Instruction Hold after #PSEN
Instruction Float after #PSEN
Address to Valid Instruction In
#PSEN Low to Address Float
#RD Pulse Width
240
177
4xT - 10
3xT -10
RD
RD
RD
RD
RD
RD
RD
RD
WRT
RD
RD
RD
RD
RD
RD/WRT 178
RD/WRT 230
WRT
WRT
WRT
RD
53
173
T - 10
3xT - 15
T PXIX
T PXIZ
0
0
87
292
10
T + 25
5xT - 20
10
T AVIV
T PLAZ
T RLRH
T WLWH
T RLDV
T RHDX
T RHDZ
T LLDV
T AVDV
T LLYL
T AVYL
T QVWH
T QVWX
T WHQX
T RLAZ
T YALH
T CHCL
T CLCX
T CLCH
T CHCX
365
365
6xT - 10
6xT - 10
#WR Pulse Width
#RD Low to Valid Data In
Data Hold after #RD
302
5xT - 10
0
0
Data Float after #RD
145
590
542
197
2xT + 20
8xT - 10
9xT - 20
3xT + 10
ALE Low to Valid Data In
Address to Valid Data In
ALE low to #WR High or #RD Low
Address Valid to #WR or #RD Low
Data Valid to #WR High
Data Valid to #WR Transition
Data Hold after #WR
#RD Low to Address Float
#W R or #RD High to ALE High
Clock Fall Time
3xT - 10
4xT - 20
7xT - 35
T - 25
403
38
73
T + 10
5
RD/WRT 53
72
T -10
T+10
Clock Low Time
Clock Rise Time
Clock High Time
T,TCLCL Clock Period
63
1/fosc
______________________________________________________________________________________________
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VMX51C900
Data Memory Read Cycle Timing
The following timing diagram shows the signal timing of Data Memory Read Cycle.
FIGURE 25: DATA MEMORY READ CYCLE TIMING
T12
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12
T1
T2
T3
OSC
ALE
1
2
#PSEN
#RD
5
7
3
ADDRESS A15-A8
PORT2
PORT0
3
4
6
8
INST in
Float
A7-A0
Float
Data in
Float
ADDRESS or
Float
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www.ramtron.com page 46 of 55
VMX51C900
Program Memory Read Cycle Timing
The following timing diagram shows the signal timing during Program Memory Read Cycle.
FIGURE 26: PROGRAM MEMORY READ CYCLE
T12
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12
T1
T2
T3
OSC
ALE
1
2
5
7
#PSEN
#RD,#WR
PORT2
PORT0
3
ADDRESS A15-A8
ADDRESS A15-A8
3
4
6
8
Float
A7-A0 Float
INST in Float
A7-A0 Float
INST in Float
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www.ramtron.com page 47 of 55
VMX51C900
Data Memory Write Cycle Timing
The following timing diagram shows the signal timing during Data Memory Write Cycle.
FIGURE 27: DATA MEMORY WRITE CYCLE TIMING
T12
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12
T1
T2
T3
OSC
ALE
1
#PSEN
#WR
5
6
2
ADDRESS A15-A8
3
PORT2
PORT0
2
4
INST in
Float
A7-A0
Data out
ADDRESS or
Float
______________________________________________________________________________________________
www.ramtron.com page 48 of 55
VMX51C900
I/O Ports Timing
The following timing diagram shows I/O Port Timing.
FIGURE 28: I/O PORTS TIMING
T7
T8
T9
T10 T11 T12
T1
T2
T3
T4
T5
T6
T7
T8
X1
Sampled
Inputs P0,P1
Sampled
Inputs P2,P3
Output by Mov
Px, Src
Current Data
Next Data
Sampled
RxD at Serial
Port Shift
Clock Mode 0
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www.ramtron.com page 49 of 55
VMX51C900
Timing Requirement of the External Clock (VSS = 0v is assumed)
FIGURE 29: TIMING REQUIREMENT OF EXTERNAL CLOCK (VSS= 0.0V IS ASSUMED)
TCLCL
Vdd - 0.5V
70% Vdd
20% Vdd-0.1V
0.45V
TCLCX
TCHCX
TCHCL
TCLCH
External Program Memory Read Cycle
The following timing diagram shows the signal timing during an External Program Memory Read Cycle.
FIGURE 30: EXTERNAL PROGRAM MEMORY READ CYCLE
TPLPH
#PSEN
TLLPL
TLHLL
ALE
TPXIZ
TAVLL TLLAX
A0-A7
TPLIV
TPXIX
TPLAZ
TAVIV
Instruction IN
A0-A7
PORT 0
PORT2
P2.0-P2.7 or AB-A15 from DPH
A8-A15
______________________________________________________________________________________________
www.ramtron.com page 50 of 55
VMX51C900
External Data Memory Read Cycle
The following timing diagram shows the signal timing during an External Data Memory Read Cycle.
FIGURE 31: EXTERNAL DATA MEMORY READ CYCLE
#PSEN
TYHLH
ALE
TLLDV
TRLRH
TLLYL
#RD
TRLDV
TRHDZ
TRHDX
DATA IN
TAVLL
TLLAX
A0-A7
TRLAZ
A0-A7
From PCL
INSTRL
IN
PORT 0
PORT 2
From Ri or DPL
TAVYL
TAVDV
P2.0-P2.7 or A8 -A15 from DPH
A8-A15 from PCH
______________________________________________________________________________________________
www.ramtron.com page 51 of 55
VMX51C900
External Data Memory Write Cycle
The following timing diagram shows the signal timing during an External Data Memory Write Cycle.
FIGURE 32: EXTERNAL DATA MEMORY WRITE CYCLE
#PSEN
TYHLH
ALE
TLHLL
TLLYL
TWLWH
#WR
TAVLL
TQVWX
TWHQX
TLLAX
TQVWH
A0-A7
From PCL
A0-A7
From Ri or DPL
INSTRL
IN
DATA OUT
PORT 0
PORT 2
TAVYL
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
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www.ramtron.com page 52 of 55
VMX51C900
Plastic Chip Carrier (PLCC-44)
L
GE
VMX51C900
PLCC-44
E
HE
Y
A2
A1
A
D
TABLE 58: DIMENSIONS OF PLCC-44 CHIP CARRIER
HD
Dimension in inch
Symbol
Dimension in mm
Minimal/Maximal
-/4.70
Minimal/Maximal
A
-/0.185
Al
A2
bl
b
C
D
E
e
GD
GE
HD
HE
L
0.020/-
0.51/
0.145/0.155
0.026/0.032
0.016/0.022
0.008/0.014
0.648/0.658
0.648/0.658
0.050 BSC
0.590/0.630
0.590/0.630
0.680/0.700
0.680/0.700
0.090/0.110
-/0.004
3.68/3.94
0.66/0.81
0.41/0.56
0.20/0.36
16.46/16.71
16.46/16.71
1.27 BSC
14.99/16.00
14.99/16.00
17.27/17.78
17.27/17.78
2.29/2.79
-/0.10
C
e
b
b1
GD
Note:
?
1. Dimensions D & E do not include interlead Flash.
2. Dimension B1 does not include dambar
protrusion/intrusion.
?y
/
/
3. Controlling dimension: Inch
4. General appearance spec should be based on
final visual inspection spec.
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www.ramtron.com page 53 of 55
VMX51C900
C
Plastic Quad Flat Package (QFP-44)
L
L1
S
S
VMX51C900
b
D2 D1 D
QFP-44
2
A2
R1
A1
A
Gage Plane
0.25mm
3
R2
E2
E1
E
TABLE 59: DIMENSIONS OF QFP-44 CHIP CARRIER
Dimension in in.
Symbol
Dimension in mm
Minimal/Maximal
-/2.55
Minimal/Maximal
A
-/0.100
Al
A2
b
c
D
D1
D2
E
E1
E2
e
0.006/0.014
0.071 / 0.087
0.012/0.018
0.004 / 0.009
0.520 BSC
0.394 BSC
0.315
0.520 BSC
0.394 BSC
0.315
0.031 BSC
0.029 / 0.041
0.063
0.005/-
0.005/0.012
0.008/-
0.15/0.35
1.80/2.20
0.30/0.45
0.09/0.20
13.20 BSC
10.00 BSC
8.00
13.20 BSC
10.00 BSC
8.00
0.80 BSC
0.73/1.03
1.60
0.13/-
0.13/0.30
0.20/-
e1
C
Seating Plane
e
L
L1
R1
R2
S
Note:
1. Dimensions D1 and E1 do not include mold
protrusion.
0
0°/7°
0°/ -
10° REF
7° REF
0.004
as left
as left
as left
as left
2. Allowance protrusion is 0.25mm per side.
3. Dimensions D1 and E1 do not include mold
mismatch and are determined datum plane.
4. Dimension b does not include dambar
protrusion.
? 1
? 2
? 3
?C
0.10
5. Allowance dambar protrusion shall be 0.08 mm
total in excess of the b dimension at maximum
material condition. Dambar cannot be located
on the lower radius of the lead foot.
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www.ramtron.com page 54 of 55
VMX51C900
Ordering Information
Device Number Structure
VMX51C900 Ordering Options
Device Number
Flash Size
RAM Size
Package
Option
PLCC-44
QFP-44
DIP-40
PLCC-44
QFP-44
DIP-40
Voltage
Temperature
Frequency
VMX51C900-25-L
VMX51C900-25-Q
VMX51C900-25-P
VMX51C900-25-LG
VMX51C900-25-QG
VMX51C900-25-PG
8KB
8KB
8KB
8KB
8KB
8KB
256B
256B
256B
256B
256B
256B
4.5V to 5.5V
4.5V to 5.5V
4.5V to 5.5V
4.5V to 5.5V
4.5V to 5.5V
4.5V to 5.5V
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
Disclaimers
Right to make change - Ramtron reserves the right to make changes to its products - including circuitry, software and services - without notice at
any time. Customers should obtain the most current and relevant information before placing orders.
Use in applications - Ramtron assumes no responsibility or liability for the use of any of its products, and conveys no license or title under any
patent, copyright or mask work right to these products and makes no representations or warranties that these products are free from patent,
copyright or mask work right infringement unless otherwise specified. Customers are responsible for product design and applications using Ramtron
parts. Ramtron assumes no liability for applications assistance or customer product design.
Life support – Ramtron products are not designed for use in life support systems or devices. Ramtron customers using or selling Ramtron products
for use in such applications do so at their own risk and agree to fully indemnify Ramtron for any damages resulting from such applications.
______________________________________________________________________________________________
www.ramtron.com
page 55 of 55
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