VRS51L570-25-L-G_技术文档

VRS51x570/580

Datasheet

Rev 1.2

Versa 8051 MCUs with 32/64KB

Overview

Feature Set

·

80C51/80C52 pin compatible

The VRS51x570 and the VRS51x580 are low cost 8-bit

microcontrollers based on the standard 80C51

12 clock periods per machine cycle

32KB / 64KB on-chip Flash memory

1024 Bytes on-chip data RAM

36 I/O lines: P0-P3 = 8-bit, P4 = 4-bit

5-Channel PWM on P1.3 to P1.7

Full duplex serial port (UART)

Three 16-bit Timers/Counters

Watch Dog Timer

8-bit Unsigned Division / Multiply

BCD arithmetic

Direct and Indirect Addressing

Two levels of interrupt priority and nested interrupts

Power saving modes

Code protection function

microcontroller family architecture.

They are pin

compatible and drop-in replacements for most 8051

MCUs.

Ideal for a wide range of applications requiring large

amounts of program/data memory, coupled with

comprehensive peripheral support, the VRS51x570/580

devices include 32KB/64KB of Flash memory,

respectively, and 1KB of SRAM, 5 PWM output

channels, a UART, three 16-bit timers, a Watch Dog

timer and power down features.

These devices also include a fifth, 4-bit, I/O port mapped

into the “no connect” pins of the standard 8051/52

package. This provides a total of 36 I/Os while

maintaining compatibility with standard 80C51/52 pin

outs.

Operates at a clock frequency of up to 40MHz

Low EMI (inhibit ALE)

Programming voltage: 12V

Industrial Temperature range (-40°C to +85°C)

5V and 3V versions available (see Ordering information.)

FIGURE 2: VRS51X570 / VRS51X580 PLCC AND QFP PINOUT DIAGRAMS

The VRS51x570 and VRS51x580 are available in

PLCC-44, QFP-44 and DIP-40 packages in the Industrial

temperature range. The Flash memory can be

programmed using programmers from Ramtron or other

3^rdparty commercial programmer suppliers.

6

40

7

1

PWM2/P1.5

39

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

#EA

PWM3/P1.6

PWM4/P1.7

RESET

FIGURE 1: VRS51X570 / VRS51X580 FUNCTIONAL DIAGRAM

RXD/P3.0

P4.3

VRS51x570/580

PLCC-44

P4.1

TXD/P3.1

#INT0/P3.2

ALE

#PSEN

P2.7/A15

P2.6/A14

P2.5/A13

#INT1/P3.3

T0/P3.4

T1/P3.5

8051

17

18

29

ADDRESS/

28

PROCESSOR

DATA BUS

64KB

FLASH

PORT 0

8

4

1024 Bytes of

RAM

PORT 1

PORT 2

PORT 3

PORT 4

UART

33

23

22

34

P0.3/AD3

P2.4/A12

P0.2/AD2

P0.1/AD1

P2.3/A11

P2.2/A10

2 INTERRUPT

INPUTS

P0.0/AD0

VDD

P2.1/A9

P2.0/A8

P4.0

VRS51x570/580

QFP-44

P4.2

TIMER 0

TIMER 1

TIMER 2

T2/P1.0

VSS

T2EX/P1.1

P1.2

XTAL1

XTAL2

POWER

CONTROL

PWM0/P1.3

PWM1/P1.4

#RD/P3.7

#WR/P3.6

44

12

11

1

WATCHDOG

TIMER

RESET

PWM

5

Ramtron International Corporation

1850 Ramtron Drive Colorado Springs

Colorado, USA, 80921

http://www.ramtron.com

MCU customer service: 1-800-943-4625, 1-514-871-2447, ext. 208

1-800-545-FRAM, 1-719-481-7000

?

page 1 of 49

VRS51x570/580

Pin Descriptions for QFP-44

TABLE 1: PIN DESCRIPTIONS FOR QFP-44/

QFP

- 44

Name

P2.6

A14

P2.7

A15

I/O

O

I/O

O

I/O

I

I/O

-

Function

QFP

- 44

Name

I/O

Function

PWM Channel 2

Bit 5 of Port 1

PWM Channel 3

Bit 6 of Port 1

PWM Channel 4

Bit 7 of Port 1

Reset

Receive Data

Bit 0 of Port 3

Bit 3 of Port 4

Transmit Data &

Bit 1 of Port 3

External Interrupt 0

Bit 2 of Port 3

External Interrupt 1

Bit 3 of Port 3

Timer 0

Bit 4 of Port 3

Timer 1 & 3

Bit 5 of Port

Ext. Memory Write

Bit 6 of Port 3

Ext. Memory Read

Bit 7 of Port 3

Oscillator/Crystal Output

Oscillator/Crystal In

Ground

Bit 0 of Port 4

Bit 0 of Port 2

Bit 8 of External Memory Address

Bit 1 of Port 2

Bit 6 of Port 2

24

25

Bit 14 of External Memory Address

Bit 7 of Port 2

Bit 15 of External Memory Address

Program Store Enable

Address Latch Enable

Bit 1 of Port 4

PWM2

P1.5

PWM3

P1.6

PWM4

P1.7

RES

RXD

P3.0

P4.3

TXD

P3.1

#INT0

P3.2

#INT1

P3.3

T0

O

I/O

O

I/O

O

I/O

I

1

2

26

27

28

29

#PSEN

ALE

P4.1

#EA

P0.7

AD7

P0.6

AD6

P0.5

AD5

P0.4

AD4

P0.3

AD3

P0.2

AD2

P0. 1

AD1

P0.0

AD0

VDD

P4.2

T2

3

4

5

6

7

External Access

Bit 7 Of Port 0

I

30

31

32

33

34

35

36

37

Data/Address Bit 7 of External Memory

Bit 6 of Port 0

Data/Address Bit 6 of External Memory

Bit 5 of Port 0

Data/Address Bit 5 of External Memory

Bit 4 of Port 0

Data/Address Bit 4 of External Memory

Bit 3 Of Port 0

I/O

O

I/O

I

I/O

I

I/O

I

I/O

I

I/O

O

I/O

O

I/O

O

8

9

Data/Address Bit 3 of External Memory

Bit 2 of Port 0

10

11

12

13

P3.4

T1

Data/Address Bit 2 of External Memory

Bit 1 of Port 0 & Data

Address Bit 1 of External Memory

Bit 0 Of Port 0 & Data

Address Bit 0 of External Memory

VCC

P3.5

#WR

P3.6

#RD

P3.7

XTAL2

XTAL1

VSS

P4.0

P2.0

A8

38

39

I/O

I

I/O

I

I/O

Bit 2 of Port 4

14

15

16

17

Timer 2 Clock Out

I

-

40

P1.0

T2EX

P1.1

P1.2

Bit 0 of Port 1

Timer 2 Control

I/O

O

41

42

Bit 1 of Port 1

Bit 2 of Port 1

18

19

20

21

22

23

P2.1

A9

P2.2

A10

P2.3

A11

P2.4

A12

I/O

O

I/O

O

I/O

O

I/O

O

PWM0

P1.3

O

PWM Channel 0

Bit 3 of Port 1

PWM Channel 1

Bit 4 of Port 1

43

44

Bit 9 of External Memory Address

Bit 2 of Port 2

Bit 10 of External Memory Address

Bit 3 of Port 2 &

Bit 11 of External Memory Address

Bit 4 of Port 2

Bit 12 of External Memory Address

Bit 5 of Port 2

I/O

O

PWM1

P1.4

I/O

P2.5

A13

I/O

O

Bit 13 of External Memory Address

33

23

22

34

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

VDD

P2.4/A12

P2.3/A11

P2.2/A10

P2.1/A9

P2.0/A8

P4.0

VRS51x570/580

QFP-44

P4.2

T2/P1.0

VSS

T2EX/P1.1

P1.2

XTAL1

XTAL2

PWM0/P1.3

PWM1/P1.4

#RD/P3.7

#WR/P3.6

44

12

11

1

________________________________________________________________________________________________

www.ramtron.com page 2 of 49

VRS51x570/580

Pin Descriptions for PLCC-44

TABLE 2: PIN DESCRIPTIONS FOR PLCC-44

PLCC

- 44

1

PLCC

- 44

Name

P4.2

I/O

Function

Bit 2 of Port 4

Name

P2.0

A8

P2.1

A9

I/O

Function

I/O

I

I/O

I

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

I

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

Bit 0 of Port 2

24

25

26

27

28

29

30

31

T2

Timer 2 Clock Out

Bit 0 of Port 1

Timer 2 Control

Bit 1 of Port 1

Bit 2 of Port 1

PWM Channel 0

Bit 3 of Port 1

PWM Channel 1

Bit 4 of Port 1

PWM Channel 2

Bit 5 of Port 1

PWM Channel 3

Bit 6 of Port 1

PWM Channel 4

Bit 7 of Port 1

Reset

Bit 8 of External Memory Address

Bit 1 of Port 2

Bit 9 of External Memory Address

Bit 2 of Port 2

Bit 10 of External Memory Address

Bit 3 of Port 2 &

Bit 11 of External Memory Address

Bit 4 of Port 2

Bit 12 of External Memory Address

Bit 5 of Port 2

Bit 13 of External Memory Address

Bit 6 of Port 2

Bit 14 of External Memory Address

Bit 7 of Port 2

Bit 15 of External Memory Address

Program Store Enable

Address Latch Enable

Bit 1 of Port 4

2

P1.0

T2EX

P1.1

P1.2

PWM0

P1.3

PWM1

P1.4

PWM2

P1.5

PWM3

P1.6

PWM4

P1.7

RES

RXD

P3.0

P4.3

TXD

P3.1

#INT0

P3.2

#INT1

P3.3

T0

P3.4

T1

P3.5

#WR

P3.6

#RD

3

4

5

P2.2

A10

P2.3

A11

P2.4

A12

P2.5

A13

P2.6

A14

P2.7

A15

#PSEN

ALE

P4.1

#EA

P0.7

6

7

8

9

10

11

12

13

32

33

34

35

O

I/O

I

I/O

I

Receive Data

I/O

O

I/O

I

I/O

I

I/O

I

I/O

I

I/O

O

I/O

O

I/O

O

Bit 0 of Port 3

Bit 3 of Port 4

Transmit Data &

Bit 1 of Port 3

External Interrupt 0

Bit 2 of Port 3

External Interrupt 1

Bit 3 of Port 3

Timer 0

Bit 4 of Port 3

Timer 1 & 3

Bit 5 of Port

Ext. Memory Write

Bit 6 of Port 3

Ext. Memory Read

Bit 7 of Port 3

Oscillator/Crystal Output

Oscillator/Crystal In

Ground

External Access

Bit 7 Of Port 0

36

37

38

39

40

Data/Address Bit 7 of External

Memory

AD7

P0.6

AD6

P0.5

AD5

P0.4

AD4

P0.3

AD3

P0.2

AD2

I/O

14

15

16

17

18

19

Bit 6 of Port 0

Data/Address Bit 6 of External

Memory

Bit 5 of Port 0

Data/Address Bit 5 of External

Memory

Bit 4 of Port 0

Data/Address Bit 4 of External

Memory

Bit 3 Of Port 0

P3.7

XTAL2

XTAL1

VSS

Data/Address Bit 3 of External

Memory

20

21

22

23

I

-

Bit 2 of Port 0

41

42

Data/Address Bit 2 of External

Memory

P4.0

I/O

Bit 0 of Port 4

P0. 1

AD1

P0.0

AD0

VDD

I/O

-

Bit 1 of Port 0 & Data

Address Bit 1 of External Memory

Bit 0 Of Port 0 & Data

Address Bit 0 of External Memory

VCC

43

44

6

40

7

1

PWM2/P1.5

39

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

#EA

PWM3/P1.6

PWM4/P1.7

RESET

RXD/P3.0

P4.3

VRS51x570/580

PLCC-44

P4.1

ALE

TXD/P3.1

#INT0/P3.2

#PSEN

P2.7/A15

P2.6/A14

P2.5/A13

#INT1/P3.3

T0/P3.4

T1/P3.5

17

18

29

28

________________________________________________________________________________________________

www.ramtron.com page 3 of 49

VRS51x570/580

VRS51x570 – VRS51x580 DIP40 Pin

Descriptions

Name

P2.0

A8

P2.1

A9

P2.2

A10

P2.3

A11

P2.4

A12

P2.5

A13

P2.6

A14

P2.7

A15

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

Function

Bit 0 of Port 2

Bit 8 of External Memory Address

Bit 1 of Port 2

Bit 9 of External Memory Address

Bit 2 of Port 2

Bit 10 of External Memory Address

Bit 3 of Port 2 &

Bit 11 of External Memory Address

Bit 4 of Port 2

Bit 12 of External Memory Address

Bit 5 of Port 2

Bit 13 of External Memory Address

Bit 6 of Port 2

Bit 14 of External Memory Address

Bit 7 of Port 2

Bit 15 of External Memory Address

Program Store Enable

Address Latch Enable

External Access

Flash programming voltage input

Bit 7 Of Port 0

Data/Address Bit 7 of External

Memory

Bit 6 of Port 0

Data/Address Bit 6 of External

Memory

Bit 5 of Port 0

Data/Address Bit 5 of External

Memory

Bit 4 of Port 0

Data/Address Bit 4 of External

Memory

Bit 3 Of Port 0

Data/Address Bit 3 of External

Memory

Bit 2 of Port 0

Data/Address Bit 2 of External

Memory

Bit 1 of Port 0 & Data

Address Bit 1 of External Memory

Bit 0 Of Port 0 & Data

Address Bit 0 of External Memory

Supply input

DIP40

21

TABLE 3: VRS51X570 – VRS51X580 PIN DESCRIPTIONS FOR DIP40 PACKAGE

22

23

24

25

26

27

28

DIP40

Name

T2

P1.0

T2EX

P1.1

P1.2

PWM0

P1.3

PWM1

P1.4

PWM2

P1.5

PWM3

P1.6

PWM4

P1.7

RESET

RXD

P3.0

TXD

P3.1

#INT0

P3.2

#INT1

P3.3

I/O

I

Function

Timer 2 Clock Out

1

I/O

I

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

I

I/O

O

I/O

I

I/O

I

I/O

I

I/O

I

I/O

O

I/O

O

I/O

O

Bit 0 of Port 1

Timer 2 Control

Bit 1 of Port 1

Bit 2 of Port 1

PWM Channel 0

Bit 3 of Port 1

PWM Channel 1

Bit 4 of Port 1

PWM Channel 2

Bit 5 of Port 1

PWM Channel 3

Bit 6 of Port 1

PWM Channel 4

Bit 7 of Port 1

Reset

2

3

4

5

6

7

29

30

#PSEN

ALE

#EA /

VPP

P0.7

O

8

9

31

I

I/O

Receive Data

10

32

Bit 0 of Port 3

Transmit Data &

Bit 1 of Port 3

External Interrupt 0

Bit 2 of Port 3

External Interrupt 1

Bit 3 of Port 3

Timer 0

Bit 4 of Port 3

Timer 1 & 3

Bit 5 of Port

Ext. Memory Write

Bit 6 of Port 3

Ext. Memory Read

Bit 7 of Port 3

Oscillator/Crystal Output

Oscillator/Crystal In

Ground

AD7

P0.6

AD6

P0.5

AD5

P0.4

AD4

P0.3

AD3

P0.2

AD2

11

12

13

14

15

16

17

33

34

35

36

T0

P3.4

T1

P3.5

#WR

P3.6

#RD

P3.7

37

38

18

19

20

XTAL2

XTAL1

VSS

I

-

P0. 1

AD1

P0.0

AD0

VDD

I/O

-

39

40

T2 / P1.0

1

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

VDD

T2EX / P1.1

P1.2

2

P0.0 / AD0

P0.1 / AD1

P0.2 / AD2

P0.3 / AD3

P0.4 / AD4

P0.5 / AD5

P0.6 / AD6

P0.7 / AD7

#EA / VPP

ALE

3

PWM0 / P1.3

PWM1 / P1.4

PWM2 / P1.5

PWM3 / P1.6

PWM4 / P1.7

RESET

4

5

6

7

8

9

VRS51x570

VRS51x580

DIP-40

RXD / P3.0

TXD / P3.1

#INT0 / P3.2

#INT1 / P3.3

T0 / P3.4

10

11

12

13

14

15

16

17

18

19

20

PSEN

P2.7 / A15

P2.6 / A14

P2.5 / A13

P2.4 / A12

P2.3 / A11

P2.2 / A10

P2.1 / A9

P2.0 / A8

T1 / P3.5

#WR / P3.6

#RD / P3.7

XTAL2

XTAL1

VSS

________________________________________________________________________________________________

www.ramtron.com page 4 of 49

VRS51x570/580

Instruction Set

Size

(bytes)

Mnemonic

Description

Instr. Cycles

The following tables describe the instruction set of the Boolean Instruction

CLR C

VRS51x570 and VRS51x580 devices. The instructions are

CLR bit

Clear Carry bit

Clear bit

Set Carry bit to 1

Set bit to 1

Complement Carry bit

Complement bit

Logical AND between Carry and bit

Logical AND between Carry and not bit

Logical ORL between Carry and bit

Logical ORL between Carry and not bit

Copy bit value into Carry

Copy Carry value into Bit

1

2

1

2

1

2

1

2

1

2

SETB C

SETB bit

CPL C

CPL bit

functional and binary code compatible with industry

standard 8051s.

ANL C,bit

ANL C,#bit

TABLE 4: LEGEND FOR INSTRUCTION SET TABLE

ORL C,bit

Symbol

A

Rn

Direct

@Ri

rel

Function

Accumulator

Register R0-R7

Internal register address

Internal register pointed to by R0 or R1 (except MOVX)

Two's complement offset byte

Direct bit address

8-bit constant

16-bit constant

ORL C,#bit

MOV C,bit

MOV bit,C

Data Transfer Instructions

MOV A, Rn

MOV A, direct

MOV A, @Ri

MOV A, #data

MOV Rn, A

MOV Rn, direct

MOV Rn, #data

MOV direct, A

MOV direct, Rn

MOV direct, direct

MOV direct, @Ri

MOV direct, #data

MOV @Ri, A

MOV @Ri, direct

MOV @Ri, #data

MOV DPTR, #data

MOVC A, @A+DPTR

Move register to A

Move direct byte to A

Move data memory to A

Move immediate to A

1

2

1

2

1

2

3

2

3

1

2

3

1

2

1

2

1

2

1

2

1

2

1

2

1

bit

#data

#data 16

addr 16

addr 11

Move A to register

16-bit destination address

11-bit destination address

Move direct byte to register

Move immediate to register

Move A to direct byte

Move register to direct byte

Move direct byte to direct byte

Move data memory to direct byte

Move immediate to direct byte

Move A to data memory

Move direct byte to data memory

Move immediate to data memory

Move immediate to data pointer

Move code byte relative DPTR to A

Move code byte relative PC to A

Move external data (A8) to A

Move external data (A16) to A

Move A to external data (A8)

Move A to external data (A16)

Push direct byte onto stack

Pop direct byte from stack

Exchange A and register

TABLE 5: VRS51X570/VRS51X580 INSTRUCTION SET

Size

(bytes)

Mnemonic

Description

Instr. Cycles

Arithmetic instructions

ADD A, Rn

ADD A, direct

ADD A, @Ri

ADD A, #data

ADDC A, Rn

ADDC A, direct

ADDC A, @Ri

ADDC A, #data

SUBB A, Rn

SUBB A, direct

SUBB A, @Ri

SUBB A, #data

INC A

INC Rn

INC direct

INC @Ri

DEC A

DEC Rn

DEC direct

DEC @Ri

INC DPTR

MUL AB

Add register to A

Add direct byte to A

Add data memory to A

Add immediate to A

Add register to A with carry

Add direct byte to A with carry

Add data memory to A with carry

Add immediate to A with carry

Subtract register from A with borrow

Subtract direct byte from A with borrow

Subtract data mem from A with borrow

Subtract immediate from A with borrow

Increment A

Increment register

Increment direct byte

Increment data memory

Decrement A

Decrement register

Decrement direct byte

Decrement data memory

Increment data pointer

Multiply A by B

Divide A by B

Decimal adjust A

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

4

1

MOVC A, @A+PC

MOVX A, @Ri

MOVX A, @DPTR

MOVX @Ri, A

MOVX @DPTR, A

PUSH direct

POP direct

XCH A, Rn

XCH A, direct

XCH A, @Ri

XCHD A, @Ri

Branching Instructions

ACALL addr 11

LCALL addr 16

RET

Exchange A and direct byte

Exchange A and data memory

Exchange A and data memory nibble

Absolute call to subroutine

Long call to subroutine

Return from subroutine

Return from interrupt

Absolute jump unconditional

Long jump unconditional

Short jump (relative address)

Jump on carry = 1

Jump on carry = 0

Jump on direct bit = 1

Jump on direct bit = 0

Jump on direct bit = 1 and clear

Jump indirect relative DPTR

Jump on accumulator = 0

Jump on accumulator 1= 0

Compare A, direct JNE relative

Compare A, immediate JNE relative

Compare reg, immediate JNE relative

Compare ind, immediate JNE relative

Decrement register, JNZ relative

Decrement direct byte, JNZ relative

2

3

1

2

3

2

3

1

2

3

2

3

2

RETI

AJMP addr 11

LJMP addr 16

SJMP rel

DIV AB

DA A

JC rel

Logical Instructions

ANL A, Rn

ANL A, direct

ANL A, @Ri

ANL A, #data

ANL direct, A

ANL direct, #data

ORL A, Rn

ORL A, direct

ORL A, @Ri

ORL A, #data

ORL direct, A

ORL direct, #data

XRL A, Rn

XRL A, direct

XRL A, @Ri

XRL A, #data

XRL direct, A

XRL direct, #data

CLR A

JNC rel

JB bit, rel

JNB bit, rel

JBC bit, rel

JMP @A+DPTR

JZ rel

JNZ rel

CJNE A, direct, rel

CJNE A, #d, rel

CJNE Rn, #d, rel

CJNE @Ri, #d, rel

DJNZ Rn, rel

DJNZ direct, rel

AND register to A

AND direct byte to A

AND data memory to A

AND immediate to A

AND A to direct byte

AND immediate data to direct byte

OR register to A

OR direct byte to A

OR data memory to A

OR immediate to A

OR A to direct byte

OR immediate data to direct byte

Exclusive-OR register to A

Exclusive-OR direct byte to A

Exclusive-OR data memory to A

Exclusive-OR immediate to A

Exclusive-OR A to direct byte

Exclusive-OR immediate to direct byte

Clear A

Compliment A

Swap nibbles of A

Rotate A left

Rotate A left through carry

Rotate A right

1

2

1

2

3

1

2

1

2

3

1

2

1

2

3

1

2

1

2

1

2

1

Miscellaneous Instruction

NOP No operation

1

Rn:

@Ri:

Any of the register R0 to R7

Indirect addressing using Register R0 or R1

#data: immediate Data provided with Instruction

#data16: Immediate data included with instruction

address at the bit level

relative address to Program counter from +127 to –128

Addr11: 11-bit address range

Addr16: 16-bit address range

bit:

rel:

CPL A

SWAP A

RL A

RLC A

RR A

RRC A

#d:

Immediate Data supplied with instruction

Rotate A right through carry

________________________________________________________________________________________________

www.ramtron.com page 5 of 49

VRS51x570/580

Special Function Registers (SFR)

Addresses 80h to FFh of the SFR address space can be accessed in direct addressing mode only. The following table

lists the VRS51x570 and VRS51x580 Special Function Registers.

TABLE 6: SPECIAL FUNCTION REGISTERS (SFR)

SFR

Register

SFR

Adrs

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

90h

97h

98h

99h

9Bh

9Fh

A0h

A3h

A4h

A5h

A6h

A7h

A8h

ACh

B0h

B8h

BFh

C8h

CAh

CBh

CCh

CDh

D0h

D8h

E0h

F0h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset Value

P0

SP

-

DPL

DPH

Reserved

RCON

DBANK

PCON

TCON

TMOD

TL0

-

RAM1

DBK1

PDOWN

IE0

RAM0

DBK0

IDLE

IT0

******00b

0***0001b

00000000b

DBANKE

SMOD

TF1

GATE1

DBK3

GF1

IE1

GATE0

DBK2

GF0

IT1

C/T0

-

TR1

C/T1

TF0

M1.1

TR0

M0.1

M1.0

M0.0

-

TL1

TH0

TH1

P1

WDTLOCK

SCON

SBUF

PWMEN

WDTCON

P2

PWMCON

PWMD0

PWMD1

PWMD2

PWMD3

IE

00000000b

SM0

-

PWM4E

WDTE

SM1

-

PWM3E

SM2

-

PWM2E

WDCLR

REN

-

PWM1E

TB8

-

PWM0E

RB8

-

WDPS2

-

TI

-

RI

-

WDPS0

-

PDCK0

NP0.0

NP1.0

NP2.0

NP3.0

EX0

NP4.0

-

PX0

ALEI

CP/RL2

-

00000***b

0*0**000b

-

WDPS1

-

PDCK1

NP0.1

NP1.1

NP2.1

NP3.1

ET0

NP4.1

-

PT0

XRAME

C/T2

-

******00b

00000000b

PWMD0.4

PWMD1.4

PWMD2.4

PWMD3.4

EA

PWMD4.4

PWMD0.3

PWMD1.3

PWMD2.3

PWMD3.3

PWMD0.2

PWMD1.2

PWMD2.2

PWMD3.2

ET2

PWMD4.2

PWMD0.1

PWMD1.1

PWMD2.1

PWMD3.1

ES

PWMD4.1

PWMD0.0

PWMD1.0

PWMD2.0

PWMD3.0

ET1

PWMD4.0

NP0.2

NP1.2

NP2.2

NP3.2

EX1

NP4.2

-

PWMD4

P3

PWMD4.3

-

PS

-

IP

PT2

-

RCLK

-

PT1

-

EXEN2

PX1

00000000b

0*****00b

00000000b

SYSCON

T2CON

RCAP2L

RCAP2H

TL2

WDRESET

TF2

EXF2

TCLK

TR2

-

TH2

PSW

CY

AC

F0

RS1

RS0

P4.3

-

OV

P4.2

-

P

P4.0

-

00000000b

****1111b

P4

-

P4.1

-

ACC

B

______________________________________________________________________________________________

www.ramtron.com page 6 of 49

VRS51x570/580

Program Memory Structure

Program Memory

Data Pointer

The VRS51x570 and VRS51x580 have one 16-bit data

pointer (DPTR). The DPTR is accessed via two SFR

addresses: DPL located at address 82h and DPH

located at address 83h.

The VRS51x580 includes 64KB of on-chip Flash that

can be used as general program memory. The Flash

memory size of the VRS51x570 is 32KB.

Data Memory

FIGURE 3: VRS51X580 / VRS51X570 INTERNAL PROGRAM MEMORY

The VRS51x580 and VRS51x570 have a total of 1KB of

on-chip RAM with a 256 byte subset of this block

mapped as the internal memory structure of a standard

8052. The remaining 768 byte sub-block can be

accessed using external memory addressing via MOVX

instruction.

FFFFh

VRS580

Flash Memory

(64K Bytes)

7FFFh

FIGURE 4: VRS51X570 /VRS51X580 RAM MEMORY

02FF

VRS570

Flash Memory

(32K Bytes)

0000h

Externally mapped

768 bytes RAM

(Can by accessed by

direct external addressing

mode, using the MOVX

instruction)

Program Status Word Register

(XRAME=1)

FF

The PSW register is a bit addressable that contains

the status flags (CY, AC, OV, P), user flag (F0) and

register bank select bits (RS1, RS0) of the 8051

processor.

Upper 128 bytes

(Indirect addressing only)

SFR

(Direct addressing only)

80

7F

Lower 128 bytes

(Can be accessed in indirect and

direct addressing mode)

00

0000

TABLE 7: PROGRAM STATUS WORD REGISTER (PSW) - SFR DOH

7

CY

6

AC

5

F0

4

RS1

3

RS0

2

OV

1

-

0

P

By default, after reset, the externally mapped block of

768 bytes of RAM is disabled and can be enabled by

setting the XRAME bit of the SYSCON register located

at address BFh in the SFR space.

Bit

Mnemonic Description

7

6

5

4

3

2

1

0

CY

AC

F0

RS1

RS0

OV

-

Carry Bit

Auxiliary Carry Bit from bit 3 to 4.

User definer flag

R0-R7 Registers bank select bit 0

R0-R7 Registers bank select bit 1

Overflow flag

Lower 128 bytes (00h to 7Fh, Bank 0 & Bank 1)

The lower 128 bytes of data memory (from 00h to 7Fh)

is summarized as follows:

-

·

Address range 00h to 7Fh can be accessed in

direct and indirect addressing modes.

Address range 00h to 1Fh includes R0-R7

registers area.

P

Parity flag

RS1

RS0

Active Bank

Address

0

1

0

1

0

1

0

1

2

3

00h-07h

08h-0Fh

10h-17h

18-1Fh

·

Address range 20h to 2Fh is bit addressable.

Address range 30h to 7Fh is not bit addressable

and can be used as general-purpose storage.

______________________________________________________________________________________________

www.ramtron.com page 7 of 49

VRS51x570/580

Upper 128 bytes (80h to FFh, Bank 2 & Bank 3)

The default setting of the RAM1 and RAM0 bits is 00

(page 0). Each page has 256 bytes.

The upper 128 bytes of the data memory ranging from

80h to FFh can be accessed using indirect addressing

or by using the bank mapping in direct addressing

mode.

TABLE 8: INTERNAL RAM CONTROL REGISTER (RCON) - SFR 85H

7

6

5

4

3

2

1

0

Unused

RAM1

RAM0

Bit

7

6

5

4

3

2

1

0

Mnemonic Description

FIGURE 5: VRS51X570 / VRS51X580 INTERNAL LOWER 256 BYTES RAM STRUCTURE

Unused

RAM1

-

FFh

SFR Area

Direct or Bit Access

Only

128 Bytes of

Indirect Access RAM

These two bits are used with Rn of instruction

MOVX @Rn, n=1,0 for mapping (see section

on extended 768 bytes)

(SP, R0,R1)

DPH

RAM0

DPL

SP

85

84

83

82

81

80

P0

RAM1, RAM0

00

01

10

Mapped area

000h-0FFh

100h-1FFh

200h-2FFh

XY00h-XYFF*

80h

7Fh

80 Bytes of

General Purpose RAM

11

30h

2Fh

*Externally generated

7F

77

7E

76

7D

75

7C

74

7B

73

7A

72

79

71

78

70

0F

07

0E

06

0D

05

0C

04

0B

03

0A

02

09

01

08

00

Example:

20h

18h

10h

08h

00h

R7

-

R0

Registers Bank 3

Registers Bank 2

Registers Bank 1

Registers Bank 0

Suppose that RAM1, RAM0 are set to 0 and 1 respectively

and Rn has a value of 45h.

R7

-

R0

R7

-

R0

R7

-

Performing MOVX @Rn, A, (where n is 0 or 1) allows the

user to transfer the value of A to the expanded RAM at

address 145h (page 1).

R0

Note that when both RAM1, RAM0 are set to 1, the

value of P2 defines the upper byte and Rn defines the

lower byte of the external address. In this case the

device will access off-chip memory in the external

memory space using the external memory control

signals, Off chip peripherals can therefore be mapped

into the “P2value”00h to “P2value”FFh address range.

Expanded RAM Access Using the MOVX @DPTR

Instruction (0000-02FF, Bank4-Bank15)

The 768 bytes of the expanded RAM data memory

occupy addresses 0000h to 02FFh. This block can be

accessed using external direct addressing (i.e. using

the MOVX instruction) or by using bank mapping direct

addressing.

Note that when accessing addresses above 02FFh, the

VRS51x570/VRS51x580 devices will access off-chip

memory in the external memory space using the

external memory control signals.

Expanded RAM Control Register

The 768 bytes of expanded RAM can also be accessed

using the MOVX @Rn instruction (where n = 0,1). The

scope of this instruction is limited to a data range of

256 bytes and therefore the internal RAM Control

Register RCON should be used to select which 256

byte block will be accesseded by the MOVX @Rn

instruction (configuring by bits RAM0 and RAM1).

______________________________________________________________________________________________

www.ramtron.com page 8 of 49

VRS51x570/580

TABLE 10: BANK MAPPING DIRECT ADDRESSING MODE

Data Bank Control Register

040h~07fh

mapping

address

DBK3

DBK2

DBK1

BSO

Note

The DBANK register allows the user to enable the Data

Bank Select function and map the entire content of the

RAM memory in the range of 40h to 7Fh for

applications that would require direct addressing of the

expanded RAM content.

Lower 128 bytes

RAM

Lower 128 bytes

RAM

Upper 128 bytes

RAM

Upper 128 bytes

RAM

On-chip externally

mapped 768 bytes

RAM

On-chip externally

mapped 768 bytes

RAM

On-chip externally

mapped 768 bytes

RAM

On-chip externally

mapped 768 bytes

RAM

On-chip externally

mapped 768 bytes

RAM

On-chip externally

mapped 768 bytes

RAM

On-chip externally

mapped 768 bytes

RAM

On-chip externally

mapped 768 bytes

RAM

On-chip externally

mapped 768 bytes

RAM

On-chip externally

mapped 768 bytes

RAM

On-chip externally

mapped 768 bytes

RAM

On-chip externally

mapped 768 bytes

RAM

0

1

0

1

0

1

000h-03Fh

040h-07Fh

080h-0BFh

0C0h-0FFh

The Data Bank Select function is activated by setting

the Data Bank Select enable bit (DBANKSE) to 1

(setting this bit to zero disables this function). The four

least significant bits of this register control the mapping

of the entire 1K Byte on-chip RAM space into the 40h-

7Fh range.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0000h-003Fh

0040h-007Fh

0080h-00BFh

00C0h-00FFh

0100h-013Fh

0140h-017Fh

0180h-01BFh

01C0h-01FFh

0200h-023Fh

0240h-027Fh

0280h-02BFh

02C0h-02FFh

TABLE 9: DATA BANK CONTROL REGISTER (DBANK) – SFR 86H

7

6

5

4

3

DBK3

2

DBK2

1

DBK1

0

DBK0

DBANKE

Unused

Bit

Mnemonic

Description

DBANKSE

7

Data Bank Select Enable Bit

DBANKE=1, Data Bank Select enabled

DBANKE=0, Data Bank Select disabled

6

5

4

3

2

1

0

Unused

DBK3

DBK2

DBK1

-

Allows the mapping of the 1K RAM into

the 040h - 07Fh RAM space.

DBK0

Windowed access to all the 1KB on-chip RAM in the

range of 40h-7Fh is described in the following table.

Example: User writes #55h to 203h address:

MOV DBANK, #8CH

;Set bank mapping 40h-07Fh to

;0200h-023Fh

MOV A, #55H

MOV 43H, A

;Store #55H to A

;Write #55H to 0203h

;address

______________________________________________________________________________________________

www.ramtron.com page 9 of 49

VRS51x570/580

TABLE 12: POWER CONTROL REGISTER (PCON) - SFR 87H

Description of Peripherals

System Control Register

7

6

5

4

3

2

1

0

Unused

RAM1

RAM0

Bit

7

Mnemonic Description

The following table describes the System Control

Register (SYSCON).

SMOD

1: Double the baud rate of the serial port

frequency that was generated by Timer 1.

The WDRESET bit (7) indicates whether a reset was

due to the Watch Dog Timer overflow.

0: Normal serial port baud rate generated by

Timer 1.

6

5

4

3

2

1

0

When set to 1, the XRAME bit allows the user to

enable the on-chip expanded 768 bytes of RAM. By

default, upon reset, the XRAME bit is set to 0.

GF1

GF0

PDOWN

IDLE

General Purpose Flag

Power down mode control bit

Idle mode control bit

Bit 0 of the SYSCON register is the ALE output inhibit

bit. Setting this bit to 1 will inhibit the Fosc/6 clock

signal output to the ALE pin.

TABLE 11: SYSTEM CONTROL REGISTER (SYSCON) – SFR BFH

7

6

5

4

3

2

1

0

WDRESET

XRAME

Unused

ALEI

Bit

7

Mnemonic Description

WDRESET

This is the Watch Dog Timer reset bit. It

will be set to 1 when the reset signal

generated by WDT overflows.

6

5

4

3

2

1

0

Unused

XRAME

ALEI

-

768 byte on-chip enable bit

ALE output inhibit bit, which is used to

reduce EMI.

Power Control Register

The VRS51x570/VRS51x580 devices provide two

power saving modes: Idle and Power Down. These two

modes serve to reduce the power consumption of the

device.

In Idle mode, the processor is stopped but the oscillator

continues to run. The content of the RAM, I/O state and

SFR registers are maintained and the Timer and

external interrupts are left operational. The processor

will be woken up when an external event, triggering an

interrupt, occurs.

In Power Down mode, the oscillator and peripherals

are disabled . The contents of the RAM and the SFR

registers, however, are maintained

The minimum VCC in Power down Mode is 2V

These power saving modes are controlled by the

PDOWN and IDLE bits of the PCON register at

address 87h.

______________________________________________________________________________________________

www.ramtron.com page 10 of 49

VRS51x570/580

FIGURE 6: INTERNAL STRUCTURE OF ONE OF THE EIGHT I/O PORT LINES

Input/Output Ports

Read Register

The VRS51x570 and VRS51x580 have a total of 36 bi-

directional I/O lines grouped into four 8-bit I/O ports

and one 4-bit I/O port. These I/Os can be individually

configured as inputs or outputs.

With the exception of the P0 I/Os, which are of the

open drain type, each I/O is made of a transistor

connected to ground and a weak pull-up resistor.

Q

Internal Bus

IC Pin

Output

D Flip-Flop

Stage

Write to

Register

Q

Writing a 0 in a given I/O port bit register will activate

the transistor connected to Vss and bring the I/O to a

LOW level.

Read Pin

Writing a 1 into a given I/O port bit register de-activates

the transistor between the pin and ground. In this case

the pull-up resistor will bring the corresponding pin to a

HIGH level.

Structure of the P1, P2, P3 and P4

The following figure provides a general idea of the

structure of the P1, P2, P3 and P4 ports. Note that the

intermediary logic that connects the output of the

register and the output stage together is not shown

because this logic varies with the auxiliary function of

each port.

To use a given I/O as an input, a 1 must be written into

its associated port register bit. By default, upon reset

all I/Os are configured as inputs.

General Structure of an I/O Port

FIGURE 7: GENERAL STRUCTURE OF THE OUTPUT STAGE OF P1, P2 AND P3

The following elements establish the link between the

core unit and the pins of the microcontroller:

Read Register

·

Special Function Register (same name as port)

Output Stage Amplifier (the structure of this

element varies with its auxiliary function)

Vcc

Pull-up

Network

From the following figure, one can see that the D flip-

flop stores the value received from the internal bus

after receiving a write signal from the core. Also, note

that the Q output of the flip-flop can be linked to the

internal bus by executing a read instruction.

Q

Internal Bus

IC Pin

D Flip-Flop

Write to

Register

X1

Q

This is how one would read the content of the register.

It is also possible to link the value of the pin to the

internal bus. This is done by the “read pin” instruction.

In short, the user may read the value of the register or

the pin.

Read Pin

Each line may be used independently as a logical

input or output. When used as an input, as mentioned

earlier, the corresponding port register bit must be

high.

Structure of Port 0

The internal structure of P0 is shown below. The

auxiliary function of this port requires a particular logic.

______________________________________________________________________________________________

www.ramtron.com page 11 of 49

VRS51x570/580

As opposed to the other ports, P0 is truly bi-directional.

In other words, when used as an input, it is considered

to be in a floating logical state (high impedance state).

This arises from the absence of the internal pull-up

resistance. The pull-up resistance is actually replaced

by a transistor that is only used when the port is

configured to access the external memory/data bus

(EA=0).

Port P0 and P2 as Address and Data Bus

The output stage may receive data from two sources

·

The outputs of register P0 or the bus address

itself multiplexed with the data bus for P0.

The outputs of the P2 register or the high byte

(A8 through A15) of the bus address for the P2

port.

When used as an I/O port, P0 acts as an open drain

port and the use of an external pull-up resistor is likely

to be required for most applications.

FIGURE 9: P2 PORT STRUCTURE

Read Register

FIGURE 8: PORT P0’S PARTICULAR STRUCTURE

Vcc

Address

Address A0/A7

Read Register

Control

Pull-up

Network

Q

Internal Bus

IC Pin

D Flip-Flop

Vcc

Write to

Register

X1

Control

Q

Internal Bus

IC Pin

D Flip-Flop

X1

Write to

Register

Q

Read Pin

When the ports are used as an address or data bus,

the special function registers P0 and P2 are

disconnected from the output stage. The 8-bits of the

P0 register are forced to 1 and the content of the P2

register remains constant.

Read Pin

When P0 is used as an external memory bus input (for

a MOVX instruction, for example), the outputs of the

register are automatically forced to 1.

Auxiliary Port1 Functions

The Port1 I/O pins are shared with the PWM outputs,

Timer 2 EXT and T2 inputs as shown below:

Mnemonic Function

P1.0 T2

P1.1 T2EX

Timer 2 counter input

Timer2 Auxiliary input

P1.2

P1.3

PWM0 output

PWM0

P1.4 PWM1

P1.5 PWM2

PWM1 output

PWM2 output

P1.6

P1.7

PWM3 output

PWM4 output

PWM3

PWM4

______________________________________________________________________________________________

www.ramtron.com page 12 of 49

VRS51x570/580

Auxiliary P3 Port Functions

Port4

The Port3 I/O pins are shared with the UART interface,

INT0 and INT1 interrupts, Timer 0 and Timer 1 inputs

and finally the #WR and #RD lines when external

memory access is performed.

Port4 has four pins and its port address is located at

0D8H.

TABLE 14: PORT 4 (P4) - SFR D8H

7

6

5

4

3

2

1

0

Unused

P4.3

P4.2

P4.1

P4.0

FIGURE 10: P3 PORT STRUCTURE

Bit

Mnemonic Description

7

6

5

4

3

2

1

0

Unused

P4.3

P4.2

P4.1

P4.0

-

Auxiliary

Function: Output

Read Register

Vcc

Used to output the setting to pins P4.3,

P4.2, P4.1, P4.0 respectively.

IC Pin

X1

Q

Internal Bus

D Flip-Flop

Write to

Register

Q

Port4 uses the pins that normally appear as no-

connects (N/C) on standard 8051

Read Pin

Auxiliary

Function: Input

By default the Port4 pins are configured as inputs and

internally pulled–up, and therefore the VRS51x570 and

VRS51x580 devices can be safely used in existing

80C51/80C52 designs where the corresponding pins

have been left unconnected.

The following table describes the auxiliary function of

the port 3 I/O pins.

TABLE 13: P3 AUXILIARY FUNCTION TABLE

In the case of an existing design where a pin

corresponding to the Port4 I/O is grounded, a small

current will flow through the P4 pull-up resistor.

Mnemonic Function

P3.0 RXD

Serial Port:

Receive data in asynchronous

mode. Input and output data in

synchronous mode.

In the case where those pins would be connected to

Vcc, care must be taken to avoid writing into the P4

register.

P3.1 TXD

Serial Port:

Transmit data in asynchronous

mode. Output clock value in

synchronous mode.

Software Particularities Concerning the Ports

P3.2

INT0

External Interrupt 0

Timer 0 Control Input

External Interrupt 1

Timer 1 Control Input

Timer 0 Counter Input

Timer 1 Counter Input

Write signal for external memory

Some instructions allow the user to read the logic state

of the output pin, while others allow the user to read

the content of the associated port register. These

instructions are called read-modify-write instructions. A

list of these instructions may be found in the table

below.

P3.3

INT1

P3.4 T0

P3.5 T1

P3.6

WR

Upon execution of these instructions, the content of the

port register (at least 1 bit) is modified. The other read

instructions take the present state of the input into

account. For example, the instruction ANL P3, #01h

obtains the value in the P3 register; performs the

desired logic operation with the constant 01h, and

recopies the result into the P3 register. When users

want to take the present state of the inputs into

P3.7

RD

Read signal for external memory

______________________________________________________________________________________________

www.ramtron.com page 13 of 49

VRS51x570/580

Reading a Port (Input)

account, they must first read these states and perform

an AND operation between the read value and the

constant.

The reading of an I/O pin takes place:

·

During T9 cycle for P0, P1

During T10 cycle for P2, P3

When the ports are configured as I/Os (see

Figure 25).

MOV A, P3; State of the inputs in the accumulator

ANL A, #01; AND operation between P3 and 01h

When the port is used as an output, the register

contains information on the state of the output pins.

Measuring the state of an output directly on the pin is

inaccurate because the electrical level depends mostly

on the type of charge that is applied to it. The functions

shown below take the value of the register rather than

that of the pin.

In order to be sampled, the signal duration present on

the I/O inputs must be longer than Fosc/12.

I/O Ports Driving Capability

The maximum allowable continuous current that the

device can sink on an I/O port is defined by the

following

TABLE 15: LIST OF INSTRUCTIONS THAT READ AND MODIFY THE PORT USING REGISTER

VALUES

Instruction Function

ANL

ORL

XRL

JBC

CPL

INC

Logical AND ex: ANL P0, A

Maximum sink current on one given I/O

Maximum total sink current for P0

Maximum total sink current for P1, 2, 3

Maximum total sink current on all I/O

10mA

26mA

15mA

70mA

Logical OR ex: ORL P2, #01110000B

Exclusive OR ex: XRL P1, A

Jump if the bit of the port is set to 0

Complement one bit of the port

Increment the port register by 1

Decrement the port register by 1

Decrement by 1 and jump if the result

is not equal to 0

On the VRS51x580, the Port4 output buffers can sink

up to 20mA, allowing direct driving of LED displays.

DEC

DJNZ

It is not recommended to exceed the sink current

outlined in the above table. Doing so is likely to make

the low-level output voltage exceed the device’s

specification and it is likely to affect the device’s

reliability.

MOV P., C Copy the held bit C to the port

CLR P.x

SETB P.x

Set the port bit to 0

Set the port bit to 1

Port Operation Timing

Writing to a Port (Output)

The VRS51x570/VRS51x580 I/O ports are not

designed to source current.

When an operation results in a modification of the

content in a port register, the new value is placed at the

output of the D flip-flop during the T12 period of the last

machine cycle that the instruction needed to execute.

It is important to note, however, that the output stage

only samples the output of the registers on the P1

phase of each period. It follows that the new value only

appears at the output after the T12 period of the

following machine cycle.

______________________________________________________________________________________________

www.ramtron.com page 14 of 49

VRS51x570/580

TABLE 16: TIMER MODE CONTROL REGISTER (TMOD) – SFR 89H

Timers

7

6

5

4

3

2

1

0

GATE

C/T

M1

M0

GATE

C/T

M1.0

M0.0

Both the VRS51x570/VRS51x580 include three 16-bit

timers: T0, T1 and T2.

Bit

7

Mnemonic Description

GATE1

1: Enables external gate control (pin INT1 for

Counter 1). When INT1 is high, and TRx bit is

set (see TCON register), a counter is

incremented every falling edge on the T1IN

input pin.

The timers can operate in two specific modes:

·

Event counting mode

Timer mode

6

C/T1

Selects timer or counter operation (Timer 1).

1 = A counter operation is performed

0 = The corresponding register will function

as a timer.

When operating in counting mode, the counter is

incremented each time an external event, such as a

transition in the logical state of the timer input (T0, T1,

T2 input), is detected. When operating in timer mode,

the counter is incremented by the microcontroller’s

direct clock pulse or by a divided version of this pulse.

Selects mode for Timer/Counter 1

5

4

3

M1.1

Selects mode for Timer/Counter 1

M0.1

If set, enables external gate control (pin INT0

for Counter 0). When INT0 is high, and TRx

bit is set (see TCON register), a counter is

incremented every falling edge on the T0IN

input pin.

GATE0

Timer 0 and Timer 1

Selects timer or counter operation (Timer 0).

1 = A counter operation is performed

0 = The corresponding register will function

as a timer.

2

C/T0

Timers 0 and 1 have four modes of operation. These

modes allow the user to change the size of the

counting register or to authorize an automatic reload

when provided with a specific value. Timer 1 can also

be used as a baud rate generator to generate

communication frequencies for the serial interface.

Selects mode for Timer/Counter 0.

1

0

M1.0

M0.0

The table below summarizes the four modes of

operation of timers 0 and 1. The timer-operating mode

is selected by the bits M1 and M0 of the TMOD

register.

Timer 1 and Timer 0 are configured by the TMOD and

TCON registers.

TABLE 17: TIMER/COUNTER MODE DESCRIPTION SUMMARY

M1 M0 Mode Function

0

1

0

1

0

Mode 0

Mode 1

Mode 2

13-bit Counter

16-bit Counter

8-bit auto-reload Counter/Timer. The reload

value is kept in TH0 or TH1, while TL0 or TL1

is incremented every machine cycle. When TLx

overflows, the value of THx is copied to TLx.

If Timer 1 M1 and M0 bits are set to 1, Timer 1

stops.

1

Mode 3

______________________________________________________________________________________________

www.ramtron.com page 15 of 49

VRS51x570/580

The user may change the operating mode by varying

the M1 and M0 bits of the TMOD SFR.

Timer 0/ Timer 1 Counter / Timer Functions

Timing Function

Mode 0

When operating as a timer, the counter is automatically

incremented at every system cycle (Fosc/12). A flag is

raised in the event that an overflow occurs and the

counter acquires a value of zero. These flags (TF0 and

TF1) are located in the TCON register.

A schematic representation of this mode of operation

can be found below in Figure 11. From the figure, we

notice that the timer operates as an 8-bit counter

preceded by a divide-by-32 prescaler composed of the

5LSB of TL1. The register of the counter is configured

to be 13 bits long. When an overflow causes the value

of the register to roll over to 0, the TFx interrupt signal

goes to 1. The count value is validated as soon as TRx

goes to 1 and the GATE bit is 0, or when INTx is 1.

TABLE 18: TIMER 0 AND 1 CONTROL REGISTER (TCON) –SFR 88H

7

TF1

6

TR1

5

TF0

4

TR0

3

IE1

2

IT1

1

IE0

0

IT0

Bit

Mnemonic Description

7

TF1

Timer 1 Overflow Flag. Set by hardware on

Timer/Counter overflow. Cleared by

hardware on Timer/Counter overflow.

Cleared by hardware when processor

vectors to interrupt routine.

FIGURE 11: TIMER/COUNTER 1 MODE 0: 13-BIT COUNTER

6

TR1

TF0

Timer 1 Run Control Bit. Set/cleared by

software to turn Timer/Counter on or off.

Timer 0 Overflow Flag. Set by hardware on

Timer/Counter overflow. Cleared by

hardware when processor vectors to

interrupt routine.

CLK

÷12

TL1

4

0

1

C/T =0

C/T =1

0

7

5

CLK

Mode 0

Control

T1PIN

Mode 1

Timer 0 Run Control Bit. Set/cleared by

software to turn Timer/Counter on or off.

Interrupt Edge Flag. Set by hardware when

external interrupt edge is detected. Cleared

when interrupt processed.

4

3

TR0

IE1

TR1

GATE

TH1

0

7

INT1 PIN

Interrupt 1 Type Control Bit. Set/cleared by

software to specify falling edge/low level

triggered external interrupts.

Interrupt 0 Edge Flag. Set by hardware

when external interrupt edge is detected.

Cleared when interrupt processed.

Interrupt 0 Type control bit. Set/cleared by

software to specify falling edge/low level

triggered external interrupts.

2

1

0

IT1

IE0

IT0

TF1

INT

Mode 1

Mode 1 is almost identical to Mode 0. They differ in

that, in Mode 1, the counter uses the full 16 bits and

has no prescaler.

Mode 2

Counting Function

In this mode, the register of the timer is configured as

an 8-bit automatically re-loadable counter. In Mode 2, it

is the lower byte TLx that is used as the counter. In the

event of a counter overflow, the TFx flag is set to 1 and

the value contained in THx, which is preset by

software, is reloaded into the TLx counter. The value of

THx remains unchanged.

When operating as a counter, the timer’s register is

incremented at every falling edge of the T0, T1 and T2

signals located at the input of the timer. In this case,

the signal is sampled at the T10 phase of each

machine cycle for Timer 0, Timer 1 and T9 for Timer 2.

When the sampler sees a high immediately followed by

a low in the next machine cycle, the counter is

incremented. Two system cycles are required to detect

and record an event. This reduces the counting

frequency by a factor of 24 (24 times less than the

oscillator’s frequency).

Operating Modes

______________________________________________________________________________________________

www.ramtron.com page 16 of 49

VRS51x570/580

FIGURE 12: TIMER/COUNTER 1 MODE 2: 8-BIT AUTOMATIC RELOAD

CLK

÷12

C/T =0

C/T=1

TL1

0

1

0

7

Control

T1 Pin

Reload

0

7

TH1

TF1

TR1

GATE

INT

INT0 PIN

Mode 3

In Mode 3, Timer 1 is blocked as if its control bit, TR1,

was set to 0. In this mode, Timer 0’s registers TL0 and

TH0 are configured as two separate 8-bit counters.

Also, the TL0 counter uses Timer 0’s control bits C/T,

GATE, TR0, INT0, TF0 and the TH0 counter is held in

Timer Mode (counting machine cycles) and gains

control over TR1 and TF1 from Timer 1. At this point,

TH0 controls the Timer 1 interrupt.

FIGURE 13: TIMER/COUNTER 0 MODE 3

TH0

0

7

CLK

Control

TF1

INTERRUPT

TR1

CLK

÷12

TL0

0

1

C/T =0

C/T =1

0

7

CLK

Control

T0PIN

TF0

INTERRUPT

TR0

GATE

INT0 PIN

______________________________________________________________________________________________

www.ramtron.com page 17 of 49

VRS51x570/580

Capture/Reload Select.

0

Timer 2

1: Capture of Timer 2 value into RCAP2H,

RCAP2L is performed if EXEN2=1 and a

negative transitions occurs on the T2EX

pin. The capture mode requires RCLK and

TCLK to be 0.

CP/RL2

Timer 2 of the VRS51x570 / VRS51x580 devices is a

16-bit Timer/Counter. Similar to timers 0 and 1, Timer 2

can operate either as an event counter or as a timer.

The user may switch functions by writing to the C/T2 bit

located in the T2CON special function register. Timer 2

has three operating modes: “Auto-Load” “Capture”, and

“Baud Rate Generator”. The T2CON SFR configures

the modes of operation of Timer 2. The following table

describes each bit in the T2CON special function

register.

0: Auto-reload reloads will occur either with

Timer 2 overflows or negative transitions at

T2EX when EXEN2=1. When either RCK

=1 or TCLK =1, this bit is ignored and the

timer is forced to auto-reload on Timer 2

overflow.

As shown below, there are different possible

combinations of control bits that may be used for the

mode selection of Timer 2.

TABLE 19: TIMER 2 CONTROL REGISTER (T2CON) –SFR C8H

7

6

5

4

3

2

TR2

1

C/T2

0

TABLE 20: TIMER 2 MODE SELECTION BITS

TF2

EXF2

RCLK

TCLK

EXEN2

CP/RL2

0

RCLK + TCLK

0

TR2 MODE

Bit

7

Mnemonic Description

16-bit Auto-

Timer 2 Overflow Flag: Set by an overflow

of Timer 2 and must be cleared by

software. TF2 will not be set when either

RCLK =1 or TCLK =1.

TF2

1

Reload Mode

16-bit Capture

Mode

0

1

Timer 2 external flag change in state occurs

when either a capture or reload is caused

by a negative transition on T2EX and

EXEN2=1. When Timer 2 is enabled,

EXF=1 will cause the CPU to Vector to the

Timer 2 interrupt routine. Note that EXF2

must be cleared by software.

6

EXF2

Baud Rate

Generator Mode

Off

1

X

1

0

X

The details of each mode are described as follows.

Serial Port Receive Clock Source.

1: Causes Serial Port to use Timer 2

overflow pulses for its receive clock in

modes 1 and 3.

5

4

3

RCLK

TCLK

Capture Mode

In Capture Mode the EXEN2 bit value defines if the

external transition on the T2EX pin will be able to

trigger the capture of the timer value.

0: Causes Timer 1 overflow to be used for

the Serial Port receive clock.

Serial Port Transmit Clock.

1: Causes Serial Port to use Timer 2

overflow pulses for its transmit clock in

modes 1 and 3.

When EXEN2 = 0, Timer 2 acts as a 16-bit timer or

counter, which, upon overflowing, will set bit TF2

(Timer 2 overflow bit). This overflow can be used to

generate an interrupt.

0: Causes Timer 1 overflow to be used for

the Serial Port transmit clock.

Timer 2 External Mode Enable.

1: Allows a capture or reload to occur as a

result of a negative transition on T2EX if

Timer 2 is not being used to clock the Serial

Port.

0: Causes Timer 2 to ignore events at

T2EX.

Start/Stop Control for Timer 2.

1: Start Timer 2

EXEN2

FIGURE 14: TIMER 2 IN CAPTURE MODE

F_OSC

÷12

0

1

TIMER

TL2

TH2

0

7

0

7

C/T2

COUNTER

T2 Pin

2

1

TR2

RCAP2L

RCAP2H

TR2

0: Stop Timer 2

Timer or Counter Select (Timer 2)

1: External event counter falling edge

triggered.

TF2

C/T2

T2 EX Pin

EXF2

0: Internal Timer (OSC/12)

EXEN2

Timer 2

Interrupt

______________________________________________________________________________________________

www.ramtron.com page 18 of 49

VRS51x570/580

When EXEN2 = 1, the above still applies. Additionally,

it is possible to allow a 1 to 0 transition at the T2EX

input to cause the current value stored in the Timer 2

registers (TL2 and TH2) to be captured by the RCAP2L

and RCAP2H registers. Furthermore, the transition at

T2EX causes bit EXF2 in T2CON to be set, and EXF2,

like TF2, can generate an interrupt. Note that both

EXF2 and TF2 share the same interrupt vector.

Baud Rate Generator Mode

The baud rate generator mode is activated when RCLK

is set to 1 and/or TCLK is set to 1. This mode will be

described in the serial port section.

FIGURE 16: TIMER 2 IN AUTOMATIC BAUD GENERATOR MODE

F_OSC

÷2

Auto-Reload Mode

0

1

TIMER

TL2

TH2

0

7

0

7

C/T2

In this mode, there are also two options. The user may

choose either option by writing to bit EXEN2 in T2CON.

COUNTER

T2 Pin

7

RCAP2L

RCAP2H

TR2

1

0

TX Clock

RX Clock

÷16

TCLK

1

If EXEN2 = 0, when Timer 2 rolls over, it not only sets

TF2, but also causes the Timer 2 registers to be

reloaded with the 16-bit value in the RCAP2L and

RCAP2H registers previously initialised. In this mode,

Timer 2 can be used as a baud rate generator source

for the serial port.

0

1

0

Timer 1 Overflow

÷2

RCLK

SMOD

Timer

Interrupt

Request

2

T2 EX Pin

EXF2

EXEN2

If EXEN2=1, then Timer 2 still performs the above

operation, but a 1 to 0 transition at the external T2EX

input will also trigger an anticipated reload of the Timer

2 with the value stored in RCAP2L, RCAP2H and set

EXF2.

FIGURE 15: TIMER 2 IN AUTO-RELOAD MODE

F_OSC

÷12

0

1

TIMER

TL2

TH2

0

7

0

7

C/T2

COUNTER

T2 Pin

RCAP2L

RCAP2H

TR2

TF2

T2 EX Pin

EXF2

EXEN2

Timer 2

Interrupt

______________________________________________________________________________________________

www.ramtron.com page 19 of 49

VRS51x570/580

9^thdata bit transmitted in modes 2 and 3

This bit must be set by software and

cleared by software.

3

2

TB8

RB8

Serial Port

The serial port included in the VRS51x570 and the

VRS51x580 can operate in full duplex; in other words,

it can transmit and receive data simultaneously. This

occurs at the same speed if one timer is assigned as

the clock source for both transmission and reception,

and at different speeds if transmission and reception

are each controlled by their own timer.

9^thdata bit received in modes 2 and 3.

In Mode 1, if SM2 = 0 , RB8 is the stop bit

that was received.

In Mode 0, this bit is not used.

This bit must be cleared by software.

Transmission Interrupt flag.

1

0

TI

Automatically set to 1 when:

· The 8^thbit has been sent in Mode 0.

· Automatically set to 1 when the stop bit

has been sent in the other modes.

This bit must be cleared by software.

Reception Interrupt flag

The serial port receive is buffered, which means that it

can begin reception of a byte even if the one previously

received byte has not been retrieved from the receive

register by the processor. However, if the first byte still

has not been read by the time reception of the second

byte is complete, the byte present in the receive buffer

will be lost.

RI

Automatically set to 1 when:

· The 8^thbit has been received in Mode 0.

· Automatically set to 1 when the stop bit

has been sent in the other modes (see

SM2 exception).

The SBUF register provides access to the transmit and

receive registers of the serial port. Reading from the

SBUF register will access the receive register, while a

write to the SBUF loads the transmit register.

This bit must be cleared by software.

TABLE 22: SERIAL PORT MODES OF OPERATION

SM0

0

SM1

0

1

Mode

Description

Baud Rate

F_osc/12

Variable

F_osc/64 or

F_osc/32

0

1

2

Shift Register

8-bit UART

9-bit UART

Serial Port Control Register

1

0

The SCON (serial port control) register contains control

and status information, and includes the 9 data bit for

transmit/receive (TB8/RB8 if required), mode selection

bits and serial port interrupt bits (TI and RI).

th

1

3

9-bit UART

Variable

Modes of Operation

TABLE 21: SERIAL PORT CONTROL REGISTER (SCON) – SFR 98H

The VRS51x570/VRS51x580 devices serial port can

operate in four different modes. In all four modes, a

transmission is initiated by an instruction that uses the

SBUF SFR as a destination register. In Mode 0,

reception is initiated by setting RI to 0 and REN to 1.

An incoming start bit initiates reception in the other

modes provided that REN is set to 1. The following

paragraphs describe the four modes.

7

SM0

6

SM1

5

SM2

4

REN

3

TB8

2

RB8

1

TI

0

RI

Bit

Mnemonic Description

7

SM0

SM1

SM2

Bit to select mode of operation (see table

below)

Bit to select mode of operation (see table

below)

Multiprocessor communication is possible

in modes 2 and 3.

6

5

In modes 2 or 3 if SM2 is set to 1, RI will

not be activated if the received 9^thdata bit

(RB8) is 0.

In Mode 1, if SM2 = 1 then RI will not be

activated if a valid stop bit was not

received.

Serial Reception Enable Bit

This bit must be set by software and

cleared by software.

4

REN

1: Serial reception enabled

0: Serial reception disabled

______________________________________________________________________________________________

www.ramtron.com page 20 of 49

VRS51x570/580

Mode 0

The SEND signal enables the output of the shift

register to the alternate output function line of P3.0 and

enables SHIFT CLOCK to the alternate output function

line of P3.1. SHIFT CLOCK is high during T11, T12

and T1, T2 and T3, T4 of every machine cycle and low

during T5, T6, T7, T8, T9 and T10. At T12 of every

machine cycle in which SEND is active and the

contents of the transmit shift register are shifted to the

right by one position.

In this mode, the serial data exits and enters through

the RXD pin. TXD is used to output the shift clock. The

signal is composed of 8 data bits starting with the LSB.

The baud rate in this mode is 1/12 the oscillator

frequency.

Internal Bus

1

Zeros come in from the left as data bits shift out to the

right. The TX control block sends its final shift and

deactivates SEND while setting T1 after one condition

is fulfilled: When the MSB of the data byte is at the

output position of the shift register; the 1 that was

initially loaded into the 9^thposition is just to the left of

the MSB; and all positions to the left of that contain

zeros. Once these conditions are met, the deactivation

of SEND and the setting of T1 occur at T1 of the 10^th

machine cycle after the “write to SBUF” pulse.

Write to

SBUF

Q

S

D

SBUF

RXD P3.0

Shift

CLK

ZERO DETECTOR

Shift

Clock

TXD P3.1

Shift

Start

TX Control Unit

TX Clock

Send

Fosc/12

TI

Serial Port

Interrupt

RI

RX Clock

Receive

Reception in Mode 0

RX Control Unit

RI

REN

Start Shift

1

0

When REN and R1 are set to 1 and 0 respectively,

reception is initiated. The bits 11111110 are written to

the receive shift register at T12 of the next machine

cycle by the RX control unit. In the following phase, the

RX control unit will activate RECEIVE.

RXD P3.0

Input Function

RXD P3.0

Shift Register

READ SBUF

SBUF

Internal Bus

SHIFT CLOCK to the alternate output function line of

P3.1 is enabled by RECEIVE. At every machine cycle,

SHIFT CLOCK makes transitions at T5 and T11. The

contents of the receive shift register are shifted one

position to the left at T12 of every machine in which

RECEIVE is active. The value that comes in from the

right is the value that was sampled at the P3.0 pin at

T10 of the same machine cycle.

FIGURE 17: SERIAL PORT MODE 0 BLOCK DIAGRAM

Transmission in Mode 0

Any instruction that uses SBUF as a destination

register may initiate a transmission. The “write to

SBUF” signal also loads a 1 into the 9 position of the

transmit shift register and tells the TX control block to

begin a transmission. The internal timing is such that

one full machine cycle will elapse between a write to

SBUF instruction and the activation of SEND.

1’s are shifted out to the left as data bits are shifted in

from the right. The RX control block is flagged to do

one last shift and load SBUF when the 0 that was

initially loaded into the rightmost position arrives at the

leftmost position in the shift register.

th

______________________________________________________________________________________________

www.ramtron.com page 21 of 49

VRS51x570/580

Mode 1

When a transmission begins, it places the start bit at

TXD. Data transmission is activated one bit time later.

This activation enables the output bit of the transmit

shift register to TXD. One bit time after that, the first

shift pulse occurs.

For an operation in Mode 1, 10 bits are transmitted

through TXD or received through RXD. The

transactions are composed of: a Start bit (Low); 8 data

bits (LSB first) and one Stop bit (high). The reception is

completed once the Stop bit sets the RB8 flag in the

SCON register. Either Timer 1 or Timer 2 controls the

baud rate in this mode.

In this mode, zeros are clocked in from the left as data

bits are shifted out to the right. When the most

significant bit of the data byte is at the output position

of the shift register, the 1 that was initially loaded into

the 9^thposition is to the immediate left of the MSB, and

all positions to the left of that contain zeros. This

condition flags the TX Control Unit to shift one more

time.

The following diagram shows the serial port structure

when configured in Mode 1.

FIGURE 18: SERIAL PORT MODE 1 AND 3 BLOCK DIAGRAM

Internal Bus

Reception in Mode 1

1

Write to

SBUF

A one to zero transition at RXD initiates reception. It is

for this reason that RXD is sampled at a rate of 16

multiplied by the baud rate that has been established.

When a transition is detected, 1FFh is written into the

input shift register and the divide-by-16 counter is

immediately reset. The divide-by-16 counter is reset in

order to align its rollovers with the boundaries of the

incoming bit times.

Timer 1

Overflow

Q

S

D

SBUF

TXD

CLK

Timer 2

Overflow

ZERO DETECTOR

÷2

0

1

Shift

Start

Data

SMOD

0

1

TX Control Unit

TCLK

TX Clock

÷16

Send

÷16

TI

1

RCLK

Serial Port

Interrupt

In total, there are 16 states in the counter. During the

7^th, 8^thand 9^thcounter states of each bit time; the bit

detector samples the value of RXD. The accepted

value is the value that was seen in at least two of the

three samples. The purpose of doing this is for noise

rejection. If the value accepted during the first bit time

is not zero, the receive circuits are reset and the unit

goes back to searching for another one to zero

transition. All false start bits are rejected by doing this.

If the start bit is valid, it is shifted into the input shift

register, and the reception of the rest of the frame will

proceed.

RX Clock

RI

Load

SBUF

RX Control Unit

1-0 Transition

Detector

Start

SHIFT

Bit

Detector

9-Bit Shift Register

Shift

RXD

LOAD SBUF

SBUF

READ SBUF

Internal Bus

For a receive operation, the data bits come in from the

right as 1’s shift out on the left. As soon as the start bit

arrives at the leftmost position in the shift register, (9-

bit register), it tells the RX control block to perform one

last shift operation: to set RI and to load SBUF and

RB8. The signal to load SBUF and RB8, and to set RI,

will be generated if, and only if, the following conditions

are met at the time the final shift pulse is generated:

Transmission in Mode 1

Transmission is initiated by any instruction that makes

use of SBUF as a destination register. The 9^thbit

position of the transmit shift register is loaded by the

“write to SBUF” signal. This event also flags the TX

Control Unit that a transmission has been requested.

It is after the next rollover in the divide-by-16 counter

when transmission actually begins at T1 of the

machine cycle. It follows that the bit times are

synchronized to the divide-by-16 counter and not to the

“write to SBUF” signal.

-

Either SM2 = 0 or the received stop bit = 1

RI = 0

______________________________________________________________________________________________

www.ramtron.com page 22 of 49

VRS51x570/580

Mode 3

If both conditions are met, the stop bit goes into RB8,

the 8 data bits go into SBUF, and RI is activated. If one

of these conditions is not met, the received frame is

completely lost. At this time, whether the above

conditions are met or not, the unit goes back to

searching for a one to zero transition in RXD.

In Mode 3, 11 bits are transmitted through TXD or

received through RXD. The transactions are

composed of: a Start bit (Low), 8 data bits (LSB first),

a programmable 9^thdata bit, and one Stop bit (High).

Mode 3 is identical to Mode 2 in all respects but one:

the baud rate. Either Timer 1 or Timer 2 generates the

baud rate in Mode 3.

Mode 2

In Mode 2 a total of 11 bits are transmitted through

TXD or received through RXD. The transactions are

composed of: a Start bit (Low), 8 data bits (LSB first), a

programmable 9^thdata bit, and one Stop bit (High).

FIGURE 20: SERIAL PORT MODE 3 BLOCK DIAGRAM

Internal Bus

1

For transmission, the 9^thdata bit comes from the TB8

bit of SCON. For example, the parity bit P in the PSW

could be moved into TB8.

Write to

SBUF

Timer 1

Q

S

D

Overflow

SBUF

TXD

In the case of receive, the 9^thdata bit is automatically

written into RB8 of the SCON register.

CLK

Timer 2

Overflow

ZERO DETECTOR

÷2

0

1

Shift

Start

Data

SMOD

0

1

In Mode 2, the baud rate is programmable to either

1/32 or 1/64 the oscillator frequency.

TX Control Unit

TCLK

TX Clock

÷16

Send

÷16

TI

1

RCLK

Serial Port

Interrupt

FIGURE 19: SERIAL PORT MODE 2 BLOCK DIAGRAM

RI

SAMPLE

RX Clock

Start

Load

SBUF

RX Control Unit

1-0 Transition

Detector

SHIFT

Internal Bus

1

Write to

SBUF

Bit

Detector

9-Bit Shift Register

Shift

RXD

LOAD SBUF

Q

S

D

SBUF

Fosc/2

÷2

TXD

SBUF

CLK

READ SBUF

ZERO DETECTOR

Internal Bus

0

1

Shift

Data

Send

Stop

Start

SMOD

TX Control Unit

TX Clock

÷16

TI

÷16

Serial Port

Interrupt

Sample

RI

RX Clock

Control

Load

SBUF

RX Control Unit

1-0 Transition

Detector

Start

SHIFT

Bit

Detector

9-Bit Shift Register

Shift

RXD

LOAD SBUF

SBUF

READ SBUF

Internal Bus

______________________________________________________________________________________________

www.ramtron.com page 23 of 49

VRS51x570/580

Mode 2 and 3: Additional Information

Reception in Mode 2 and Mode 3

As mentioned previously, for an operation in these

modes, 11 bits are transmitted through TXD or

received through RXD. The signal comprises: a logical

low Start bit, 8 data bits (LSB first), a programmable 9^th

data bit, and one logical high Stop bit.

One to zero transitions at RXD initiate reception. It is

for this reason that RXD is sampled at a rate of 16

multiplied by the baud rate that has been established.

When a transition is detected, the 1FFh is written into

the input shift register and the divide-by-16 counter is

immediately reset.

On transmit, (TB8 in SCON) can be assigned the value

th

of 0 or 1. On receive; the 9 data bit goes into RB8 in

During the 7^th, 8^thand 9^thcounter states of each bit

time; the bit detector samples the value of RXD. The

accepted value is the value that was seen in at least

two of the three samples. If the value accepted during

the first bit time is not zero, the receive circuits are

reset and the unit goes back to searching for another

one to zero transition. If the start bit is valid, it is shifted

into the input shift register, and the reception of the rest

of the frame will proceed.

SCON. The baud rate is programmable to either 1/32

or 1/64 the oscillator frequency in Mode 2. Mode 3 may

have a variable baud rate generated from either Timer

1 or Timer 2 depending on the states of TCLK and

RCLK.

Transmission in Mode 2 and Mode 3

The transmission is initiated by any instruction that

makes use of SBUF as the destination register. The 9^th

bit position of the transmit shift register is loaded by the

“write to SBUF” signal. This event also informs the TX

control unit that a transmission has been requested.

After the next rollover in the divide-by-16 counter, a

transmission actually begins at T1 of the machine

cycle. It follows that the bit times are synchronized to

the divide-by-16 counter and not to the “write to SBUF”

signal, as in the previous mode.

For a receive operation, the data bits come in from the

right as 1’s shift out on the left. As soon as the start bit

arrives at the leftmost position in the shift register (9-bit

register), it tells the RX control block to do one more

shift, to set RI, and to load SBUF and RB8. The signal

to set RI and to load SBUF and RB8 will be generated

if, and only if, the following conditions are satisfied at

the instance when the final shift pulse is generated:

- Either SM2 = 0 or the received 9^thbit is equal to 1

- RI = 0

Transmissions begin when the SEND signal is

activated, which places the Start bit at TXD. Data is

activated one bit time later. This activation enables the

output bit of the transmit shift register to TXD. The first

shift pulse occurs one bit time after that.

If both conditions are met, the 9^thdata bit received

goes into RB8, and the first 8 data bits go into SBUF. If

one of these conditions is not met, the received frame

is completely lost. One bit time later, whether the

above conditions are met or not, the unit goes back to

searching for a one to zero transition at the RXD input.

Please note that the value of the received stop bit is

unrelated to SBUF, RB8 or RI.

The first shift clocks a Stop bit (1) into the 9^thbit

position of the shift register to TXD. Thereafter, only

zeros are clocked in. Thus, as data bits shift out to the

right, zeros are clocked in from the left. When TB8 is at

the output position of the shift register, the stop bit is

just to the left of TB8, and all positions to the left of that

contain zeros. This condition signals to the TX control

unit to shift one more time and set TI, while de-

activating SEND. This occurs at the 11^thdivide-by-16

rollover after “write to SBUF”.

______________________________________________________________________________________________

www.ramtron.com page 24 of 49

VRS51x570/580

The value to write into the TH1 register is defined by

the following formula:

UART Baud Rates Calculation

In Mode 0, the baud rate is fixed and can be

represented by the following formula:

TH1 = 256 -

2^SMODx Fosc

32 x 12x (Baud Rate)

Mode 0 Baud Rate = Oscillator Frequency

12

It is possible to use Timer 1 in 16-bit mode to generate

the baud rate for the serial port. To do this, leave the

Timer 1 interrupt enabled, configure the timer to run as

a 16-bit timer (high nibble of TMOD = 0001B), and use

the Timer 1 interrupt to perform a 16-bit software

reload. This can achieve very low baud rates.

In Mode 2, the baud rate depends on the value of the

SMOD bit in the PCON SFR. From the formula below,

we can see that if SMOD = 0 (which is the value on

reset), the baud rate is 1/32 the oscillator frequency.

Generating Baud Rates with Timer 2

Timer 2 is often preferred to generate the baud rate, as

it can be easily configured to operate as a 16-bit timer

with auto-reload. This allows for much better resolution

than using Timer 1 in 8-bit auto-reload mode.

Mode 2 Baud Rate = 2^SMODx (Oscillator Frequency)

64

The baud rate using Timer 2 is defined as:

The Timer 1 and/or Timer 2 overflow rate determines

the baud rates in modes 1 and 3.

Generating Baud Rates with Timer 1

Mode 1, 3 Baud Rate = Timer 2 Overflow Rate

16

When Timer 1 functions as a baud rate generator, the

baud rate in modes 1 and 3 are determined by the

Timer 1 overflow rate.

The timer can be configured as either a timer or a

counter in any of its 3 running modes. In most typical

application, it is configured as a timer (C/T2 is set to 0).

Mode 1, 3 Baud Rate = 2^SMODx Timer 1 Overflow Rate

32

To make the Timer 2 operate as a baud rate generator

the TCLK and RCLK bits of the T2CON register must

be set to 1.

Timer 1 must be configured as an 8-bit timer (TL1) with

auto-reload with TH1 value when an overflow occurs

(Mode 2). In this application, the Timer 1 interrupt

should be disabled.

The baud rate generator mode is similar to the auto-

reload mode in that an overflow in TH2 causes the

Timer 2 registers to be reloaded with the 16-bit value in

registers RCAP2H and RCAP2L, which are preset by

software. However, when Timer 2 is configured as a

baud rate generator, its clock source is Osc/2.

The two following formulas can be used to calculate

the baud rate and the reload value to be written into the

TH1 register.

Mode 1, 3 Baud Rate =

2^SMODx Fosc

32 x 12(256 – TH1)

______________________________________________________________________________________________

www.ramtron.com page 25 of 49

VRS51x570/580

The following formula can be used to calculate the

baud rate in modes 1 and 3 using the Timer 2:

Modes 1, 3 Baud Rate =

Oscillator Frequency

32x[65536 – (RCAP2H, RCAP2L)]

The formula below is used to define the reload value to

put into the RCAP2h, RCAP2L registers to achieve a

given baud rate.

(RCAP2H, RCAP2L) = 65536 -

Fosc

32x[Baud Rate]

In the above formula, RCAP2H and RCAP2L are the

content of RCAP2H and RCAP2L taken as a 16-bit

unsigned integer.

Note that a rollover in TH2 does not set TF2, and will

not generate an interrupt and because of this, the

Timer 2 interrupt does not have to be disabled when

Timer 2 is configured in baud rate generator mode.

Also, if EXEN2 is set, a 1-to-0 transition in T2EX will

set EXF2 but will not cause a reload from RCAP2x to

Tx2. Therefore, when Timer 2 is used as a baud rate

generator, T2EX can be used as an extra external

interrupt.

Furthermore, when Timer 2 is running (TR2 is set to 1)

as a timer in baud rate generator mode, the user

should not try to read or write to TH2 or TL2. When

operating under these conditions, the timer is being

incremented every state time and the results of a read

or write command may be inaccurate.

The RCAP2 registers, however, may be read but

should not be written to, because a write may overlap a

reload operation and generate write and/or reload

errors. In this case, before accessing the Timer 2 or

RCAP2 registers, be sure to turn the timer off by

clearing TR2.

______________________________________________________________________________________________

www.ramtron.com

page 26 of 49

VRS51x570/580

PWM Registers - P1 CON, PWMCON, PWMR

PWM Registers - Port1 Configuration Register

Pulse Width Modulation (PWM)

The VRS51x570 and VRS51x580 devices include a

Pulse Width Modulation (PWM) module that has five 8-

bit channels. Each channel uses an 8-bit PWM data

register (PWMD) to set the number of continuous

pulses within a PWM frame cycle.

TABLE 23: PORT1 CONFIGURATION REGISTER (PWME, $9B)

7

6

5

4

PWM4E

PWM3E

PWM2E

PWM1E

3

2

1

0

PWM0E

Unused

PWM Function Description

Bit

7

6

5

4

Mnemonic

PWM4E

PWM3E

PWM2E

PWM1E

PWM0E

Description

When bit is set to one, the

Each 8-bit PWM channel is composed of an 8-bit

register that consists of a 5-bit PWM (5 MSBs) and a 3-

bit (LSBs) Narrow pulse generator (NP). The 5-bit

PWM determines the duty cycle of the output. The 3-bit

NPx generates and inserts narrow pulses among the

PWM frame made of 8 cycles.

corresponding PWM pin is active as

a PWM function. When the bit is

cleared, the corresponding PWM pin

is active as an I/O pin. These five

bits are cleared upon reset.

-

3

[2:0] Unused

The number of pulses generated is equal to the

number programmed into the 3-bit NP. The NP is used

to generate an equivalent 8-bit resolution PWM type

DAC with a reasonably high repetition rate through a 5-

bit PWM clock speed. The PDCK [1:0] setting of the

PWMCON (A3h) register is used to derive the PWM

clock from Fosc.

PWM Registers -PWM Control Register

The following table describes the PWM Control

Register signals.

TABLE 24: PWMCONTROL REGISTER (PWMCON) – SFR A3H

7

6

5

4

3

2

1

0

PDCK1

PDCK0

Unused

Bit

[7:2]

1

Mnemonic

Unused

PDCK1

Description

-

Input Clock Frequency Divider Bit 1

Input Clock Frequency Divider Bit 0

PWM Clock =

F_osc

2^{(PDCK [1:0] +1)}

0

PDCK0

The following table describes the relationship between

the values of PDCK1/PDCK0 and the value of the

divider. Numerical values of the corresponding

frequencies are also provided.

The PWM output cycle frame repetition rate

(frequency) is calculated using the following formula:

PWM clock,

Fosc=12MHz

6 MHz

PWM clock,

Fosc=25MHz

12.5 MHz

PDCK1 PDCKO

Divider

0

1

0

1

0

1

2

4

8

3 MHz

1.5 MHz

0.75 MHz

6.25 MHz

3.12 MHz

1.56 MHz

PWM Frame =

F_osc

16

32 x 2^{(PDCK [1:0] +1)}

Or Simply

PWM Frame =

PWM Clock

32

______________________________________________________________________________________________

www.ramtron.com page 27 of 49

VRS51x570/580

PWM Data Registers

Bit Mnemonic

Description

7

6

5

4

3

2

1

0

PWMD2.4

PWMD2.3

PWMD2.2

PWMD2.1

PWMD2.0

NP2.2

Contents of PWM Data Register 2 Bit 4

Contents of PWM Data Register 2 Bit 3

Contents of PWM Data Register 2 Bit 2

Contents of PWM Data Register 2 Bit 1

Contents of PWM Data Register 2 Bit 0

Inserts Narrow Pulses in a 8-PWM-Cycle

Frame

The following tables describe the PWM Data Register

bits. The 5 most significant bits of the PWMDx

registers determine the duty cycle of the PWM output

waveform.

NP2.1

NP2.0

The three least significant bits of the PWMDx registers

control a system that will insert short pulses into the

PWM frame cycle. The number of narrow pulses

inserted during PWM Frame cycle is proportional to the

value written into the 3 least significant bits of the

PWMDx register.

TABLE 28: PWMDATA REGISTER 3 (PWMD1) – SFR A7H

7

6

5

4

PWMD3.4

PWMD3.3

PWMD3.2

PWMD3.1

3

2

1

0

PWMD3.0

NP3.2

NP3.1

NP3.0

The net result of this system is that the average PWM

output will have an equivalent resolution of 8-bits.

Bit Mnemonic

Description

7

6

5

4

3

2

1

0

PWMD3.4

PWMD3.3

PWMD3.2

PWMD3.1

PWMD3.0

NP3.2

Contents of PWM Data Register 3 Bit 4

Contents of PWM Data Register 3 Bit 3

Contents of PWM Data Register 3 Bit 2

Contents of PWM Data Register 3 Bit 1

Contents of PWM Data Register 3 Bit 0

Inserts Narrow Pulses in a 8-PWM-Cycle

Frame

TABLE 25: PWMDATA REGISTER 0 (PWMD0) – SFR A4H

7

6

5

4

PWMD0.4

PWMD0.3

PWMD0.2

PWMD0.1

3

2

1

0

NP3.1

NP3.0

PWMD0.0

NP0.2

NP0.1

NP0.0

Bit Mnemonic

Description

TABLE 29: PWMDATA REGISTER 4 (PWMD1) – SFR ACH

7

6

5

4

3

2

1

0

PWMD0.4]

PWMD0.3

PWMD0.2

PWMD0.1

PWMD0.0

NP0.2

Contents of PWM Data Register 0 Bit 4

Contents of PWM Data Register 0 Bit 3

Contents of PWM Data Register 0 Bit 2

Contents of PWM Data Register 0 Bit 1

Contents of PWM Data Register 0 Bit 0

Inserts Narrow Pulses in a 8-PWM-Cycle

Frame

7

6

5

4

PWMD4.4

PWMD4.3

PWMD4.2

PWMD4.1

3

2

1

0

PWMD4.0

NP4.2

NP4.1

NP4.0

NP0.1

NP0.0

Bit Mnemonic

Description

7

6

5

4

3

2

1

0

PWMD4.4

PWMD4.3

PWMD4.2

PWMD4.1

PWMD4.0

NP4.2

Contents of PWM Data Register 4 Bit 4

Contents of PWM Data Register 4 Bit 3

Contents of PWM Data Register 4 Bit 2

Contents of PWM Data Register 4 Bit 1

Contents of PWM Data Register 4 Bit 0

Inserts Narrow Pulses in a 8-PWM-Cycle

Frame

TABLE 26: PWMDATA REGISTER 1 (PWMD1) – SFR A5H

7

6

5

4

PWMD1.4

PWMD1.3

PWMD1.2

PWMD1.1

3

2

1

0

NP4.1

NP4.0

PWMD1.0

NP1.2

NP1.1

NP1.0

Bit Mnemonic

Description

The following table shows the number of extra short

pulses inserted in an 8-PWM cycles frame when we

vary the NP number.

7

6

5

4

3

2

1

0

PWMD1.4

PWMD1.3

PWMD1.2

PWMD1.1

PWMD1.0

NP1.2

Contents of PWM Data Register 1 Bit 4

Contents of PWM Data Register 1 Bit 3

Contents of PWM Data Register 1 Bit 2

Contents of PWM Data Register 1 Bit 1

Contents of PWM Data Register 1 Bit 0

Inserts Narrow Pulses in a 8-PWM-Cycle

Frame

Number of PWM cycles inserted

N = NP [4:0][2:0]

in an 8-cycle frame

NP1.1

NP1.0

000

001

010

011

100

101

110

111

0

1

2

3

4

5

6

7

TABLE 27: PWMDATA REGISTER 2 (PWMD2) – SFR A6H

7

6

5

4

PWMD2.4

PWMD2.3

PWMD2.2

PWMD2.1

3

2

1

0

PWMD2.0

NP2.2

NP2.1

NP2.0

______________________________________________________________________________________________

www.ramtron.com page 28 of 49

VRS51x570/580

Example of PWM Timing

MOV PWMD0 #83H

MOV PWME, #08H

; PWMD04:0]=10h (=16T high, 16T low), NP02:0] = 3

; Enable P1.3 as PWM output pin

FIGURE 21: PWMTIMING DIAGRAM

1st Cycle

frame

2nd Cycle

frame

3rd Cycle

frame

4th Cycle

frame

5th Cycle

frame

6th Cycle

frame

7th Cycle

frame

8th Cycle

frame

32T

16

1T

(Narrow pulse inserted by NP0[2:0]=3)

SPWM clock= 1/T= Fosc / 2^(PDCK+1)

The SPWM output cycle frame frequency = SPWM clock/32 = [Fosc/2^(PDCK+1)]/32

If Fosc = 20MHz, PDCK[1:0] of SPWWC = #03H, then PWM clock = 20MHz/2^4 = 20MHz/16 = 1.25MHz.

PWM output cycle frame frequency = (20MHz/2^4)/32 = 39.1 kHz.

______________________________________________________________________________________________

www.ramtron.com page 29 of 49

VRS51x570/580

Interrupts

Interrupt Vectors

The VRS51x570 and VRS51x580 have 8 interrupt

sources (9 if we include the WDT) and 7 interrupt

vectors (including reset) used for handling.

The following table specifies each interrupt source, its

flag and its vector address.

TABLE 31: INTERRUPT VECTOR CORRESPONDING FLAGS ANS VECTOR ADDRESS

The interrupts are enabled via the IE register shown

below:

Interrupt Source

Flag

Vector

Address

0000h

0003h

000Bh

0013h

001Bh

0023h

002Bh

TABLE 30: IEN0INTERRUPT ENABLE REGISTER –SFR A8H

RESET (+ WDT)

INT0

WDRESET

IE0

7

EA

6

-

5

ET2

4

ES

3

ET1

2

EX1

1

ET0

0

EX0

Timer 0

TF0

INT1

IE1

Bit

Mnemonic Description

Timer 1

TF1

7

EA

Disables All Interrupts

Serial Port

Timer 2

RI+TI

TF2+EXF2

0: no interrupt acknowledgment

1: Each interrupt source is individually

enabled or disabled by setting or clearing

its enable bit.

6

5

4

3

2

1

0

-

Reserved

Timer 2 Interrupt Enable Bit

External Interrupts

ET2

ES

ET1

EX1

ET0

EX0

Serial Port Interrupt Enable Bit

Timer 1 Interrupt Enable Bit

External Interrupt 1 Enable Bit

Timer 0 Interrupt Enable Bit

External Interrupt 0 Enable Bit

The VRS51x570 and VRS51x580 have two external

interrupt inputs (INT0 and INT1). These interrupt lines

are shared with P3.2 and P3.3.

The bits IT0 and IT1 of the TCON register determine

whether the external interrupts are level or edge

sensitive.

The following figure illustrates the various interrupt

sources on the VRS51x570 / VRS51x580.

If ITx = 1, the interrupt will be raised when a 1 to 0

transition occurs at the interrupt pin. For the interrupt

to be noticed by the processor the duration of the sum

high and low condition must be at least equal to 12

oscillator cycles.

FIGURE 22: INTERRUPT SOURCES

INT0

TF0

IT0

IE0

If ITx = 0, the interrupt will occur when a logic low

condition is present on the interrupt pin.

The state of the external interrupt, when enabled, can

be monitored using the flags, IE0 and IE1 of the TCON

register that are set when the interrupt condition

occurs.

INTERRUPT

SOURCES

INT1

TF1

IT1

IE1

In the case where the interrupt was configured as edge

sensitive, the associated flag is automatically cleared

when the interrupt is serviced.

T1

RI

If the interrupt is configured as level sensitive, then the

interrupt flag must be cleared by the software.

TF2

EXF2

______________________________________________________________________________________________

www.ramtron.com page 30 of 49

VRS51x570/580

Timer 0 and Timer 1 Interrupt

Execution of an Interrupt

Both Timer 0 and Timer 1 can be configured to

When the processor receives an interrupt request, an

automatic jump to the desired subroutine occurs. This

jump is similar to executing a branch to a subroutine

instruction: the processor automatically saves the

address of the next instruction on the stack. An internal

flag is set to indicate that an interrupt is taking place,

and then the jump instruction is executed. An interrupt

subroutine must always end with the RETI instruction.

This instruction allows users to retrieve the return

address placed on the stack.

generate an interrupt when

a

rollover of the

timer/counter occurs (except Timer 0 in Mode 3).

The TF0 and TF1 flags serve to monitor timer overflow

occurring from Timer 0 and Timer 1. These interrupt

flags are automatically cleared when the interrupt is

serviced.

Timer 2 interrupt

The RETI instruction also allows updating of the

internal flag that will take into account an interrupt with

the same priority.

A Timer 2 interrupt can occur if TF2 and/or EXF2 flags

are set to 1 and if the Timer 2 interrupt is enabled.

The TF2 flag is set when a rollover of the Timer 2

Counter/Timer occurs. The EXF2 flag can be set by a 1

to 0 transition on the T2EX pin by the software.

Interrupt Enable and Interrupt Priority

When the VRS51x570/VRS51x580 device is initialized,

all interrupt sources are inhibited by the bits of the IE

register being reset to 0. It is necessary to start by

enabling the interrupt sources that the application

requires. This is achieved by setting bits in the IE

register, as discussed previously.

Note that neither flag is cleared by the hardware upon

execution of the interrupt service routine. The service

routine may have to determine whether it was TF2 or

EXF2 that generated the interrupt. These flag bits will

have to be cleared by the software.

Every bit that generates interrupts can either be

cleared or set by the software, yielding the same result

as when the operation is done by the hardware. In

other words, pending interrupts can be cancelled and

interrupts can be generated by the software.

This register is part of the bit addressable internal

RAM. For this reason, it is possible to modify each bit

individually in one instruction without having to modify

the other bits of the register. All interrupts can be

inhibited by setting EA to 0.

The order in which interrupts are serviced is shown in

the following table:

Serial Port Interrupt

The serial port can generate an interrupt upon byte

reception or once the byte transmission is completed.

TABLE 32: INTERRUPT NATURAL PRIORITY

Interrupt Source

RESET + WDT (Highest Priority)

IE0

TF0

IE1

Those two conditions share the same interrupt vector

and it is up to the user developed interrupt service

routine software to ascertain the cause of the interrupt

by looking at the serial interrupt flags RI and TI.

TF1

Note that neither of these flags is cleared by the

hardware upon execution of the interrupt service

routine. The software must clear these flags.

RI+TI

TF2+EXF2 (Lowest Priority)

______________________________________________________________________________________________

www.ramtron.com page 31 of 49

VRS51x570/580

Once the WDT is enabled, the user software must

clear it periodically. In the case where the WDT is not

cleared, its overflow will trigger a reset of the device.

Modifying the Interrupt Order of Priority

The VRS51x570 / VRS51x580 devices allows the user

to modify the natural priority of the interrupts. One may

modify the order by programming the bits in the IP

(Interrupt Priority) register. When any bit in this register

is set to 1, it gives the corresponding source a greater

priority than interrupts coming from sources that don’t

have their corresponding IP bit set to 1.

The user should check the WDRESET bit of the

SYSCON register whenever an unpredicted reset has

taken place.

The WDT timeout delay can be adjusted by configuring

the clock divider input for the time base source clock of

the WDT. To select the divider value, bit2-bit0

(WDPS2~WDPS0) of the Watch Dog Timer Control

Register (WDTCON) should be set accordingly.

The IP register is represented in the table below.

TABLE 33: IP INTERRUPT PRIORITY REGISTER –SFR B8H

7

EA

6

-

5

ET2

4

ES

3

ET1

2

EX1

1

ET0

0

EX0

Clearing the WDT is accomplished by setting the CLR

bit of the WDTCON to 1. This action will clear the

contents of the 16-bit counter and force it to restart.

Bit

Mnemonic Description

7

6

-

Watch Dog Timer Registers

Gives Timer 2 Interrupt Higher Priority

5

PT2

PS

PT1

PX1

PT0

PX0

Gives Serial Port Interrupt Higher Priority

Gives Timer 1 Interrupt Higher Priority

Gives INT1 Interrupt Higher Priority

Gives Timer 0 Interrupt Higher Priority

Gives INT0 Interrupt Higher Priority

4

3

2

1

0

Three registers of the VRS51x570/VRS51x580 devices

are associated with the Watch Dog Timer: WDTCON,

the WDTLOCK and the SYSCON registers. The

WDTCON register allows the user to enable the WDT,

to clear the counter and to divide the clock source. The

WDRESET bit of the SYSCON register indicates

whether the Watch Dog Timer has caused the device

reset.

Watch Dog Timer

The Watch Dog Timer (WDT) is a 16-bit free-running

counter that generates a reset signal if the counter

overflows. The WDT is useful for systems that are

susceptible to noise, power glitches and other

conditions that can cause the software to go into

infinite dead loops or runaways. The WDT function

gives the user software a recovery mechanism from

abnormal software conditions.

TABLE 34: WATCHDOG TIMER REGISTERS: WDTCON – SFR 9FH

7

6

5

4

3

2

1

0

WDCLR

WDTE

Unused

WDTPS [2:0]

Bit

7

Mnemonic

WDTE

Description

Watch Dog Timer Enable Bit

6

5

[4:3]

2

Unused

WDCLR

Unused

-

Watch Dog Timer Counter Clear Bit

-

The Watch Dog Timer of the VRS51x570 and

VRS51x580 devices is driven by an auxiliary RC

oscillator having an operating frequency of about

250kHz. This makes the WDT operation independent

of the processor oscillator operation.

WDPS [2:0]

Watchdog Timer Clock Source Divider

1

0

To enable the WDT, the user must set bit 7 (WDTE) of

the WDTCON register to 1. Once WDTE has been set

to 1, the 16-bit counter will start to count with the

selected time base source clock configured in

WDPS2~WDPS0. The Watch Dog Timer will generate

a reset signal if an overflow has taken place.

The WDTE bit will be cleared to 0 automatically when

the device is reset by either the hardware or a WDT

reset.

______________________________________________________________________________________________

www.ramtron.com page 32 of 49

VRS51x570/580

The table below provides examples of Watch Dog

timeout periods the user will obtain for different values

of the WDPSx bits of the Watch Dog Timer Register.

The System Control Register

The System Control register is used to monitor the

status of the Watch Dog Timer, enabling the operation

of the 768 bytes of Expanded RAM and inhibiting the

address Latch Enable signal output.

TABLE 35: WATCH DOG TIMER PERIOD VS. WDWDPS [2:0] BIT

WDPS [2:0]

000

WDT Timeout (ms)

2

001

4.1

TABLE 37: THE SYSTEM CONTROL REGISTER (SYSCON)–SFR BFH

010

8.2

7

6

5

4

3

2

1

0

ALEI

WDRESET

Unused

XRAME

011

16.4

32.7

65.5

131

262

100

Bit

7

[6:3]

2

1

0

Mnemonic

WDRESET

Unused

XRAME

ALEI

Description

Watch Dog Timer Reset Status Bit

101

-

110

111

1: Enable Electromagnetic Interference

Reducer

0: Disable Electromagnetic Interference

Reducer

Accessing the WDTCON Register

The WDRESET bit of the SYSCON register is the

Watch Dog Timer Reset bit. It will be set to 1 when a

reset signal is generated by the WDT overflow. The

user should check the WDRESET bit state if a reset

has taken place in application where the Watchdog

timer is activated

By default and as a protection feature, the WDTCON

register is read only. This feature is in place to prevent

inadvertently writing to this register.

The WDTLOCK register is located at SFR address

97h. In order to be able to perform a write operation to

the WDTCON register, two consecutive write

operations to the WDTLOCK register must first be

performed..

Reduced EMI Function

The VRS51x570 and VRS51x580 devices can also be

set up to reduce its EMI (electromagnetic interference)

by setting bit 0 (ALEI) of the SYSCON register to 1.

This function will inhibit the Fosc/6Hz clock signal

output to the ALE pin.

TABLE 36: WATCHDOG TIMER LOCK REGISTERS: WDTLOCK – SFR 97H

7

6

5

4

3

2

1

0

WDTLOCK [7:0]

To Enable Write operations into the WDTCON register:

You must perform the two following operations:

MOV WDTLOCK, #01Eh

MOV WDTLOCK, #0E1h

…At this point, Write operations are allowed to

the WDTCON register such as Watch Dog

timer Configuration or Watch Dog Timer Clear

operations.

To disable any further Write operations to the

WDTCON register, you must then perform the two

following operations:

MOV WDTLOCK, #0E1h

MOV WDTLOCK, #01Eh

______________________________________________________________________________________________

www.ramtron.com page 33 of 49

VRS51x570/580

Crystal Consideration

The crystal connected to the VRS51x570/VRS51x580

oscillator input should be of a parallel type, operating in

fundamental mode.

The following table shows the value of capacitors and

feedback resistor that must be used at different

operating frequencies.

XTAL

C1

C2

3MHz

30 pF

open

6MHz

30 pF

open

12MHz

30 pF

open

16MHz 25MHz

30 pF

open

15 pF

62KO

R

Note: Oscillator circuits may differ with different

crystals or ceramic resonators in higher oscillation

frequency.

Crystals or ceramic resonator characteristics vary from

one manufacturer to the other.

The user should check the specific crystal or ceramic

resonator technical literature available or contact the

manufacturer to select the appropriate values for the

external components.

XTAL1

XTAL

VRS51x570

VRS51x580

R

XTAL2

C2

C1

______________________________________________________________________________________________

www.ramtron.com page 34 of 49

VRS51x570/580

Operating Conditions

TABLE 38: OPERATING CONDITIONS

Symbol

TA

TS

VCC5V

VCC3V

Description

Min.

-40

-55

4.5

3.0

Typ.

25

5.0

3.3

Max.

85

155

5.5

Unit

ºC

V

Remarks

Ambient temperature operating

Operating temperature

Storage temperature

Supply voltage

5 Volts devices

3.3 Volts devices

Supply voltage

3.6

V

25

MHz

For 5V & 3.3V application

DC Characteristics

TABLE 39: DC CHARACTERISTICS

AMBIENT TEMPERATURE = -40°C TO 85°C, 3.0V TO 5.5V

Symbol Parameter

Valid

Port 0,1,2,3,4,#EA

RES, XTAL1

Port 0,1,2,3,4,#EA

RES, XTAL1

Port 0, ALE, #PSEN

Port 1,2,3,4

Min.

-0.5

0

Max.

0.8

0_.8

Unit

V

Test Conditions

VIL1

VIL2

VIH1

VI H2

VOL1

VOL2

Input Low Voltage

Input High Voltage

Output Low Voltage

2.0

VCC+0.5

70% VCC VCC+0.5

0.45

IOL=3.2mA

IOL=1.6mA

IOH=-800uA (Vcc = 5V)

0.45

2.4

VOH1

Output High Voltage

Port 0

90% VCC

2.4

V

IOH=-80uA

IOH=-60uA (Vcc = 5V)

IOH=-10uA

Port

1,2,3,4,ALE,#PSEN

VOH2

IIL

Output High Voltage

90% VCC

Logical 0 Input Current

Port 1,2,3,4

-75

uA

Vin=0.45V

Logical Transition

Current

Port 1,2,3,4

Port 0, #EA

RES

-650

+10

uA

Vin=2.OV

ITL

ILI

Input Leakage Current

uA

0.45V<Vin<VCC

R RES Reset Pull-down

Resistance

50

300

10

Kohm

C^-10

Pin Capacitance

pF

Freq=1 MHz, Ta=25^°C

10

7

mA

Active mode 25MHz

Active mode 16MHz

ICC

Power Supply Current

VDD

7

4.5

10

mA

uA

Idle mode 25MHz

Idle mode, 16MHz

Power down mode

FIGURE 23: ICC IDLE MODE TEST CIRCUIT

FIGURE 24: ICC ACTIVE MODE TEST CIRCUIT

Vcc

Icc

VCC

8

RST

8

PO

EA

PO

EA

RST

VRS51x570

VRS51x580

XTAL2

VRS51x570

VRS51x580

XTAL2

XTAL1

VSS

(NC)

Clock Signal

XTAL1

VSS

Clock Signal

______________________________________________________________________________________________

www.ramtron.com page 35 of 49

VRS51x570/580

AC Characteristics

TABLE 40: AC CHARACTERISTICS

Fosc 16

Variable Fosc

Valid

Symbol

T LHLL

T AVLL

T LLAX

T LLIV

T LLPL

T PLPH

T PLIV

Parameter

ALE Pulse Width

Cycle

Unit

nS

Min.

Type Max.

Min.

Type

Max.

RD/WRT 115

RD/WRT 43

RD/WRT 53

RD

2xT - 10

T - 20

T - 10

Address Valid to ALE Low

Address Hold after ALE Low

ALE Low to Valid Instruction In

ALE Low to #PSEN low

#PSEN Pulse Width

#PSEN Low to Valid Instruction In

Instruction Hold after #PSEN

Instruction Float after #PSEN

Address to Valid Instruction In

#PSEN Low to Address Float

#RD Pulse Width

240

177

4xT - 10

3xT -10

RD

WRT

RD

RD/WRT 178

RD/WRT 230

WRT

RD

53

173

T - 10

3xT - 15

T PXIX

T PXIZ

0

87

292

10

T + 25

5xT - 20

10

T AVI V

T PLAZ

T RLRH

T WLWH

T RLDV

T RHDX

T RHDZ

T LLDV

T AVDV

T LLYL

T AVYL

T QVWH

T QVWX

T WHQX

T RLAZ

T YALH

T CHCL

T CLCX

T CLCH

T CHCX

365

6xT - 10

#WR Pulse Width

#RD Low to Valid Data In

Data Hold after #RD

302

5xT - 10

0

Data Float after #RD

145

590

542

197

2xT + 20

8xT - 10

9xT - 20

3xT + 10

ALE Low to Valid Data In

Address to Valid Data In

ALE low to #WR High or #RD Low

Address Valid to #WR or #RD Low

Data Valid to #WR High

Data Valid to #WR Transition

Data Hold after #WR

#RD Low to Address Float

#W R or #RD High to ALE High

Clock Fall Time

3xT - 10

4xT - 20

7xT - 35

T - 25

403

38

73

T + 10

5

RD/WRT 53

72

T -10

T+10

Clock Low Time

Clock Rise Time

Clock High Time

T,TCLCL Clock Period

63

1/fosc

______________________________________________________________________________________________

www.ramtron.com page 36 of 49

VRS51x570/580

Data Memory Read Cycle Timing

The following timing diagram shows what occurs at each signal during a Data Memory Read Cycle.

FIGURE 25: DATA MEMORY READ CYCLE TIMING

T12

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10 T11 T12

T1

T2

T3

OSC

ALE

1

2

#PSEN

#RD

5

7

3

ADDRESS A15-A8

PORT2

PORT0

3

4

6

8

INST in

Float

A7-A0

Float

Data in

Float

ADDRESS or

Float

______________________________________________________________________________________________

www.ramtron.com page 37 of 49

VRS51x570/580

Program Memory Read Cycle Timing

The following timing diagram shows what occurs at each signal during a Program Memory Read Cycle.

FIGURE 26: PROGRAM MEMORY READ CYCLE

T12

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10 T11 T12

T1

T2

T3

OSC

ALE

1

2

5

7

#PSEN

#RD,#WR

PORT2

PORT0

3

ADDRESS A15-A8

3

4

6

8

Float

A7-A0 Float

INST in Float

A7-A0 Float

INST in Float

______________________________________________________________________________________________

www.ramtron.com page 38 of 49

VRS51x570/580

Data Memory Write Cycle Timing

The following timing diagram shows what occurs at each signal during a Data Memory Write Cycle.

FIGURE 27: DATA MEMORY WRITE CYCLE TIMING

T12

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10 T11 T12

T1

T2

T3

OSC

ALE

1

#PSEN

#WR

5

6

2

ADDRESS A15-A8

3

PORT2

PORT0

2

4

INST in

Float

A7-A0

Data out

ADDRESS or

Float

______________________________________________________________________________________________

www.ramtron.com page 39 of 49

VRS51x570/580

I/O Port Timing

The following timing diagram shows what occurs during I/O Port Timing.

FIGURE 28: I/O PORTS TIMING

T7

T8

T9

T10 T11 T12

T1

T2

T3

T4

T5

T6

T7

T8

X1

Sampled

Inputs P0,P1

Sampled

Inputs P2,P3

Output by Mov

Px, Src

Current Data

Next Data

Sampled

RxD at Serial

Port Shift

Clock Mode 0

______________________________________________________________________________________________

www.ramtron.com page 40 of 49

VRS51x570/580

External Clock Timing

FIGURE 29: TIMING REQUIREMENT OF EXTERNAL CLOCK (VSS= 0.0V IS ASSUMED)

TCLCL

Vdd - 0.5V

70% Vdd

20% Vdd-0.1V

0.45V

TCLCX

TCHCX

TCHCL

TCLCH

External Program Memory Read Cycle

The following timing diagram shows what occurs at each signal during an External Program Memory Read Cycle.

FIGURE 30: EXTERNAL PROGRAM MEMORY READ CYCLE

TPLPH

#PSEN

TLLPL

TLHLL

ALE

TPXIZ

TAVLL TLLAX

A0-A7

TPLIV

TPXIX

TPLAZ

TAVIV

Instruction IN

A0-A7

PORT 0

PORT2

P2.0-P2.7 or AB-A15 from DPH

A8-A15

______________________________________________________________________________________________

www.ramtron.com page 41 of 49

VRS51x570/580

External Data Memory Read Cycle

The following timing diagram shows what occurs at each signal during an External Data Memory Read Cycle.

FIGURE 31: EXTERNAL DATA MEMORY READ CYCLE

#PSEN

TYHLH

ALE

TLLDV

TRLRH

TLLYL

#RD

TRLDV

TRHDZ

TRHDX

DATA IN

TAVLL

TLLAX

A0-A7

TRLAZ

A0-A7

From PCL

INSTRL

IN

PORT 0

PORT 2

From Ri or DPL

TAVYL

TAVDV

P2.0-P2.7 or A8 -A15 from DPH

A8-A15 from PCH

______________________________________________________________________________________________

www.ramtron.com page 42 of 49

VRS51x570/580

External Data Memory Write Cycle

The following timing diagram shows what occurs at each signal during an External Data Memory Write Cycle.

FIGURE 32: EXTERNAL DATA MEMORY WRITE CYCLE

#PSEN

TYHLH

ALE

TLHLL

TLLYL

TWLWH

#WR

TAVLL

TQVWX

TWHQX

TLLAX

TQVWH

A0-A7

From PCL

A0-A7

From Ri or DPL

INSTRL

IN

DATA OUT

PORT 0

PORT 2

TAVYL

P2.0-P2.7 or A8-A15 from DPH

A8-A15 from PCH

.

Plastic Chip Carrier (PLCC)

______________________________________________________________________________________________

www.ramtron.com page 43 of 49

VRS51x570/580

VRS51x570

VRS51x580

PLCC-44

E

HE

D

HD

C

e

b

b1

GD

Note:

1. Dimensions D & E do not include interlead Flash.

2. Dimension B1 does not include dambar protrusion/intrusion.

3. Controlling dimension: Inch

4. General appearance spec should be based on final visual inspection spec.

______________________________________________________________________________________________

www.ramtron.com

page 44 of 49

VRS51x570/580

L

GE

Y

A2

A

A1

TABLE 41: DIMENSIONS OF PLCC-44 CHIP CARRIER

Dimension in inch

Symbol

Dimension in mm

Minimal/Maximal

-/4.70

Minimal/Maximal

A

-/0.185

Al

A2

bl

b

C

D

E

e

GD

GE

HD

HE

L

0.020/-

0.51/

0.145/0.155

0.026/0.032

0.016/0.022

0.008/0.014

0.648/0.658

0.050 BSC

0.590/0.630

0.680/0.700

0.090/0.110

-/0.004

3.68/3.94

0.66/0.81

0.41/0.56

0.20/0.36

16.46/16.71

1.27 BSC

14.99/16.00

17.27/17.78

2.29/2.79

-/0.10

?

?y

/

______________________________________________________________________________________________

www.ramtron.com page 45 of 49

VRS51x570/580

Quad Flat Package (QFP)

2

R1

VRS51x570

VRS51x580

QFP-44

D2 D1 D

Gage Plane

0.25mm

3

R2

E2

E1

E

e1

C

Seating Plane

e

Note:

1. Dimensions D1 and E1 do not include mold protrusion.

2. Allowance protrusion is 0.25mm per side.

3. Dimensions D1 and E1 do not include mold mismatch and are determined datum plane.

4. Dimension b does not include dambar protrusion.

5. Allowance dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition.

Dambar cannot be located on the lower radius of the lead foot.

______________________________________________________________________________________________

www.ramtron.com

page 46 of 49

VRS51x570/580

C

L

L1

S

b

A2

A1

A

TABLE 42: DIMENSIONS OF QFP-44 CHIP CARRIER

Dimension in in.

Symbol

Dimension in mm

Minimal/Maximal

-/2.55

Minimal/Maximal

A

-/0.100

Al

A2

b

c

D

D1

D2

E

E1

E2

e

0.006/0.014

0.071 / 0.087

0.012/0.018

0.004 / 0.009

0.520 BSC

0.394 BSC

0.315

0.520 BSC

0.394 BSC

0.315

0.031 BSC

0.029 / 0.041

0.063

0.005/-

0.005/0.012

0.008/-

0.15/0.35

1.80/2.20

0.30/0.45

0.09/0.20

13.20 BSC

10.00 BSC

8.00

13.20 BSC

10.00 BSC

8.00

0.80 BSC

0.73/1.03

1.60

0.13/-

0.13/0.30

0.20/-

L

L1

R1

R2

S

0

0°/7°

as left

? 1

? 2

? 3

?C

0°/ -

10° REF

7° REF

as left

0.10

0.004

______________________________________________________________________________________________

www.ramtron.com page 47 of 49

VRS51x570/580

Ordering Information

Device Number Structure

VRS51x570 Ordering Options

Device Number

Flash Size

RAM Size

Package

Option

Voltage

Temperature

Frequency

VRS51C570-40-L

VRS51L570-25-L

VRS51C570-40-Q

VRS51L570-25-Q

32KB

1KB

PLCC-44

QFP-44

4.5V to 5.5V

3.0V to 3.6V

4.5V to 5.5V

3.0V to 3.6V

-40°C to +85°C

40MHz

25MHz

40MHz

25MHz

VRS51C570-40-P

VRS51L570-25-P

VRS51C570-40-LG

VRS51L570-25-LG

VRS51C570-40-QG

VRS51L570-25-QG

VRS51C570-40-PG

VRS51L570-25-PG

32KB

1KB

DIP-40

4.5V to 5.5V

3.0V to 3.6V

4.5V to 5.5V

3.0V to 3.6V

4.5V to 5.5V

3.0V to 3.6V

4.5V to 5.5V

3.0V to 3.6V

-40°C to +85°C

40MHz

25MHz

40MHz

25MHz

40MHz

25MHz

40MHz

25MHz

PLCC-44

QFP-44

DIP-40

______________________________________________________________________________________________

www.ramtron.com page 48 of 49

VRS51x570/580

VRS51x580 Ordering Options

Device Number

Flash Size

RAM Size

Package

Option

Voltage

Temperature

Frequency

VRS51C580-40-L

VRS51L580-25-L

VRS51C580-40-Q

VRS51L580-25-Q

64KB

1KB

PLCC-44

QFP-44

4.5V to 5.5V

3.0V to 3.6V

4.5V to 5.5V

3.0V to 3.6V

-40°C to +85°C

40MHz

25MHz

40MHz

25MHz

VRS51C580-40-P

VRS51L580-25-P

VRS51C580-40-LG

VRS51L580-25-LG

VRS51C580-40-QG

VRS51L580-25-QG

64KB

1KB

DIP-40

PLCC-44

QFP-44

4.5V to 5.5V

3.0V to 3.6V

4.5V to 5.5V

3.0V to 3.6V

4.5V to 5.5V

3.0V to 3.6V

-40°C to +85°C

40MHz

25MHz

40MHz

25MHz

40MHz

25MHz

VRS51C580-40-PG

VRS51L580-25-PG

64KB

1KB

DIP-40

4.5V to 5.5V

3.0V to 3.6V

-40°C to +85°C

40MHz

25MHz

Disclaimers

Right to make change - Ramtron reserves the right to make changes to its products - including circuitry, software and services - without notice at

any time. Customers should obtain the most current and relevant information before placing orders.

Use in applications - Ramtron assumes no responsibility or liability for the use of any of its products, and conveys no license or title under any

patent, copyright or mask work right to these products and makes no representations or warranties that these products are free from patent,

copyright or mask work right infringement unless otherwise specified. Customers are responsible for product design and applications using Ramtron

parts. Ramtron assumes no liability for applications assistance or customer product design.

Life support – Ramtron products are not designed for use in life support systems or devices. Ramtron customers using or selling Ramtron products

for use in such applications do so at their own risk and agree to fully indemnify Ramtron for any damages resulting from such applications

______________________________________________________________________________________________

www.ramtron.com

page 49 of 49


型号：	VRS51L570-25-L-G
厂家：	ETC
描述：	Versa 8051 MCUs with 32/64KB 的Versa 8051 MCU可提供32 / 64KB
文件：	总49页 (文件大小：2071K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

VRS51L570-25-L-G [ETC]

相关型号：

VRS51L570-25-LG

VRS51L570-25-P

VRS51L570-25-P-G

VRS51L570-25-PG

VRS51L570-25-Q

VRS51L570-25-Q-G

VRS51L570-25-QG

VRS51L570-40-L

VRS51L570-40-L-G

VRS51L570-40-P

VRS51L570-40-P-G

VRS51L570-40-Q