VZN20 [ETC]
NOCKANSCHALTER VARIO 20A ; NOCKANSCHALTER VARIO 20A\n
| 型号： | VZN20 |
| 厂家： | 
ETC |
| 描述： | NOCKANSCHALTER VARIO 20A
|
| 文件： | 总19页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W.A.R.P. 1.1
WEIGHT ASSOCIATIVE RULE PROCESSOR
ADVANCED DATA
High Speed Rules Processing
Antecedent Membership Functions with any
Shape
Up to 256 Rules (4 Antecedents,1
Consequent)
Up to 16 Input ConfigurableVariables
Up to 16 Membership Functions for an Input
Variable
Up to 16 OutputVariables
Up to 128 Membership Functions for all
Consequents
CPGA 100
PLCC84
MAX-DOT Inference Method
Defuzzification on chip
Figure 1. Logic Diagram
MCLK VS S VDD
Software Tools and Emulators Availability
100-pin CPGA100 Ceramic Package
84-lead Plastic Leaded Chip Carrier package
GENERAL DESCRIPTION
10
FIN
W.A.R.P. is a VLSI Fuzzy Logic controller whose
architecture arises from the need of realizing an
integrated structure with high inferencing perform-
ances andflexibility. To get those results a modular
architecture based on a set of parallel memory
blocks has been implemented.
In orderto obtainhigh performancesW.A.R.P.uses
different data representations during the various
phases of the computational cycle, so that it is
always operating on the optimal data repre-
sentation. A vectorial characterization has been
adopted for the Antecedent Membership Func-
tions. W.A.R.P. exploits a SGS-THOMSON pat-
entedstrategyto store the AntecedentMembership
O0-O9
SYNC
4
8
OCNT0-OCNT3
I0-I7
EPA0-EPA2
A0-A9
W.A.R.P.
1.1
3
STB
NP
10
EP
CHM OFL PRST
Table 1. W.A.R.P. Configuration Settings
Number of Inputs
Configurable [1..8]
Standard Rule Format
Rules Number
4 Antecedents, 1 Consequent [or subsets]
Max 256 Rules in the 4 Antecedent, 1 Consequent format
Antecedent’s MFs Number
Consequent’s MFs Number
Input Data Resolution
Output Data Resolution
Configurable [up to 16 for an input variable]
Max 256 for all outputs variables
8 bit
8 bit
1/19
May 1996
This is advance information on a new productnow in development or undergoing evaluation. Details are subject to change without notice.
W.A.R.P.1.1
Figure 2. CPGA100 Pin Configuration
Table 2. Absolute Maximum Ratings
Symbol
VDD
VI
Parameter
Supply Voltage
Value
-0.5 to 7
Unit
V
Input Voltage
-0.5 to VDD+0.5
-0.5 to VDD+0.5
+24
V
VO
Ouput Voltage
V
IOL
Output Sink Peak Current
Output Source Peak Current
Operating Temperature
Storage Temperature (Ceramic)
Storage Temperature (Plastic)
mA
mA
°C
°C
°C
IOH
-12
TOPT
0 to +70
-65 to +150
-45 to +125
TSTG
Notes:
Stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating
sections of thisspecification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect
device reliability.Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.
2/19
W.A.R.P.1.1
Figure 3. PLCC84 Pin Configuration
11 10
9
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75
12
74
73
72
71
70
69
68
67
66
65
64
63
62
VSS
13
14
15
16
17
18
19
20
21
22
23
24
VDD
VSS
VDD
MCLK
I0
I1
SYNC
OTST
OMTS
STB
I2
I3
I4
I5
EP
I6
VSS
W.A.R.P. 1.1
I7
NP
CHM
OCNT3
OCNT2
OCNT1
OCNT0
FIN
OFL
PRST
TE
25
26
27
28
29
61
60
59
58
57
56
55
54
MTE
VSS
VSS
VDD
30
31
32
VDD
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
Table 3. Recomended Operation Conditions (Ta=0 to +70 °C unless otherwise specified)
Symbol
VDD
Parameter
Supply Voltage
Min
Typ
Max
5.25
0.8
Unit
V
4.75
5.0
VIL
Input Voltage
V
VIH
Input Voltage
2
V
VOL
Ouput Voltage
0.5
V
VOH
FCLK
CL
Ouput Voltage
2.4
10
V
Clock Frequency
Output Load Capacitance
40
85
MHz
pF
3/19
W.A.R.P.1.1
Table 4. Pin Description
Name
VDD
Pins Type
Function
-
-
Power Supply
VSS
Ground
A0-A9
I0-I7
I/O
I
Memory Address Bus
Data Input Bus
Preset
PRST
FIN
I
I
First Input Signal
Off-Line/On-Line Switch
Charge Mode Switch
OFL
I
CHM
I
TE
I
Testing (it must be connected to VSS
Testing (it must be connected to VSS
Clock (up to 40 MHz)
)
)
MTE
I
MCLK
EPA0-EPA2*
O0-O9
OCNT0-OCNT3
STB
I
O
O
O
O
O
O
O
O
O
EPROM Address Bus
Defuzzified Output
Output Counter
Strobe (Output Ready Signal)
End Process
EP
NP
New Process
OTST
OMTS
SYNC
Testing (it must be connected to VSS
Testing (it must be connected to VSS
External Synchronization
)
)
* Pins not used in W.A.R.P. 1.0
Functionsindedicatedmemories in orderto reduce
the computationaltime. Therefore a great amount
of W.A.R.P. processing is based on a look-up table
approach rather than on on-line calculation.
tional microcontrollers which shall perform normal
control tasks while W.A.R.P. will be indipendently
responsible for all the fuzzy related computing.
W.A.R.P. is manufactured using the high perform-
ance, reliable HCMOS4T (O.7µm) SGS-THOM-
SON Microelectronics process.
Those Membership Functions (MFs), each one
portrayed by a configurable resolution of 26 or 27
elements, are stored in four internal RAMs (1Kbyte
each). The consequent MFs, due to the different
modelling, are loaded in a single RAM by storing
for each MF its area and its barycentre. This is due
to theadoption of the Center ofGravity defuzzifica-
tion method.
PIN DESCRIPTION
V
DD, VSS: Power is supplied to W.A.R.P. using
these pins. VDD is the power connectionand VSS is
the ground connection;multi-connections are nec-
essary.
The downloading phase allows the setting of the
device, in terms of I/O number, universes of dis-
course andMF shapes. Duringthis phase W.A.R.P.
prepares its internal memories for the on-line
elaboration phase and loads the microcode in its
programmemory. Thismicrocode, which drives the
on-line phase, is generated by the Compiler (see
W.A.R.P.-SDT User Manual) according to the
adoptedconfiguration.Thepossible configurations
are shown in table 1.
A0-A9: When the CHM pin is low they accept as
input the addresses for the internalmemory bus. In
the off-linemode theyareused toaddress W.A.R.P.
memories where the microprogram and data of
antecedentand consequentmembership functions
must be loaded.
Each A0-A9 word is composed by assembling the
data containedin the memorysupport related to .cs
and .add files (see W.A.R.P.-SDT User Manual). In
particular,couplesofdatarespectivelycoming from
.cs and .add files are joined to form a single A0-A9
word in the following way:
During the on-line phase (up to 40MHz working
frequency),W.A.R.P. processes the input data and
produces its outputsaccording to the configuration
loaded in the downloading phase.
W.A.R.P. is conceived to work together with tradi-
4/19
W.A.R.P.1.1
must be sent to W.A.R.P. from the outside by
means of the input pins A0-A9.
When CHM is high W.A.R.P. automaticallygener-
ates the addresses of its internal memories and
manages the EPROMs reading by means of the
addresses contained in EPA0-EPA2 and A0-A9
output pins (13 bits).
add7 add6 add5 add4 add3 add2 add1 add0
cs6 cs5 cs4 cs3 cs2 cs1 cs0
cs7
TE: For testing purpose only. It must be connected
to VSS
.
cs2 cs1 cs0 add6 add5 add4 add3 add2 add1 add0
MTE: For testing purpose only. It must be con-
nected to VSS
A9
A0
.
MCLK: This is the input master clock whose fre-
quency can reach up to 40MHz (MAX).
During the off-line phase with CHM high, the
DCLK signal with a frequency of MCLK/32 is gen-
erated in order to drive the downloading phase
timing.
This resulting word allows to identify the appropri-
ate memory [cs2-cs0] and its respective address
[add6-add0] where the relative I0-I7 are to be
stored.
When the CHM pin is high, during the off-line
phase, W.A.R.P. generates the addresses for its
internalmemories and sendthoseaddresses to the
single external memory support where data (.dat
file) are located. These addresses, which are sent
by means of the EPA0-EPA2 and A0-A9 (EPA0
MSB, A9 LSB) output pins, allow to identify the
data (on the EPROM) that have be loaded in
W.A.R.P. internal memories.
EPA0-EPA2: During the off-line phase and in cor-
respondencewith CHM high, theseoutputpins are
joined (as MSB) to A0-A9 to obtaine the complete
address of the memory support where to read the
data to be loaded in W.A.R.P. internal memories.
EPA0-EPA2 are not used when CHM is low or in
W.A.R.P. 1.0 release.
O0-O9: These pins carry out the output values.
When the STB (strobe pin) is high, one output
variable can be read by external devices(in on-line
mode). The resolution of output variables is 1024
points (10 bits). If there are more than one output,
the output variables are calculated one by one and
they are provided in the sequencestabilized during
the editing phase (see W.A.R.P.-SDT User Man-
ual).
In on-line mode A0-A9 are not used.
I0-I7: During the off-line phase these 8 data input
pins accept the microcode configuration and data
to be written into the internal memories. The ante-
cedent memory word size is 64 bits, so it is neces-
sary to give each word 8 bits at a time. In the same
way are written the words of consequent memory
and of program memory.
In on-line mode this bus carries the input variables
to W.A.R.P.. Input values have a resolution of 6 or
7 bits in accordance with the configuration setting.
OCNT0-OCNT3: This4 bit outputbus provides the
output variables with a progressive number during
the on-line phase. As a consequenceit is possible
to know to which variable correspond the data that
are on the outputdata bus (O0-O9).The dimension
of OCNT bus is connected with the maximum
number of output variables (16).
PRST: This is the restart pin of W.A.R.P.. It is
possible to restart thework during the computation
(on-line phase) or before the writing of internal
memories (off-line phase). In both cases it must be
put low at least for a clock period.
STB: The strobe pin enables the user to utilize the
output. When thispin is high itindicates that a new
output variable has been calculated and it is ready
on the output bus (O0-O9). This signal synchro-
nizes the external devices and in particular the
interfaces with the controlled processes (on-line
mode).
FIN: During the on-line phase it will start the run-
time acquisition cycle. This pin is activated by
providing a positive pulse for a time no lower than
an entire clock period. When all expected inputs
have been processed, a new FIN pulse must be
sent to activate a new process.
OFL: When this pin is high, the chip is enabled to
load data in the internal RAMs (off-line phase). It
must below when the fuzzycontrolleris waiting for
input values and during the processing phase (on-
line phase).
EP: This signal low indicates that the processing
of all the rules has been completed.
NP: This output pin indicates that a new process
can start. NP is automatically set low before the
lastoutputhas beencalculated, so thatit ispossible
to start a new data acquisition before (with a new
FIN) the computation is terminated.
CHM:Thispin,which isusedonly duringthe off-line
phase, determines the charge mode. CHM is not
present in W.A.R.P. 1.0 release.
When CHM is low the addresses of the internal
memory locations where data have to be stored
5/19
W.A.R.P.1.1
Figure 4. Block Diagram
OTST: For testing purpose only. It must be con-
Off-line MODE (OFL High)
On-line MODE (OFLLow)
OFF-LINE MODE
nected to VSS
.
OMTS: For testing purpose only. It must be con-
nected to VSS
.
All W.A.R.P. memories are loaded during the off-
line phase. The membership functions are written
inside their related memories and theprocess con-
trol rules are loaded inside the program memory.
If the CHM switch has been set low then the
addresses of the words to be written in the memo-
ries are provided by an external bus (A0-A9), while
data must be loaded 8 bit a time in the data bus.
If the CHM switch has been set high then the
addresses of the words to be written in the memo-
ries are internally generated while the addresses
of the EPROM’s locations to be read are directly
SYNC: W.A.R.P. uses this pin to synchronize input
data from an external database in off-line mode.
The database contains information about antece-
dent and consequent membership functions and
about fuzzy rules. To memorize this database it is
possible to use an host processor or a non volatile
memory.
FUNCTIONAL DESCRIPTION
W.A.R.P. works in two modedependingon the OFL
control signal level:
Table 5. Available Configurations on a Single Antecedent Memory.
Number of Membership Functions
for TermSet
Numbers of Input
Data Resolution
1
2*
2
128 (7 bit)
128 (7 bit)
64 (6 bit)
64 (6 bit)
64 (6 bit)
16
8
16
2x8 + 1x16
8
3
4
* This configuration is not available in W.A.R.P. 1.0.
6/19
W.A.R.P.1.1
provided by W.A.R.P. by means of A0-A9 and
EPA0-EPA2output pins.
Data must be loaded 8 bit a time in the data bus
and can be read from an external non volatile
memory or loaded by an host processor.
Input Router. This internal block performs the
input data routing. Data are read one byte a time
from the input data bus, storedin 4 different buffers
and, thanks to a pipeline process, sent together to
4 indipendent modules to be processed in parallel
according to the chosen set-up configuration.Input
data resolution is decided by the user (MAX 128
points) according to the available configurations,
as shown in table 5.
ON-LINE MODE
In On-line mode W.A.R.P. is enabled to elaborate
input values andcalculate outputsaccording to the
fuzzy rules stored into the microprogram. W.A.R.P.
reads the input values one a time in the input data
bus when all the inputs are given, a NP signal is
pulledhigh to indicate that the computationis start-
ing.Thecomputationalphaseisdividedintwo main
parts. During the first one the input values are read
and the corresponding ALPHA values (activation
levels) are extractedfrom theinternal memories. In
the second part the computation of the fuzzy rules
and the defuzzification are implemented.
The cycle starts when a positive pulse is applied at
FIN for a time no lower than an entireclock period
and continues until a new FIN (after NP low) or a
PRST signal is given.
Fuzzifier. This block generates the addresses of
the antecedentmemories wheretheALPHAvalues
for each sampled input value are stored. It reads
the first four input values and calculates the corre-
sponding antecedent memories addresses. After-
wards it reads other four inputs values and
simultaneously sends, thanks to a pipeline proc-
ess, the previous four ALPHA values into internal
registers.TheseALPHAvalues are then sent to the
Inference Unit. W.A.R.P. stores all ALPHA values
comprising a term set, which is formed by the MFs
connected to the IF-part of a rule, in successive
memory locations of the same memory word (see
figure 4). The vectors characterizing the MFs of a
term set are stored so that the ALPHAs of different
MFs corresponding to the same universe of dis-
course point (for the same input) are stored se-
quentially. So W.A.R.P. retrieves all the alpha
values of a term set using the crisp input value to
calculate the memory word address in the used
fuzzy memory device.The Fuzzifier Unit is driven
The block diagram shown in figure 3 describes the
structure of W.A.R.P..
Antecedent Memory. It is formed by 4 benchs
each one containing one to four fuzzy sets bonded
to the input variables.
Consequent Memory. It is formed by one bench
where the fuzzysetsbondedto theoutputvariables
are stored .
Program Memory. It is formed by a single bench.
Each line contains an operating code to execute
the computation of a rule. This code selects the
antecedentweights(ALPHA) involvedin a rule, and
connectsthem by the programmed connective op-
erators (AND,OR).
Figure 5. Antecedent Memory Organization
7/19
W.A.R.P.1.1
Figure 6. Inference Unit Structure
by the configurationin accordancewith the antece-
dent part of the fuzzy rules. The duration of the
fuzzification process depends from the chosen
configuration and the input number.
is firstly modified by a rule weight in accordance to
MAX-DOT method.
Output value (X) is deduced from the centroids (x)
i
and themodified MFs (Ωi *Ai) by using the formula:
Inference Unit. Thanksto the Theta Operator, the
InferenceUnit generatesthe THETA weights which
are used to manipulate the consequent MFs.
n
Ω i
A i
x i
∑
This is a calculation of the maximum and/or mini-
mum performed on ALPHAvalues according to the
logical connectives of fuzzy rules. It is possible to
utilize the AND/OR connectives and to directly ex-
ploit ALPHA weights or the negated values. The
numberof THETA weights depends on the number
of rules.
1
X =
n
Ω
A i
i
∑
1
n = number of MFs defined for the Output Variable
Ai= MFi Area
The rules can have at maximum four ALPHA
weights (however they are connected). Two or
more rules can be only joined with the OR connec-
tive.
xi=absciss of the MFi centroid
Ωi =membership degree of the output MFi.
Inference Unit structure is shown in figure 5.
To represent a membership function related with
the THEN-part of a rule W.A.R.P. uses a single
memory bench. For each consequent MF each
memory wordcontainsboththearea multiplied with
the barycentre and the area itself. This area is
related to the first truth level (there are 16 truth
levels (4 bit), so a multiplication with the calculated
THETA must be performed on-line.
Defuzzifier. It generates the output crisp values
implementing the consequent part of the rules ac-
cording to MAX-DOT method.
In this method consequent MFs are multiplied by a
weight value Ω (OMEGA), which is calculated on
the basis of antecedent MFs and logical operators.
Allthe termsneeded to evaluatesumsinnumerator
and denominator of center of gravity equation (see
formula) are stored during the off-line phase.
Two parallel blocks calculate the numerator and
denominator values to implement the centroids
formula. A final division block calculates the output
values (see figure 6).
The processing of fuzzy rules produces, for each
output variable, a resulting membership function.
Each MF related to the processed output variable
8/19
W.A.R.P.1.1
Figure 7. Defuzzifier Structure
ELECTRICAL SPECIFICATIONS
DC PARAMETRICS Across Temperature Range (T=0 to +70 °C unless otherwise specified) -
TTL INTERFACE
2.4V
2V
2.4V
0.4V
0.8V
0.4V
Input
Output
Table 6. DC Characteristics
Symbol
VIL
Parameter
Min
Typ
Max
Unit
V
Low Level Input Voltage
High Level Input Voltage
Low Level Output Voltage
High Level Output Voltage
Low Level Input Current
High Level Input Current
0.8
VIH
2.0
V
VOL
VOH
IIL
0.2
3.4
0.4
V
2.4
V
VI=VSS
VI=VDD
+1
-1
µA
µΑ
IIH
9/19
W.A.R.P.1.1
DC PARAMETRICS
DC PARAMETRICS Across Temperature Range (T=0 to +70 °C unless otherwise specified
TTL INTERFACE
tCLL
tCLH
50%
tC P
50%
Data
tSET
tHLD
50%
Clock
Table 7. AC Characteristics
CK=20MHz
CK=40MHz
Symbol
Parameters
Test Conditions
Unit
Min
Max Min
Max
tCP
tCLH
tCLL
tCR
Clock Period
Clock High
Clock Low
Clock Rise
Clock Fall
Setup
50
25
30 10
30 10
4
ns
ns
ns
ns
ns
ns
ns
20
15
15
4
20
0.8V to 2V
2V to 0V
tCF
4
4
tSET
tHLD
12
15
12
Hold
15
10/19
W.A.R.P.1.1
W.A.R.P. TIMING TABLES
Off-line Phase Timing (Internal RAMs Loading with Charge Mode ”0”)
O F L
F IN d e te c tio n
D ATA0 a c q uis ition
D ATA1 a c q uis ition
D ATAn a c q uis ition
M C L K
F IN
T
A C Q
D ATA 0
D ATA 1
D ATA n
I0 -I6
N P
E P
T
AC Q
=
2 0 0 n s fo r a c o n fig u ra tio n w ith 1 6 in p u ts , 8 o u tp u ts , 2 8 ru le s
Timing Table Description: OFF-LINE phase (CHM ”0”)
- CHM [INPUT] low will enable the ’manual downloading’by specifying the address and data to be loaded
into W.A.R.P..
- MCLK [INPUT] must be connected with the external synchronization signal.
- PRST [INPUT] must be set high to enable the device.
- OFL[INPUT]must be sethigh toenablethe configurationloading phase into theinternalRAMs of W.A.R.P..
- The input to be written into the internal memories at the address specified in A0-A9 must be put into I0-I7
bus .
- SYNC [OUTPUT] will be provided to synchronize input data (I0-I7,A0-A9) coming from an external
database.SYNC frequency is MCLK/32 with a phase delay of tCSP ns . W.A.R.P. stores the data present
on input buses at the rising edge of MCLK, returns a SYNC pulse after tCSP ns indicating that is waiting for
new data and address that must be given within next 31MCLK pulses. Afterwards W.A.R.P. stores the data
on input buses and restores a new SYNC pulse.
W.A.R.P. stores the data situated in I0-I7 andthe addresses A0-A9 into its internal registers.
Figure 8. Block Diagram for W.A.R.P. downloading (CHM ”0”)
11/19
W.A.R.P.1.1
Off-line Phase Timing (Internal RAMs Loading with Charge Mode ”1”)
C HM
P R S T
MC LK
W.A.R .P. store s DATA0
W.A.R .P. store s DATA1
W.A.R .P. store s DATAn
DC LK
O F L
E PA0 -E PA2 +
A0-A9
AD DRE S S 0
AD DR E S S 1
AD DRE S S n
DATA0
DATA1
DATAn
I0 -I7
S YNC
Timing Table Description: OFF-LINE phase (CHM ”1”)
- CHM [INPUT] high will enable the ’automatic downloading’, specifying the address of the non-volatile
memory where are data to be loaded into W.A.R.P.. Internal memory addresses are automatically
generated.
- MCLK [INPUT] must be connected with the external synchronization signal.
- PRST [INPUT] must be set high to enable the device.
- OFL [INPUT] must be set high to enable the loading phase of data into the internal RAMs of W.A.R.P..
- SYNC [OUTPUT] will be provided to synchronizeinput data (I0-I7) coming from the external database.
SYNC frequencyis MCLK/32.
- DCLK [INTERNAL] sets theworking frequencyaccordingto theOFL controlsignal.It drives theaddressing
of data coming from the externalmemory support by the I0-I7 input bus. The externalmemory support must
return the data (addressed by EPA0-EPA2+A0-A9 [OUTPUT]) into I0-I7 in a period of time no longer than
half a period of DCLK. DCLK frequency is MCLK/32.
Figure 9.
Block Diagram for W.A.R.P. downloading (CHM ”1”)
12/19
W.A.R.P.1.1
On-line Phase Timing (Acquisition and Elaboration) Working Frequency 40MHz
OFL
DATA1 acquisition
FIN detection
DATA0 acquisition
DATAn acquisition
MCLK
FIN
T
ACQ
DATA0
DATA1
DATAn
I0-I6
NP
EP
T
ACQ = 200 ns for a configuration with 16 input s, 8 outputs, 28 rules
Timing Table Description: ON-LINE phase
1st step: Acquisition
- MCLK [INPUT] must be connectedwith the external synchronization signal.
- OFL [INPUT] must be set low to enable the acquisition/elaborationphase of W.A.R.P..
- FIN [INPUT] must be set high for at least 1clock period to start the acquisition phase. OFL must already
be low since at least 4 clock periods before providing a FIN pulse. FIN duration must be in the range
[1clock,2clockperiods]. FIN pulse mustn’t coincide with NP transitions.
- NP [OUTPUT] will remain low during the acquisition phase.
- The input data must be sent to I0-I6 after OFL has been set low and FIN has been set high. Data situated
in I0-I6 are stored into its internal registers at each next rising edge of the MCLK.
- After the current inputs have been acquired, the NP [OUTPUT] high signal informs that the elaboration
phase can start. This information is provided thanks to the configuration stored in the program memory.
Figure 10. Input/Output Connection Block Diagram
13/19
W.A.R.P.1.1
On-line Phase Timing (Output Generation) Working Frequency 40MHz
MCLK
d ata output
storag e
data output
storage
d ata output
storag e
S TB
start of
computation
NEW DATA
ACQUISITION
NP
EP
COMP
COMP
COMP
T
COMP
T
T
T
end of
computation
last output data
DATA OUT 2
DATA OUT n-1
DATA OUT 1
OUT NUM 1
O0-O9
la st output number
OUT NUM 2
OUT NUM n-1
OCNT0-3
T
comp= 600 ns (first process, pipeline empty), 310 ns (next proces ses) for a configuration with 16 inputs, 8 outputs, 28 rules
.
Elapsed time from the first data acquisition to the first output: 810 ns for the first cycle , 525ns for the other ones
Timing Table Description: ON-LINE phase
2nd step:Elaboration
- MCLK [INPUT] must be connectedwith the external synchronization signal.
- OFL [INPUT] must remain low during this phase.
- NP [OUTPUT] remains high during this phase.
- EP [OUTPUT] is set high during this phase.
- STB [OUTPUT] is set high for a clock period every time an output value has been calculated. It informs
that it is possible to utilize the outputwhich is situated in the output bus (O0-O9). The STB pulse starts at
the rising edge of the MCLK and stops at the next rising edge of the MCLK. At the falling edge of the STB
the data situated on the O0-O9 bus can be stored.
- The current output on the O0-O9 [OUTPUT] bus is provided exactly when the STB signal rises and it
does not change until a new STB signal occurs.
- The output identifier on theOCNT0-OCNT3 [OUTPUT] bus is provided exactly when the STB signal rises
and it does not change until a new STB signal occurs.
- NP [OUTPUT] is set low when the penultimate STROBE is disabled allowing a new acquisition phase to
start while W.A.R.P. is still elaborating the last output.
- When the last output has been provided, EP will be automaticallyset low.
14/19
W.A.R.P.1.1
PROGRAMMING TOOL
FUZZYSTUDIO 1.0 - W.A.R.P. Software Development Tool
Figure 11. W.A.R.P. Software Development Tools
BASIC TOOLS
EDITOR
SUPPORT TOOLS
EXPORTER
EMULATOR
C model
FUZZYSTUDIO
MODELER
RULE
EXTRACTOR
&
MATLAB
OPTIMIZER
FUZZYSTUDIO
APPLICATION
DEVELOPMENT
BOARD
RS232
INTEL HX
FILE
COMPILER
FUZZYSTUDIO
S IMULATOR
Proprietary
DEBUGGER
ANCILLARY,
HIGH LEVEL
SUPPORT TOOLS
FUZZYSTUDIO
W.A.R.P.-SDT
SGS-THOMSON has developed some software
tools(see figure11)to supportthe use of W.A.R.P.1
allowing easy configurating and loading of the
memoriesandfunctionalsimulations.It isfullycom-
patible with the W.A.R.P. board.
It has been designed in order to be used with the
following hardware/software requirements:
to check the results of the entire control process
by using a list of patterns stored into a file.
It allows to show:
– Alpha values
– Theta values
– Defuzzification partial values
– Output values
80386 (or higher) processor
W.A.R.P.-SDT Exporter:
VGA / SVGAscreen
it generatesfiles to be imported indifferentenviron-
ments in order to develop W.A.R.P. based simula-
tions exploiting user-developed models.
Windows Version 3.0 or Higher
The constituting blocks are:
W.A.R.P.-SDT Editor:
It addresses the following environments:
it is a tool to define the fuzzy controller with a
User-Friendly Interface.
Standard C: the exporter generates a C function
that can be recalled by an user program
It is composed by:
– Variable Editor (to define the I/O variable)
– Membership Editor (to define the member-
ship function shape)
Matlab: the exporter generates a ’.M’ file that can
be used to perform simulations in Matlab environ-
ments
W.A.R.P.-SDT Simulator:
– Rule Editor (to define the base of knowledge)
it allows to:
– define models of the controlled system in
terms of differential equations
– define the external inputs and set points
– resolve the differential equations by using
Runge-Kutta algorithm
W.A.R.P-SDT Compiler:
it generates the code to be loaded in W.A.R.P.
memories according to the data defined through
the editor. It also generates the data base for
Debugger, Exporterand Simulator.
W.A.R.P-SDT Debugger:
– functionally simulate W.A.R.P.
it allows the userto examinestep-by-stepthe fuzzy
computationfor a defined application. It also allows
– show the simulation results in graphic
charts.
15/19
W.A.R.P.1.1
W.A.R.P. Application Development Board
An automatic trigger is used to synchronize
W.A.R.P. with the external environment (working
connectedwith a PC).
When the board is used as a stand alone device all
the fuzzy data (membership functions and rules)
are storedinEPROMs. Theboard allows thestand-
alone/PCworking to be selected by settinga switch
(see W.A.R.P.-SDT User Manual). A block diagram
of the board is described in figure 12.
The board has been designed to be connected to
the RS232 port of an IBM PC 386 (or higher), but
it canalso work stand alone. Inputs and outputs are
provided at TTLcompatible level. The board allows
the user to charge the rules and the membership
functions (seeW.A.R.P.-SDTUserManual) into the
W.A.R.P. memories.
It can manage up to 16 inputs and 16 outputs.
The clock generatorfrequencyon board is 24MHz.
Figure 12. Board Block Diagram
16/19
16/15
W.A.R.P.1.1
PACKAGE DIMENSIONS
mm
inch
Typ.
Dim.
Min.
Typ.
Max.
Min.
Max.
A
A1
A3
B
4.20
5.08
0.16
0.19
0.56
2.54
0.38
0.02
0.10
0.01
B1
D
1.14
0.003
1.19
1.15
1.13
1.19
1.15
1.13
30.10
29.20
27.69
30.10
29.20
27.69
30.35
29.41
28.70
30.35
29.41
28.70
1.18
1.14
1.11
1.18
1.14
1.11
D1
D3
E
E1
E3
e
1.27
0.05
D
30.10
29.20
27.69
30.35
29.41
28.70
0.50
1.18
1.14
1.11
1.19
1.15
D1
D3
F
1.13
0.020
0.070
G
1.78
Figure 13. W.A.R.P. 84 Pin PLCC84 Plastic Package
NE
h
Number of Pins
Pin 1
h
K1
B
B1
D3 D1
D
ND
e
L
E3
E1
E
A1
A3
A
VR01534
17/19
W.A.R.P.1.1
PACKAGE DIMENSIONS
mm
Typ.
inch
Typ.
Dim.
Min.
Max.
33.58
17.78
2.24
Min.
Max.
1.332
0.700
0.088
0.100
0.185
0.055
0.065
1.212
A
B
C
c1
D
2.54
4.70
d1
d2
E
1.40
1.68
30.78
e
2.54
0.100
F
0.50
1.78
0.020
0.070
G
Figure 14. W.A.R.P. 100 Pin CPGA100 Ceramic Package
18/19
W.A.R.P.1.1
Functionsin dedicatedmemories in orderto reduce
the computationaltime. Therefore a great amount
of W.A.R.P. processing is based on a look-up table
approach rather than on on-line calculation.
program memory. Thismicrocode, which drives the
on-line phase, is generated by the Compiler (see
W.A.R.P.-SDT User Manual) according to the
adoptedconfiguration.Thepossible configurations
are shown in table 1.
During the on-line phase (up to 40MHz working
frequency),W.A.R.P. processes the input data and
produces its outputsaccording to the configuration
loaded in the downloadingphase.
W.A.R.P. is conceived to work together with tradi-
tional microcontrollers which shall perform normal
control tasks while W.A.R.P. will be indipendently
responsible for all the fuzzy related computing.
W.A.R.P. is manufactured using the high perform-
ance,reliable HCMOS4T (O.7µm) SGS-THOMSON
Microelectronics process.
Those Membership Functions (MFs), each one
portrayed by a configurableresolution of 26 or 27
elements, are storedin four internal RAMs (1Kbyte
each). The consequent MFs, due to the different
modelling, are loaded in a single RAM by storing
for each MF its area and its barycentre. This is due
to the adoptionof the Center of Gravity defuzzifica-
tion method.
The downloading phase allows the setting of the
device, in terms of I/O number, universes of dis-
course andMF shapes. Duringthis phaseW.A.R.P.
prepares its internal memories for the on-line
elaboration phase and loads the microcode in its
Table 8. Ordering Information
Part Number
STFLWARP11/PG
STFLWARP11/PL
Maximum Frequency
40 MHz
Supply Voltage
5±5%
Temperature Range
0 °C to 70 °C
Package
CPGA100
PLCC84
40 MHz
5±5%
0 °C to 70 °C
Development Tools
Type
Device
FUZZYSTUDIO ADB
W.A.R.P.1.X
FUZZYSTUDIO SDT
W.A.R.P.1.X programmer
EPROM programmer
RS-232 communication handler
Internal Clock
Variables and Rules Editor
W.A.R.P. Compiler/Debugger
Exporter for ANSI C and MATLAB
STFLWARP11/PG
STFLWARP11/PL
STFLSTUDIO10/KIT
Order Code
Description
Supported Target
Functionalities
Rules Minimizer
System Requirement
STFLWARP11/PG
STFLWARP11/PL
STFLWARP20/PL
ANSI C
MS-DOS 3.1or higher
Windows 3.0 or later
486, PENTIUM compatible
8 MB RAM
Step-by-Step Simulation
Simulation from File
Local Tuning
WTA-FAMfor Building Rules
BACK-FAMfor Building MFs
STFLAFM10/SW
MATLAB
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices orsystems without express
written approval of SGS-THOMSON Microelectronics.
1996 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved
FUZZYSTUDI O is a trademark of SGS-THOMSON Microelectronics
MS-DOS , Microsoft and Microsoft Windows are registered trademarks of Microsoft Corporation.
MATLAB is a registered trademark of Mathworks Inc.
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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19/19
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