W24L257S70LE [ETC]
x8 SRAM ; X8 SRAM\n
| 型号： | W24L257S70LE |
| 厂家： | 
ETC |
| 描述： | x8 SRAM
|
| 文件： | 总11页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W24L257
´ 8 CMOS STATIC RAM
32K
GENERAL DESCRIPTION
The W24L257 is a normal-speed, very low-power CMOS static RAM organized as 32768 ´ 8 bits that
operates on a wide voltage range from 3V to 5.5V power supply. This device is manufactured using
Winbond's high performance CMOS technology.
FEATURES
· Low power consumption:
· Access time: 70 nS
· 3.3V/5V power supply
· Fully static operation
· All inputs and outputs directly TTL compatible
· Three-state outputs
· Battery back-up operation capability
· Data retention voltage: 2V (min.)
· Packaged in 330 mil SOP, and standard type
one STSOP (8 mm ´ 13.4 mm)
PIN CONFIGURATIONS
BLOCK DIAGRAM
CLK GEN.
PRECHARGE CKT.
A12
28
27
26
25
24
23
22
21
20
19
18
VDD
A14
A2
A14
1
R
O
W
2
#WE
A13
A8
A12
A7
A6
A5
A4
A3
A2
A1
A0
CORE CELL ARRAY
512 ROWS
A3
3
D
E
C
O
D
E
R
A4
32 X 8 COLUMNS
4
A5
A9
5
A6
A11
A7
6
A13
#OE
A10
7
I/O1
:
I/O8
I/O CKT.
DATA
CNTRL
8
COLUMN DECODER
9
CS
CLK
GEN.
I/O8
I/O7
I/O6
I/O5
I/O4
10
11
12
13
14
A0 A8
A1
A9
A10
A11
#WE
I/O1
I/O2
I/O3
#CS
#OE
17
16
15
V
SS
PIN DESCRIPTION
SYMBOL
DESCRIPTION
#OE
A11
A9
A8
A13
1
2
3
4
5
6
7
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
Address Inputs
A0 - A14
I/O1 - I/O8
#CS
#CS
I/O8
I/O7
I/O6
I/O5
I/O4
Data Inputs/Outputs
Chip Select Input
Write Enable Input
Output Enable Input
Power Supply
#W
VDD
A14
A12
8
9
V
SS
28-pin
TSOP
I/O3
I/O2
I/O1
A0
A1
#WE
A7
A6
A5
A4
A3
10
11
12
13
14
#OE
A2
VDD
VSS
Ground
NC
No Connection
Publication Release Date: October 3, 2001
Revision A5
- 1 -
W24L257
TRUTH TABLE
#CS
#OE
#WE
MODE
VDD CURRENT
I/O1-I/O8
H
X
X
Not Selected
High Z
ISB, ISB1
L
L
L
H
L
H
H
L
Output Disable
Read
High Z
IDD
IDD
IDD
Data Out
Data In
X
Write
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
3.3V
-0.5 to +4.6
5V
Supply Voltage to VSS Potential
Input/Output to VSS Potential
Allowable Power Dissipation
Storage Temperature
-0.5 to +7.0
V
V
-0.5 to VDD +0.5
1.0
W
°C
°C
-65 to +150
Operating Temperature
L/LL
LE
LI
0 to 70
-20 to 85
-40 to 85
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Operating Characteristics
(VDD = 5V ±10%; VDD = 3.3V ±5%; VSS = 0V; TA (°C) = 0 to 70 for L/LL, -20 to 85 for LE, -40 to 85 for LI)
PARAMETER
SYM. TEST CONDITIONS
3.3V
MAX.
+0.6
5V
MAX.
+0.8
UNIT
MIN.
MIN.
Input Low Voltage
VIL
VIH
ILI
-
-0.5
-0.5
V
V
Input High Voltage
-
+2.0 VDD +0.5 +2.2 VDD +0.5
Input Leakage Current
Output Leakage Current
VIN = VSS to VDD
-1
-1
+1
+1
-2
-2
+2
+2
mA
mA
ILO
VI/O = VSS to VDD,
#CS = VIH (Min.) or
#OE = VIH (Min.) or
#CS = VIL (Max.)
Output Low Voltage
Output High Voltage
VOL
IOL = +2.1 mA
-
2.2
-
0.4
-
-
2.4
-
0.4
-
V
V
VOH IOH = -1.0 mA
Operating Power Supply
Current
IDD
#CS = VIL (Max.)
and I/O = 0 mA,
Cycle = Min.
35
70
mA
Duty = 100%
- 2 -
W24L257
Operating Characteristics, continued
PARAMETER
SYM.
TEST CONDITIONS
3.3V
5V
UNIT
MIN. MAX. MIN. MAX.
#CS = VIH (min.) or
Cycle = min. Duty = 100%
mA
Standby Power Supply
Current
-
1
-
3
ISB
LL/LE/LI
L
ISB1 #CS ³ VDD -0.2V
-
-
15
30
-
-
15
30
mA
Note: Typical parameter is measured under ambient temperature TA = 25° C and VDD = 3.3V/5V
CAPACITANCE
(VDD = 5V ±10%; VDD = 3V ±5%, TA = 25° C, f = 1 MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYM.
CIN
CONDITIONS
VIN = 0V
MAX.
UNIT
6
8
pF
pF
CI/O
VOUT = 0V
Note: These parameters are sampled but not 100% tested.
AC Characteristics
AC Test Conditions
PARAMETER
Input Pulse Levels
CONDITIONS
0V to 3.0V
5 nS
Input Rise and Fall Times
Input and Output Timing Reference Level
Output Load
1.5V
See the drawing below
AC Test Loads and Waveform
1 TTL
1 TTL
OUTPUT
OUTPUT
100 pF
Including
Jig and
Scope
5 pF
Including
Jig and
Scope
(For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW
)
90%
10%
5 nS
3.0 V
90%
10%
0 V
5 nS
Publication Release Date: October 3, 2001
Revision A5
- 3 -
W24L257
AC Characteristics, continued
Read Cycle
(VDD = 5V ±10%; VDD = 3V ±5%; VSS = 0V; TA (°C) = 0 to 70 for L/LL, -20 to 85 for LE, -40 to 85 for LI)
PARAMETER
SYMBOL
3.3V/5V
UNIT
MIN.
MAX.
Read Cycle Time
TRC
70
-
-
nS
nS
nS
nS
nS
nS
nS
nS
nS
Address Access Time
TAA
70
70
35
-
Chip Select Access Time
TACS
TAOE
TCLZ*
TOLZ*
TCHZ*
TOHZ*
TOH
-
Output Enable to Output Valid
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
* These parameters are sampled but not 100% tested
-
10
5
-
-
30
30
-
-
10
Write Cycle
PARAMETER
SYMBOL
3.3V/5V
UNIT
MIN.
70
55
55
0
MAX.
Write Cycle Time
TWC
TCW
TAW
TAS
-
-
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
-
-
Write Pulse Width
TWP
TWR
TDW
TDH
40
0
-
Write Recovery Time
#CS, #WE
-
Data Valid to End of Write
Data Hold from End of Write
Write to Output in High Z
35
0
-
-
TWHZ*
TOHZ*
TOW
-
25
25
-
Output Disable to Output in High Z
Output Active from End of Write
-
5
* These parameters are sampled but not 100% tested
- 4 -
W24L257
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
T
RC
Address
TAA
T
OH
TOH
D
OUT
Read Cycle 2
(Chip Select Controlled)
#CS1
T
ACS
T
CHZ
T
CLZ
D
OUT
Read Cycle 3
(Output Enable Controlled)
RC
T
Address
#OE
T
AA
T
OH
TAOE
OLZ
T
#CS
T
OHZ
TACS
TCLZ
CHZ
T
D
OUT
Publication Release Date: October 3, 2001
Revision A5
- 5 -
W24L257
Timing Waveforms, continued
Write Cycle 1
T
WC
Address
#OE
T
WR
T
CW
#CS
T
AW
#WE
T
WP
T
AS
T
OHZ
(1, 4)
DOUT
DIN
T
T
DH
DW
Write Cycle 2
(#OE = VIL Fixed)
T
WC
Address
#CS
T
WR
T
CW
T
AW
#WE
T
T
OH
WP
T
AS
(2)
(3)
T
WHZ
T
OW
(1, 4)
D
OUT
DIN
T
DW
TDH
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. DOUT provides the read data for the next address.
4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
- 6 -
W24L257
DATA RETENTION CHARACTERISTICS
(TA (°C) = 0 to 70 for L/LL, -20 to 85 for LE, -40 to 85 for LI)
PARAMETER
VDD for Data Retention
Data Retention Current
SYM.
VDR
TEST CONDITIONS
#CS ³ VDD -0.2V
MIN. TYP. MAX. UNIT
2.0
-
-
-
-
-
V
IDDDR
LL/LE/LI
-
-
15
30
-
#CS ³ VDD -0.2V,
mA
mA
nS
VDD = 3V
L
Chip Deselect to Data
Retention Time
TCDR See data retention waveform
TR
0
Operation Recovery Time
TRC*
-
-
nS
* Read Cycle Time
DATA RETENTION WAVEFORM
V
DD
0.9VDD
0.9VDD
V
>
DR 2V
=
T
CDR
T
R
#CS
>
VDD
#CS
-0.2V
=
Publication Release Date: October 3, 2001
Revision A5
- 7 -
W24L257
ORDERING INFORMATION
PART NO.
ACCESS OPERATING
OPERATING
STANDBY
PACKAGE
TIME
(nS)
70
VOLTAGE
TEMPERATURE CURRENT MAX.
(V)
(mA)
(°C)
W24L257S70L
W24L257S70LL
W24L257S70LE
W24L257S70LI
W24L257Q70L
W24L257Q70LL
W24L257Q70LE
W24L257Q70LI
Notes:
3.3V/5V
3.3V/5V
3.3V/5V
3.3V/5V
3.3V/5V
3.3V/5V
3.3V/5V
3.3V/5V
0 to 70
0 to 70
30
15
15
15
30
15
15
15
330 mil SOP
330 mil SOP
330 mil SOP
330 mil SOP
Small TSOP
Small TSOP
Small TSOP
Small TSOP
70
70
-20 to 85
-40 to 85
0 to 70
70
70
70
0 to 70
70
-20 to 85
-40 to 85
70
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
- 8 -
W24L257
BONDING PAD DIAGRAM
PAD NO.
1
X
Y
6
4
3
5
2
1
30
29
27
WEB A13
28
26 25 24
A8
A11
A9
-232.25
-351.70
-471.15
-590.60
-710.05
-829.50
-992.79
-992.79
-857.86
-738.41
-594.84
-451.06
-310.67
-171.78
24.45
1445.22
1445.22
1445.22
1445.22
1445.22
1445.22
1362.24
-1306.11
-1452.79
-1452.79
-1414.13
-1414.13
-1414.13
-1405.28
-1405.28
-1414.13
-1414.13
-1414.13
-1414.13
-1414.13
-1452.79
-1312.15
1373.67
1445.22
1445.22
1445.22
1445.22
1445.22
1444.65
1444.65
A4 A5
A7 A12 A14 VDD VDD
A6
23
7
AC5394
2
A3
OEB
3
4
5
6
7
8
9
Y
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
X
151.80
298.07
443.28
588.20
732.84
871.11
992.75
992.75
810.09
690.64
571.19
451.74
332.29
120.25
-93.23
8
22
A10
A2
9
10
A0
11 12
I/O0 I/O1
15 16
SS
17
18 19 20
13 14
SS
21
V
I/O4
I/O3
I/O5 I/O6
I/O7
CSB
A1
I/O2
V
Note: For bare chip form (C.O.B.) applications, the substrate must be connected to VDD or left floating in the PCB layout.
Publication Release Date: October 3, 2001
- 9 -
Revision A5
W24L257
PACKAGE DIMENSIONS
28-pin SOP
Dimension in Inches
Dimension in mm
Symbol
A
Min. Nom. Max. Min. Nom. Max.
2.85
0.112
0.004
0.093 0.098 0.103
0.10
2.36
0.36
0.20
28
15
1
A
2.49
0.41
0.25
18.11
8.41
1.27
2.62
0.51
0.36
18.62
8.53
1.42
2
A
e
1
0.014 0.016
0.008 0.010
0.020
0.014
b
c
D
E
e
0.713 0.733
E
H E
8.28
1.12
0.326 0.331 0.336
0.044 0.050 0.056
0.453 0.465 0.477 11.51 11.81 12.12
E
H
0.028 0.036 0.044
0.91
1.70
1.12
0.71
1.50
L
L
Detail F
0.059 0.067 0.075
0.047
1.91
1.19
14
E
1
L
b
S
y
q
0.10
10
0.004
10
0
0
Notes:
1. Dimension D Max. & S include mold flash
or tie bar burrs.
2. Dimension b does not include dambar
protrusion/intrusion.
e
1
D
c
A
A2
A1
3. Dimension D & E include mold mismatch
.
and determined at the mold parting line.
4. Controlling dimension: Inches.
S
e
L E
y
5. General appearance spec should be based
on final visual inspection spec.
See Detail F
Seating Plane
28-pin Standard Type One TSOP
H
D
D
Dimension In Inches
Dimension In mm
Symbol
Max.
1.20
Min. Nom. Max. Min. Nom.
0.047
c
A
A 1
0.05
0.006
0.041
0.15
0.002
0.035
1
0.95
0.17
0.10
1.00
0.20
0.040
1.05
0.27
2
A
e
0.007 0.008 0.011
0.004 0.008
b
c
D
0.15
0.21
0.006
E
11.90
11.70
7.90
11.80
8.00
0.461 0.465 0.469
0.311 0.315 0.319
8.10
E
b
0.520 0.528 0.536
0.022
13.60
13.20
13.40
0.55
0.60
0.25
D
H
e
L
L1
Y
q
0.020
0.50
0.70
0.024 0.028
0.010
0.000
0
0.10
5
0.004
0.00
0
A
A
2
3
5
3
q
Controlling dimension: Millimeters
A
1
L
Y
L
1
- 10 -
W24L257
VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A1
A2
May 2000
Nov. 2000
-
Initial Issued
Add in 5V specification
1, 2, 3, 4, 7
1, 9
Modify package as 330 mil SOP and standard type
one TSOP (8 mm ´ 13.4 mm)
2, 3, 7, 8
Add in LE, LI specification
A3
A4
Dec. 2000
Jun. 2001
2, 4, 5
Modify the 3.3V ±10%, to 3.3V ±5%
Correct Ordering Information SOP description
Correct Standby Current
8
8
4
A5
Oct. 3, 2001
Correct Write Recover Time (TWR) parameter
Winbond Electronics (H.K.) Ltd. Winbond Electronics North America Corp
Headquarters
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd;
Kowloon, Hong Kong
TEL: 852-27513100
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
FAX: 852-27552064
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
TEL: 408-9436666
FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
Publication Release Date: October 3, 2001
Revision A5
- 11 -
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