W72M64V-XBX [ETC]
Flash MCP ; 闪存MCP
| 型号： | W72M64V-XBX |
| 厂家： | 
ETC |
| 描述： | Flash MCP
|
| 文件： | 总15页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W72M64V-XBX
2Mx64 3.3V Simultaneous Operation Flash Multi-Chip Package
*Preliminary
FEATURES
!
Access Times of 100, 120, 150ns
!
!
!
!
Unlock Bypass Program command
!
Packaging
•
Reduces overall programming time when
issuing multiple program command sequences
•
159 PBGA, 13x22mm - 1.27mm pitch
Ready/Busy output (RY/BY)
!
!
1,000,000 Erase/Program Cycles
Sector Architecture
•
Hardware method for detecting program or erase
cycle completion
•
•
Bank 1 (8Mb): eight 4K word, fifteen 32K word
Bank 2 (24Mb): forty-eight 32K word
Hardware reset pin (RESET)
•
Hardware method of resetting the internal state
machine to the read mode
!
!
!
!
Bottom boot block
Zero Power Operation
Organized as 2Mx64 or 2x2Mx32
WP/ACC input pin
•
Write protect (WP) function allows protection of
two outermost boot sectors, regardless of
sector protect status
Commercial, Industrial and Military Temperature
Ranges
!
!
3.3 Volt for Read and Write Operations
Simultaneous Read/Write Operation:
•
Acceleration (ACC) function accelerates
program timing
!
Sector Protection
•
Data can be continuously read from one bank
while executing erase/program functions in
another bank
•
Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within
that sector
•
Zero latency between read and write operations
!
!
Erase Suspend/Resume
•
Temporary Sector Unprotect allows changing
data in protected sectors in-system
•
Suspends erase operations to allow
programming in same bank
Data Polling and Toggle Bits
Note: For programming information refer to Flash Programming
W72M64V-XBX Application Note.
•
Provides a software method of detecting the
status of program or erase cycles
* Preliminary datasheet. This datasheet describes a product that is not characterized or qualified and is subject to
change without notice.
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
November2003 Rev. 1
W72M64V-XBX
FIG 1: PIN CONFIGURATION FOR W72M64V-XBX
TOP VIEW
PIN DESCRIPTION
1
2
3
4
5
6
7
8
9 10
DQ0-63
A0-20
Data Inputs/Outputs
Address Inputs
GND GND GND
V
CC
V
CC
GND GND GND
V
CC
A
B
C
D
E
F
WE1-4
CS1-4
OE
Write Enables
Chip Selects
V
CC
CC
GND DQ41 WE
3
V
CC
DQ57 DNU WE
4
V
CC
V
CC
Output Enable
Hardware Reset
V
DQ33 DQ43 DQ45 DQ47 DQ49 DQ59 DQ61 DQ63
V
CC
RESET
Hardware Write
Protect/Acceleration
V
CC
CC
DQ40 DQ35 DQ37 DQ39 DQ56 DQ51 DQ53 DQ55
DQ32 DQ42 DQ44 DQ46 DQ48 DQ58 DQ60 DQ62
V
CC
CC
WP/ACC
V
V
RY/BY Ready/Busy Output
VCC
GND
DNU
Power Supply
Ground
GND
GND
GND
CS
3
DQ34 DQ36 DQ38 CS
4
DQ50 DQ52 DQ54 GND
Do Not Use
OE
A
0
DNU
V
CC
A12
A
16
DNU*
A
20
GND
GND
G
H
J
A
2
WP/ACC
A
11
GND
V
CC
A
7
A
10
A15
GND
GND
A
3
4
A
6
A
9
V
CC
GND
A
1
RESET
A
13
GND
GND
GND
A
A
17
RY/BY GND
A
14
A
5
A
18
A
8
K
L
GND DQ17 WE
2
DQ29 DNU DQ
9
DQ
4
WE1
A
19
V
CC
DQ24 DQ19 DQ21 DQ31 DQ
1
DQ11 DQ
6
DQ15
V
CC
CC
M
N
P
R
T
V
CC DQ16 DQ26 DQ28 DQ23 DQ
8
DQ
3
DQ13 DQ
7
V
V
CC
CC
CS
2
DQ18 DQ20 DQ30 DQ
0
DQ10 DQ
5
DQ14
V
CC
CC
V
VCC
DQ25 DQ27 DQ22 CS
1
DQ
2
DQ12 GND
V
V
CC
GND GND GND
VCC
V
CC
GND GND GND
VCC
BLOCK DIAGRAM
WE
1
WE
2
WE
3
WE
4
* Ball G8 is DNU on this device and will become A21
on the W74M64V-XBX
CS
4
CS
3
CS
1
CS
2
RY/BY
RESET
OE
A0-20
BYTE
BYTE
BYTE
2M x 16
2M x 16
2M x 16
2M x 16 BYTE
VCC
WP/ACC
DQ32-47
DQ48-63
DQ0-15
DQ16-31
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
2
W72M64V-XBX
ABSOLUTEMAXIMUMRATINGS
CAPACITANCE
(TA = +25°C)
Parameter
Unit
°C
Parameter
Symbol
Conditions
Max Unit
Operating Temperature
Supply Voltage Range (VCC)
Signal Voltage Range
Storage Temperature Range
Endurance (write/erase cycles)
NOTES:
-55 to +125
-0.5 to +4.0
WE1-4 capacitance
CWE
CCS
CI/O
V
V
IN = 0 V, f = 1.0 MHz 25
pF
pF
pF
pF
pF
pF
pF
V
-0.5 to Vcc +0.5
-55 to +150
V
CS1-4 capacitance
IN = 0 V, f = 1.0 MHz 25
°C
Data I/O capacitance
V
V
V
V
V
I/O = 0 V, f = 1.0 MHz 12
IN = 0 V, f = 1.0 MHz 25
IN = 0 V, f = 1.0 MHz 20
IN = 0 V, f = 1.0 MHz 20
IN = 0 V, f = 1.0 MHz 30
1,000,000 min.
cycles
Address input capacitance CAD
1. Stresses above the absolute maximum rating may cause
permanent damage to the device. Extended operation at the maximum
levels may degrade performance and affect reliability.
RESET capacitance
RY/BY capacitance
WP/ACC capacitance
CRS
CRB
CWA
RECOMMENDEDOPERATINGCONDITIONS
This parameter is guaranteed by design but not tested.
Parameter
Symbol
VCC
TA
Min
3.0
-55
-40
Max
3.6
Unit
V
Supply Voltage
DATA RETENTION
Operating Temp. (Mil.)
Operating Temp. (Ind.)
+125
+85
°C
°C
Parameter
Test Conditions
150°C
Min
10
Unit
TA
Pattern Data
Retention Time
Years
Years
125°C
20
DCCHARACTERISTICS-CMOSCOMPATIBLE
(VCC = 3.3V ± 0.3V, TA = -55°C to +125°C)
Parameter
Symbol
ILI
Conditions
Min
Max
10
Unit
µA
Input Leakage Current
Output Leakage Current
VCC = 3.6V, VIN = GND to VCC
VCC = 3.6V, VOUT = GND to VCC
CS = VIL, OE = VIH, f = 5MHz
CS = VIL, OE = VIH, WE = VIL
-10
-10
ILO
10
µA
VCC Active Current for Read (1)
ICC1
ICC2
65
mA
mA
VCC Active Current for Program or Erase (2,3)
120
VCC Standby Current (2)
VCC Reset Current (2)
ICC3
ICC4
ICC5
CS = RESET = VCC ± 0.3V
RESET = VSS ± 0.3V
20
20
µA
µA
Automatic Sleep Mode (2,4)
VIH = VCC ± 0.3V;
VIL = VSS ± 0.3V
20
µA
mA
mA
VCC Active Read-While-Program Current (1,2)
VCC Active Program-While-Erase Current (1,2)
ICC6
ICC7
ICC8
CS = VIL, OE = VIH
CS = VIL, OE = VIH
180
180
VCC Active Program-While-Erase-Suspended
Current (2,5)
CS = VIL, OE = VIH
140
mA
ACC Accelerated Program Current
IACC
ACC Pin
40
CS = VIL, OE = VIH VCC Pin
120
mA
V
Input Low Voltage
Input High Voltage
VIL
VIH
-0.5
0.8
0.7 x Vcc
Vcc + 0.3
V
Voltage for WP/ACC Sector
Protect/Unprotect and Program Acceleration
VHH
Vcc = 3.0V + 0.3V
8.5
8.5
9.5
V
Voltage for Autoselect and Temporary
Sector Unprotect
VID
Vcc = 3.0V + 0.3V
12.5
0.45
V
V
Output Low Voltage
VOL
IOL = 4.0 mA, VCC = 3.0V
Output High Voltage
VOH1
VLKO
IOH = -2.0 mA, VCC = 3.0V
0.85 X VCC
2.3
V
V
Low VCC Lock-Out Voltage (5)
2.5
NOTES:
1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz). The frequency
component typically is less than 8 mA/MHz, with OE at VIH.
2. Maximum ICC specifications are tested with VCC = VCC MAX
3. ICC active while Embedded Algorithm (program or erase) is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30ns.
5. Not 100% tested.
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W72M64V-XBX
ACCHARACTERISTICS–WRITE/ERASE/PROGRAMOPERATIONS-CSCONTROLLED
(VCC = 3.3V ± 0.3V, TA = -55°C to +125°C)
Parameter
Symbol
-100
-120
-150
Unit
Min Max
Min Max Min Max
Write Cycle Time
tAVAV
tWLEL
tELEH
tAVWL
tDVEH
tEHDX
tELAX
tEHEL
tW C
tW S
tCP
100
0
120
0
150
0
ns
ns
Write Enable Setup Time
Chip Select Pulse Width
Address Setup Time
45
0
50
0
50
0
ns
tAS
ns
Data Setup Time
tDS
45
0
50
0
50
0
ns
Data Hold Time
tDH
ns
Address Hold Time
tAH
45
30
300
15
0
50
30
50
30
ns
Chip Select Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase Time (2)
tCPH
ns
t WHWH1
tWHWH2
tGHEL
300
15
300
15
µs
sec
ns
Read Recovery Time Before Write (3)
Chip Programming Time (4)
0
0
108
108
108
sec
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH2 is 0.7 sec.
3. Guaranteed by design, but not tested.
4. Typical value is 36 sec. The typical chip programming time is considerably less than the maximum chip programming time
listed, since most bytes program faster than the maximum program times listed.
ACTESTCONDITIONS
FIG 2: AC TEST CIRCUIT
Parameter
Typ
Unit
V
I
OL
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
NOTES:
VIL = 0, VIH = 2.5
5
ns
V
Current Source
1.5
1.5
V
V
Z
≈ 1.5V
D.U.T.
EFF = 50 pf
(Bipolar Supply
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75Ω.
C
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive
load circuit.
IOH
Current Source
ATE tester includes jig capacitance.
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
4
W72M64V-XBX
ACCHARACTERISTICS–WRITE/ERASE/PROGRAMOPERATIONS-WECONTROLLED
(VCC = 3.3V ± 0.3V, TA = -55°C to +125°C)
Parameter
Symbol
-100
-120
Min
-150
Min
Unit
Min
Max
Max
Max
Write Cycle Time
tAVAV
tELWL
tWC
100
0
120
0
150
0
ns
ns
ns
Chip Select Setup Time
tCS
tWP
tAS
Write Enable Pulse Width
Address Setup Time
tWLWH
tAVWL
tDVWH
tWHDX
tWLAX
tWHWL
tWHWH1
tWHWH2
tGHWL
tVCS
50
0
50
0
65
0
ns
ns
Data Setup Time
tDS
50
0
50
0
65
0
Data Hold Time
tDH
ns
ns
Address Hold Time
tAH
50
30
300
15
0
50
30
300
15
0
65
35
Write Enable Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase (2)
tWPH
ns
300
15
µs
sec
ns
µs
sec
ns
Read Recovery Time before Write (3)
VCC Setup Time
0
50
50
50
Chip Programming Time (4)
Address Setup Time to OE low during toggle bit polling
108
108
108
tA S O
15
15
15
Address Hold Time From CS or OE high
during toggle
tA H T
tO E P H
tSR /W
t R B
0
20
0
0
20
0
0
20
0
ns
ns
ns
ns
ns
Output Enable High during toggle bit polling
Latency Between Read and Write Operations
Write Recovery Time from RY/BY
0
0
0
Program/Erase Valid to RY/BY
tB U S Y
90
90
90
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH2 is 0.7 sec.
3. Guaranteed by design, but not tested.
4. Typical value is 36 sec. The typical chip programming time is considerably less than the maximum chip programming time listed, since most
bytes program faster than the maximum program times listed.
ACCHARACTERISTICS–READ-ONLYOPERATIONS
(VCC = 3.3V ± 0.3V, TA = -55°C to +125°C)
Parameter
Symbol
-100
Min Max Min Max Min Max
100 120 150
-120
-150
Unit
Read Cycle Time
tAVAV
tRC
tACC
tCE
tOE
tDF
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
100
100
40
120
120
50
150
150
55
Chip Select Access Time
Output Enable to Output Valid
Chip Select High to Output High Z (1)
Output Enable High to Output High Z (1)
20
20
20
tDF
20
20
20
Output Hold from Addresses, CS or OE Change,
Whichever occurs first
tOH
0
0
0
Read
tOEH
0
0
0
Output Enable Hold Time (1)
Toggleand
Data Polling
10
10
10
1. Guaranteed by design, not tested.
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W72M64V-XBX
FIG 3: AC WAVEFORMS FOR READ OPERATIONS
tRC
Addresses
CS
Addresses Stable
tACC
tDF
tOE
OE
tOEH
WE
tCE
tOH
High Z
High Z
Outputs
Output Valid
RESET
RY/BY
OV
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
6
W72M64V-XBX
ACCHARACTERISTICS–HARDWARERESET(RESET)
Parameter
Symbol
-100
-120
-150
Unit
Min
Max
Min
Max
Min
Max
RESET Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
tready
20
20
20
µs
RESET Pin Low (NOT During Embedded Algorithms)
to Read Mode (See Note)
tready
tRP
500
500
500
ns
ns
ns
µs
ns
RESET Pulse Width
500
50
20
0
500
50
20
0
500
50
20
0
RESET High Time Before Read (See Note)
RESET Low to Standby Mode
RY/BY Recovery Time
tRH
tRPD
tRB
Note: Not tested.
FIG 4: RESET TIMINGS NOT DURING EMBEDDEDALGORITHMS
RY/BY
CS, OE
t
RH
RESET
t
RP
t
Ready
FIG 5: RESET TIMINGS DURING EMBEDDEDALGORITHMS
t
Ready
RY/BY
t
RB
CS, OE
RESET
t
RP
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W72M64V-XBX
FIG 6: PROGRAM OPERATION
tWC
tAS
Addresses
CS
555h
PA
PA
PA
tAS
tCH
OE
tWHWH1
tWP
WE
tCS
tWPH
tDS
tDH
A0h
Status
DOUT
PD
Data
tRB
tBUSY
RY/BY
V
CC
tVCS
NOTES:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. DOUT is the output of the data written to the device.
4. Figure indicates last two bus cycles of four bus cycle sequence.
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
8
W72M64V-XBX
FIG 7: ACCELERATED PROGRAM TIMING DIAGRAM
VHH
VIL or VIH
WP/ACC
VIL or VIH
tVHH
tVHH
FIG 8: CHIP/SECTOR ERASE OPERATION TIMINGS
tWC
tAS
Addresses
CS
2AAh
SA
VA
VA
555h for
chip erase
tAH
tCH
OE
tWP
WE
tCS
tWHWH2
tWPH
tDS
tDH
In
Progress
55h
Complete
tRB
30h
Data
RY/BY
VCC
10 for Chip Erase
tBUSY
tVCS
Notes:
1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W72M64V-XBX
FIG 9: BACK TO BACK READ/WRITE CYCLE TIMINGS
tWC
tWC
tRC
tWC
Valid PA
Valid PA
Valid PA
Valid RA
Addresses
CS
tAH
tCPH
tACC
tCE
tCP
tOE
OE
tOEH
tWP
tGHWL
WE
tDF
tWPH
tDS
tOH
tDH
Valid In
Data
Valid In
Valid In
Valid Out
tSR/W
WE Controlled Write Cycle
Read Cycle
CS Controlled Write Cycle
FIG. 10: DATAPOLLING TIMINGS (DURING EMBEDDEDALGORITHMS)
tRC
Addresses
CS
VA
VA
VA
t
ACC
tCE
tCH
tOE
OE
tOEH
tDF
WE
tOH
High Z
High Z
DQ
7
Complement
True
True
Valid Data
Complement
Status Data
Valid Data
Status Data
DQ0-DQ6
tBUSY
RY/BY
NOTE: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
10
W72M64V-XBX
FIG 11: TOGGLE BIT TIMINGS (DURING EMBEDDEDALGORITHMS)
tAHT
tAS
Addresses
tAHT
tASO
CS
tCEPH
tOEH
WE
tOEPH
OE
tDH
tOE
Valid
Data
Valid
Status
Valid
Status
Valid
Status
Valid Data
DQ6/DQ2
(Stops Toggling)
(First Read)
(Second Read)
RY/BY
NOTE: VA = Valid address, not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
FIG 12: DQ2 VS. DQ6
Enter
Embedded
Erasing
Erase
Resume
Enter Erase
Suspend Program
Erase
Suspend
Erase
Complete
Erase
Suspend
Program
Erase Suspend
Read
Erase
Erase Suspend
Read
Erase
WE
DQ6
DQ2
NOTE: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE or CS to toggle DQ2 and DQ6.
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W72M64V-XBX
FIG 13: SECTOR/SECTOR BLOCK PROTECTAND UNPROTECTTIMING DIAGRAM
V
ID
IH
V
RESET
SA, A
6,
Valid*
Verify
40h
Valid*
Status
Valid*
A1
, A0
Sector/Sector Block Protect or Unprotect
60h
60h
Data
Sector/Sector Block Protect: 150 µs
Sector/Sector Block Unprotect: 15 ms
1 µs
CS
WE
OE
NOTES:
For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
ACCHARACTERISTICS–ALTERNATECSCONTROLLEDERASEANDPROGRAMOPERATIONS
Parameter
Speed Options
JEDEC
Std
tWC
Description
100
90
0
120
120
0
150
150
0
Unit
ns
tAVAV
tAVWL
tELAX
Write Cycle Time (1)
Address Setup Time
Address Hold Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Typ
tAS
ns
tAH
45
45
0
50
50
0
50
50
0
ns
tDVEH
tEHDX
tGHEL
tDS
Data Setup Time
ns
tDH
Data Hold Time
ns
tGHEL
tWS
Read Recovery Time Before Write (OE High to WE Low)
WE Setup Time
0
0
0
ns
tWLEL
tEHWH
tELEH
0
0
0
ns
tWH
WE Hold Time
0
0
0
ns
tCP
CS Pulse Width
45
30
9
50
30
9
50
30
9
ns
tEHEL
tCPH
tWHWH1
tWHWH1
tWHWH2
CS Pulse Width High
ns
tWHWH1
tWHWH1
tWHWH2
Programming Operation
Byte
µs
Accelerated Programming Operation, Word or Byte
Sector Erase Operation
7
7
7
µs
0.7
0.7
0.7
sec
NOTE:
1. Not tested.
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
12
W72M64V-XBX
FIG 14: ALTERNATE CS CONTROLLED WRITE (ERASE/PROGRAM)
OPERATION TIMINGS
555 for Program
2AA for Erase
PA for Program
SA for Sector Erase
555 for Chip Erase
Data Polling
PA
Addresses
WE
tAS
t
WC
WH
tAH
t
tGHEL
OE
CS
t
CP
t
WHWH1 OR 2
t
WS
tCPH
t
BUSY
t
DS
tDH
Data
DQ7
DOUT
tHR
A0 for Program
55 for Erase
PD for Program
30 for Sector Erase
10 for Chip Erase
RESET
RY/BY
NOTES:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7 is the complement of the data written to the device. DOUT is the data written to the device.
13
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W72M64V-XBX
PACKAGE:159PBGA
BOTTOM VIEW
159 Y Ø 0.762 (0.030) NOM
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
0.61 (0.024)
NOM
1.27 (0.050) NOM
11.43 (0.450) NOM
13.1 (0.516) MAX
2.03 (0.080) MAX
ALL LINEAR DIMENSIONSARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES.
ORDERING INFORMATION
W 7 2M64 V XXX B X
WHITE ELECTRONIC DESIGNS CORP.
Flash
ORGANIZATION, 2M x 64
User configurable as 2 x 2M x 32
3.3V Power supply
ACCESS TIME (ns)
100 = 100ns
120 = 120ns
150 = 150ns
PACKAGETYPE:
B = 159 Plastic BGA, 13mm x 22mm
DEVICE GRADE:
M
I
C
=
=
=
Military Screened
Industrial
Commercial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
14
W72M64V-XBX
Document Title
2M x 64 Simultaneous Operation Flash Multi-Chip Package
Revision History
Rev #
Rev 0
Rev 1
History
Release Date
Status
Initial Release
November 2002
November 2003
Advanced
Preliminary
Update (pg 1, 14, 15)
1.1 Change status to preliminary
1.2 Change mechanical drawing to new style
15
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
相关型号：
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