WED3DG648V-D2 [ETC]
SDRAM Modules - 168 Pin DIMM. Unbuffered ; SDRAM模块 - 168针DIMM 。无缓冲\n
| 型号： | WED3DG648V-D2 |
| 厂家： | 
ETC |
| 描述： | SDRAM Modules - 168 Pin DIMM. Unbuffered
|
| 文件： | 总5页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WED3DG648V-D2
64MB- 8Mx64 SDRAM UNBUFFERED
FEATURES
DESCRIPTION
PC100 and PC133 compatible
Burst Mode Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
The WED3DG648V is a 8Mx64 synchronous DRAM module
which consists of eight 4Mx16 SDRAM components in TSOP- 11
package and one 2K EEPROM in an 8- pin TSSOP package for
Serial Presence Detect which are mounted on a 168 Pin DIMM
multilayer FR4 Substrate.
Fully synchronous: All signals are registered on the positive
edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full Page
3.3 volt + 0.3v Power Supply
*
This product is subject to change without notice.
168- Pin DIMM JEDEC
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PIN NAMES
Pin
1
Front
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
NC
Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Front
DQM1
CS0
DNU
VSS
A0
Pin
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Front
DQ18
DQ19
VDD
DQ20
NC
NC
CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
Pin
85
Back
VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
DQM5
CS1
RAS
VSS
A1
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
DQ50
DQ51
VDD
DQ52
NC
A0 – A11
BA0-1
DQ0-63
CLK0,CLK2
CKE0,CKE1
CS0-CS3
RAS
Address input (Multiplexed)
Select Bank
2
86
Data Input/Output
Clock input
3
87
4
88
Clock Enable input
Chip select Input
Row Address Strobe
Column Address Strobe
Write Enable
DQM
Power Supply (3.3V)
Ground
5
89
6
A2
90
A3
NC
7
A4
91
A5
DNU
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
8
A6
92
A7
CAS
9
A8
93
A9
WE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A10/AP
BA1
VDD
VDD
CLK0
VSS
DNU
CS2
DQM2
DQM3
DNU
VDD
NC
94
BA0
A11
DQM0-7
VDD
95
96
VDD
NC
NC
VSS
CKE0
CS3
DQM6
DQM7
NC
VSS
97
SDA
Serial data I/O
Serial clock
Do not use
No Connect
98
SCL
99
DNU
100
101
102
103
104
105
106
107
108
109
110
111
112
NC
DQ46
DQ47
NC
VDD
NC
NC
NC
*
WP (write protect) option is available on
Pin 81, see ordering information on page 5.
VSS
NC
NC
VDD
WE
DQM0
NC
CLK2
NC
*WP
**SDA
**SCL
VDD
VSS
NC
NC
NC
**SA0
**SA1
**SA2
VDD
NC
NC
NC
NC
NC
NC
** These pins should be NC in the system which
does not support SPD.
VSS
DQ16
DQ17
VDD
VSS
DQ48
DQ49
CAS
DQM4
White Electronic Designs Corp reserves the right to change products or specifications without notice.
White Electronic Designs Corporation • (508) 485-4000 • www.whiteedc.com
June 2003 Rev. 1
ECO #16361
1
WED3DG648V-D2
FUNCTIONAL BLOCK DIAGRAM
2
U
U
U
U
2
3
U
U
U
U
White Electronic Designs Corp reserves the right to change products or specifications without notice.
White Electronic Designs Corporation • (508) 485-4000 • www.whiteedc.com
2
June 2003 Rev. 1
ECO #16361
WED3DG648V-D2
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VIN, Vout
VDD, VDDQ
TSTG
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
8
Units
V
Voltage on any pin relative to VSS
Voltage on VDD supply relative to VSS
Storage Temperature
V
°C
W
Power Dissipation
PD
Short Circuit Current
IOS
50
mA
Note:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device relIability.
RECOMMENDED DC OPERATING CONDITIONS
(Voltage Referenced to: VSS = 0V, TA = 0°C to +70°C)
Parameter
Symbol
VDD
VIH
Min
3.0
2.0
-0.3
2.4
—
Typ
3.3
Max
3.6
Unit
V
Note
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
3.0 VDDQ+0.3
V
1
VIL
—
—
—
—
0.8
—
V
2
VOH
VOL
ILI
V
IOH= -2mA
IOL= -2mA
3
0.4
10
V
-10
µA
Note:
1. VIH (max)= 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min)= -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(TA = 23°C, f = 1MHz, VDD = 3.3V, VREF=1.4V 6200mV)
Parameter
Symbol
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
-
Min
Max
45
45
25
13
15
10
45
pF
Unit
pF
pF
pF
pF
pF
pF
pF
Input Capacitance (A0-A12)
Input Capacitance (RAS,CAS,WE)
Input Capacitance (CKE0)
-
-
-
Input Capacitance (CLK0,CLK2)
Input Capacitance (CS0,CS2)
Input Capacitance (DQM0-DQM7)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)Cout
-
-
-
-
12
White Electronic Designs Corp reserves the right to change products or specifications without notice.
White Electronic Designs Corporation • (508) 485-4000 • www.whiteedc.com
June 2003 Rev. 1
ECO #16361
3
WED3DG648V-D2
OPERATING CURRENT CHARACTERISTICS
(VCC = 3.3V, TA = 0°C to +70°C)
Version
Parameter
Symbol
Conditions
Burst Length = 1
133
620
100
500
Units Note
Operating Current
(One bank active)
ICC1
mA
1
tRC ≥ tRC(min)
IOL = 0mA
Precharge Standby Current
in Power Down Mode
ICC2P
ICC2PS
Icc2N
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tcc = 10ns
Input signals are charged one time during 20
20
20
mA
Precharge Standby Current
in Non-Power Down Mode
120
Icc2NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞
Input signals are stable
mA
mA
50
25
25
Active standby current in
power-down mode
ICC3P
ICC3PS
ICC3N
CKE ≥ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tcc = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tcc = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞
input signals are stable
Active standby current in
non power-down mode
200
120
mA
mA
mA
ICC3NS
Io = mA
Operating current (Burst mode)
ICC4
Page burst
650
660
540
600
1
2
4 Banks activated
tCCD = 2CLK
Refresh current
ICC5
ICC6
tRC ≥ tRC(min)
mA
mA
Self refresh current
CKE ≤ 0.2V
10
Notes:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS (VIH/VIL = VDDQ/VssQ)
White Electronic Designs Corp reserves the right to change products or specifications without notice.
White Electronic Designs Corporation • (508) 485-4000 • www.whiteedc.com
4
June 2003 Rev. 1
ECO #16361
WED3DG648V-D2
ORDERING INFORMATION
Part Number
Speed
CAS Latency
CL=2
Part Number
Speed
100MHz
133MHz
133MHz
CAS Latency
CL=2
WED3DG648V10D2
WED3DG648V7D2
WED3DG648V75D2
100MHz
133MHz
133MHz
WED3DG638V10D2
WED3DG638V7D2
WED3DG638V75D2
CL=2
CL=2
CL=3
CL=3
Note: Available with WP (write protect) on pin 81.
Note: Modules are available in industrial temperature - 40°C to 85°C. Add an "I"
to the end of the part number.
PACKAGE DIMENSIONS
ALL DIMENSIONS ARE IN INCHES
White Electronic Designs Corp reserves the right to change products or specifications without notice.
White Electronic Designs Corporation • (508) 485-4000 • www.whiteedc.com
June 2003 Rev. 1
ECO #16361
5
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