WF128K32-120G1UM5A [ETC]
EEPROM ; EEPROM\n
| 型号： | WF128K32-120G1UM5A |
| 厂家： | 
ETC |
| 描述： | EEPROM
|
| 文件： | 总16页 (文件大小：427K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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5 Volt Programming. 5V 10ꢀ Supply
Low Power CMOS, 1mA Standby Typical
Embedded Erase and Program Algorithms
TTL Compatible Inputs and CMOS Outputs
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Access Times of 50*, 60, 70, 90, 120, 150ns
Packaging:
•66 pin, PGA Type, 1.075 inch square, Hermetic
Ceramic HIP (Package 400)
•68 lead, Hermetic CQFP (G2U)1, 22.4mm (0.880 inch)
square, 3.56mm (0.140 inch) high (Package 510)
Built-in Decoupling Caps and Multiple Ground Pins for
Low Noise Operation
•68 lead, Hermetic CQFP (G1U), 23.9mm (0.940 inch)
square, 3.56mm (0.140 inch) high (Package 519)
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Page Program Operation and Internal Program Control
Time
•68 lead, Hermetic CQFP (G1T), 23.9mm (0.940 inch)
square, 4.06mm (0.160 inch) high (Package 524)
Weight
WF128K32-XG1UX5 - 5 grams typical
WF128K32-XG1TX5 - 5 grams typical
WF128K32-XG2UX51 - 8 grams typical
WF128K32-XH1X5 - 13 grams typical
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Sector Architecture
•8 equal size sectors of 16KBytes each
•Any combination of sectors can be concurrently
erased.
Also supports full chip erase
Note 1: Package Not Recommended For New Design
Note: For programming information refer to Flash Programming 1M5
Application Note.
* The access time of 50ns is available in Industrial and Commercial temperature
ranges only.
n 100,000 Erase/Program Cycles Typical, 0°C to +70°C
Organized as 128Kx32
n Commercial, Industrial and Military Temperature Ranges
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PIN CONFIGURATION FOR WF128K32N-XH1X5
I/O0-31
A0-16
WE1-4
CS1-4
OE
DataInputs/Outputs
AddressInputs
WriteEnables
ChipSelects
I/O24
I/O25
I/O26
A7
VCC
CS4
WE4
I/O27
A4
I/O31
I/O30
I/O29
I/O28
A1
I/O8
I/O9
I/O10
A14
WE2
CS2
GND
I/O11
A10
I/O15
I/O14
I/O13
I/O12
OE
OutputEnable
PowerSupply
Ground
VCC
A12
A16
GND
NC
NC
A5
A2
A11
A9
NC
NotConnected
A13
A6
A3
A0
A15
WE1
I/O7
I/O6
I/O5
I/O4
A8
WE3
CS3
GND
I/O19
I/O23
I/O22
I/O21
I/O20
NC
I/O0
I/O1
I/O2
VCC
CS1
NC
I/O16
I/O17
I/O18
I/O3
June 2002 Rev. 5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
PIN CONFIGURATION FOR WF128K32-XG1UX5, WF128K32-XG1TX5 AND
WF128K32-XG2UX51
I/O0-31
DataInputs/Outputs
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
A0-16
WE1-4
CS1-4
OE
AddressInputs
WriteEnables
ChipSelects
OutputEnable
PowerSupply
Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VCC
GND
NC
GND
I/O
I/O
8
9
NotConnected
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Note1:PackageNotRecommendedForNewDesign
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
SupplyVoltage
VCC
VIH
VIL
4.5
2.0
5.5
VCC + 0.3
+0.8
V
V
OperatingTemperature
-55 to +125
-2.0to+7.0
-2.0to+7.0
-65 to +150
+300
°C
V
InputHighVoltage
SupplyVoltageRange(VCC)
InputLowVoltage
-0.5
-55
V
Signalvoltagerange(anypinexceptA9)(2)
StorageTemperatureRange
V
OperatingTemp.(Mil.)
A9 VoltageforSectorProtect
TA
+125
12.5
°C
V
°C
°C
VID
11.5
LeadTemperature(soldering,10seconds)
DataRetentionMilTemp
10years
Endurance(write/erasecycles)MilTemp
A9 Voltageforsectorprotect(VID)(3)
10,000 cycles min.
-2.0to+14.0
V
(TA = +25ºC)
1. Stresses above the absolute maximum rating may cause permanent damage to
the device. Extended operation at the maximum levels may degrade
performance and affect reliability.
2. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions,
inputs may overshoot Vss to -2.0 V for periods of up to 20ns. Maximum DC
voltage on output and I/O pins is Vcc + 0.5V. During voltage transitions, outputs
may overshoot to Vcc + 2.0 V for periods of up to 20ns.
3. Minimum DC input voltage on A9 pin is -0.5V. During voltage transitions, A9
may overshoot Vss to -2V for periods of up to 20ns. Maximum DC input voltage
on A9 is +13.5V which may overshoot to 14.0 V for periods up to 20ns.
OEcapacitance
COE
CWE
V
V
IN = 0 V, f = 1.0 MHz
IN = 0 V, f = 1.0 MHz
50
pF
pF
WE1-4 capacitance
HIP (PGA)
20
15
CQFP G2U/G1U/G1T
CS1-4 capacitance
CCS
CI/O
CAD
V
IN = 0 V, f = 1.0 MHz
I/O = 0 V, f = 1.0 MHz
IN = 0 V, f = 1.0 MHz
20
20
50
pF
pF
pF
DataI/Ocapacitance
Addressinputcapacitance
V
V
This parameter is guaranteed by design but not tested.
(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)
InputLeakageCurrent
ILI
VCC =5.5, VIN =GNDtoVCC
VCC =5.5, VIN =GNDtoVCC
CS=VIL, OE=VIH
10
10
µA
µA
OutputLeakageCurrent
VCC ActiveCurrentforRead(1)
ILOx32
ICC1
140
200
mA
mA
VCC ActiveCurrentforProgram
orErase(2)
ICC2
CS=VIL, OE=VIH
VCC StandbyCurrent
VCC StaticCurrent
ICC3
ICC4
VOL
VCC = 5.5, CS = VIH, f = 5MHz
VCC =5.5, CS=VIH
6.5
0.6
mA
mA
V
OutputLowVoltage
OutputHighVoltage
IOL = 8.0 mA, VCC = 4.5
IOH = -2.5 mA, VCC = 4.5
0.45
VOH1
0.85 x
VCC
V
OutputHighVoltage
VOH2
VLKO
IOH = -100 µA, VCC = 4.5
VCC
-0.4
V
V
LowVCC LockOutVoltage
3.2
1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz).
The frequency component typically is less than 2 mA/MHz, with OE at VIH.
2. ICC active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
(VCC = 5.0V, VSS = 0V, TA = -55°C TO+125°C)
Write Cycle Time
tAVAV
tWLEL
tELEH
tWC
tWS
tCP
50
0
60
0
70
90
0
120
0
150
0
ns
ns
WESetupTime
0
CSPulseWidth
25
0
30
0
35
45
0
50
0
50
0
ns
AddressSetup Time
DataSetupTime
tAVEL
tAS
tDS
0
ns
tDVEH
tEHDX
tELAX
tEHWH
tEHEL
25
0
30
0
30
45
0
50
0
50
0
ns
Data Hold Time
tDH
tAH
tWH
tCPH
0
ns
AddressHoldTime
WE Hold from WE High
CSPulseWidthHigh
DurationofProgrammingOperation
DurationofEraseOperation
ReadRecoverybeforeWrite
ChipProgrammingTime
40
0
45
0
45
45
0
50
0
50
0
ns
0
ns
20
14
2.2
0
20
14
2.2
0
20
20
14
2.2
0
20
14
2.2
0
20
14
2.2
0
ns
tWHWH1
tWHWH2
tGHEL
14
µs
sec
ns
60
60
2.2 60
0
60
60
60
12.5
12.5
12.5
12.5
12.5
12.5 sec
InputPulseLevels
InputRiseandFall
VIL = 0, VIH = 3.0
V
ns
V
5
InputandOutputReferenceLevel
OutputTimingReferenceLevel
1.5
1.5
V
Notes:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 ý.
VZ is typically the midpoint of VOH and VOL.
IOL & IOHare adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)
Write Cycle Time
tAVAV
tELWL
tWC
tCS
50
0
60
0
70
0
90
0
120
0
150
0
ns
ns
ChipSelectSetupTime
WriteEnablePulseWidth
AddressSetupTime
tWLWH
tAVWL
tDVWH
tWHDX
tWLAX
tWHEH
tWP
tAS
tDS
25
0
30
0
35
0
45
0
50
0
50
0
ns
ns
DataSetupTime
25
0
30
0
30
0
45
0
50
0
50
0
ns
Data Hold Time
tDH
tAH
tCH
tWPH
ns
AddressHoldTime
40
0
45
0
45
0
45
0
50
0
50
0
ns
Chip Select Hold Time
WriteEnablePulseWidthHigh
Duration of Byte Programming Operation (min)
Sector Erase Time
ns
tWHWL
tWHWH1
tWHWH2
tGHWL
20
14
2.2
0
20
14
2.2
0
20
14
2.2
0
20
14
2.2
0
20
14
2.2
0
20
14
2.2
0
ns
µs
sec
ns
60
60
60
60
60
60
Read Recovery Time Before Write
VCC SetupTime
tVCS
50
50
50
50
50
50
µs
sec
ns
ChipProgrammingTime
OutputEnableSetupTime
12.5
12.5
12.5
12.5
12.5
12.5
tOES
0
0
0
0
0
0
OutputEnableHoldTime(1)
1. For Toggle and Data Polling.
tOEH
10
10
10
10
10
10
ns
(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)
Read Cycle Time
tAVAV
tAVQV
tELQV
tRC
50
60
70
90
120
150
ns
ns
ns
ns
ns
ns
ns
AddressAccessTime
Chip Select Access Time
OEtoOutputValid
tACC
tCE
50
50
25
20
20
60
60
30
20
20
70
70
35
20
20
90
90
40
25
25
120
120
50
150
150
55
tGLQV
tEHQZ
tGHQZ
tAXQX
tOE
tDF
ChipSelecttoOutputHighZ(1)
OEHightoOutputHighZ(1)
30
35
tDF
30
35
OutputHoldfromAddress,CSorOEChange,
whicheverisfirst
tOH
0
0
0
0
0
0
1. Guaranteed by design, not tested.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the output of the complement of the data written to the device (for each chip).
4. DOUT is the output of the data written to the device.
5.Figure indicates last two bus cycles of four bus cycle sequence.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
Notes:
1. SA is the sector address for Sector Erase.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
ACWAVEFORMSFORDATAPOLLINGDURINGEMBEDDEDALGORITHMOPERATIONS
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
NOTES:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D7 is the output of the complement of the data written to the device (for each chip).
4. DOUT is the output of the data written to the device.
5. Figure indicates the last two bus cycles of a four bus cycle sequence.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
PACKAGE510:68LEAD,CERAMICQUADFLATPACK,CQFP(G2U)1
TheWhite68leadG2UCQFP
fillsthesamefitandfunctionas
theJEDEC68leadCQFJor68
PLCCꢀButtheG2Uhasthe
TCEandleadinspection
advantageoftheCQFPformꢀ
Note1:PackageNotRecommendedForNewDesign
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
PACKAGE519:68LEAD,CERAMICQUADFLATPACK,LOWPROFILECQFP(G1U)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
PACKAGE524:68LEAD,CERAMICQUADFLATPACK,LOWPROFILECQFP(G1T)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
ORDERINGINFORMATION
W F 128K32 X - XXX X X 5 X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
VPP PROGRAMMINGVOLTAGE
5 = 5V
DEVICE GRADE:
Q = MIL - STD 833 Compliant
M = Military Screened -55°C to +125°C
I = Industrial
-40°C to +85°C
0°C to + 70°C
C = Commercial
PACKAGETYPE:
H1 = 1ꢀ075" sqꢀ Ceramic Hex In-line Package, HIP (Package 400)
G2U1 = 22ꢀ4mm Ceramic Quad Flat Pack, Low Profile CQFP (Package 510)
G1U = 23ꢀ9mm Ceramic Quad Flat Pack, Low Profile CQFP (Package 519)
G1T = 23ꢀ9mm Ceramic Quad Flat Pack, Low Profile CQFP (Package 524)
ACCESS TIME (ns)
IMPROVEMENTMARK
N = No Connect at pin 8, 21, 28 and 39 in HIP for Upgrade
ORGANIZATION, 128K x 32
User configurable as 256K x 16 or 512K x 8
Flash
WHITE ELECTRONIC DESIGNS CORP%
Note1:PackageNotRecommendedForNewDesign
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
DEVICETYPE
SPEED
PACKAGE
SMD NOꢀ
128Kx32Flash
128Kx32Flash
128Kx32Flash
128Kx32Flash
128Kx32Flash
150ns
120ns
90ns
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
5962-9471601H8X
5962-9471602H8X
5962-9471603H8X
5962-9471604H8X
5962-9471605H8X
70ns
60ns
128Kx32Flash
128Kx32Flash
128Kx32Flash
128Kx32Flash
128Kx32Flash
150ns
120ns
90ns
68 leadCQFP(G1U)
68 leadCQFP(G1U)
68 leadCQFP(G1U)
68 leadCQFP(G1U)
68 leadCQFP(G1U)
5962-9471601H9X
5962-9471602H9X
5962-9471603H9X
5962-9471604H9X
5962-9471605H9X
70ns
60ns
128Kx32Flash
128Kx32Flash
128Kx32Flash
128Kx32Flash
128Kx32Flash
150ns
120ns
90ns
68 leadCQFP(G2U)1
68 leadCQFP(G2U)1
68 leadCQFP(G2U)1
68 leadCQFP(G2U)1
68 leadCQFP(G2U)1
5962-9471601HNX1
5962-9471602HNX1
5962-9471603HNX1
5962-9471604HNX1
5962-9471605HNX1
70ns
60ns
Note1:PackageNotRecommendedForNewDesign
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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