WF128K32-120G2Q5A [ETC]
EEPROM ; EEPROM\n
| 型号： | WF128K32-120G2Q5A |
| 厂家： | 
ETC |
| 描述： | EEPROM
|
| 文件： | 总15页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WF128K32-XXX5
HI-RELIABILITY PRODUCT
128KX32 5V FLASH MODULE, SMD 5962-94716
FEATURES
■ Access Times of 50*, 60, 70, 90, 120, 150ns
■ Commercial, Industrial and Military Temperature Ranges
■ 5 Volt Programming. 5V ± 10% Supply
■ Packaging:
• 66 pin, PGA Type, 1.075 inch square, Hermetic
Ceramic HIP (Package 400)
■ Low Power CMOS, 1mA Standby Typical
■ Embedded Erase and Program Algorithms
■ TTL Compatible Inputs and CMOS Outputs
• 68 lead, 40mm, Low Profile 3.5mm (0.140"), CQFP
(Package 502)
• 68 lead, Hermetic CQFP, 22.4mm (0.880 inch) square.
Designed to fit JEDEC 68 lead 0.990" CQFJ footprint.
■ Built-in Decoupling Caps and Multiple Ground Pins for
Low Noise Operation
■ Page Program Operation and Internal Program Control Time
– G2 (Package 500), 5.08mm (0.200 inch) high
– G2U (Package 510), 3.56mm (0.140 inch) high
■ Weight
WF128K32-XG2X5 - 8 grams typical
WF128K32-XG2UX5 - 8 grams typical
WF128K32-XH1X5 - 13 grams typical
WF128K32-XG4TX5 - 20 grams typical
■ Sector Architecture
• 8 equal size sectors of 16KBytes each
• Any combination of sectors can be concurrently erased.
Also supports full chip erase
Note: For programming information refer to Flash Programming 1M5
Application Note.
■ 100,000 Erase/Program Cycles Typical, 0°C to +70°C
■ Organized as 128Kx32
*
The access time of 50ns is available in Industrial and Commercial
temperature ranges only.
FIG. 1 PIN CONFIGURATION FOR WF128K32N-XH1X5
TOP VIEW
PIN DESCRIPTION
1
12
23
34
45
56
I/O0-31
Data Inputs/Outputs
I/O8
I/O9
I/O10
A14
A16
A11
A0
WE2
CS2
GND
I/O11
A10
I/O15
I/O14
I/O13
I/O12
OE
I/O24
I/O25
I/O26
A7
VCC
CS4
WE4
I/O27
A4
I/O31
I/O30
I/O29
I/O28
A1
A0-16
WE1-4
CS1-4
OE
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
VCC
A12
GND
NC
A9
NC
NC
A5
A2
Not Connected
A15
WE1
I/O7
I/O6
I/O5
I/O4
A13
A6
A3
BLOCK DIAGRAM
WE1CS1
WE2CS2
WE3CS3
WE4CS4
NC
VCC
CS1
NC
A8
WE3
CS3
GND
I/O19
I/O23
I/O22
I/O21
I/O20
OE
0-16
A
I/O0
I/O1
I/O2
I/O16
I/O17
I/O18
128K x 8
128K x 8
128K x 8
128K x 8
I/O3
8
8
8
8
11
22
33
44
55
66
I/O16-23
I/O24-31
I/O0-7
I/O8-15
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
June 2000 Rev. 2
WF128K32-XXX5
FIG. 2 PIN CONFIGURATION FOR WF128K32-XG4TX5
PIN DESCRIPTION
TOP VIEW
I/O0-31
A0-16
WE
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Selects
9
8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
I/O0
I/O1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
CS1-4
OE
I/O2
Output Enable
Power Supply
Ground
I/O3
I/O4
VCC
I/O5
GND
NC
I/O6
I/O7
Not Connected
GND
I/O8
BLOCK DIAGRAM
I/O9
CS
CS
4
CS
CS
3
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
1
2
WE
OE
A0-16
128K x 8
128K x 8
128K x 8
128K x 8
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
8
8
8
8
I/O16-23
I/O24-31
I/O0-7
I/O8-15
FIG. 3 PIN CONFIGURATION FOR WF128K32-XG2X5 (Dual Cavity)
AND WF128K32-XG2UX5 (Single Cavity)
TOP VIEW
PIN DESCRIPTION
I/O0-31
Data Inputs/Outputs
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
A0-16
WE1-4
CS1-4
OE
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
0.940"
VCC
GND
NC
GND
The White 68 lead G2/G2U CQFP
fills the same fit and function as
the JEDEC 68 lead CQFJ or 68
PLCC. But the G2/G2U has the
TCE and lead inspection advan-
tage of the CQFP form.
I/O
I/O
8
9
Not Connected
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
BLOCK DIAGRAM
WE1CS1
WE2CS2
WE3CS3
WE4CS4
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
OE
0-16
A
128K x 8
128K x 8
128K x 8
128K x 8
8
8
8
8
I/O16-23
I/O24-31
I/O0-7
I/O8-15
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF128K32-XXX5
ABSOLUTE MAXIMUM RATINGS (1)
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
VCC
VIH
Min
4.5
Max
5.5
Unit
V
Parameter
Unit
°C
V
Supply Voltage
Operating Temperature
-55 to +125
-2.0 to +7.0
-2.0 to +7.0
-65 to +150
+300
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
A9 Voltage for Sector Protect
2.0
VCC + 0.3
+0.8
V
Supply Voltage Range (VCC)
VIL
-0.5
-55
V
Signal voltage range (any pin except A9) (2)
Storage Temperature Range
V
TA
+125
°C
V
°C
°C
VID
11.5
12.5
Lead Temperature (soldering, 10 seconds)
Data Retention Mil Temp
10 years
Endurance (write/erase cycles) Mil Temp
A9 Voltage for sector protect (VID) (3)
10,000 cycles min.
-2.0 to +14.0
CAPACITANCE
V
(TA = +25°C)
NOTES:
Parameter
Symbol
COE
Conditions
IN = 0 V, f = 1.0 MHz
IN = 0 V, f = 1.0 MHz
Max Unit
1. Stresses above the absolute maximum rating may cause permanent damage
to the device. Extended operation at the maximum levels may degrade
performance and affect reliability.
OE capacitance
V
V
50
pF
pF
WE1-4 capacitance
HIP (PGA)
CWE
2. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions,
inputs may overshoot VSS to -2.0 V for periods of up to 20ns. Maximum DC
voltage on output and I/O pins is VCC + 0.5V. During voltage transitions,
outputs may overshoot to Vcc + 2.0 V for periods of up to 20ns.
3. Minimum DC input voltage on A9 pin is -0.5V. During voltage transitions, A9 may
overshoot Vss to -2V for periods of up to 20ns. Maximum DC input voltage on A9
is +13.5V which may overshoot to 14.0 V for periods up to 20ns.
20
50
20
15
CQFP G4T
CQFP G2
CQFP G2U
CS1-4 capacitance
CCS
CI/O
CAD
V
IN = 0 V, f = 1.0 MHz
I/O = 0 V, f = 1.0 MHz
IN = 0 V, f = 1.0 MHz
20
20
50
pF
pF
pF
Data I/O capacitance
Address input capacitance
V
V
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS - CMOS COMPATIBLE
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter
Symbol
Conditions
Unit
Min
Max
10
Input Leakage Current
ILI
ILOx32
ICC1
VCC = 5.5, VIN = GND to VCC
VCC = 5.5, VIN = GND to VCC
CS = VIL, OE = VIH
µA
µA
Output Leakage Current
VCC Active Current for Read (1)
10
140
200
mA
mA
VCC Active Current for Program
or Erase (2)
ICC2
CS = VIL, OE = VIH
VCC Standby Current
VCC Static Current
Output Low Voltage
Output High Voltage
ICC3
ICC4
VOL
VCC = 5.5, CS = VIH, f = 5MHz
VCC = 5.5, CS = VIH
6.5
0.6
mA
mA
V
IOL = 8.0 mA, VCC = 4.5
0.45
VOH1
IOH = -2.5 mA, VCC = 4.5
0.85 x
VCC
V
Output High Voltage
VOH2
VLKO
IOH = -100 µA, VCC = 4.5
VCC
-0.4
V
V
Low VCC Lock Out Voltage
3.2
NOTES:
1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz).
The frequency component typically is less than 2 mA/MHz, with OE at VIH.
2. ICC active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF128K32-XXX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, CS CONTROLLED
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter
Symbol
-50
-60
-70
Max Min Max
70
-90
Min Max
90
-120
-150
Unit
Min Max Min
Min Max Min Max
Write Cycle Time
tAVAV
tWC
tWS
tCP
50
0
60
0
120
0
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
ns
WE Setup Time
tWLEL
tELEH
0
35
0
0
45
0
CS Pulse Width
25
0
30
0
50
0
50
0
Address Setup Time
Data Setup Time
tAVEL
tAS
tDVEH
tEHDX
tELAX
tDS
tDH
tAH
tWH
tCPH
25
0
30
0
30
0
45
0
50
0
50
0
Data Hold Time
Address Hold Time
40
0
45
0
45
0
45
0
50
0
50
0
WE Hold from WE High
CS Pulse Width High
Duration of Programming Operation
Duration of Erase Operation
Read Recovery before Write
Chip Programming Time
tEHWH
tEHEL
20
14
2.2
0
20
14
2.2
0
20
14
20
14
20
14
2.2
0
20
14
2.2
0
tWHWH1
tWHWH2
tGHEL
60
60
2.2 60
2.2
0
60
60
60
0
12.5
12.5
12.5
12.5
12.5
12.5 sec
AC TEST CONDITIONS
FIG. 4
AC TEST CIRCUIT
Parameter
Typ
Unit
V
IOL
Current Source
Input Pulse Levels
VIL = 0, VIH = 3.0
Input Rise and Fall
5
ns
V
Input and Output Reference Level
Output Timing Reference Level
1.5
1.5
V
D.U.T.
VZ
≈
1.5V
(Bipolar Supply)
Ceff = 50 pf
NOTES:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 Ω.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
IOH
Current Source
4
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WF128K32-XXX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, WE CONTROLLED
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter
Symbol
-50
-60
-70
-90
-120
-150
Unit
Min Max Min
Max Min Max Min Max Min
Max Min Max
Write Cycle Time
tAVAV
tWC
tCS
50
0
60
0
70
0
90
0
120
0
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
ns
µs
sec
ns
ns
Chip Select Setup Time
Write Enable Pulse Width
Address Setup Time
Data Setup Time
tELWL
tWLWH
tAVWL
tDVWH
tWHDX
tWLAX
tWHEH
tWHWL
tWP
tAS
25
0
30
0
35
0
45
0
50
0
50
0
tDS
tDH
tAH
tCH
tWPH
25
0
30
0
30
0
45
0
50
0
50
0
Data Hold Time
Address Hold Time
40
0
45
0
45
0
45
0
50
0
50
0
Chip Select Hold Time
Write Enable Pulse Width High
20
14
2.2
0
20
14
2.2
0
20
14
2.2
0
20
14
2.2
0
20
14
2.2
0
20
14
Duration of Byte Programming Operation (min) tWHWH1
Sector Erase Time
tWHWH2
tGHWL
60
60
60
60
60
2.2
0
60
Read Recovery Time Before Write
VCC Setup Time
tVCS
50
50
50
50
50
50
Chip Programming Time
Output Enable Setup Time
Output Enable Hold Time (1)
1. For Toggle and Data Polling.
12.5
12.5
12.5
12.5
12.5
12.5
tOES
0
0
0
0
0
0
tOEH
10
10
10
10
10
10
AC CHARACTERISTICS – READ ONLY OPERATIONS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter
Symbol
-50
Min Max Min Max
50 60
-60
-70
Min Max Min Max
70 90
-90
-120
-150
Unit
Min Max
Min Max
Read Cycle Time
tAVAV
tRC
tACC
tCE
tOE
tDF
tDF
tOH
120
120
120
50
150
150
150
55
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
50
50
25
20
20
60
60
30
20
20
70
70
35
20
20
90
90
40
25
25
Chip Select Access Time
OE to Output Valid
Chip Select to Output High Z (1)
OE High to Output High Z (1)
30
35
30
35
Output Hold from Address, CS or OE Change,
whichever is first
0
0
0
0
0
0
1. Guaranteed by design, not tested.
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF128K32-XXX5
FIG. 5
AC WAVEFORMS FOR READ OPERATIONS
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF128K32-XXX5
FIG. 6
WRITE/ERASE/PROGRAM OPERATION, WE CONTROLLED
NOTES:
1. PA is the address of the memory location
to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the output of the complement of the
data written to the device (for each chip).
4. DOUT is the output of the data written to
the device.
5. Figure indicates last two bus cycles of four bus
cycle sequence.
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF128K32-XXX5
FIG. 7
AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS
NOTES:
1. SA is the sector address
for Sector Erase.
8
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF128K32-XXX5
FIG. 8
AC WAVEFORMS FOR DATA POLLING DURING
EMBEDDED ALGORITHM OPERATIONS
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF128K32-XXX5
FIG. 9
WRITE/ERASE/PROGRAM OPERATION, CS CONTROLLED
NOTES:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D7 is the output of the complement of the data written to the device (for each chip).
4. DOUT is the output of the data written to the device.
5. Figure indicates the last two bus cycles of a four bus cycle sequence.
10
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF128K32-XXX5
PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1)
27.3 (1.075) ± 0.25 (0.010) SQ
PIN 1 IDENTIFIER
SQUARE PAD
ON BOTTOM
25.4 (1.0) TYP
4.34 (0.171)
MAX
3.81 (0.150)
± 0.13 (0.005)
1.42 (0.056) ± 0.13 (0.005)
0.76 (0.030) ± 0.13 (0.005)
2.54 (0.100)
TYP
1.27 (0.050) TYP DIA
15.24 (0.600) TYP
25.4 (1.0) TYP
0.46 (0.018) ± 0.05 (0.002) DIA
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 502: 68 LEAD, CERAMIC QUAD FLAT PACK, LOW PROFILE CQFP (G4T)
3.56 (0.140) MAX
39.6 (1.56) ± 0.38 (0.015) SQ
PIN 1 IDENTIFIER
Pin 1
12.7 (0.500)
± 0.5 (0.020)
4 PLACES
5.1 (0.200)
± 0.25 (0.010)
4 PLACES
0.25 (0.010)
± 0.05 (0.002)
0.38 (0.015)
1.27 (0.050)
TYP
± 0.08 (0.003)
68 PLACES
38 (1.50) TYP
4 PLACES
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF128K32-XXX5
PACKAGE 500: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2)
25.1 (0.990) ± 0.25 (0.010) SQ
5.1 (0.200) MAX
22.4 (0.880) ± 0.25 (0.010) SQ
0.25 (0.010) ± 0.1 (0.002)
Pin 1
0.25 (0.010) REF
R 0.25
(0.010)
24.0 (0.946)
± 0.25 (0.010)
0.25 (0.010)
± 0.127 (0.005)
1° / 7°
1.0 (0.040)
± 0.127 (0.005)
23.87
(0.940) REF
DETAIL A
1.27 (0.050) TYP
SEE DETAIL "A"
0.38 (0.015) ± 0.05 (0.002)
20.3 (0.800) REF
The White 68 lead G2 CQFP fills
the same fit and function as the
JEDEC 68 lead CQFJ or 68 PLCC.
But the G2 has the TCE and lead
inspection advantage of the
CQFP form.
0.940"
TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
12
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF128K32-XXX5
PACKAGE 510: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U)
25.15 (0.990) ± 0.25 (0.010) SQ
3.51 (0.140) MAX
22.36 (0.880) ± 0.25 (0.010) SQ
0.25 (0.010) ± 0.10 (0.002)
Pin 1
0.25 (0.010) REF
R 0.25
(0.010)
24.0 (0.946)
± 0.25 (0.010)
0.53 (0.021)
± 0.18 (0.007)
1° / 7°
1.01 (0.040)
± 0.13 (0.005)
23.87
(0.940) REF
DETAIL A
1.27 (0.050) TYP
SEE DETAIL "A"
0.38 (0.015) ± 0.05 (0.002)
20.3 (0.800) REF
The White 68 lead G2U CQFP
fills the same fit and function as
the JEDEC 68 lead CQFJ or 68
PLCC. But the G2U has the TCE
and lead inspection advantage
of the CQFP form.
0.940"
TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
13
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF128K32-XXX5
ORDERING INFORMATION
W F 128K32 X - XXX X X 5 X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
VPP PROGRAMMING VOLTAGE
5 = 5V
DEVICE GRADE:
Q = MIL - STD 833 Compliant
M = Military Screened -55°C to +125°C
I
= Industrial
-40°C to +85°C
0°C to + 70°C
C = Commercial
PACKAGE TYPE:
H1 = 1.075" sq. Ceramic Hex In-line Package, HIP (Package 400)
G2 = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 500)
G2U = 22.4mm Ceramic Quad Flat Pack, Low Profile CQFP (Package 510)
G4T = 40mm Ceramic Low Profile, CQFP (Package 502)
ACCESS TIME (ns)
IMPROVEMENT MARK
N = No Connect at pin 8, 21, 28 and 39 in HIP for Upgrade
ORGANIZATION, 128K x 32
User configurable as 256K x 16 or 512K x 8
Flash
WHITE ELECTRONIC DESIGNS CORP.
14
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF128K32-XXX5
DEVICE TYPE
SPEED
PACKAGE
SMD NO.
128K x 32 Flash
128K x 32 Flash
128K x 32 Flash
128K x 32 Flash
128K x 32 Flash
150ns
120ns
90ns
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
5962-94716 01H8X
5962-94716 02H8X
5962-94716 03H8X
5962-94716 04H8X
5962-94716 05H8X
70ns
60ns
128K x 32 Flash
128K x 32 Flash
128K x 32 Flash
128K x 32 Flash
128K x 32 Flash
150ns
120ns
90ns
68 lead CQFP/J (G2)
68 lead CQFP/J (G2)
68 lead CQFP/J (G2)
68 lead CQFP/J (G2)
68 lead CQFP/J (G2)
5962-94716 01HMX
5962-94716 02HMX
5962-94716 03HMX
5962-94716 04HMX
5962-94716 05HMX
70ns
60ns
128K x 32 Flash
128K x 32 Flash
128K x 32 Flash
128K x 32 Flash
128K x 32 Flash
150ns
120ns
90ns
68 lead CQFP/J (G2U)
68 lead CQFP/J (G2U)
68 lead CQFP/J (G2U)
68 lead CQFP/J (G2U)
68 lead CQFP/J (G2U)
5962-94716 01HNX
5962-94716 02HNX
5962-94716 03HNX
5962-94716 04HNX
5962-94716 05HNX
70ns
60ns
128K x 32 Flash
128K x 32 Flash
128K x 32 Flash
128K x 32 Flash
128K x 32 Flash
150ns
120ns
90ns
68 lead CQFP Low Profile (G4T)
68 lead CQFP Low Profile (G4T)
68 lead CQFP Low Profile (G4T)
68 lead CQFP Low Profile (G4T)
68 lead CQFP Low Profile (G4T)
5962-94716 01H4X
5962-94716 02H4X
5962-94716 03H4X
5962-94716 04H4X
5962-94716 05H4X
70ns
60ns
15
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
相关型号：
WF128K32-120G4I5
Flash Module, 512KX8, 120ns, CQFP68, 40 X 40 MM, HERMETIC SEALED, CERAMIC, QFP-68
WEDC
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