WM8728SEDSV [ETC]
24-bit, 192kHz Stereo DAC with Volume Control;
| 型号： | WM8728SEDSV |
| 厂家： | 
ETC |
| 描述： | 24-bit, 192kHz Stereo DAC with Volume Control |
| 文件： | 总31页 (文件大小：471K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM8728
w
24-bit, 192kHz Stereo DAC with
Volume Control
DESCRIPTION
FEATURES
•
•
Stereo DAC with 24 bit PCM
Audio Performance
The WM8728 is a high performance stereo DAC designed
for audio applications such as DVD, home theatre systems,
and digital TV. The WM8728 supports PCM data input word
lengths from 16 to 32-bits and sampling rates up to 192kHz.
The WM8728 consists of a serial interface port, digital
interpolation filters, multi-bit sigma delta modulators and
-
-
106dB SNR (‘A’ weighted @ 48kHz) DAC
-97dB THD
•
•
•
DAC Sampling Frequency: 8kHz - 192kHz
2 or 3-Wire Serial Control Interface or Hardware Control
Programmable Audio Data Interface Modes
stereo DAC in
a small 20-lead SSOP package. The
WM8728 also includes a digitally controllable mute and
attenuate function for each channel.
-
I2S, Left, Right Justified, DSP
-
16/20/24/32 bit Word Lengths
The WM8728 supports a variety of connection schemes for
audio DAC control. The 2 or 3-wire MPU serial port provides
access to a wide range of features including on-chip mute,
attenuation and phase reversal. A hardware controllable
interface is also available
•
Independent Digital Volume Control on Each Channel with
127.5dB Range in 0.5dB Steps
•
•
•
3.0V - 5.5V Supply Operation
20-lead SSOP Package
The WM8728 is an ideal device to interface to AC-3™,
DTS™, and MPEG audio decoders for surround sound
applications, or for use in DVD players supporting DVD-A.
Exceeds Dolby Class A Performance Requirements
APPLICATIONS
•
•
•
•
DVD-Audio and DVD ‘Universal’ Players
Home theatre systems
Digital TV
Digital broadcast receivers
BLOCK DIAGRAM
Production Data, August 2008, Rev 4.6
Copyright ©2008 Wolfson Microelectronics plc
WOLFSON MICROELECTRONICS plc
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WM8728
Production Data
TABLE OF CONTENTS
DESCRIPTION ............................................................................................................1
FEATURES..................................................................................................................1
APPLICATIONS ..........................................................................................................1
BLOCK DIAGRAM ......................................................................................................1
TABLE OF CONTENTS ..............................................................................................2
PIN CONFIGURATION................................................................................................3
ORDERING INFORMATION .......................................................................................3
PIN DESCRIPTION .....................................................................................................4
ABSOLUTE MAXIMUM RATINGS..............................................................................5
DC ELECTRICAL CHARACTERISTICS .....................................................................6
ELECTRICAL CHARACTERISTICS ...........................................................................6
TERMINOLOGY................................................................................................................. 7
MASTER CLOCK TIMING.................................................................................................. 8
DIGITAL AUDIO INTERFACE............................................................................................ 8
POWER SUPPLY TIMING ................................................................................................. 9
POWER ON RESET (POR) ............................................................................................... 9
MPU 3-WIRE INTERFACE TIMING ..................................................................................12
MPU 2-WIRE INTERFACE TIMING ..................................................................................13
DEVICE DESCRIPTION............................................................................................14
INTRODUCTION...............................................................................................................14
CLOCKING SCHEMES .....................................................................................................14
DIGITAL AUDIO INTERFACE...........................................................................................15
AUDIO DATA SAMPLING RATES.....................................................................................17
HARDWARE CONTROL MODES .....................................................................................18
SOFTWARE CONTROL INTERFACE...............................................................................20
REGISTER MAP ...............................................................................................................21
ATTENUATION CONTROL...............................................................................................22
DIGITAL FILTER CHARACTERISTICS.............................................................................25
DAC FILTER RESPONSES...............................................................................................25
DIGITAL DE-EMPHASIS CHARACTERISTICS........................................................26
APPLICATIONS INFORMATION ..............................................................................27
RECOMMENDED EXTERNAL COMPONENTS (PCM AUDIO).........................................27
RECOMMENDED EXTERNAL COMPONENTS VALUES.................................................27
RECOMMENDED ANALOGUE LOW PASS FILTER FOR PCM DATA FORMAT
(OPTIONAL)......................................................................................................................28
PACKAGE DIMENSIONS .........................................................................................29
IMPORTANT NOTICE...............................................................................................30
ADDRESS: ........................................................................................................................30
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PIN CONFIGURATION
ORDERING INFORMATION
MOISTURE SENSITIVITY
LEVEL
PEAK SOLDERING
DEVICE
TEMP. RANGE
-40 to +85oC
-40 to +85oC
PACKAGE
TEMP
20-lead SSOP
(Pb-free)
MSL2
WM8728SEDS/V
WM8728SEDS/RV
260°C
20-lead SSOP
MSL2
260°C
(Pb-free, tape and reel)
Note:
Reel quantity = 2,000
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PIN DESCRIPTION
PIN
1
NAME
LRCIN
DIN
TYPE
Digital Input
Digital Input
Digital Input
Digital Input
Digital Output (Open drain)
Supply
DESCRIPTION
DAC Sample Rate Clock Input: PCM Input Mode
Serial Audio Data Input: PCM Input Mode
Audio Data Bit Clock Input
2
3
BCKIN
MCLK
ZERO
DGND
DVDD
VOUTR
AGND
AVDD
VOUTL
VMID
4
Master Clock Input
5
Infinite ZERO Detect Flag (L = IZD detected, H = IZD not detected).
Digital Ground Supply
6
7
Supply
Digital Positive Supply
8
Analogue Output
Supply
Right Channel DAC Output
9
Analogue Ground Supply
10
11
12
13
14
15
Supply
Analogue Positive Supply
Analogue Output
Analogue Output
Supply
Left Channel DAC Output
Mid Rail Decoupling Point
VREFN
VREFP
CSBIWL
DAC Negative Reference – normally AGND, must not be below AGND
DAC Positive Reference – normally AVDD, must not be above AVDD
Software Mode: 3-Wire Serial Control Chip Select
Hardware Mode: Input Word Length
Supply
Digital Input
(pull-up)
16
17
18
MODE
MUTEB
SDIDEM
Digital Input (pull-down)
Digital Bi-directional
Digital Bi-directional
Control Mode Selection (L = Hardware, H = Software)
Mute Control (L = Mute on, H = Mute off, Z = Automute Enabled)
Software Mode: 3 or 2-Wire Serial Control Data Input:
Hardware Mode: De-Emphasis Select
19
20
SCK
Digital Input (pull-down)
Software Mode: 3 or 2-Wire Serial Control Clock Input
Software Mode 3-Wire Serial Control Load Input
Hardware Mode: Input Data Format Selection
LATI2S
Digital Input
(pull-up)
Note:
Digital input pins have Schmitt trigger input buffers.
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
MIN
-0.3V
MAX
+7V
Digital supply voltage
Analogue supply voltage
Voltage range digital inputs
Voltage range analogue inputs
Master Clock Frequency
Operating temperature range, TA
Storage temperature after soldering
-0.3V
+7V
DGND -0.3V
AGND -0.3V
DVDD +0.3V
AVDD +0.3V
50MHz
-40°C
-65°C
+85°C
+150°C
Note:
Analogue and digital grounds must always be within 0.3V of each other.
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DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
DVDD
TEST CONDITIONS
MIN
3.0
TYP
MAX
UNIT
V
Digital supply range
Analogue supply range
Ground
5.5
5.5
AVDD
3.0
V
AGND, DGND
0
0
V
Difference DGND to AGND
Analogue supply current
Digital supply current
Analogue supply current
Digital supply current
-0.3
+0.3
V
AVDD = 5V
DVDD = 5V
AVDD = 3.3V
DVDD = 3.3V
19
8
mA
mA
mA
mA
18
4
Note:
DVDD supply needs to be active before AVDD supply for correct device power on reset. See Power Supply Timing section.
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Logic Levels (TTL Levels)
Input LOW level
VIL
VIH
0.8
V
V
V
V
Input HIGH level
2.0
Output LOW
VOL
VOH
I
OL = 1mA
DGND + 0.3V
Output HIGH
I
OH = 1mA
DVDD – 0.3V
(VREFP -
Analogue Reference Levels
Reference voltage
VMID
(VREFP -
(VREFP -
V
VREFN)/2 - VREFN)/2 VREFN)/2 +
50mV
50mV
Potential divider resistance
RVMID
10k
Ω
DAC Output (Load = 10kΩ 50pF)
0dBFs Full scale output voltage
At DAC outputs
1.1 x
AVDD/5
106
Vrms
dB
SNR (Note 1,2,3)
SNR (Note 1,2,3)
SNR (Note 1,2,3)
SNR (Note 1,2,3)
A-weighted,
@ fs = 48kHz
A-weighted
@ fs = 96kHz
A-weighted
100
106
106
102
dB
dB
@ fs = 192kHz
A-weighted,
dB
@ fs = 48kHz
AVDD, DVDD = 3.3V
A-weighted
@ fs = 96kHz
AVDD, DVDD = 3.3V
SNR (Note 1,2,3)
SNR (Note 1,2,3)
102
103
dB
dB
Non ‘A’ weighted @ fs
= 48kHz
THD (Note 1,2,3)
1kHz, 0dBFs
-97
106
100
dB
dB
dB
THD+N (Dynamic range, Note 2)
DAC channel separation
1kHz, -60dBFs
100
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Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analogue Output Levels
Output level
Load = 10kΩ, 0dBFS
1.1
VRMS
VRMS
Load = 10kΩ, 0dBFS,
0.726
(AVDD = 3.3V)
Gain mismatch
channel-to-channel
±1
1
%FSR
kΩ
Minimum resistance load
To midrail or a.c.
coupled
To midrail or a.c.
coupled
600
ohms
(AVDD = 3.3V)
Maximum capacitance load
Output d.c. level
5V or 3.3V
100
pF
V
(VREFP -
VREFN)/2
Power On Reset (POR)
POR threshold
2.4
V
Notes:
1. Ratio of output level with 1kHz full scale input, to the output level with all ZEROS into the digital input, over a 20Hz to
20kHz bandwidth.
2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a
filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical
Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification
values.
3. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
TERMINOLOGY
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full-scale output and the output with a
ZERO signal applied. (No Auto-ZERO or Automute function is employed in achieving these results).
2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a
THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g.
THD+N @ -60dB= -32dB, DR= 92dB).
3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).
5. Channel Separation (dB) - Also known as Cross Talk. This is a measure of the amount one channel is isolated from the
other. Normally measured by sending a full-scale signal down one channel and measuring the other.
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MASTER CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Master Clock Timing Information
MCLK Master clock pulse width high
MCLK Master clock pulse width low
MCLK Master clock cycle time
MCLK Duty cycle
tMCLKH
tMCLKL
tMCLKY
13
13
ns
ns
ns
26
40:60
60:40
DIGITAL AUDIO INTERFACE
tBCH
tBCL
BCKIN
LRCIN
DIN
tBCY
tLRSU
tDS
tLRH
tDH
Figure 2 Digital Audio Data Timing
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCKIN cycle time
tBCY
tBCH
tBCL
40
16
16
8
ns
ns
ns
ns
BCKIN pulse width high
BCKIN pulse width low
LRCIN set-up time to
BCKIN rising edge
tLRSU
LRCIN hold time from
BCKIN rising edge
tLRH
tDS
8
8
8
ns
ns
ns
DIN set-up time to BCKIN
rising edge
DIN hold time from BCKIN
rising edge
tDH
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POWER SUPPLY TIMING
Figure 3 Power Supply Timing Requirements
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply Input Timing Information
DVDD set up time to AVDD
rising edge
TPSU
Measured from DVDD=+2.4V to
AVDD=+0.7V
100
µs
POWER ON RESET (POR)
The WM8728 has an internal power-on-reset (POR) circuit which is used to reset the digital logic
into a default state after power up. A block diagram of the reset circuit is shown in Figure 4
Figure 4 Block Diagram of Power-On-Reset Circuit
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The POR circuit requires that the DVDD is applied before the AVDD. The active low reset signal
NPOR will be asserted low until VMID rises to 1.2V. When this threshold has been reached, then
the NPOR is released and the digital interface has been reset. This is illustrated in the diagram
shown in Figure 5.
Figure 5 NPOR Generation At Power On Reset
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Figure 6 and Figure 7 illustrate the NPOR generation when the AVDD and DVDD power are
removed. Figure 6 illustrates the removal of DVDD before AVDD. Figure 7 illustrates the removal
of AVDD before AVDD.
DVDD
1.0V (Typ)
AVDD
VMID
Normal operation mode
Reset
NPOR
Figure 6 NPOR Generation at Power-off Reset (DVDD falls before AVDD)
DVDD
AVDD
1.0V (Typ)
VMID
Normal operation mode
Reset
NPOR
NPOR falls
with AVDD
Figure 7 NPOR Generation at Power-off Reset (AVDD falls before DVDD)
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MPU 3-WIRE INTERFACE TIMING
Figure 8 Program Register Input Timing - 3-Wire Serial Control Mode
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCK rising edge to LATI2S
rising edge
tSCS
40
ns
SCK pulse cycle time
tSCY
tSCL
80
20
20
20
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK pulse width low
SCK pulse width high
tSCH
tDSU
tDHO
tCSL
SDIDEM to SCK set-up time
SCK to SDIDEM hold time
LATI2S pulse width low
LATI2S pulse width high
LATI2S rising to SCK rising
CSBIWL to LATI2S set-up time
LATI2S to CSBIWL hold time
tCSH
tCSS
tCSSU
tCSSH
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MPU 2-WIRE INTERFACE TIMING
Figure 9 Program Register Input Timing - 2-Wire Serial Control Mode
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCK pulse cycle time
tSCY
tSCL
tSCH
tSSU
80
20
20
10
ns
ns
ns
ns
SCK pulse width low
SCK pulse width high
SDIDEM to SCK data set-up
time for start signal
SDIDEM from SCK data hold
time for start signal
tSHD
tDSU
10
20
ns
ns
SDIDEM to SCK data set-up
time
SCK to SDIDEM data hold time
SCK rise time
tDHD
tSCR
tSCF
tDR
20
5
ns
ns
ns
ns
ns
ns
SCK fall time
5
SDIDEM rise time
SDIDEM fall time
5
tDF
5
SDIDEM to SCK data set-up
time for stop signal
tESU
10
Notes:
1. The address for the device in the 2-wire mode is 001101X (binary) with the last bit selectable.
2. In the two-wire interface mode, the CSBIWL pin indicates the final bit of the chip address.
3. In 2-wire mode the LATI2S pin should be tied to either DGND or DVSS to avoid noise toggling the interface into 3-wire
mode.
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DEVICE DESCRIPTION
INTRODUCTION
The WM8728 is a high performance DAC designed for digital consumer audio applications. Its
range of features makes it ideally suited for use in DVD players, AV receivers and other high-end
consumer audio equipment.
WM8728 is a complete 2-channel stereo audio digital-to-analogue converter, including digital
interpolation filter, multi-bit sigma delta with dither, switched capacitor multi-bit stereo DAC and
output smoothing filters. The WM8728 includes an on-chip digital volume control, configurable
digital audio interface and a 2 or 3 wire MPU control interface. It is fully compatible and an ideal
partner for a range of industry standard microprocessors, controllers and DSPs.
Control of internal functionality of the device is by either hardware control (pin programmed) or
software control (2 or 3-wire serial control interface). The MODE pin selects between hardware
and software control. The software control interface may be asynchronous to the audio data
interface. In which case control data will be re-synchronised to the audio processing internally.
Operation using a master clock of 256fs, 384fs, 512fs or 768fs is provided, selection between
clock rates being automatically controlled in hardware mode, or serial controlled when in software
mode. Sample rates (fs) from less than 8ks/s to 96ks/s are allowed, provided the appropriate
master clock is input. Support is also provided for up to 192ks/s using a master clock of 128fs or
192fs.
The audio data interface supports right justified, left justified and I2S (Philips left justified, one bit
delayed) interface formats along with a highly flexible DSP serial port interface. When in hardware
mode, the three serial interface pins become control pins to allow selection of, input data format
type (I2S or right justified), input word length (20 or 24 bit) and de-emphasis functions.
The device is packaged in a small 20-pin SSOP.
CLOCKING SCHEMES
In a typical digital audio system there is only one central clock source producing a reference clock
to which all audio data processing is synchronised. This clock is often referred to as the audio
system’s Master Clock. The external master system clock can be applied directly through the
MCLK input pin with no software configuration necessary for sample rate selection.
Note that on the WM8728, MCLK is used to derive clocks for the DAC path. The DAC path
consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In
a system where there are a number of possible sources for the reference clock it is recommended
that the clock source with the lowest jitter be used to optimise the performance of the DAC.
WM8728 always acts as a slave and requires clocks to be inputs.
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DIGITAL AUDIO INTERFACE
Audio data is applied to the internal DAC filters via the Digital Audio Interface. Five popular
interface formats are supported:
•
•
•
•
•
Left Justified mode
Right Justified mode
I2S mode
DSP mode A
DSP mode B
All five formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits with the
exception that 32 bit data is not supported in right justified mode. DIN and LRCIN maybe
configured to be sampled on the rising or falling edge of BCKIN.
In left justified, right justified and I2S modes, the digital audio interface receives data on the DIN
input. Audio Data is time multiplexed with LRCIN indicating whether the left or right channel is
present. LRCIN is also used as a timing reference to indicate the beginning or end of the data
words. The minimum number of BCKINs per LRCIN period is 2 times the selected word length.
LRCIN must be high for a minimum of word length BCKINs and low for a minimum of word length
BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above requirements are
met
The WM8728 will automatically detect when data with a LRCIN period of exactly 32 BCKINs is
sent, and select 16-bit mode - overriding any previously programmed word length. Word length
will revert to a programmed value only if a LRCIN period other than 32 BCKINs is detected.
In DSP mode A or B, the data is time multiplexed onto DIN. LRCIN is used as a frame sync signal
to identify the MSB of the first word. The minimum number of BCKINs per LRCIN period is 2
times the selected word length. Any mark to space ratio is acceptable on LRCIN provided the
rising edge is correctly positioned. (See Figure 13 and Figure 14)
LEFT JUSTIFIED MODE
In left justified mode, the MSB is sampled on the first rising edge of BCKIN following a LRCIN
transition. LRCIN is high during the left data word and low during the right data word.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN
1
2
3
n
n-2 n-1
1
2
3
n
n-2 n-1
MSB
LSB
MSB
LSB
Figure 10 Left Justified Mode Timing Diagram
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RIGHT JUSTIFIED MODE
In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN
transition. LRCIN is high during the left data word and low during the right data word.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
MSB
LSB
Figure 11 Right Justified Mode Timing Diagram
I2S MODE
In I2S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN
transition. LRCIN is low during the left data word and high during the right data word.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
1 BCKIN
1 BCKIN
DIN
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
LSB
LSB
MSB
MSB
Figure 12 I2S Mode Timing Diagram
DSP MODE A
In DSP mode A, the first bit is sampled on the BCKIN rising edge following the one that detects a
low to high transition on LRCIN. No BCKIN edges are allowed between the data words. The word
order is DIN left, DIN right.
1 BCKIN
1 BCKIN
1/fs
LRCIN
BCKIN
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DIN
1
2
n
1
2
n
n-1
n-1
MSB
LSB
Input Word Length (IWL)
Figure 13 DSP Mode A Timing Diagram
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DSP MODE B
In DSP mode B, the first bit is sampled on the BCKIN rising edge, which detects a low to high
transition on LRCIN. No BCKIN edges are allowed between the data words. The word order is
DIN left, DIN right.
1/fs
LRCIN
BCKIN
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DIN
1
2
n
1
2
n
1
n-1
n-1
MSB
LSB
Input Word Length (IWL)
Figure 14 DSP Mode B Timing Diagram
AUDIO DATA SAMPLING RATES
The master clock for WM8728 can range from 128fs to 768fs, where fs is the audio sampling
frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The master clock is used
to operate the digital filters and the noise shaping circuits.
The WM8728 has a master clock detection circuit that automatically determines the relationship
between the master clock frequency and the sampling rate (to within +/- 32 system clocks). If
there is a greater than 32 clocks error, the interface shuts down the DAC and mutes the output.
The master clock should be synchronised with LRCIN, although the WM8728 is tolerant of phase
differences or jitter on this clock. See Table 1
SAMPLING
RATE
MASTER CLOCK FREQUENCY (MHZ) (MCLK)
128fs
192fs
256fs
384fs
512fs
768fs
(LRCIN)
32kHz
4.096
5.6448
6.114
6.144
8.467
8.192
11.2896
12.288
24.576
12.288
16.9340
18.432
36.864
16.384
22.5792
24.576
24.576
33.8688
36.864
44.1kHz
48kHz
9.216
96kHz
12.288
24.576
18.432
36.864
Unavailable Unavailable
192kHz
Unavailable Unavailable Unavailable Unavailable
Table 1 Typical Relationships Between Master Clock Frequency and Sampling Rate
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HARDWARE CONTROL MODES
When the MODE pin is held low, the following hardware modes of operation are available.
MUTE AND AUTOMUTE OPERATION
In both hardware and software modes, pin 17 (MUTEB) controls the selection of MUTE directly,
and can be used to enable and disable the automute function. Automute is enabled by leaving
MUTEB pin floating, it is disabled by applying a signal to the pin. When left floating this pin
becomes an output and indicates infinite ZERO detect (IZD), see also pin 5 (ZERO). The status
of IZD controls the selection of MUTE when automute is enabled. When IZD is detected MUTE is
enabled and when IZD is not detected MUTE is disabled.
MUTEB PIN
DESCRIPTION
0
1
Mute DAC channels
Normal Operation
Floating
MUTEB becomes an output to indicate when IZD occurs.
L=IZD detected (MUTE enabled), H=IZD not detected (MUTE disabled).
Table 2 Mute and Automute Control
ZERO PIN
DESCRIPTION
0
1
Indicates Infinite Zero detected from the digital input.
Indicates Infinite Zero not detected from the digital input.
Table 3 Zero Pin Output
Figure 15 shows the application and release of MUTE whilst a full amplitude sinusoid is being
played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace)
begins to decay exponentially from the DC level of the last input sample. The output will decay
towards VMID with a time constant of approximately 64 input samples. When MUTE is de-
asserted, the output will restart almost immediately from the current input sample.
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
0
0.001
0.002
0.003
0.004
0.005
0.006
Time(s)
Figure 15 Application and Release of Soft Mute
The MUTEB pin is an input to select mute or not mute. MUTEB is active low; taking the pin low
causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking
MUTEB high again allows data into the filter.
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The automute function detects a series of ZERO value audio samples of 1024 samples long
being applied to both channels. After such an event, a latch is set whose output (AUTOMUTED)
is wire OR’ed through a 10kohm resistor to the MUTEB pin. Thus if the MUTEB pin is not being
driven, the automute function will assert mute.
If MUTEB is tied high, AUTOMUTED is overridden and will not mute unless the IZD register bit is
set. If MUTEB is driven from a bi-directional source, then both MUTE and automute functions are
available. If MUTEB is not driven, AUTOMUTED appears as a weak output (10kOhm-source
impedance) so can be used to drive external mute circuits. AUTOMUTED will be removed as
soon as any channel receives a non-ZERO input.
A diagram showing how the various Mute modes interact is shown below Figure 16.
IZD (Register Bit)
AUTOMUTED
(Internal Signal)
10kΩ
SOFTMUTE
(Internal
Signal)
MUTEB
PIN
MUT (Register Bit)
Figure 16 Selection Logic for MUTE Modes
INPUT FORMAT SELECTION
In hardware mode, LATI2S (pin 20) and CSBIWL (pin 15) become input controls for selection of
input data format type and input data word length.
LATI2S
CSBIWL
INPUT DATA MODE
24-bit right justified
0
0
1
0
1
0
20-bit right justified
16-bit I2S
24-bit I2S
1
1
Table 4 Input Format Selection
Note:
In 24 bit I2S mode, any width of 24 bits or less is supported provided that LRCIN is high for a
minimum of 24 BCKINs and low for a minimum of 24 BCKINs. If exactly 32 BCKINs occur in one
LRCIN (16 high, 16 low) the chip will auto detect and run a 16 bit data mode.
DE-EMPHASIS CONTROL
In hardware mode, SDIDEM (pin 18) becomes an input control for selection of de-emphasis
filtering to be applied.
SDIDEM
DE-EMPHASIS
0
Off
On
1
Table 5 De-emphasis Control
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SOFTWARE CONTROL INTERFACE
The software control interface may be operated using a 2-wire interface compatible or 3-wire (SPI-
compatible) interface.
SELECTION OF CONTROL MODE
The WM8728 may be programmed to operate in hardware or software control modes. This is
achieved by setting the state of the MODE pin.
MODE
INTERFACE FORMAT
Hardware Control Mode
Software Control Mode
0
1
Table 6 Control Interface Mode Selection
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
In this mode, SDIDEM is used for the program data, SCK is used to clock in the program data
and LATI2S is used to latch in the program data. The 3-wire interface protocol is shown in Figure
17.
Figure 17 3-Wire Serial Interface
Notes:
1. B[15:9] are Control Address Bits
2. B[8:0] are Control Data Bits
3. CSBIWL needs to be low during writes – see Figure 8
2-WIRE SERIAL CONTROL MODE
In 2-wire mode, which is the default, SDIDEM is used for the program data and SCK is used to
clock in the program data see Figure 18.
WM8728 has an address of 001101X (binary) which represents an audio device. The final
address digit is dependent on pin CSBIWL, which should be tied to either DVDD or DGND. This
allows the device to have a choice of two identification header addresses used in the 2 wire
interface word. This feature allows more than one WM8728 device to be present on the interface
bus.
LATI2S should be tied to either DVDD or DGND, as it is unused. This pin if toggled from low to
high and high to low, will cause the device to enter the 3-wire interface mode and cannot be
placed back into 2-wire mode except by toggling the MODE pin, or powering off the device.
Figure 18 2-Wire Serial Interface
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REGISTER MAP
WM8728 uses a total of 4 program registers, which are 16-bits long. These registers are all loaded through input pin SDIDEM.
Using either 2-wire or 3-wire serial control mode as shown Figure 8 and Figure 9
B15
B14
B13
B12
B11
B10
B9
0
B8
B7
B6
LAT6
RAT6
0
B5
LAT5
RAT5
IW2
B4
LAT4
RAT4
IW1
B3
LAT3
RAT3
IW0
0
B2
LAT2
RAT2
B1
LAT1
RAT1
B0
LAT0
RAT0
M0
M1
M2
M3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
UPDATEL LAT7
UPDATER RAT7
0
1
0
0
0
0
0
PWDN DEEMPH MUT
I2S
0
1
IZD
0
BCP
REV
ATC
LRP
ADDRESS
DATA
Table 7 Mapping of Program Registers
REGISTER
ADDRESS
(A3,A2,A1,A0)
0000
BITS
NAME
DEFAULT
DESCRIPTION
[7:0]
8
LAT[7:0] 11111111 (0dB) Attenuation data for left channel in 0.5dB steps, see Table 10
DACL
UPDATEL
0
Attenuation data load control for left channel.
Attenuation
0: Store DACL in intermediate latch (no change to output)
1: Store DACL and update attenuation on both channels.
0001
[7:0]
8
RAT[7:0] 11111111 (0dB) Attenuation data for right channel in 0.5dB steps, see Table 10
DACR
Attenuation
UPDATER
0
0
0
0
Attenuation data load control for right channel.
0: Store DACR in intermediate latch (no change to output)
1: Store DACR and update attenuation on both channels.
Left and right DACs soft mute control.
0: No mute
0010
0
1
2
MUT
DAC Control
1: Mute
DEEMPH
PWDN
De-emphasis control.
0: De-emphasis off
1: De-emphasis on
Left and Right DACs Power-down Control
0: All DACs running, output is active
1: All DACs in power saving mode, output muted
Audio data format select, see Table 15
Audio data format select, see Table 15
Polarity select for LRCIN/DSP mode select.
0: normal LRCIN polarity/DSP late mode
1: inverted LRCIN polarity/DSP early mode
Attenuator Control.
[5:3]
0
IW[2:0]
I2S
0
0
0
0011
Interface
Control
1
LRP
2
ATC
0
0: All DACs use attenuation as programmed.
1: Right channel DACs use corresponding left DAC
attenuation
4
5
REV
BCP
0
0
Output phase reverse.
BCKIN Polarity
0 : normal BCKIN polarity
1: inverted BCKIN polarity
8
IZD
0
Infinite ZERO detection circuit control and automute control
0: Infinite ZERO detect disabled
1: Infinite ZERO detect enabled
Table 8 Register Bit Descriptions
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ATTENUATION CONTROL
Each DAC channel can be attenuated digitally before being applied to the digital filter. Attenuation
is 0dB by default but can be set between 0 and 127.5dB in 0.5dB steps using the 8 Attenuation
control bits. All attenuation registers are double latched allowing new values to be pre-latched to
both channels before being updated synchronously. Setting the UPDATE bit on any attenuation
write will cause all pre-latched values to be immediately applied to the DAC channels.
REGISTER
ADDRESS
BITS
LABEL
DEFAULT
DESCRIPTION
0000
[7:0]
LAT[7:0]
11111111 (0dB)
Attenuation data for Left channel DACL in 0.5dB steps.
Attenuation
DACL
8
UPDATEL
0
Controls simultaneous update of all Attenuation Latches
0: Store DACL in intermediate latch (no change to output)
1: Store DACL and update attenuation on all channels.
Attenuation data for Right channel DACR in 0.5dB steps.
0001
[7:0]
8
RAT[7:0]
11111111 (0dB)
0
Attenuation
DACR
UPDATER
Controls simultaneous update of all Attenuation Latches
0: Store DACR in intermediate latch (no change to output)
1: Store DACR and update attenuation on all channels.
Table 9 Attenuation Register Map
Note:
1. The UPDATE bit is not latched. If UPDATE=0, the Attenuation value will be written to the pre-latch but not applied to the
relevant DAC. If UPDATE=1, all pre-latched values and the current value being written will be applied on the next input
sample.
2. Care should be used in reducing the attenuation as rapid large volume changes can introduce zipper noise.
DAC OUTPUT ATTENUATION
Registers LAT and RAT control the left and right channel attenuation. Table 9 shows how the
attenuation levels are selected from the 8-bit words.
XAT[7:0]
ATTENUATION LEVEL
00(hex)
∞dB (mute)
01(hex)
127dB
:
126.5 dB
:
:
:
:
FE(hex)
FF(hex)
0.5dB
0dB
Table 10 Attenuation Control Levels
MUTE MODES
Setting the MUT register bit will apply a 'soft' mute to the input of the digital filters:
REGISTER ADDRESS
0010
BIT
LABEL
DEFAULT
DESCRIPTION
Soft Mute select
0
MUT
0
DAC Control
0 : Normal Operation
1: Soft mute all channels
Table 11 Mute control
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DE-EMPHASIS MODE
Setting the DEEMPH register bit puts the digital filters into de-emphasis mode:
REGISTER ADDRESS
0010
BIT
LABEL
DEFAULT
DESCRIPTION
1
DEEMPH
0
De-emphasis mode select:
0 : De-emphasis Off
DAC Control
1: De-emphasis On
Table 12 De-emphasis Control
POWERDOWN MODE
Setting the PWDN register bit immediately connects all outputs to VMID and selects a low power
mode. All trace of the previous input samples is removed, and all control register settings are
cleared. When PWDN is cleared again the first 16 input samples will be ignored, as the FIR will
repeat it's power-on initialisation sequence.
REGISTER ADDRESS
0010
BIT
LABEL
DEFAULT
DESCRIPTION
Power Down Mode Select:
0 : Normal Mode
2
PWDN
0
DAC Control
1: Power Down Mode
Table 13 Powerdown control
DIGITAL AUDIO INTERFACE CONTROL REGISTERS
The WM8728 has a fully featured digital audio interface that is a superset of that contained in the
WM8716. Interface format is selected via the IWL[2:0] register bits in register M2 and the I2S
register bit in M3.
REGISTER ADDRESS
0010
BIT
LABEL
DEFAULT
DESCRIPTION
5:3
IWL[2:0]
000000
Interface format Select
DAC Control
0011
0
I2S
0
Interface format Select
Interface Control
Table 14 Interface Format Controls
IW2
I2S
IW1
IW0
AUDIO INTERFACE DESCRIPTION
(NOTE 1)
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
16 bit right justified mode
20 bit right justified mode
24 bit right justified mode
24 bit left justified mode
16 bit I2S mode
24 bit I2S mode
20 bit I2S mode
20 bit left justified mode
16 bit DSP mode
20 bit DSP mode
24 bit DSP mode
32 bit DSP mode
16 bit left justified mode
Table 15 Audio Data Input Format
Note:
In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the
DAC is programmed to receive 16 or 20 bit data, the WM8728 pads the unused LSBs with
ZEROS. If the DAC is programmed into 32-bit mode, the 8 LSBs are treated as zero.
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SELECTION OF LRCIN POLARITY
In left justified, right justified or I2S modes, the LRP register bit controls the polarity of LRCIN. If
this bit is set high, the expected polarity of LRCIN will be the opposite of that shown in Figure 10,
Figure 11 and Figure 12. Note that if this feature is used as a means of swapping the left and right
channels, a 1 sample phase difference will be introduced.
REGISTER ADDRESS
0011
BIT
LABEL
DEFAULT
DESCRIPTION
1
LRP
0
LRCIN Polarity (normal)
0 : normal LRCIN polarity
1: inverted LRCIN polarity
Interface Control
Table 16 LRCIN Polarity Control
In DSP modes, the LRCIN register bit is used to select between early and late modes (see Figure
13 and Figure 14.
REGISTER ADDRESS
0011
BIT
LABEL
DEFAULT
DESCRIPTION
1
LRP
0
DSP Format (DSP modes)
0 : Late DSP mode
Interface Control
1: Early DSP mode
Table 17 DSP Format Control
In DSP early mode, the first bit is sampled on the BCKIN rising edge following the one that
detects a low to high transition on LRCIN. In DSP late mode, the first bit is sampled on the BCKIN
rising edge, which detects a low to high transition on LRCIN. No BCKIN edges are allowed
between the data words. The word order is DIN left, DIN right.
ATTENUATOR CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both left
and right channel DACs from the next audio input sample. No update to the attenuation registers
is required for ATC to take effect.
REGISTER ADDRESS
0011
BIT
LABEL
DEFAULT
DESCRIPTION
2
ATC
0
Attenuator Control Mode:
0 : Right channels use Right
attenuation
Interface Control
1: Right Channels use Left
Attenuation
Table 18 Attenuation Control Select
OUTPUT PHASE REVERSAL
The REV register bit controls the phase of the output signal. Setting the REV bit causes the
phase of the output signal to be inverted.
REGISTER ADDRESS
0011
BIT
LABEL
DEFAULT
DESCRIPTION
Analogue Output Phase
0: Normal
4
REV
0
Interface Control
1: Inverted
Table 19 Output Phase Control
BCKIN POLARITY
By default, LRCIN and DIN are sampled on the rising edge of BCKIN and should ideally change
on the falling edge. Data sources which change LRCIN and DIN on the rising edge of BCKIN can
be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCKIN to the
inverse of that shown in Figure 10, Figure 11, Figure 12, Figure 13 and Figure 14.
REGISTER ADDRESS
0011
BIT
LABEL
DEFAULT
DESCRIPTION
BCKIN Polarity
5
BCP
0
0 : normal BCKIN polarity
1: inverted BCKIN polarity
Interface Control
Table 20 BCKIN Polarity Control
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INFINITE ZERO DETECTION
Setting the IZD register bit determines whether the device is automuted when a sequence of more
than 1024 ZEROS is detected.
REGISTER ADDRESS
0011
BIT
LABEL
DEFAULT
DESCRIPTION
8
IZD
0
Infinite ZERO detection circuit
control and automute control
Interface Control
0: Infinite ZERO detect disabled
1: Infinite ZERO detect enabled
Table 21 IZD Control
DIGITAL FILTER CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
-3dB
MIN
TYP
MAX
UNIT
Passband Edge
Passband Ripple
Stopband Attenuation
0.487fs
f < 0.444fs
f > 0.555fs
0.05
dB
dB
-60
Table 22 Digital Filter Characteristics
DAC FILTER RESPONSES
0.2
0.15
0.1
0
-20
-40
0.05
0
-60
-0.05
-0.1
-0.15
-0.2
-80
-100
-120
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (Fs)
Frequency (Fs)
Figure 19 DAC Digital Filter Frequency Response
-44.1, 48 and 96kHz
Figure 20 DAC Digital Filter Ripple
-44.1, 48 and 96kHz
0.2
0
-20
-40
-60
-80
0
-0.2
-0.4
-0.6
-0.8
-1
0
0.2
0.4
0.6
0.8
1
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (Fs)
Frequency (Fs)
Figure 21 DAC Digital Filter Frequency Response
-192kHz
Figure 22 DAC Digital Filter Ripple
-192kHz
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DIGITAL DE-EMPHASIS CHARACTERISTICS
0
1
0.5
0
-2
-4
-0.5
-1
-6
-1.5
-2
-8
-2.5
-3
-10
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
Frequency (kHz)
Frequency (kHz)
Figure 23 De-Emphasis Frequency Response (32kHz)
Figure 24 De-Emphasis Error (32kHz)
0
0.4
0.3
0.2
0.1
0
-2
-4
-6
-0.1
-0.2
-0.3
-0.4
-8
-10
0
5
10
15
20
0
5
10
15
20
Frequency (kHz)
Frequency (kHz)
Figure 25 De-Emphasis Frequency Response (44.1kHz)
Figure 26 De-Emphasis Error (44.1kHz)
0
1
0.8
0.6
0.4
0.2
0
-2
-4
-6
-0.2
-0.4
-0.6
-0.8
-1
-8
-10
0
5
10
15
20
0
5
10
15
20
Frequency (kHz)
Frequency (kHz)
Figure 27 De-Emphasis Frequency Response (48kHz)
Figure 28 De-Emphasis Error (48kHz)
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APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS (PCM AUDIO)
Figure 29 External Components Diagram
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT
REFERENCE
SUGGESTED
VALUE
DESCRIPTION
C1 and C5
C2 to C4
C6 and C7
C8
10µF
0.1µF
10µF
0.1µF
10µF
10µF
10kΩ
33Ω
De-coupling for DVDD and AVDD/VREFP
De-coupling for DVDD and AVDD/VREFP
Output AC coupling caps to remove midrail DC level from outputs.
Reference de-coupling capacitors for VMID pin.
C9
C10
Filtering for VREFP. Omit if AVDD low noise.
10k pull-up to DVDD
R1
R2
Filtering for VREP. Use 0Ω if AVDD low noise.
Table 23 External Components Description
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RECOMMENDED ANALOGUE LOW PASS FILTER FOR PCM DATA FORMAT
(OPTIONAL)
4.7kΩ
4.7k
Ω
+VS
_
51
Ω
10uF
1.8kΩ
7.5KΩ
+
+
-VS
1.0nF
680pF
47kΩ
Figure 30 Recommended Low Pass Filter (Optional)
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PACKAGE DIMENSIONS
DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm)
DM0015.C
b
e
20
11
E1
E
GAUGE
PLANE
Θ
1
10
D
0.25
L
c
A1
A A2
L
1
-C-
0.10 C
SEATING PLANE
Dimensions
(mm)
NOM
-----
Symbols
MIN
-----
MAX
2.0
-----
1.85
0.38
0.25
7.50
A
A1
A2
b
c
D
e
E
E1
L
0.05
1.65
0.22
0.09
6.90
-----
1.75
0.30
-----
7.20
0.65 BSC
7.80
7.40
5.00
0.55
8.20
5.60
0.95
5.30
0.75
L1
θ
1.25 REF
0o
4o
8o
-
JEDEC.95, MO 150
REF:
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.
D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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IMPORTANT NOTICE
Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,
delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right
to make changes to its products and specifications or to discontinue any product or service without notice. Customers should
therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.
Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating
safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product
design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such
selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction
can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of
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Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this
datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that
person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon
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ADDRESS:
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EH11 2QB
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: sales@wolfsonmicro.com
PD, Rev 4.6, August 2008
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Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Cirrus Logic:
WM8728SEDS/V
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