WS512K32NBV-15 [ETC]
512Kx32 3.3V SRAM MODULE; 512Kx32 3.3V SRAM模块
| 型号： | WS512K32NBV-15 |
| 厂家： | 
ETC |
| 描述： | 512Kx32 3.3V SRAM MODULE |
| 文件： | 总8页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WS512K32BV-XXXE
512Kx32 3.3V SRAM MODULE PRELIMINARY*
FEATURES
■ Access Times of 15†, 17, 20ns
■ MIL-STD-883 Compliant Devices Available
■ Low Voltage Operation
■ Commercial, Industrial and Military Temperature Ranges
■ 3.3 Volt Power Supply
■ BiCMOS
■ TTL Compatible Inputs and Outputs
■ Packaging
■ Built-in Decoupling Caps and Multiple Ground Pins for Low
• 66-pin, PGA Type, 1.385 inch square Hermetic Ceramic HIP
(Package 402)
Noise Operation
■ Weight
• 68 lead, Hermetic CQFP (G2), 22mm (0.880 inch) square
(Package 500). Designed to fit JEDEC 68 lead 0.990" CQFJ
footprint
WS512K32BV-XG2XE - 8 grams typical
WS512K32NBV-XH2XE - 13 grams typical
■ Organized as 512Kx32; User Configurable as 1Mx16 or 2Mx8
■ Radiation Tolerant with Epitaxial Layer Die
*
This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
† This speed is Advanced information.
PIN CONFIGURATION FOR WS512K32NBV-XH2XE
TOP VIEW
PIN DESCRIPTION
1
12
23
34
45
56
I/O0-31 Data Inputs/Outputs
A0-18
WE1-4
CS1-4
OE
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
I/O
I/O
8
9
WE
2
I/O15
I/O14
I/O13
I/O12
OE
I/O24
I/O25
I/O26
V
CC
I/O31
I/O30
I/O29
I/O28
CS2
CS
4
I/O10
GND
I/O11
WE
4
VCC
A
A
A
A
A
13
14
15
16
17
A
A
6
7
I/O27
GND
NC
A10
A11
A12
VCC
A
A
3
4
5
3
3
A
A
A
0
1
2
Not Connected
A18
NC
BLOCK DIAGRAM
WE1
A
8
9
A
WE1CS1
WE2CS2
WE3CS3
WE4CS4
I/O
I/O
I/O
I/O
7
A
WE
CS
I/O23
I/O22
I/O21
I/O20
OE
0-18
A
I/O
I/O
I/O
0
1
2
CS
NC
I/O
1
6
I/O16
I/O17
I/O18
512K x 8
512K x 8
512K x 8
512K x 8
5
4
GND
I/O19
3
8
8
8
8
11
22
33
44
55
66
I/O16-23
I/O24-31
I/O0-7
I/O8-15
February 1998
1
White Microelectronics • Phoenix, AZ • (602) 437-1520
WS512K32BV-XXXE
PIN CONFIGURATION FOR WS512K32BV-XG2XE
TOP VIEW
PIN DESCRIPTION
I/O0-31 Data Inputs/Outputs
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
A0-18
WE1-4
CS1-4
OE
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
Vcc
0.940"
GND
NC
GND
The White 68 lead G2 CQFP fills
the same fit and function as the
JEDEC 68 lead CQFJ or 68 PLCC.
But the G2 has the TCE and lead
inspection advantage of the
Not Connected
I/O
8
9
I/O
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
BLOCK DIAGRAM
CQFP form.
WE1CS1
WE2CS2
WE3CS3
WE4CS4
OE
0-18
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A
512K x 8
512K x 8
512K x 8
512K x 8
8
8
8
8
I/O16-23
I/O24-31
I/O0-7
I/O8-15
White Microelectronics • Phoenix, AZ • (602) 437-1520
2
WS512K32BV-XXXE
ABSOLUTE MAXIMUM RATINGS
TRUTH TABLE
Parameter
Symbol
TA
Min
-55
-65
-0.5
Max
+125
+150
4.6
Unit
°C
°C
V
CS
H
L
L
L
OE
X
L
X
H
WE
X
H
L
H
Mode
Standby
Read
Write
Out Disable
Data I/O
High Z
Data Out
Data In
High Z
Power
Standby
Active
Active
Active
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
TSTG
VG
TJ
150
4.6
°C
V
VCC
-0.5
CAPACITANCE
(TA = +25°C)
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
VCC
Min
3.0
Max
3.6
Unit
V
Parameter
Symbol
COE
Conditions
Max Unit
Supply Voltage
Input High Voltage
Input Low Voltage
OE capacitance
V
V
IN = 0 V, f = 1.0 MHz
IN = 0 V, f = 1.0 MHz
50
pF
pF
VIH
2.2
VCC + 0.3
+0.8
V
WE1-4 capacitance
HIP (PGA)
CWE
20
20
VIL
-0.3
V
CQFP G2
CS1-4 capacitance
CCS
CI/O
CAD
V
IN = 0 V, f = 1.0 MHz
I/O = 0 V, f = 1.0 MHz
VIN = 0 V, f = 1.0 MHz
20
20
50
pF
pF
pF
Data I/O capacitance
V
Address input capacitance
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
(VCC = 3.3V ± 0.3V, VSS = 0V, TA = -55°C to +125°C)
Parameter
Sym
Conditions
Units
Min
Max
Input Leakage Current
Output Leakage Current
ILI
ILO
VIN = GND to VCC
10
µA
µA
mA
mA
V
CS = VIH, OE = VIH, VOUT = GND to VCC
CS = VIL, OE = VIH, f = 5MHz, VCC = 3.6V
CS = VIH, OE = VIH, f = 5MHz, VCC = 3.6V
IOL = 8mA
10
Operating Supply Current (x 32 Mode)
Standby Current
ICC x 32
ISB
480
110
0.4
Output Low Voltage
VOL
Output High Voltage
VOH
IOH = -4.0mA
2.4
V
NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V
3
White Microelectronics • Phoenix, AZ • (602) 437-1520
WS512K32BV-XXXE
AC CHARACTERISTICS
(VCC = 3.3V, TA = -55°C to +125°C)
Parameter
Symbol
-15*
-17
-20
Units
Read Cycle
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
tAA
15
17
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
15
17
20
Output Hold from Address Change
Chip Select Access Time
tOH
0
0
0
tACS
tOE
15
7
17
8
20
10
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
tCLZ1
tOLZ1
tCHZ1
tOHZ1
2
0
2
0
2
0
7
7
8
8
10
10
1. This parameter is guaranteed by design but not tested.
* Advanced information.
AC CHARACTERISTICS
(VCC = 3.3V, TA = -55°C to +125°C)
Parameter
Symbol
-15*
-17
-20
Units
Write Cycle
Min
15
10
10
8
Max
Min
17
12
12
9
Max
Min
20
14
14
10
14
0
Max
Write Cycle Time
tWC
tCW
tAW
tDW
tWP
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
12
0
14
0
Address Setup Time
Address Hold Time
tAH
0
0
0
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
tOW1
tWHZ1
tDH
2
3
3
8
8
9
0
0
0
1. This parameter is guaranteed by design but not tested.
* Advanced information.
AC TEST CIRCUIT
AC TEST CONDITIONS
IOL
Parameter
Typ
Unit
V
Current Source
Input Pulse Levels
VIL = 0, VIH = 2.5
Input Rise and Fall
5
ns
V
Input and Output Reference Level
Output Timing Reference Level
1.5
1.5
V
D.U.T.
VZ ≈ 1.5V
(Bipolar Supply)
Ceff = 50 pf
NOTES:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 Ω.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
IOH
Current Source
White Microelectronics • Phoenix, AZ • (602) 437-1520
4
WS512K32BV-XXXE
TIMING WAVEFORM - READ CYCLE
tRC
ADDRESS
CS
tAA
tRC
tCHZ
tACS
ADDRESS
tCLZ
tAA
OE
tOE
tOLZ
tOH
tOHZ
DATA I/O
DATA I/O
PREVIOUS DATA VALID
DATA VALID
DATA VALID
HIGH IMPEDANCE
READ CYCLE 1 (CS = OE = V , WE = V
)
READ CYCLE 2 (WE = V )
IH
IL IH
WRITE CYCLE - WE CONTROLLED
tWC
ADDRESS
tAW
tAH
tCW
CS
WE
tAS
tWP
tOW
tDH
tWHZ
tDW
DATA I/O
DATA VALID
WRITE CYCLE 1, WE CONTROLLED
WRITE CYCLE - CS CONTROLLED
tWC
ADDRESS
WS32K32-XHX
tCW
tAW
tAH
tAS
CS
tWP
WE
tDW
tDH
DATA I/O
DATA VALID
WRITE CYCLE 2, CS CONTROLLED
5
White Microelectronics • Phoenix, AZ • (602) 437-1520
WS512K32BV-XXXE
PACKAGE 402: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H2)
35.2 (1.385) ± 0.38 (0.015) SQ
PIN 1 IDENTIFIER
SQUARE PAD
ON BOTTOM
25.4 (1.0) TYP
5.7 (0.223)
MAX
3.81 (0.150)
± 0.1 (0.005)
1.27 (0.050) ± 0.1 (0.005)
0.76 (0.030) ± 0.1 (0.005)
2.54 (0.100)
TYP
1.27 (0.050) TYP DIA
15.24 (0.600) TYP
25.4 (1.0) TYP
0.46 (0.018) ± 0.05 (0.002) DIA
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Microelectronics • Phoenix, AZ • (602) 437-1520
6
WS512K32BV-XXXE
PACKAGE 500: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2)
25.1 (0.990) ± 0.25 (0.010) SQ
5.1 (0.200) MAX
22.4 (0.880) ± 0.25 (0.010) SQ
0.25 (0.010) ± 0.1 (0.002)
Pin 1
0.25 (0.010) REF
R 0.25
(0.010)
24.0 (0.946)
± 0.25 (0.010)
0.25 (0.010)
± 0.127 (0.005)
1° / 7°
1.0 (0.040)
± 0.127 (0.005)
23.87
(0.940) REF
DETAIL A
1.27 (0.050) TYP
SEE DETAIL "A"
0.38 (0.015) ± 0.05 (0.002)
20.3 (0.800) REF
The White 68 lead G2 CQFP fills
the same fit and function as the
JEDEC 68 lead CQFJ or 68 PLCC.
But the G2 has the TCE and lead
inspection advantage of the
CQFP form.
0.940"
TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
7
White Microelectronics • Phoenix, AZ • (602) 437-1520
WS512K32BV-XXXE
ORDERING INFORMATION
W S 512K 32 X B V - XXX X X E X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
E = Epitaxial Layer
DEVICE GRADE:
M= Military Screened -55°C to +125°C
I = Industrial
C = Commercial
-40°C to +85°C
0°C to +70°C
PACKAGE TYPE:
H2 = Ceramic Hex-In-line Package, HIP (Package 402)
G2 = 22 mm Ceramic Quad Flat Pack, CQFP (Package 500)
ACCESS TIME (ns)
Low Voltage Supply 3.3V ± 10%
BiCMOS
IMPROVEMENT MARK:
N = No Connect at pin 21 and 39 in HIP for Upgrades
ORGANIZATION, 512Kx32
User configurable as 1Mx16 or 2Mx8
SRAM
WHITE MICROELECTRONICS
White Microelectronics • Phoenix, AZ • (602) 437-1520
8
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