WS57C71C- [ETC]
WS57C71C MILITARY HIGH SPEED 32K X 8 CMOS PROM/RPROM ; WS57C71C军事高速32K ×8 CMOS PROM / RPROM\n
| 型号： | WS57C71C- |
| 厂家： | 
ETC |
| 描述： | WS57C71C MILITARY HIGH SPEED 32K X 8 CMOS PROM/RPROM
|
| 文件： | 总2页 (文件大小：22K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WS57C71C
MILITARY HIGH SPEED 32K x 8 CMOS PROM/RPROM
KEY FEATURES
• Ultra-Fast Access Time
— 45 ns
• Immune to Latch-UP
— Up to 200 mA
• Low Power Consumption
• Fast Programming
• ESD Protection Exceeds 2000V
• Available in 300 and 600 Mil DIP
and CLLCC
GENERAL DESCRIPTION
The WS57C71C is a High Performance 256K UV Erasable Electrically Re-Programmable Read Only Memory
(RPROM). It is manufactured in an advanced CMOS technology and utilizes WSI's patented self-aligned split gate
EPROM cell.
The industry standard PROM pin configuration of the WS57C71C provides an easy upgrade path from a 16K x 8
device.
This RPROM is capable of operating at speeds as fast as 35 ns address access time, which enables it to be used
directly with today's fast microprocessors and DSP processors without introducing any wait states. All inputs and
outputs are TTL compatible. The WS57C71C is a low power device even when operated at its fastest speed. The
DIP version is packaged in a 300 mil wide DIP package saving board space for the user.
MODE SELECTION
PIN CONFIGURATION
PINS CS1/
TOP VIEW
CS2
CS3
V
OUTPUTS
CC
V
MODE
PP
Chip Carrier
CERDIP
Read
V
V
V
V
D
IL
IH
IL
CC
CC
OUT
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
A
A
A
A
A
A
A
A
A
O
O
O
V
A
A
A
A
A
9
8
7
6
5
4
3
2
1
0
0
1
2
CC
10
11
12
13
14
Output
Disable
V
X
X
X
V
High Z
High Z
High Z
2
IH
4
3
2
30
32 31
1
3
A
A
A
A
A
A
A
A
A
A
5
29
6
5
4
3
2
1
0
12
13
14
4
Output
Disable
6
28
27
26
25
24
23
22
21
X
V
V
5
IL
CC
7
6
NC
8
7
Output
Disable
CS3
CS3
CS2
CS1/V
9
X
X
X
V
V
V
V
IH
CC
8
CS2
10
11
12
13
9
CS1/V
PP
PP
Program
V
V
D
10
11
12
13
14
O
PP
IH
CC
IN
7
NC
O
7
O
O
6
O
O
0
Program
Verify
6
V
V
V
D
5
14 15 16
18
20
17
19
O
IL
IH
IL
CC
OUT
O
4
O
GND
3
O
O
NC O
O
4 5
Program
Inhibit
1
2
3
V
X
V
V
HIGH Z
PP
IL
CC
PRODUCT SELECTION GUIDE
PARAMETER
WS57C71C-45
45 ns
WS57C71C-55
55 ns
WS57C71C-70
70 ns
Address Access Time (Max)
CS to Output Valid Time (Max)
20 ns
20 ns
30 ns
4-13
Return to Main Menu
WS57C71C
ORDERING INFORMATION
OPERATING
WSI
SPEED
PART NUMBER
(ns)
PACKAGE
TYPE
PACKAGE
DRAWING
TEMPERATURE MANUFACTURING
RANGE
PROCEDURE
WS57C71C-45TMB
WS57C71C-55CMB
WS57C71C-55DMB
WS57C71C-55TMB
WS57C71C-70TMB
45
55
55
55
70
28 Pin CERDIP, 0.3"
32 Pad CLLCC
T2
C2
D2
T2
T2
Military
Military
Military
Military
Military
MIL-STD-883C
MIL-STD-883C
MIL-STD-883C
MIL-STD-883C
MIL-STD-883C
28 Pin CERDIP, 0.6"
28 Pin CERDIP, 0.3"
28 Pin CERDIP, 0.3"
NOTE: 9. The actual part marking will not include the initials "WS."
PROGRAMMING/ALGORITHMS/ERASURE/PROGRAMMERS
REFER TO
PAGE 5-1
The WS57C71C is programmed using Algorithm D shown on page 5-9.
For complete data sheet and electrical specifications see page 2-55.
4-14
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