X24256Z-2.5 [ETC]
EEPROM ; EEPROM\n
| 型号： | X24256Z-2.5 |
| 厂家： | 
ETC |
| 描述： | EEPROM
|
| 文件： | 总18页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
256K
X24256
32K x 8 Bit
400KHz 2-Wire Serial E2PROM
FEATURES
DESCRIPTION
• 400KHz 2-Wire Serial Interface
—Schmitt Trigger Input Noise Suppression
—Output Slope Control for Ground Bounce
Noise Elimination
The X24256 is a CMOS Serial E2PROM, internally
organized 32K x 8. The device features a serial inter-
face and software protocol allowing operation on a
simple two wire bus.
• Longer Battery Life With Lower Power
—Active Read Current Less Than 1mA
—Active Write Current Less Than 3mA
—Standby Current Less Than 1µA
• 1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V Power
Supply Versions
Two device select inputs (S –S ) allow up to four
devices to share a common two wire bus.
0
1
These pins have internal pull downs, so they are read
as LOW if not connected.
A WP pin, when pulled HIGH prevents any nonvolatile
writes to the array. When not connected WP is pulled
LOW, so the device is not normally protected.
• 64 Byte Page Write Mode
—Minimizes Total Write Time Per Word
• Internally Organized 32K x 8
• Bidirectional Data Transfer Protocol
• Self-Timed Write Cycle
—Typical Write Cycle Time of 5ms
• High Reliability
Xicor E2PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
• 8-Lead XBGA
• 8-Lead SOIC
• 14-Lead TSSOP
FUNCTIONAL DIAGRAM
DATA REGISTER
Y DECODE LOGIC
SERIAL E2PROM DATA
AND ADDRESS (SDA)
COMMAND
DECODE
SCL
PAGE
DECODE
LOGIC
AND
CONTROL
LOGIC
WRITE PROTECT
CONTROL LOGIC
SERIAL E2PROM
ARRAY
32K x 8
DEVICE
SELECT
LOGIC
S1
S0
WRITE VOLTAGE
CONTROL
WP
Xicor, 2000 Patents Pending
9800-5004.1 1/31/00 EP
Characteristics subject to change without notice. 1 of 18
X24256
PIN DESCRIPTIONS
Serial Clock (SCL)
PIN NAMES
Symbol
S , S
Description
Device Select Inputs
Serial Data
The SCL input is used to clock all data into and out of
the device.
0
1
SDA
SCL
WP
Serial Data (SDA)
Serial Clock
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs.
Write Protect
Ground
V
SS
V
Supply Voltage
No Connect
CC
NC
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-
up resistor selection graph at the end of this data
sheet.
PIN CONFIGURATION
8-Lead XBGA: Top View
Device Select (S , S )
0
1
The device select inputs (S , S ) are used to set bits in
0
1
1
S
S
8
7
6
5
1
0
WP
the slave address. This allows up to four devices to
share a common bus. These inputs can be static or
actively driven. If used statically they must be tied to
VCC
2
3
4
VSS
NC
SDA
SCL
V
or V
as appropriate. If actively driven, they
SS
CC
must be driven with CMOS levels (driven to V
or
CC
V
) and they must be constant between each start
SS
and stop issued on the SDA bus. These pins have an
active pull down internally and will be sensed as low if
the pin is left unconnected.
14 Lead TSSOP
S
1
2
0
14
13
V
CC
S
1
WP
NC
12
11
10
9
NC
NC
NC
NC
Write Protect (WP)
3
4
NC
NC
WP must be constant between each start and stop
issued on the SDA bus and is always active (not
gated). The WP pin has an active pull down to disable
the write protection when the input is left floating. The
Write Protect input controls the Hardware Write Pro-
tect feature. When held LOW, Protection is disabled
and the device operates normally. When this input is
held HIGH, the device is protected, preventing
changes to any and all locations in the EEPROM array.
X24256
5
6
7
SCL
SDA
V
8
SS
8 Lead PDIP/SOIC
S
0
S
1
1
2
8
7
6
5
V
CC
WP
SCL
X24256
NC
3
4
V
SS
SDA
Characteristics subject to change without notice. 2 of 18
X24256
DEVICE OPERATION
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers, and pro-
vide the clock for both transmit and receive operations.
Therefore, the device will be considered a slave in all
applications.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
Figure 1. Data Validity
SCL
SDA
DATA STABLE
DATA
CHANGE
Figure 2. Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
Characteristics subject to change without notice. 3 of 18
X24256
Stop Condition
The device will respond with an acknowledge after rec-
ognition of a start condition and its slave address. If
both the device and a write operation have been
selected, the device will respond with an acknowledge
after the receipt of each subsequent 8-bit word.
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the standby power mode after a read
sequence. A stop condition can only be issued after
the transmitting device has released the bus.
In the read mode the device will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. If an acknowledge is not
detected, the device will terminate further data trans-
missions. The master must then issue a stop condition
to return the device to the standby power mode and
place the device into a known state.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 3.
Figure 3. Acknowledge Response From Receiver
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
DEVICE ADDRESSING
pins. If the compare is not successful, no acknowledge
is output during the ninth clock cycle and the device
returns to the standby mode.
Following a start condition, the master must output the
address of the slave it is accessing. The first four bits
of the Slave Address Byte are the device type identifier
bits. These must equal “1010”. The next bit is a “0”.
On power up the internal address is undefined, so the
first read or write operation must supply an address.
The following 2 bits are the device select bits S and
0
The word address is either supplied by the master or
obtained from an internal counter, depending on the
operation. The master must supply the two Word
Address Bytes as shown in Figure 4.
S . This allows up to 4 devices to share a single bus.
1
These bits are compared to the S and S device
0
1
select input pins. The last bit of the Slave Address
Byte defines the operation to be performed. When the
R/W bit is a one, then a read operation is selected.
When it is zero then a write operation is selected.
Refer to Figure 4. After loading the Slave Address
Byte from the SDA bus, the device compares the
device type bits with the value “1010” and the device
select bits with the status of the device select input
The internal organization of the E2 array is 512 pages
by 64 bytes per page. The page address is partially
contained in the Word Address Byte 1 and partially in
bits 7 through 6 of the Word Address Byte 0. The byte
address is contained in bits 5 through 0 of the Word
Address Byte 0. See Figure 4.
Characteristics subject to change without notice. 4 of 18
X24256
Figure 4. Device Addressing
DEVICE TYPE
IDENTIFIER
DEVICE
SELECT
1
0
1
0
0
S
S
R/W
1
0
SLAVE ADDRESS BYTE
HIGH ORDER WORD ADDRESS
0
A14 A13 A12 A11 A10 A9
A8
X24256WORD ADDRESS BYTE 1
LOW ORDER WORD ADDRESS
A7
A6
A4 A3
A2 A1
A0
A5
WORD ADDRESS BYTE 0
D7 D6 D5
D4 D3
D2 D1 D0
DATA BYTE
WRITE OPERATIONS
Byte Write
Page Write
The device is capable of a 64 byte page write opera-
tion. It is initiated in the same manner as the byte write
operation; but instead of terminating the write opera-
tion after the first data word is transferred, the master
can transmit up to sixty-three more words. The device
will respond with an acknowledge after the receipt of
each word, and then the byte address is internally
incremented by one. The page address remains con-
stant. When the counter reaches the end of the page,
it “rolls over” and goes back to the first byte of the cur-
rent page. This means that the master can write 64
bytes to the page beginning at any byte. If the master
begins writing at byte 32, and loads 64 bytes, then the
first 32 bytes are written to bytes 32 through 63, and
the last 16 words are written to bytes 0 through 31.
Afterwards, the address counter would point to byte 32.
For a write operation, the device follows “3 byte” proto-
col, consisting of one Slave Address Byte, one Word
Address Byte 1, and the Word Address Byte 0, which
gives the master access to any one of the words in the
array. Upon receipt of the Word Address Byte 0, the
device responds with an acknowledge, and waits for
the first eight bits of data. After receiving the 8 bits of
the data byte, the device again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition, at which time the
device begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress
the device inputs are disabled and the device will not
respond to any requests from the master. The SDA pin
is at high impedance. See Figure 5.
Characteristics subject to change without notice. 5 of 18
X24256
If the master writes more than 64 bytes, then the previ-
ously loaded data is overwritten by the new data, one
byte at a time.
all inputs are disabled until completion of the internal
write cycle. Refer to Figure 6 for the address, acknowl-
edge, and data transfer sequence.
The master terminates the data byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
Figure 5. Byte Write Sequence
S
SIGNALS
FROMTHE
MASTER
S
T
A
R
T
WORDADDRESS WORD ADDRESS
BYTE 1
SLAVE
ADDRESS
T
O
P
BYTE 0
DATA
SDA BUS
S 1 0 1 0 0
0
P
A
C
K
A
C
K
A
C
K
A
C
K
SIGNALS
FROMTHE
SLAVE
Figure 6. Page Write Sequence
(0≤n≤64)
S
SIGNALS
FROMTHE
MASTER
T
A
R
T
WORD ADDRESS WORDADDRESS
BYTE 1
DATA
(0)
DATA
(n)
SLAVE
ADDRESS
S
T
O
P
BYTE 0
SDA BUS
0
0
1 0 1 0
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
SIGNALS
FROMTHE
SLAVE
Stop and Write Modes
Acknowledge Polling
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the device will reset itself without
performing the write. The contents of the array will not
be affected.
The maximum write cycle time can be significantly
reduced using Acknowledge Polling. To initiate
Acknowledge Polling, the master issues a start condi-
tion followed by the Slave Address Byte for a write or
read operation. If the device is still busy with the inter-
nal write cycle, then no ACK will be returned. If the
device has completed the internal write operation, an
ACK will be returned and the host can then proceed
with the read or write operation. Refer to Figure 7.
Characteristics subject to change without notice. 6 of 18
X24256
Figure 7. Acknowledge Polling Sequence
READ OPERATIONS
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.
BYTE LOAD COMPLETED
BY ISSUING STOP.
ENTER ACK POLLING
Current Address Read
ISSUE
START
Internally, the device contains an address counter that
maintains the address of the last word read or written
incremented by one. After a read operation from the
last address in the array, the counter will “roll over” to
the first address in the array. After a write operation to
the last address in a given page, the counter will “roll
over” to the first address on the same page.
ISSUE SLAVE
ADDRESS BYTE
(READ OR WRITE)
ISSUE STOP
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The
master terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Refer to Figure 8 for
the address, acknowledge, and data transfer
sequence.
ACK
RETURNED?
NO
YES
HIGH
VOLTAGE
CYCLE COMPLETE.
CONTINUE
NO
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
SEQUENCE?
YES
CONTINUE NORMAL
READ OR WRITE
ISSUE STOP
COMMAND SEQUENCE
Figure 8. Current Address Read Sequence
S
SIGNALS
FROM THE
MASTER
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
PROCEED
SDA BUS
S 1 0 1 0 0
1
P
A
C
K
SIGNALS
FROM THE
SLAVE
DATA
Characteristics subject to change without notice. 7 of 18
X24256
Random Read
The next Current Address Read operation will read
from the newly loaded address.
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “Dummy” write operation.
The master issues the start condition and the Slave
Address Byte with the R/W bit low, receives an
acknowledge, then issues the Word Address Byte 1,
receives another acknowledge, then issues the Word
Address Byte 0. After the device acknowledges receipt
of the Word Address Byte 0, the master issues another
start condition and the Slave Address Byte with the R/
W bit set to one. This is followed by an acknowledge
and then eight bits of data from the device. The master
terminates the read operation by not responding with
an acknowledge and then issuing a stop condition.
Refer to Figure 9 for the address, acknowledge, and
data transfer sequence.
Sequential Read
Sequential reads can be initiated as either a current
address read or random read. The first Data Byte is
transmitted as with the other modes; however, the
master now responds with an acknowledge, indicating
it requires additional data. The device continues to out-
put data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1.
The address counter for read operations increments
through all byte addresses, allowing the entire memory
contents to be read during one operation. At the end of
the address space the counter “rolls over” to address
0000h and the device continues to output data for
each acknowledge received. Refer to Figure 10 for the
acknowledge and data transfer sequence.
The device will perform a similar operation called “Set
Current Address” if a stop is issued instead of the
second start shown in Figure 9. The device will go into
standby mode after the stop and all bus activity will be
ignored until a start is detected. The effect of this oper-
ation is that the new address is loaded into the
address counter, but no data is output by the device.
Figure 9. Random Read Sequence
S
S
SIGNALS
FROMTHE
MASTER
T
A
R
T
A
R
WORDADDRESS WORD ADDRESS
SLAVE
ADDRESS
S
T
O
P
SLAVE
ADDRESS
BYTE 1
BYTE 0
T
T
1
SDA BUS
S 1 0 1 0 0
0
S
P
A
C
K
A
C
K
A
C
K
A
C
K
SIGNALS
FROMTHE
SLAVE
DATA
Figure 10. Sequential Read Sequence
SIGNALS
FROM THE
MASTER
A
C
K
A
C
K
A
C
K
S
T
O
P
SLAVE
ADDRESS
SDA BUS
1
P
A
C
K
SIGNALS
FROM THE
SLAVE
DATA
(1)
DATA
(2)
DATA
(n–1)
DATA
(n)
(n is any integer greater than 1)
Characteristics subject to change without notice. 8 of 18
X24256
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this speci-
fication is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
X24256 ......................................... –65°C to +135°C
Storage Temperature........................ –65°C to +150°C
Voltage on any Pin with Respect
to V ......................................................–1V to +7V
SS
D.C. Output Current.............................................. 5mA
Lead Temperature
(Soldering, 10 seconds)................................. 300°C
Supply Voltage
Limits
RECOMMENDED OPERATING CONDITIONS
X24256
4.5V to 5.5V
2.5V to 5.5V
1.8V to 3.6V
Temperature
Min.
0°C
Max.
+70°C
+85°C
X24256–2.5
X24256–1.8
Commercial
Industrial
–40°C
D.C. OPERATING CHARACTERISTICS
equals the range indicated for each device type, unless otherwise stated.
V
CC
V
= 1.8 to 3.6V
V
= 2.5 to 5.5V
V = 4.5 to 5.5V
CC
CC
CC
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Units
Test Conditions
Active Supply
Current (Read)
0.5
1
1
mA
V = V X 0.1
IL
CC
I
CC1
V
= V X 0.9
IH
CC
f
= 400KHz
Active Supply
Current (Write)
1.5
1
3
1
3
1
mA
mA
SCL
I
CC2
SDA = Open
V = V X 0.1
IL
CC
V
= V X 0.9
= 400KHz
Standby
Current AC
(2)
IH
CC
I
SB1
f
SCL
SDA = Open
Standby
Voltage (Test)
V – 0.1
CC
V – 0.2
CC
V – 0.3
CC
V
V
SB
1
1
10
mA
V
= V = V
SCL SB,
Standby
Current DC
SDA
Others = GND or SB
(2)
I
SB2
V
Input Leakage
Current
10
10
10
10
10
10
mA
mA
V
I
V
= GND to V
CC
IN
LI
V
= GND to V
CC
OutputLeakage
Current
SDA
Device is in Standby(2)
I
LO
Input LOW
Voltage
–0.5
V
x 0.3
–0.5
V
x 0.3
–0.5
V
x 0.3
(3)
CC
CC
CC
V
lL
Input HIGH
Voltage
(3)
V
x 0.7
V
+ 0.5
V
x 0.7
V
+ 0.5
V
x 0.7
V
+ 0.5
V
V
V
CC
CC
CC
CC
CC
CC
IH
Schmitt
Trigger Input
Hysteresis
0.2
0.2
0.2
V
HYS
Fixed input level
V
related level
V
x 0.05
V
x 0.05
V
x 0.05
V
V
CC
CC
CC
CC
Output LOW
Voltage
I
= 3mA
OL
V
0.4
0.4
0.4
OL
Characteristics subject to change without notice. 9 of 18
X24256
CAPACITANCE T = +25°C, f = 1MHz, V
= 5V
A
CC
Symbol
Parameter
Input/Output Capacitance (SDA)
Input Capacitance (S , S , SCL, WP)
Max.
Units
Test Conditions
(3)
C
V
= 0V
= 0V
8
pF
I/O
I/O
(3)
C
V
6
pF
IN
0
1
IN
Notes:
(1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave Address Byte are
incorrect; 200ns after a stop ending a read operation; or t after a stop ending a write operation.
WC
(2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; t
after a stop that intiates a high voltage
WC
cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
(3) VIL Min. and VIH Max. are for reference only and are not tested.
A.C. CONDITIONS OF TEST
EQUIVALENT A.C. LOAD CIRCUIT
V
x 0.1 to V x 0.9
Input Pulse Levels
CC
CC
5V
Input Rise and Fall Times
10ns
for V = 0.4V
OL
1.53KΩ
Input and Output Timing
Levels
I
= 3mA
OL
V
X 0.5
CC
OUTPUT
Output Load
Standard Output Load
100pF
A.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions, unless otherwise stated.
Read & Write Cycle Limits
V
1.8V
V
2.5V
CC
CC
Symbol
Parameter
SCL Clock Frequency
Min.
0
Max.
Min.
0
Max.
Units
KHz
ns
f
t
t
100
n/a
3.5
400
SCL
Pulse width Suppression Time at Inputs
SCL LOW to SDA Data Out Valid
n/a
0.3
50
IN
0.1
0.9
µs
AA
Time the Bus Must Be Free Before a
New Transmission Can Start
t
4.7
1.3
µs
BUF
t
t
t
t
t
t
t
t
t
Clock LOW Period
4.7
4.0
4.7
4.0
250
0
1.3
µs
µs
µs
µs
ns
µs
µs
ns
ns
LOW
Clock HIGH Period
0.6
HIGH
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
0.6
SU:STA
HD:STA
SU:DAT
HD:DAT
SU:STO
DH
0.6
100
Data In Hold Time
0
0.6
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
4.7
300
50
20+ .1Cb(3)
1000
300
R
Characteristics subject to change without notice. 10 of 18
X24256
A.C. OPERATING CHARACTERISTICS (CONTINUED)
(Over the recommended operating conditions, unless otherwise stated.
Read & Write Cycle Limits
V
1.8V
V
2.5V
CC
CC
Symbol
Parameter
SDA and SCL Fall Time
Min.
Max.
Min.
Max.
Units
ns
20+ .1Cb(3)
t
t
t
300
300
F
S0, S1, and WP Setup Time
S0, S1, and WP Hold Time
Capacitive load for each bus line
0.4
0
0.6
0
ns
SU:S0, S1, WP
HD:S0, S1, WP
ns
Cb
400
400
pF
POWER-UP TIMING(4)
Symbol
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max.
Units
ms
t
1
5
PUR
t
ms
PUW
Notes:
(4)
t
and t
are the delays required from the time V
is stable until the specified operation can be initiated. These parameters are periodically
PUR
PUW
CC
sampled and not 100% tested.
(5) Typical values are for T = 25°C and nominal supply voltage (5V), Cb = total capacitance of one bus line in pF.
A
Bus Timing
t
t
t
t
HIGH
LOW
R
F
SCL
t
t
t
t
t
SU:STA
HD:STA
HD:DAT
SU:DAT
SU:STO
SDAIN
t
t
t
AA
DH
BUF
SDAOUT
Characteristics subject to change without notice. 11 of 18
X24256
S0, S1, and WP Pin Timing
SCL
Clk 1
Clk 9
Slave Address Byte
SDAIN
t
t
HD: S0, S1, WP
SU: S0, S1, WP
S0, S1, and WP
Write Cycle Limits
Symbol
Parameter
Write Cycle Time
Min.
Typ.
Max.
10
Units
(6)
T
—
5
ms
WC
Notes:
(6)
t
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device
WC
requires to automatically complete the internal write operation.
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write
cycle. During the write cycle, the X24256 bus interface circuits are disabled, SDA is allowed to remain HIGH, and
the device does not respond to its slave address.
Write CycleTiming
SCL
ACK
SDA
8th BIT
WORD n
t
WC
STOP
CONDITION
START
CONDITION
Characteristics subject to change without notice. 12 of 18
X24256
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
120
V
CC MAX
R
=
Must be
steady
Will be
steady
MIN
I
100
80
OL MIN
t
R
R
=
MAX
May change
from Low to
High
Will change
from Low to
High
C
BUS
MAX.
60
40
20
0
RESISTANCE
May change
from High to
Low
Will change
from High to
Low
MIN.
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
RESISTANCE
20 40 60 80
0
100 120
N/A
Center Line
is High
Impedance
BUS CAPACITANCE (pF)
Characteristics subject to change without notice. 13 of 18
X24256
PACKAGING INFORMATION
14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.002 (.05)
.0118 (.30)
.006 (.15)
.010 (.25)
Gage Plane
0° Ð 8°
Seating Plane
.019 (.50)
.029 (.75)
DetailA (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 14 of 18
X24256
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7∞
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
0.050" TYPICAL
X 45∞
0.050"
TYPICAL
0∞– 8∞
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
TYPICAL
8 PLACES
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 15 of 18
X24256
PACKAGING INFORMATION
8-LEAD PLASTIC, 0.200” WIDE SMALL OUTLINE
GULLWING PACKAGE TYP “A” (EIAJ SOIC)
0.020 (.508)
0.012 (.305)
.213 (5.41)
.205 (5.21)
.330 (8.38)
.300 (7.62)
PIN 1 ID
.050 (1.27) BSC
.212 (5.38)
.203 (5.16)
.080 (2.03)
.070 (1.78)
.013 (.330)
.004 (.102)
0
8
REF
.010 (.254)
.007 (.178)
.035 (.889)
.020 (.508)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
Characteristics subject to change without notice. 16 of 18
X24256
PACKAGING INFORMATION
8-Lead XBGA
8-Lead XBGA
Complete Part Number
X24256: Bottom View
Top Mark
A1
X24256Z-2.5
X24256ZI-2.5
X24256B-2.5
X24256BI-2.5
XAAI
XAAU
XAAI
XAAU
S1
S0
WP
8-Lead XBGA: Top View
PIN 1
V
CC
.079”
C
S1
WP
8
1
V
VCC
SDA
SCL
SO
SS
7
6
5
E
2
3
4
.137”
VSS
SDA
SCL
NC
e
NC
F
D
D
Dwg
Symbol
8L XBGA
A1
Contact Factory
Contact Factory
Contact Factory
Contact Factory
Contact Factory
Contact Factory
Contact Factory
A
A1
C
D
E
A
C
ALL DIMENSIONS IN µM (to convert to inches, 1µm = 3.94 x 10-5 inch)
ALL DIMENSIONS ARE TYPICAL VALUES
e
F
Characteristics subject to change without notice. 17 of 18
X24256
ORDERING INFORMATION
X24256
X
X
-X
V
Range
CC
Device
Blank = 5V ±10%
2.5 = 2.5V to 5.5V
1.8 = 1.8V to 3.6V
Temperature Range
Blank = 0°C to +70°C
I = –40°C to +85°C
Package
X24256
Z = 8-Lead XBGA
V14 = 14-Lead TSSOP
S8 = 8-Lead SOIC, 150 mil wide, JEDEC
A8 = 8-Lead SOIC, 200 mil wide, EIAJ
B = 8-Lead XBGA
PART MARK CONVENTION
XBGA PACKAGE
TSSOP/SOIC
X24256
Complete Part Number Top Mark
V14 = 14-Lead TSSOP
S8 = 8-Lead SOIC (JEDEC)
A8 = 8-Lead SOIC (EIAJ)
X
X24256Z - 2.5
X24256ZI - 2.5
X24256B - 2.5
X24256BI - 2.5
XAAI
XAAU
XAAI
X
XAAU
Blank = 4.5V to 5.5V, 0°C to +70°C
I = 4.5V to 5.5V, –40°C to +85°C
J = 2.5V to 5.5V, 0°C to +70°C
K = 2.5V to 5.5V, –40°C to +85°C
AG = 1.8V to 3.6V, 0°C to +70°C
AH = 1.8V to 3.6V, –40°C to +85°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express,
statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes
no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and
without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor andthe Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137;
5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and
correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1.
Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2.
A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 18 of 18
相关型号：
X24256ZI
EEPROMWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
X24256ZI-1.8
EEPROMWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
X24256ZI-2.5
EEPROMWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
X24257
400kHz 2-Wire Serial EEPROM with Block LockWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XICOR
X24257A8
EEPROM, 32KX8, Serial, CMOS, PDSO8, 0.200 INCH, EIAJ, PLASTIC, SOIC-8Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XICOR
X24257A8-1.8
EEPROM,Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XICOR
X24257A8-2.5
400kHz 2-Wire Serial EEPROM with Block LockWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XICOR
X24257A8AG
EEPROM, 32KX8, Serial, CMOS, PDSO8, 0.200 INCH, EIAJ, PLASTIC, SOIC-8Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XICOR
X24257A8AH
EEPROM, 32KX8, Serial, CMOS, PDSO8, 0.200 INCH, EIAJ, PLASTIC, SOIC-8Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XICOR
X24257A8I-1.8
EEPROM,Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XICOR
X24257A8I-2.5
400kHz 2-Wire Serial EEPROM with Block LockWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XICOR
X24257B-2.5
400kHz 2-Wire Serial EEPROM with Block LockWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XICOR
©2020 ICPDF网 联系我们和版权申明