XC5206-3VQ100I_技术文档

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XC5200 Series

R

Field Programmable Gate Arrays

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7*

November 5, 1998 (Version 5.2)

Product Specification

-

Footprint compatibility in common packages within

the XC5200 Series and with the XC4000 Series

Over 150 device/package combinations, including

advanced BGA, TQ, and VQ packaging available

Features

• Low-cost, register/latch rich, SRAM based

reprogrammable architecture

-

0.5µm three-layer metal CMOS process technology

256 to 1936 logic cells (3,000 to 23,000 “gates”)

Price competitive with Gate Arrays

•

Fully Supported by Xilinx Development System

-

Automatic place and route software

Wide selection of PC and Workstation platforms

Over 100 3rd-party Alliance interfaces

•

System Level Features

-

System performance beyond 50 MHz

6 levels of interconnect hierarchy

VersaRing^™I/O Interface for pin-locking

Dedicated carry logic for high-speed arithmetic

functions

Supported by shrink-wrap Foundation software

Description

The XC5200 Field-Programmable Gate Array Family is

engineered to deliver low cost. Building on experiences

gained with three previous successful SRAM FPGA fami-

lies, the XC5200 family brings a robust feature set to pro-

grammable logic design. The VersaBlock^™logic module,

the VersaRing I/O interface, and a rich hierarchy of inter-

connect resources combine to enhance design flexibility

and reduce time-to-market. Complete support for the

XC5200 family is delivered through the familiar Xilinx soft-

ware environment. The XC5200 family is fully supported on

popular workstation and PC platforms. Popular design

entry methods are fully supported, including ABEL, sche-

matic capture, VHDL, and Verilog HDL synthesis. Design-

ers utilizing logic synthesis can use their existing tools to

design with the XC5200 devices.

-

Cascade chain for wide input functions

Built-in IEEE 1149.1 JTAG boundary scan test

circuitry on all I/O pins

-

Internal 3-state bussing capability

Four dedicated low-skew clock or signal distribution

nets

•

Versatile I/O and Packaging

7

-

Innovative VersaRing^™I/O interface provides a high

logic cell to I/O ratio, with up to 244 I/O signals

Programmable output slew-rate control maximizes

performance and reduces noise

Zero Flip-Flop hold time for input registers simplifies

system timing

Independent Output Enables for external bussing

.

Table 1: XC5200 Field-Programmable Gate Array Family Members

Device

XC5202

XC5204

480

XC5206

784

XC5210

1,296

XC5215

1,936

Logic Cells

256

3,000

2,000 - 3,000

8 x 8

Max Logic Gates

Typical Gate Range

VersaBlock Array

CLBs

6,000

4,000 - 6,000

10 x 12

120

10,000

16,000

23,000

6,000 - 10,000 10,000 - 16,000 15,000 - 23,000

14 x 14

196

18 x 18

324

22 x 22

484

64

Flip-Flops

256

480

784

1,296

196

1,936

244

I/Os

84

124

148

TBUFs per Longline

10

14

16

20

24

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XC5200 Series Field Programmable Gate Arrays

Table 2: Xilinx Field-Programmable Gate Array

Families

XC5200 Family Compared to

XC4000/Spartan™ and XC3000

Series

For readers already familiar with the XC4000/Spartan and

XC3000 FPGA Families, this section describes significant

differences between them and the XC5200 family. Unless

otherwise indicated, comparisons refer to both

XC4000/Spartan and XC3000 devices.

Parameter

XC5200 Spartan XC4000 XC3000

CLB function

generators

4

3

2

CLB inputs

20

12

9

5

2

CLB outputs

4

Global buffers

User RAM

4

8

2

Configurable Logic Block (CLB) Resources

Each XC5200 CLB contains four independent 4-input func-

tion generators and four registers, which are configured as

four independent Logic Cells™ (LCs). The registers in each

XC5200 LC are optionally configurable as edge-triggered

D-type flip-flops or as transparent level-sensitive latches.

no

yes

no

yes

no

yes

no

yes

Edge decoders

Cascade chain

Fast carry logic

Internal 3-state

Boundary scan

Slew-rate control

no

yes

no

The XC5200 CLB includes dedicated carry logic that pro-

vides fast arithmetic carry capability. The dedicated carry

logic may also be used to cascade function generators for

implementing wide arithmetic functions.

yes

XC4000 family: XC5200 devices have no wide edge

decoders. Wide decoders are implemented using cascade

logic. Although sacrificing speed for some designs, lack of

wide edge decoders reduces the die area and hence cost

of the XC5200.

Routing Resources

The XC5200 family provides a flexible coupling of logic and

local routing resources called the VersaBlock. The XC5200

VersaBlock element includes the CLB, a Local Interconnect

Matrix (LIM), and direct connects to neighboring Versa-

Blocks.

XC4000/Spartan family: XC5200 dedicated carry logic

differs from that of the XC4000/Spartan family in that the

sum is generated in an additional function generator in the

adjacent column. This design reduces XC5200 die size and

hence cost for many applications. Note, however, that a

loadable up/down counter requires the same number of

function generators in both families. XC3000 has no dedi-

cated carry.

The XC5200 provides four global buffers for clocking or

high-fanout control signals. Each buffer may be sourced by

means of its dedicated pad or from any internal source.

Each XC5200 TBUF can drive up to two horizontal and two

vertical Longlines. There are no internal pull-ups for

XC5200 Longlines.

XC4000/Spartan family: XC5200 lookup tables are opti-

mized for cost and hence cannot implement RAM.

Input/Output Block (IOB) Resources

Configuration and Readback

The XC5200 family maintains footprint compatibility with

the XC4000 family, but not with the XC3000 family.

The XC5200 supports a new configuration mode called

Express mode.

To minimize cost and maximize the number of I/O per Logic

Cell, the XC5200 I/O does not include flip-flops or latches.

XC4000/Spartan family: The XC5200 family provides a

global reset but not a global set.

For high performance paths, the XC5200 family provides

direct connections from each IOB to the registers in the

adjacent CLB in order to emulate IOB registers.

XC5200 devices use a different configuration process than

that of the XC3000 family, but use the same process as the

XC4000 and Spartan families.

Each XC5200 I/O Pin provides a programmable delay ele-

ment to control input set-up time. This element can be used

to avoid potential hold-time problems. Each XC5200 I/O

Pin is capable of 8-mA source and sink currents.

XC3000 family: Although their configuration processes dif-

fer, XC5200 devices may be used in daisy chains with

XC3000 devices.

XC3000 family: The XC5200 PROGRAM pin is a sin-

gle-function input pin that overrides all other inputs. The

PROGRAM pin does not exist in XC3000.

IEEE 1149.1-type boundary scan is supported in each

XC5200 I/O.

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XC5200 Series Field Programmable Gate Arrays

XC3000 family: XC5200 devices support an additional pro-

gramming mode: Peripheral Synchronous.

Input/Output Blocks (IOBs)

XC3000 family: The XC5200 family does not support

Power-down, but offers a Global 3-state input that does not

reset any flip-flops.

VersaRing

XC3000 family: The XC5200 family does not provide an

on-chip crystal oscillator amplifier, but it does provide an

internal oscillator from which a variety of frequencies up to

12 MHz are available.

GRM

Versa-

Block

Versa-

Block

Versa-

Block

GRM

Architectural Overview

Versa-

Block

Versa-

Block

Versa-

Block

Figure 1 presents a simplified, conceptual overview of the

XC5200 architecture. Similar to conventional FPGAs, the

XC5200 family consists of programmable IOBs, program-

mable logic blocks, and programmable interconnect. Unlike

other FPGAs, however, the logic and local routing

resources of the XC5200 family are combined in flexible

VersaBlocks (Figure 2). General-purpose routing connects

to the VersaBlock through the General Routing Matrix

(GRM).

GRM

Versa-

Block

Versa-

Block

Versa-

Block

VersaRing

X4955

Figure 1: XC5200 Architectural Overview

VersaBlock: Abundant Local Routing Plus

Versatile Logic

GRM

4

The basic logic element in each VersaBlock structure is the

Logic Cell, shown in Figure 3. Each LC contains a 4-input

function generator (F), a storage device (FD), and control

logic. There are five independent inputs and three outputs

to each LC. The independence of the inputs and outputs

allows the software to maximize the resource utilization

within each LC. Each Logic Cell also contains a direct

feedthrough path that does not sacrifice the use of either

the function generator or the register; this feature is a first

for FPGAs. The storage device is configurable as either a D

flip-flop or a latch. The control logic consists of carry logic

for fast implementation of arithmetic functions, which can

also be configured as a cascade chain allowing decode of

very wide input functions.

24

7

TS

CLB

LC3

4

LC2

LC1

LC0

4

LIM

4

Direct Connects

X5707

Figure 2: VersaBlock

CO

DO

DI

D

Q

F4

F3

FD

F

F2

F1

X

CI

CE CK

CLR

X4956

Figure 3: XC5200 Logic Cell (Four LCs per CLB)

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XC5200 Series Field Programmable Gate Arrays

The XC5200 CLB consists of four LCs, as shown in

Figure 4. Each CLB has 20 independent inputs and 12

independent outputs. The top and bottom pairs of LCs can

be configured to implement 5-input functions. The chal-

lenge of FPGA implementation software has always been

to maximize the usage of logic resources. The XC5200

family addresses this issue by surrounding each CLB with

two types of local interconnect — the Local Interconnect

Matrix (LIM) and direct connects. These two interconnect

resources, combined with the CLB, form the VersaBlock,

represented in Figure 2.

The LIM provides 100% connectivity of the inputs and out-

puts of each LC in a given CLB. The benefit of the LIM is

that no general routing resources are required to connect

feedback paths within a CLB. The LIM connects to the

GRM via 24 bidirectional nodes.

The direct connects allow immediate connections to neigh-

boring CLBs, once again without using any of the general

interconnect. These two layers of local routing resource

improve the granularity of the architecture, effectively mak-

ing the XC5200 family a “sea of logic cells.” Each

Versa-Block has four 3-state buffers that share a common

enable line and directly drive horizontal and vertical Lon-

glines, creating robust on-chip bussing capability. The

VersaBlock allows fast, local implementation of logic func-

tions, effectively implementing user designs in a hierarchi-

cal fashion. These resources also minimize local routing

congestion and improve the efficiency of the general inter-

connect, which is used for connecting larger groups of

logic. It is this combination of both fine-grain and

coarse-grain architecture attributes that maximize logic uti-

lization in the XC5200 family. This symmetrical structure

takes full advantage of the third metal layer, freeing the

placement software to pack user logic optimally with mini-

mal routing restrictions.

CO

LC3

DO

DI

D

Q

X

F4

F3

F2

F1

FD

F

LC2

DO

Q

DI

VersaRing I/O Interface

The interface between the IOBs and core logic has been

redesigned in the XC5200 family. The IOBs are completely

decoupled from the core logic. The XC5200 IOBs contain

dedicated boundary-scan logic for added board-level test-

ability, but do not include input or output registers. This

approach allows a maximum number of IOBs to be placed

around the device, improving the I/O-to-gate ratio and

decreasing the cost per I/O. A “freeway” of interconnect

cells surrounding the device forms the VersaRing, which

provides connections from the IOBs to the internal logic.

These incremental routing resources provide abundant

connections from each IOB to the nearest VersaBlock, in

addition to Longline connections surrounding the device.

The VersaRing eliminates the historic trade-off between

high logic utilization and pin placement flexibility. These

incremental edge resources give users increased flexibility

in preassigning (i.e., locking) I/O pins before completing

their logic designs. This ability accelerates time-to-market,

since PCBs and other system components can be manu-

factured concurrent with the logic design.

F4

F3

F2

F1

X

LC1

DO

Q

DI

F4

F3

F2

F1

X

LC0

DO

Q

DI

D

F4

F3

F2

F1

General Routing Matrix

The GRM is functionally similar to the switch matrices

found in other architectures, but it is novel in its tight cou-

pling to the logic resources contained in the VersaBlocks.

Advanced simulation tools were used during the develop-

ment of the XC5200 architecture to determine the optimal

level of routing resources required. The XC5200 family

contains six levels of interconnect hierarchy — a series of

X

CI

CE CK

CLR

X4957

Figure 4: Configurable Logic Block

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XC5200 Series Field Programmable Gate Arrays

single-length lines, double-length lines, and Longlines all

routed through the GRM. The direct connects, LIM, and

logic-cell feedthrough are contained within each

Versa-Block. Throughout the XC5200 interconnect, an effi-

cient multiplexing scheme, in combination with three layer

metal (TLM), was used to improve the overall efficiency of

silicon usage.

Detailed Functional Description

Configurable Logic Blocks (CLBs)

Figure 4 shows the logic in the XC5200 CLB, which con-

sists of four Logic Cells (LC[3:0]). Each Logic Cell consists

of an independent 4-input Lookup Table (LUT), and a

D-Type flip-flop or latch with common clock, clock enable,

and clear, but individually selectable clock polarity. Addi-

tional logic features provided in the CLB are:

Performance Overview

The XC5200 family has been benchmarked with many

designs running synchronous clock rates beyond 66 MHz.

The performance of any design depends on the circuit to be

implemented, and the delay through the combinatorial and

sequential logic elements, plus the delay in the intercon-

nect routing. A rough estimate of timing can be made by

assuming 3-6 ns per logic level, which includes direct-con-

nect routing delays, depending on speed grade. More

accurate estimations can be made using the information in

the Switching Characteristic Guideline section.

• An independent 5-input LUT by combining two 4-input

LUTs.

• High-speed carry propagate logic.

• High-speed pattern decoding.

• High-speed direct connection to flip-flop D-inputs.

•

Individual selection of either a transparent,

level-sensitive latch or a D flip-flop.

Four 3-state buffers with a shared Output Enable.

5-Input Functions

Taking Advantage of Reconfiguration

Figure 5 illustrates how the outputs from the LUTs from

LC0 and LC1 can be combined with a 2:1 multiplexer

(F5_MUX) to provide a 5-input function. The outputs from

the LUTs of LC2 and LC3 can be similarly combined.

FPGA devices can be reconfigured to change logic function

while resident in the system. This capability gives the sys-

tem designer a new degree of freedom not available with

any other type of logic.

Hardware can be changed as easily as software. Design

updates or modifications are easy, and can be made to

products already in the field. An FPGA can even be recon-

figured dynamically to perform different functions at differ-

ent times.

7

CO

DO

DI

Q

D

FD

F4

F3

F2

F1

I1

I2

I3

I4

F

X

Reconfigurable logic can be used to implement system

self-diagnostics, create systems capable of being reconfig-

ured for different environments or operations, or implement

multi-purpose hardware for a given application. As an

added benefit, using reconfigurable FPGA devices simpli-

fies hardware design and debugging and shortens product

time-to-market.

LC1

DO

F5_MUX

out

DI

I5

D

Q

Qout

FD

F4

F3

F2

F1

F

X

LC0

CI

CE CK

CLR

5-Input Function

X5710

Figure 5: Two LUTs in Parallel Combined to Create a

5-input Function

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XC5200 Series Field Programmable Gate Arrays

carry out

CO

carry3

CO

A3

or

B3

DO

DI

Q

D

FD

CY_MUX

F4

F3

F2

F1

F3

F2

F1

A3 and B3

to any two

XOR

half sum3

carry2

sum3

sum2

sum1

X

LC3

DO

LC3

A2

or

B2

DO

DI

D

Q

D

Q

CY_MUX

FD

F4

F3

F2

F1

F4

F3

F2

F1

A2 and B2

to any two

XOR

half sum2

carry1

X

LC2

DO

LC2

A1

or

B1

DI

DO

DI

D

Q

D

Q

FD

F4

F3

F2

F1

CY_MUX

F4

F3

F2

F1

A1 and B1

to any two

XOR

half sum1

carry0

X

LC1

DO

LC1

DO

A0

or

DI

D

Q

B0

Q

D

FD

CY_MUX

FD

F4

F3

F2

F1

F4

F3

F2

F1

A0 and B0

to any two

XOR

half sum0

sum0

X

CI

LC0

CE CK

CLR

CK

CI

CE

CLR LC0

carry in

0

CY_MUX

Initialization of

carry chain (One Logic Cell)

F=0

X5709

Figure 6: XC5200 CY_MUX Used for Adder Carry Propagate

which also generates the half-sum for the four-bit adder. An

adjacent CLB is responsible for XORing the half-sum with

the corresponding carry-out. Thus an adder or counter

requires two LCs per bit. Notice that the carry chain

requires an initialization stage, which the XC5200 family

accomplishes using the carry initialize (CY_INIT) macro

and one additional LC. The carry chain can propagate ver-

tically up a column of CLBs.

Carry Function

The XC5200 family supports a carry-logic feature that

enhances the performance of arithmetic functions such as

counters, adders, etc. A carry multiplexer (CY_MUX) sym-

bol is used to indicate the XC5200 carry logic. This symbol

represents the dedicated 2:1 multiplexer in each LC that

performs the one-bit high-speed carry propagate per logic

cell (four bits per CLB).

The XC5200 library contains a set of Relationally-Placed

Macros (RPMs) and arithmetic functions designed to take

advantage of the dedicated carry logic. Using and modify-

ing these macros makes it much easier to implement cus-

While the carry propagate is performed inside the LC, an

adjacent LC must be used to complete the arithmetic func-

tion. Figure 6 represents an example of an adder function.

The carry propagate is performed on the CLB shown,

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XC5200 Series Field Programmable Gate Arrays

tomized RPMs, freeing the designer from the need to

become an expert on architectures.

results or other incoming data in flip-flops, and connect

their outputs to the interconnect network as well. The CLB

storage elements can also be configured as latches.

cascade out

Table 3: CLB Storage Element Functionality

(active rising edge is shown)

CO

DO

Mode

CK

CE

CLR

D

Q

DI

out

Q

D

Power-Up or

GR

X

0

FD

CY_MUX

A15

A14

A13

A12

F4

F3

F2

F1

X

__/

0

X

1*

X

1

X

D

X

D

X

0

AND

Flip-Flop

0*

D

Q

D

Q

X

LC3

DO

DI

1

1*

0

Latch

Both

D

Q

0

FD

CY_MUX

A11

A10

A9

F4

F3

F2

F1

X

AND

Legend:

X

__/

0*

Don’t care

Rising edge

Input is Low or unconnected (default value)

Input is High or unconnected (default value)

A8

LC2

DO

DI

1*

D

Q

FD

CY_MUX

A7

A6

A5

A4

F4

F3

F2

F1

Data Inputs and Outputs

AND

The source of a storage element data input is programma-

ble. It is driven by the function F, or by the Direct In (DI)

block input. The flip-flops or latches drive the Q CLB out-

puts.

X

LC1

DO

DI

7

Q

D

FD

CY_MUX

Four fast feed-through paths from DI to DO are available,

as shown in Figure 4. This bypass is sometimes used by

the automated router to repower internal signals. In addi-

tion to the storage element (Q) and direct (DO) outputs,

there is a combinatorial output (X) that is always sourced

by the Lookup Table.

A3

A2

A1

A0

F4

F3

F2

F1

AND

X

LC0

CK

CI

CE

CLR

cascade in

CY_MUX

Initialization of

The four edge-triggered D-type flip-flops or level-sensitive

latches have common clock (CK) and clock enable (CE)

inputs. Any of the clock inputs can also be permanently

enabled. Storage element functionality is described in

Table 3.

F=0

carry chain (One Logic Cell)

X5708

Figure 7: XC5200 CY_MUX Used for Decoder Cascade

Logic

Clock Input

Cascade Function

The flip-flops can be triggered on either the rising or falling

clock edge. The clock pin is shared by all four storage ele-

ments with individual polarity control. Any inverter placed

on the clock input is automatically absorbed into the CLB.

Each CY_MUX can be connected to the CY_MUX in the

adjacent LC to provide cascadable decode logic. Figure 7

illustrates how the 4-input function generators can be con-

figured to take advantage of these four cascaded

CY_MUXes. Note that AND and OR cascading are specific

cases of a general decode. In AND cascading all bits are

decoded equal to logic one, while in OR cascading all bits

are decoded equal to logic zero. The flexibility of the LUT

achieves this result. The XC5200 library contains gate

macros designed to take advantage of this function.

Clock Enable

The clock enable signal (CE) is active High. The CE pin is

shared by the four storage elements. If left unconnected

for any, the clock enable for that storage element defaults

to the active state. CE is not invertible within the CLB.

Clear

CLB Flip-Flops and Latches

An asynchronous storage element input (CLR) can be used

to reset all four flip-flops or latches in the CLB. This input

The CLB can pass the combinatorial output(s) to the inter-

connect network, but can also store the combinatorial

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XC5200 Series Field Programmable Gate Arrays

can also be independently disabled for any flip-flop. CLR is

active High. It is not invertible within the CLB.

Three-State Buffers

The XC5200 family has four dedicated Three-State Buffers

(TBUFs, or BUFTs in the schematic library) per CLB (see

Figure 9). The four buffers are individually configurable

through four configuration bits to operate as simple

non-inverting buffers or in 3-state mode. When in 3-state

mode the CLB output enable (TS) control signal drives the

enable to all four buffers. Each TBUF can drive up to two

horizontal and/or two vertical Longlines. These 3-state buff-

ers can be used to implement multiplexed or bidirectional

buses on the horizontal or vertical longlines, saving logic

resources.

STARTUP

GR

GTS

PAD

Q2

Q3

Q1Q4

IBUF

DONEIN

CLK

X9009

Figure 8: Schematic Symbols for Global Reset

Global Reset

The 3-state buffer enable is an active-High 3-state (i.e. an

active-Low enable), as shown in Table 4.

A separate Global Reset line clears each storage element

during power-up, reconfiguration, or when a dedicated

Reset net is driven active. This global net (GR) does not

compete with other routing resources; it uses a dedicated

distribution network.

Table 4: Three-State Buffer Functionality

IN

X

T

1

0

OUT

Z

GR can be driven from any user-programmable pin as a

global reset input. To use this global net, place an input pad

and input buffer in the schematic or HDL code, driving the

GR pin of the STARTUP symbol. (See Figure 9.) A specific

pin location can be assigned to this input using a LOC

attribute or property, just as with any other user-program-

mable pad. An inverter can optionally be inserted after the

input buffer to invert the sense of the Global Reset signal.

Alternatively, GR can be driven from any internal node.

IN

Another 3-state buffer with similar access is located near

each I/O block along the right and left edges of the array.

The longlines driven by the 3-state buffers have a weak

keeper at each end. This circuit prevents undefined float-

ing levels. However, it is overridden by any driver. To

ensure the longline goes high when no buffers are on, add

an additional BUFT to drive the output High during all of the

previously undefined states.

Using FPGA Flip-Flops and Latches

Figure 10 shows how to use the 3-state buffers to imple-

ment a multiplexer. The selection is accomplished by the

buffer 3-state signal.

The abundance of flip-flops in the XC5200 Series invites

pipelined designs. This is a powerful way of increasing per-

formance by breaking the function into smaller subfunc-

tions and executing them in parallel, passing on the results

through pipeline flip-flops. This method should be seriously

considered wherever throughput is more important than

latency.

TS

To include a CLB flip-flop, place the appropriate library

symbol. For example, FDCE is a D-type flip-flop with clock

enable and asynchronous clear. The corresponding latch

symbol is called LDCE.

CLB

LC3

LC2

LC1

LC0

In XC5200-Series devices, the flip-flops can be used as

registers or shift registers without blocking the function

generators from performing a different, perhaps unrelated

task. This ability increases the functional capacity of the

devices.

The CLB setup time is specified between the function gen-

erator inputs and the clock input CK. Therefore, the speci-

fied CLB flip-flop setup time includes the delay through the

function generator.

Horizontal

Longlines

X9030

Figure 9: XC5200 3-State Buffers

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XC5200 Series Field Programmable Gate Arrays

Z = D • A + D • B + D • C + D • N

A

B

C

N

~100 kΩ

D

N

A

B

C

BUFT

A

B

C

N

X6466

"Weak Keeper"

Figure 10: 3-State Buffers Implement a Multiplexer

Input/Output Blocks

User-configurable input/output blocks (IOBs) provide the

interface between external package pins and the internal

logic. Each IOB controls one package pin and can be con-

figured for input, output, or bidirectional signals.

Table 5: Supported Sources for XC5200-Series Device

Inputs

XC5200 Input Mode

5 V,

TTL

5 V,

CMOS

Source

The I/O block, shown in Figure 11, consists of an input

buffer and an output buffer. The output driver is an 8-mA

full-rail CMOS buffer with 3-state control. Two slew-rate

control modes are supported to minimize bus transients.

Both the output buffer and the 3-state control are invertible.

The input buffer has globally selected CMOS or TTL input

thresholds. The input buffer is invertible and also provides a

programmable delay line to assure reliable chip-to-chip

set-up and hold times. Minimum ESD protection is 3 KV

using the Human Body Model.

Any device, Vcc = 3.3 V,

CMOS outputs

√

Unreliable

Data

Any device, Vcc = 5 V,

TTL outputs

Any device, Vcc = 5 V,

CMOS outputs

√

Optional Delay Guarantees Zero Hold Time

XC5200 devices do not have storage elements in the IOBs.

However, XC5200 IOBs can be efficiently routed to CLB

flip-flops or latches to store the I/O signals.

7

Vcc

Delay

Input

Buffer

The data input to the register can optionally be delayed by

several nanoseconds. With the delay enabled, the setup

time of the input flip-flop is increased so that normal clock

routing does not result in a positive hold-time requirement.

A positive hold time requirement can lead to unreliable,

temperature- or processing-dependent operation.

Pullup

I

Output

Buffer

PAD

Pulldown

O

T

The input flip-flop setup time is defined between the data

measured at the device I/O pin and the clock input at the

CLB (not at the clock pin). Any routing delay from the

device clock pin to the clock input of the CLB must, there-

fore, be subtracted from this setup time to arrive at the real

setup time requirement relative to the device pins. A short

specified setup time might, therefore, result in a negative

setup time at the device pins, i.e., a positive hold-time

requirement.

Slew Rate

Control

X9001

Figure 11: XC5200 I/O Block

IOB Input Signals

The XC5200 inputs can be globally configured for either

TTL (1.2V) or CMOS thresholds, using an option in the bit-

stream generation software. There is a slight hysteresis of

about 300mV.

When a delay is inserted on the data line, more clock delay

can be tolerated without causing a positive hold-time

requirement. Sufficient delay eliminates the possibility of a

data hold-time requirement at the external pin. The maxi-

mum delay is therefore inserted as the software default.

The inputs of XC5200-Series 5-Volt devices can be driven

by the outputs of any 3.3-Volt device, if the 5-Volt inputs are

in TTL mode.

The XC5200 IOB has a one-tap delay element: either the

delay is inserted (default), or it is not. The delay guarantees

a zero hold time with respect to clocks routed through any

of the XC5200 global clock buffers. (See “Global Lines” on

page 96 for a description of the global clock buffers in the

XC5200.) For a shorter input register setup time, with

Supported sources for XC5200-Series device inputs are

shown in Table 5.

November 5, 1998 (Version 5.2)

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XC5200 Series Field Programmable Gate Arrays

non-zero hold, attach a NODELAY attribute or property to

the flip-flop or input buffer.

For XC5200 devices, maximum total capacitive load for

simultaneous fast mode switching in the same direction is

200 pF for all package pins between each Power/Ground

pin pair. For some XC5200 devices, additional internal

Power/Ground pin pairs are connected to special Power

and Ground planes within the packages, to reduce ground

bounce.

IOB Output Signals

Output signals can be optionally inverted within the IOB,

and pass directly to the pad. As with the inputs, a CLB

flip-flop or latch can be used to store the output signal.

For slew-rate limited outputs this total is two times larger for

each device type: 400 pF for XC5200 devices. This maxi-

mum capacitive load should not be exceeded, as it can

result in ground bounce of greater than 1.5 V amplitude and

more than 5 ns duration. This level of ground bounce may

cause undesired transient behavior on an output, or in the

internal logic. This restriction is common to all high-speed

digital ICs, and is not particular to Xilinx or the XC5200

Series.

An active-High 3-state signal can be used to place the out-

put buffer in a high-impedance state, implementing 3-state

outputs or bidirectional I/O. Under configuration control,

the output (OUT) and output 3-state (T) signals can be

inverted. The polarity of these signals is independently

configured for each IOB.

The XC5200 devices provide a guaranteed output sink cur-

rent of 8 mA.

Supported destinations for XC5200-Series device outputs

are shown in Table 6.(For a detailed discussion of how to

interface between 5 V and 3.3 V devices, see the 3V Prod-

ucts section of The Programmable Logic Data Book.)

XC5200-Series devices have a feature called “Soft

Start-up,” designed to reduce ground bounce when all out-

puts are turned on simultaneously at the end of configura-

tion. When the configuration process is finished and the

device starts up, the first activation of the outputs is auto-

matically slew-rate limited. Immediately following the initial

activation of the I/O, the slew rate of the individual outputs

is determined by the individual configuration option for

each IOB.

An output can be configured as open-drain (open-collector)

by placing an OBUFT symbol in a schematic or HDL code,

then tying the 3-state pin (T) to the output signal, and the

input pin (I) to Ground. (See Figure 12.)

Table 6: Supported Destinations for XC5200-Series

Outputs

Global Three-State

XC5200 Output Mode

A separate Global 3-State line (not shown in Figure 11)

forces all FPGA outputs to the high-impedance state,

unless boundary scan is enabled and is executing an

EXTEST instruction. This global net (GTS) does not com-

pete with other routing resources; it uses a dedicated distri-

bution network.

5 V,

CMOS

Destination

XC5200 device, V =3.3 V,

CC

√

some

√

CMOS-threshold inputs

Any typical device, V = 3.3 V,

1

CC

CMOS-threshold inputs

GTS can be driven from any user-programmable pin as a

global 3-state input. To use this global net, place an input

pad and input buffer in the schematic or HDL code, driving

the GTS pin of the STARTUP symbol. A specific pin loca-

tion can be assigned to this input using a LOC attribute or

property, just as with any other user-programmable pad. An

inverter can optionally be inserted after the input buffer to

invert the sense of the Global 3-State signal. Using GTS is

similar to Global Reset. See Figure 8 on page 90 for

details. Alternatively, GTS can be driven from any internal

node.

Any device, V = 5 V,

CC

TTL-threshold inputs

Any device, V = 5 V,

CC

√

CMOS-threshold inputs

1. Only if destination device has 5-V tolerant inputs

OPAD

Other IOB Options

OBUFT

X6702

There are a number of other programmable options in the

XC5200-Series IOB.

Figure 12: Open-Drain Output

Pull-up and Pull-down Resistors

Output Slew Rate

Programmable IOB pull-up and pull-down resistors are

useful for tying unused pins to Vcc or Ground to minimize

power consumption and reduce noise sensitivity. The con-

figurable pull-up resistor is a p-channel transistor that pulls

The slew rate of each output buffer is, by default, reduced,

to minimize power bus transients when switching non-criti-

cal signals. For critical signals, attach a FAST attribute or

property to the output buffer or flip-flop.

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November 5, 1998 (Version 5.2)

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XC5200 Series Field Programmable Gate Arrays

to Vcc. The configurable pull-down resistor is an n-channel

transistor that pulls to Ground.

The value of these resistors is 20 kΩ − 100 kΩ. This high

value makes them unsuitable as wired-AND pull-up resis-

tors.

OSC1

OSCS

OSC2

The pull-up resistors for most user-programmable IOBs are

active during the configuration process. See Table 13 on

page 124 for a list of pins with pull-ups active before and

during configuration.

OSC1

CK_DIV

OSC2

After configuration, voltage levels of unused pads, bonded

or unbonded, must be valid logic levels, to reduce noise

sensitivity and avoid excess current. Therefore, by default,

unused pads are configured with the internal pull-up resis-

tor active. Alternatively, they can be individually configured

with the pull-down resistor, or as a driven output, or to be

driven by an external source. To activate the internal

pull-up, attach the PULLUP library component to the net

attached to the pad. To activate the internal pull-down,

attach the PULLDOWN library component to the net

attached to the pad.

5200_14

Figure 13: XC5200 Oscillator Macros

VersaBlock Routing

The General Routing Matrix (GRM) connects to the

Versa-Block via 24 bidirectional ports (M0-M23). Excluding

direct connections, global nets, and 3-statable Longlines,

all VersaBlock inputs and outputs connect to the GRM via

these 24 ports. Four 3-statable unidirectional signals

(TQ0-TQ3) drive out of the VersaBlock directly onto the

horizontal and vertical Longlines. Two horizontal global

nets and two vertical global nets connect directly to every

CLB clock pin; they can connect to other CLB inputs via the

GRM. Each CLB also has four unidirectional direct con-

nects to each of its four neighboring CLBs. These direct

connects can also feed directly back to the CLB (see

Figure 14).

JTAG Support

Embedded logic attached to the IOBs contains test struc-

tures compatible with IEEE Standard 1149.1 for boundary

scan testing, simplifying board-level testing. More informa-

tion is provided in “Boundary Scan” on page 98.

7

Oscillator

XC5200 devices include an internal oscillator. This oscilla-

tor is used to clock the power-on time-out, clear configura-

tion memory, and source CCLK in Master configuration

modes. The oscillator runs at a nominal 12 MHz frequency

that varies with process, Vcc, and temperature. The output

CCLK frequency is selectable as 1 MHz (default), 6 MHz,

or 12 MHz.

In addition, each CLB has 16 direct inputs, four direct con-

nections from each of the neighboring CLBs. These direct

connections provide high-speed local routing that

bypasses the GRM.

Local Interconnect Matrix

The Local Interconnect Matrix (LIM) is built from input and

output multiplexers. The 13 CLB outputs (12 LC outputs

The XC5200 oscillator divides the internal 12-MHz clock or

a user clock. The user then has the choice of dividing by 4,

16, 64, or 256 for the “OSC1” output and dividing by 2, 8,

32, 128, 1024, 4096, 16384, or 65536 for the “OSC2” out-

put. The division is specified via a “DIVIDEn_BY=x”

attribute on the symbol, where n=1 for OSC1, or n=2 for

OSC2. These frequencies can vary by as much as -50% or

+ 50%.

plus a V /GND signal) connect to the eight VersaBlock

cc

outputs via the output multiplexers, which consist of eight

fully populated 13-to-1 multiplexers. Of the eight

VersaBlock outputs, four signals drive each neighboring

CLB directly, and provide a direct feedback path to the input

multiplexers. The four remaining multiplexer outputs can

drive the GRM through four TBUFs (TQ0-TQ3). All eight

multiplexer outputs can connect to the GRM through the

bidirectional M0-M23 signals. All eight signals also connect

to the input multiplexers and are potential inputs to that

CLB.

The OSC5 macro is used where an internal oscillator is

required. The CK_DIV macro is applicable when a user

clock input is specified (see Figure 13).

November 5, 1998 (Version 5.2)

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XC5200 Series Field Programmable Gate Arrays

To GRM

M0-M23

24

8

TS

4

Global Nets

4

To

C

OUT

Longlines

and GRM

TQ0-TQ3

4

North

South

East

CLB

5

3

LC3

LC2

LC1

LC0

Input

Multiplexers

Output

Multiplexers

West

3

Direct to

East

V

CC

/GND

4

8

3

4

Direct North

4

CLK

CE

Feedback

4

CLR

C

IN

Direct West

4

X5724

Direct South

Figure 14: VersaBlock Details

CLB inputs have several possible sources: the 24 signals

from the GRM, 16 direct connections from neighboring

VersaBlocks, four signals from global, low-skew buffers,

and the four signals from the CLB output multiplexers.

Unlike the output multiplexers, the input multiplexers are

not fully populated; i.e., only a subset of the available sig-

nals can be connected to a given CLB input. The flexibility

of LUT input swapping and LUT mapping compensates for

this limitation. For example, if a 2-input NAND gate is

required, it can be mapped into any of the four LUTs, and

use any two of the four inputs to the LUT.

The direct connects also provide a high-speed path from

the edge CLBs to the VersaRing input/output buffers, and

thus reduce pin-to-pin set-up time, clock-to-out, and combi-

national propagation delay. Direct connects from the input

buffers to the CLB DI pin (direct flip-flop input) are only

available on the left and right edges of the device. CLB

look-up table inputs and combinatorial/registered outputs

have direct connects to input/output buffers on all four

sides.

The direct connects are ideal for developing customized

RPM cells. Using direct connects improves the macro per-

formance, and leaves the other routing channels intact for

improved routing. Direct connects can also route through a

CLB using one of the four cell-feedthrough paths.

Direct Connects

The unidirectional direct-connect segments are connected

to the logic input/output pins through the CLB input and out-

put multiplexer arrays, and thus bypass the general routing

matrix altogether. These lines increase the routing channel

utilization, while simultaneously reducing the delay

incurred in speed-critical connections.

General Routing Matrix

The General Routing Matrix, shown in Figure 15, provides

flexible bidirectional connections to the Local Interconnect

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November 5, 1998 (Version 5.2)

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XC5200 Series Field Programmable Gate Arrays

Matrix through a hierarchy of different-length metal seg-

ments in both the horizontal and vertical directions. A pro-

GRM

Versa-

Block

Versa-

Block

Versa-

Block

1

GRM

Versa-

Block

Versa-

Block

Versa-

Block

2

GRM

Versa-

Block

Versa-

Block

Versa-

Block

3

4

7

Six Levels of Routing Hierarchy

GRM

4

1

2

Single-length Lines

24

TS

Double-length Lines

CLB

LC3

LC2

LC1

LC0

4

3

Direct Connects

4

5

Longlines and Global Lines

Local Interconnect Matrix

6

LIM

5

Logic Cell Feedthrough

Path (Contained within each

Logic Cell)

6

4

X4963

Direct Connects

Figure 15: XC5200 Interconnect Structure

grammable interconnect point (PIP) establishes an electri-

cal connection between two wire segments. The PIP, con-

sisting of a pass transistor switch controlled by a memory

element, provides bidirectional (in some cases, unidirec-

tional) connection between two adjoining wires. A collec-

tion of PIPs inside the General Routing Matrix and in the

Local Interconnect Matrix provides connectivity between

various types of metal segments. A hierarchy of PIPs and

associated routing segments combine to provide a power-

ful interconnect hierarchy:

•

Forty bidirectional single-length segments per CLB

provide ten routing channels to each of the four

neighboring CLBs in four directions.

Sixteen bidirectional double-length segments per CLB

provide four routing channels to each of four other

(non-neighboring) CLBs in four directions.

Eight horizontal and eight vertical bidirectional Longline

November 5, 1998 (Version 5.2)

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XC5200 Series Field Programmable Gate Arrays

segments span the width and height of the chip,

respectively.

carry/cascade logic described above, implementing a wide

logic function in place of the wired function. In the case of

3-state bus applications, the user must insure that all states

of the multiplexing function are defined. This process is as

simple as adding an additional TBUF to drive the bus High

when the previously undefined states are activated.

Two low-skew horizontal and vertical unidirectional glo-

bal-line segments span each row and column of the chip,

respectively.

Single- and Double-Length Lines

Global Lines

The single- and double-length bidirectional line segments

make up the bulk of the routing channels. The dou-

ble-length lines hop across every other CLB to reduce the

propagation delays in speed-critical nets. Regenerating the

signal strength is recommended after traversing three or

four such segments. Xilinx place-and-route software auto-

matically connects buffers in the path of the signal as nec-

essary. Single- and double-length lines cannot drive onto

Longlines and global lines; Longlines and global lines can,

however, drive onto single- and double-length lines. As a

general rule, Longline and global-line connections to the

general routing matrix are unidirectional, with the signal

direction from these lines toward the routing matrix.

Global buffers in Xilinx FPGAs are special buffers that drive

a dedicated routing network called Global Lines, as shown

in Figure 16. This network is intended for high-fanout

clocks or other control signals, to maximize speed and min-

imize skewing while distributing the signal to many loads.

The XC5200 family has a total of four global buffers (BUFG

symbol in the library), each with its own dedicated routing

channel. Two are distributed vertically and two horizontally

throughout the FPGA.

The global lines provide direct input only to the CLB clock

pins. The global lines also connect to the General Routing

Matrix to provide access from these lines to the function

generators and other control signals.

Longlines

Four clock input pads at the corners of the chip, as shown

in Figure 16, provide a high-speed, low-skew clock network

to each of the four global-line buffers. In addition to the ded-

icated pad, the global lines can be sourced by internal

logic. PIPs from several routing channels within the Ver-

saRing can also be configured to drive the global-line buff-

ers.

Longlines are used for high-fan-out signals, 3-state busses,

low-skew nets, and faraway destinations. Row and column

splitter PIPs in the middle of the array effectively double the

total number of Longlines by electrically dividing them into

two separated half-lines. Longlines are driven by the

3-state buffers in each CLB, and are driven by similar buff-

ers at the periphery of the array from the VersaRing I/O

Interface.

Details of all the programmable interconnect for a CLB is

shown in Figure 17.

Bus-oriented designs are easily implemented by using Lon-

glines in conjunction with the 3-state buffers in the CLB and

in the VersaRing. Additionally, weak keeper cells at the

periphery retain the last valid logic level on the Longlines

when all buffers are in 3-state mode.

GCK4

GCK1

Longlines connect to the single-length or double-length

lines, or to the logic inside the CLB, through the General

Routing Matrix. The only manner in which a Longline can

be driven is through the four 3-state buffers; therefore, a

Longline-to-Longline or single-line-to-Longline connection

through PIPs in the General Routing Matrix is not possible.

Again, as a general rule, long- and global-line connections

to the General Routing Matrix are unidirectional, with the

signal direction from these lines toward the routing matrix.

The XC5200 family has no pull-ups on the ends of the Lon-

glines sourced by TBUFs, unlike the XC4000 Series. Con-

sequently, wired functions (i.e., WAND and WORAND) and

wide multiplexing functions requiring pull-ups for undefined

states (i.e., bus applications) must be implemented in a dif-

ferent way. In the case of the wired functions, the same

functionality can be achieved by taking advantage of the

GCK3

GCK2

X5704

Figure 16: Global Lines

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November 5, 1998 (Version 5.2)

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XC5200 Series Field Programmable Gate Arrays

.

7

Figure 17: Detail of Programmable Interconnect Associated with XC5200 Series CLB

November 5, 1998 (Version 5.2)

7-97

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XC5200 Series Field Programmable Gate Arrays

VersaRing Input/Output Interface

XC5200 devices support all the mandatory boundary-scan

instructions specified in the IEEE standard 1149.1. A Test

Access Port (TAP) and registers are provided that imple-

ment the EXTEST, SAMPLE/PRELOAD, and BYPASS

instructions. The TAP can also support two USERCODE

instructions. When the boundary scan configuration option

is selected, three normal user I/O pins become dedicated

inputs for these functions. Another user output pin

becomes the dedicated boundary scan output.

The VersaRing, shown in Figure 18, is positioned between

the core logic and the pad ring; it has all the routing

resources of a VersaBlock without the CLB logic. The Ver-

saRing decouples the core logic from the I/O pads. Each

VersaRing Cell provides up to four pad-cell connections on

one side, and connects directly to the CLB ports on the

other side.

Boundary-scan operation is independent of individual IOB

configuration and package type. All IOBs are treated as

independently controlled bidirectional pins, including any

unbonded IOBs. Retaining the bidirectional test capability

after configuration provides flexibility for interconnect test-

ing.

VersaRing

2

8

2

Also, internal signals can be captured during EXTEST by

connecting them to unbonded IOBs, or to the unused out-

puts in IOBs used as unidirectional input pins. This tech-

nique partially compensates for the lack of INTEST

support.

Pad

2

GRM

10

Interconnect

4

The user can serially load commands and data into these

devices to control the driving of their outputs and to exam-

ine their inputs. This method is an improvement over

bed-of-nails testing. It avoids the need to over-drive device

outputs, and it reduces the user interface to four pins. An

optional fifth pin, a reset for the control logic, is described in

the standard but is not implemented in Xilinx devices.

4

VersaBlock

8

Interconnect

8

2

Pad

2

The dedicated on-chip logic implementing the IEEE 1149.1

functions includes a 16-state machine, an instruction regis-

ter and a number of data registers. The functional details

can be found in the IEEE 1149.1 specification and are also

discussed in the Xilinx application note XAPP 017: “Bound-

ary Scan in XC4000 and XC5200 Series devices”

GRM

10

4

VersaBlock

2

Figure 19 on page 99 is a diagram of the XC5200-Series

boundary scan logic. It includes three bits of Data Register

per IOB, the IEEE 1149.1 Test Access Port controller, and

the Instruction Register with decodes.

8

2

X5705

Figure 18: VersaRing I/O Interface

The public boundary-scan instructions are always available

prior to configuration. After configuration, the public instruc-

tions and any USERCODE instructions are only available if

specified in the design. While SAMPLE and BYPASS are

available during configuration, it is recommended that

boundary-scan operations not be performed during this

transitory period.

Boundary Scan

The “bed of nails” has been the traditional method of testing

electronic assemblies. This approach has become less

appropriate, due to closer pin spacing and more sophisti-

cated assembly methods like surface-mount technology

and multi-layer boards. The IEEE boundary scan standard

1149.1 was developed to facilitate board-level testing of

electronic assemblies. Design and test engineers can

imbed a standard test logic structure in their device to

achieve high fault coverage for I/O and internal logic. This

structure is easily implemented with a four-pin interface on

any boundary scan-compatible IC. IEEE 1149.1-compatible

devices may be serial daisy-chained together, connected in

parallel, or a combination of the two.

In addition to the test instructions outlined above, the

boundary-scan circuitry can be used to configure the FPGA

device, and to read back the configuration data.

All of the XC4000 boundary-scan modes are supported in

the XC5200 family. Three additional outputs for the User-

Register are provided (Reset, Update, and Shift), repre-

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November 5, 1998 (Version 5.2)

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XC5200 Series Field Programmable Gate Arrays

senting the decoding of the corresponding state of the

boundary-scan internal state machine.

DATA IN

1

0

sd

D

Q

D

Q

LE

1

0

IOB.O

IOB.T

0

1

sd

D

Q

D

Q

0

LE

IOB

sd

1

0

D

Q

D

Q

LE

1

0

IOB.I

1

sd

D

Q

D

Q

0

LE

1

0

IOB.O

IOB.T

BYPASS

REGISTER

0

1

7

M

U

X

TDO

TDI

1

sd

INSTRUCTION REGISTER

TDI

D

Q

D

Q

0

LE

M

U

X

INSTRUCTION REGISTER

TDO

1

sd

BYPASS

REGISTER

D

Q

D

Q

IOB

0

LE

1

0

IOB.I

1

sd

D

Q

D

Q

0

LE

0

1

IOB.O

DATAOUT

SHIFT/

UPDATE

EXTEST

IOB

CLOCK DATA

REGISTER

CAPTURE

X1523_01

Figure 19: XC5200-Series Boundary Scan Logic

November 5, 1998 (Version 5.2)

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XC5200 Series Field Programmable Gate Arrays

XC5200-Series devices can also be configured through the

boundary scan logic. See XAPP 017 for more information.

Bit Sequence

The bit sequence within each IOB is: 3-State, Out, In. The

data-register cells for the TAP pins TMS, TCK, and TDI

have an OR-gate that permanently disables the output

buffer if boundary-scan operation is selected. Conse-

quently, it is impossible for the outputs in IOBs used by TAP

inputs to conflict with TAP operation. TAP data is taken

directly from the pin, and cannot be overwritten by injected

boundary-scan data.

Data Registers

The primary data register is the boundary scan register.

For each IOB pin in the FPGA, bonded or not, it includes

three bits for In, Out and 3-State Control. Non-IOB pins

have appropriate partial bit population for In or Out only.

PROGRAM, CCLK and DONE are not included in the

boundary scan register. Each EXTEST CAPTURE-DR

state captures all In, Out, and 3-State pins.

The primary global clock inputs (PGCK1-PGCK4) are

taken directly from the pins, and cannot be overwritten with

boundary-scan data. However, if necessary, it is possible to

drive the clock input from boundary scan. The external

clock source is 3-stated, and the clock net is driven with

boundary scan data through the output driver in the

clock-pad IOB. If the clock-pad IOBs are used for non-clock

signals, the data may be overwritten normally.

The data register also includes the following non-pin bits:

TDO.T, and TDO.O, which are always bits 0 and 1 of the

data register, respectively, and BSCANT.UPD, which is

always the last bit of the data register. These three bound-

ary scan bits are special-purpose Xilinx test signals.

The other standard data register is the single flip-flop

BYPASS register. It synchronizes data being passed

through the FPGA to the next downstream boundary scan

device.

Pull-up and pull-down resistors remain active during

boundary scan. Before and during configuration, all pins

are pulled up. After configuration, the choice of internal

pull-up or pull-down resistor must be taken into account

when designing test vectors to detect open-circuit PC

traces.

The FPGA provides two additional data registers that can

be specified using the BSCAN macro. The FPGA provides

two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are

the decodes of two user instructions, USER1 and USER2.

For these instructions, two corresponding pins

(BSCAN.TDO1 and BSCAN.TDO2) allow user scan data to

From a cavity-up view of the chip (as shown in XDE or

Epic), starting in the upper right chip corner, the boundary

scan data-register bits are ordered as shown in Table 8.

The device-specific pinout tables for the XC5200 Series

include the boundary scan locations for each IOB pin.

be shifted out on TDO.

The data register clock

(BSCAN.DRCK) is available for control of test logic which

the user may wish to implement with CLBs. The NAND of

TCK and RUN-TEST-IDLE is also provided (BSCAN.IDLE).

Table 8: Boundary Scan Bit Sequence

Bit Position

I/O Pad Location

Top-edge I/O pads (right to left)

...

Instruction Set

Bit 0 (TDO)

The XC5200-Series boundary scan instruction set also

includes instructions to configure the device and read back

the configuration data. The instruction set is coded as

shown in Table 7.

Bit 1

...

Left-edge I/O pads (top to bottom)

Bottom-edge I/O pads (left to right)

Right-edge I/O pads (bottom to top)

BSCANT.UPD

...

Table 7: Boundary Scan Instructions

Bit N (TDI)

Instruction I2

I1 I0

Test

Selected

I/O Data

Source

TDO Source

BSDL (Boundary Scan Description Language) files for

XC5200-Series devices are available on the Xilinx web site

in the File Download area.

0

1

EXTEST

DR

SAMPLE/PR

ELOAD

Pin/Logic

Including Boundary Scan

0

1

0

1

0

USER 1

BSCAN.

TDO1

User Logic

Pin/Logic

If boundary scan is only to be used during configuration, no

special elements need be included in the schematic or HDL

code. In this case, the special boundary scan pins TDI,

TMS, TCK and TDO can be used for user functions after

configuration.

USER 2

BSCAN.

TDO2

READBACK Readback

Data

To indicate that boundary scan remain enabled after config-

uration, include the BSCAN library symbol and connect pad

symbols to the TDI, TMS, TCK and TDO pins, as shown in

Figure 20.

1

0

1

0

1

CONFIGURE

Reserved

DOUT

Disabled

—

BYPASS

Bypass

Register

7-100

November 5, 1998 (Version 5.2)

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XC5200 Series Field Programmable Gate Arrays

Typically, a 0.1 µF capacitor connected near the Vcc and

Ground pins of the package will provide adequate decou-

pling.

Optional

To User

Logic

IBUF

BSCAN

RESET

Output buffers capable of driving/sinking the specified 8 mA

loads under specified worst-case conditions may be capa-

ble of driving/sinking up to 10 times as much current under

best case conditions.

UPDATE

SHIFT

TDO

TDI

Noise can be reduced by minimizing external load capaci-

tance and reducing simultaneous output transitions in the

same direction. It may also be beneficial to locate heavily

loaded output buffers near the Ground pads. The I/O Block

output buffers have a slew-rate limited mode (default)

which should be used where output rise and fall times are

not speed-critical.

TMS

TCK

DRCK

IDLE

To User

Logic

TDO1

TDO2

SEL1

From

User Logic

SEL2

X9000

Figure 20: Boundary Scan Schematic Example

Even if the boundary scan symbol is used in a schematic,

the input pins TMS, TCK, and TDI can still be used as

inputs to be routed to internal logic. Care must be taken not

to force the chip into an undesired boundary scan state by

inadvertently applying boundary scan input patterns to

these pins. The simplest way to prevent this is to keep

TMS High, and then apply whatever signal is desired to TDI

and TCK.

GND

Ground and

Vcc Ring for

I/O Drivers

Avoiding Inadvertent Boundary Scan

Vcc

If TMS or TCK is used as user I/O, care must be taken to

ensure that at least one of these pins is held constant dur-

ing configuration. In some applications, a situation may

occur where TMS or TCK is driven during configuration.

This may cause the device to go into boundary scan mode

and disrupt the configuration process.

Logic

Power Grid

7

GND

X5422

To prevent activation of boundary scan during configura-

tion, do either of the following:

Figure 21: XC5200-Series Power Distribution

•

TMS: Tie High to put the Test Access Port controller

in a benign RESET state

TCK: Tie High or Low—do not toggle this clock input.

Pin Descriptions

There are three types of pins in the XC5200-Series

devices:

•

For more information regarding boundary scan, refer to the

Xilinx Application Note XAPP 017, “Boundary Scan in

XC4000 and XC5200 Devices.“

•

Permanently dedicated pins

User I/O pins that can have special functions

Unrestricted user-programmable I/O pins.

Power Distribution

Before and during configuration, all outputs not used for the

configuration process are 3-stated and pulled high with a

20 kΩ - 100 kΩ pull-up resistor.

Power for the FPGA is distributed through a grid to achieve

high noise immunity and isolation between logic and I/O.

Inside the FPGA, a dedicated Vcc and Ground ring sur-

rounding the logic array provides power to the I/O drivers,

as shown in Figure 21. An independent matrix of Vcc and

Ground lines supplies the interior logic of the device.

After configuration, if an IOB is unused it is configured as

an input with a 20 kΩ - 100 kΩ pull-up resistor.

Device pins for XC5200-Series devices are described in

Table 9. Pin functions during configuration for each of the

seven configuration modes are summarized in “Pin Func-

This power distribution grid provides a stable supply and

ground for all internal logic, providing the external package

power pins are all connected and appropriately decoupled.

November 5, 1998 (Version 5.2)

7-101

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XC5200 Series Field Programmable Gate Arrays

tions During Configuration” on page 124, in the “Configura-

tion Timing” section.

Table 9: Pin Descriptions

I/O

During

After

Pin Name

Config. Config.

Pin Description

Permanently Dedicated Pins

Five or more (depending on package) connections to the nominal +5 V supply voltage.

All must be connected, and each must be decoupled with a 0.01 - 0.1 µF capacitor to

Ground.

VCC

GND

I

Four or more (depending on package type) connections to Ground. All must be con-

nected.

During configuration, Configuration Clock (CCLK) is an output in Master modes or Asyn-

chronous Peripheral mode, but is an input in Slave mode, Synchronous Peripheral

mode, and Express mode. After configuration, CCLK has a weak pull-up resistor and

can be selected as the Readback Clock. There is no CCLK High time restriction on

XC5200-Series devices, except during Readback. See “Violating the Maximum High

and Low Time Specification for the Readback Clock” on page 113 for an explanation of

this exception.

CCLK

I or O

I

DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it

indicates the completion of the configuration process. As an input, a Low level on

DONE can be configured to delay the global logic initialization and the enabling of out-

puts.

DONE

I/O

O

The exact timing, the clock source for the Low-to-High transition, and the optional

pull-up resistor are selected as options in the program that creates the configuration bit-

stream. The resistor is included by default.

PROGRAM is an active Low input that forces the FPGA to clear its configuration mem-

ory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA

executes a complete clear cycle, before it goes into a WAIT state and releases INIT.

The PROGRAM pin has an optional weak pull-up after configuration.

PROGRAM

I

User I/O Pins That Can Have Special Functions

During Peripheral mode configuration, this pin indicates when it is appropriate to write

another byte of data into the FPGA. The same status is also available on D7 in Asyn-

chronous Peripheral mode, if a read operation is performed when the device is selected.

After configuration, RDY/BUSY is a user-programmable I/O pin.

RDY/BUSY

O

I/O

RDY/BUSY is pulled High with a high-impedance pull-up prior to INIT going High.

During Master Parallel configuration, each change on the A0-A17 outputs is preceded

by a rising edge on RCLK, a redundant output signal. RCLK is useful for clocked

PROMs. It is rarely used during configuration. After configuration, RCLK is a user-pro-

grammable I/O pin.

RCLK

O

I/O

As Mode inputs, these pins are sampled before the start of configuration to determine

the configuration mode to be used. After configuration, M0, M1, and M2 become us-

er-programmable I/O.

During configuration, these pins have weak pull-up resistors. For the most popular con-

figuration mode, Slave Serial, the mode pins can thus be left unconnected. A pull-down

resistor value of 3.3 kΩ is recommended for other modes.

M0, M1, M2

I

I/O

O

If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used,

this pin is a 3-state output, after configuration is completed.

This pin can be user output only when called out by special schematic definitions. To

use this pin, place the library component TDO instead of the usual pad symbol. An out-

put buffer must still be used.

TDO

O

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November 5, 1998 (Version 5.2)

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XC5200 Series Field Programmable Gate Arrays

Table 9: Pin Descriptions (Continued)

I/O

During

After

Pin Name

Config. Config.

Pin Description

If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select

inputs respectively. They come directly from the pads, bypassing the IOBs. These pins

can also be used as inputs to the CLB logic after configuration is completed.

If the BSCAN symbol is not placed in the design, all boundary scan functions are inhib-

ited once configuration is completed, and these pins become user-programmable I/O.

In this case, they must be called out by special schematic definitions. To use these pins,

place the library components TDI, TCK, and TMS instead of the usual pad symbols. In-

put or output buffers must still be used.

I/O

or I

(JTAG)

TDI, TCK,

TMS

I

High During Configuration (HDC) is driven High until the I/O go active. It is available as

a control output indicating that configuration is not yet completed. After configuration,

HDC is a user-programmable I/O pin.

HDC

LDC

O

I/O

Low During Configuration (LDC) is driven Low until the I/O go active. It is available as a

control output indicating that configuration is not yet completed. After configuration,

LDC is a user-programmable I/O pin.

Before and during configuration, INIT is a bidirectional signal. A 1 kΩ - 10 kΩ external

pull-up resistor is recommended.

As an active-Low open-drain output, INIT is held Low during the power stabilization and

internal clearing of the configuration memory. As an active-Low input, it can be used

to hold the FPGA in the internal WAIT state before the start of configuration. Master

mode devices stay in a WAIT state an additional 50 to 250 µs after INIT has gone High.

During configuration, a Low on this output indicates that a configuration data error has

occurred. After the I/O go active, INIT is a user-programmable I/O pin.

INIT

I/O

I or I/O

I/O

7

Four Global inputs each drive a dedicated internal global net with short delay and min-

imal skew. These internal global nets can also be driven from internal logic. If not used

to drive a global net, any of these pins is a user-programmable I/O pin.

The GCK1-GCK4 pins provide the shortest path to the four Global Buffers. Any input

pad symbol connected directly to the input of a BUFG symbol is automatically placed on

one of these pins.

GCK1 -

GCK4

Weak

Pull-up

These four inputs are used in Asynchronous Peripheral mode. The chip is selected

when CS0 is Low and CS1 is High. While the chip is selected, a Low on Write Strobe

(WS) loads the data present on the D0 - D7 inputs into the internal data buffer. A Low

on Read Strobe (RS) changes D7 into a status output — High if Ready, Low if Busy —

and drives D0 - D6 High.

CS0, CS1,

WS, RS

I

In Express mode, CS1 is used as a serial-enable signal for daisy-chaining.

WS and RS should be mutually exclusive, but if both are Low simultaneously, the Write

Strobe overrides. After configuration, these are user-programmable I/O pins.

During Master Parallel configuration, these 18 output pins address the configuration

EPROM. After configuration, they are user-programmable I/O pins.

A0 - A17

D0 - D7

O

I

I/O

During Master Parallel, Peripheral, and Express configuration, these eight input pins re-

ceive configuration data. After configuration, they are user-programmable I/O pins.

During Slave Serial or Master Serial configuration, DIN is the serial configuration data

input receiving data on the rising edge of CCLK. During Parallel configuration, DIN is

the D0 input. After configuration, DIN is a user-programmable I/O pin.

DIN

I

I/O

During configuration in any mode but Express mode, DOUT is the serial configuration

data output that can drive the DIN of daisy-chained slave FPGAs. DOUT data changes

on the falling edge of CCLK.

DOUT

O

I/O

In Express mode, DOUT is the status output that can drive the CS1 of daisy-chained

FPGAs, to enable and disable downstream devices.

After configuration, DOUT is a user-programmable I/O pin.

November 5, 1998 (Version 5.2)

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XC5200 Series Field Programmable Gate Arrays

Table 9: Pin Descriptions (Continued)

I/O

During

After

Pin Name

Config. Config.

Pin Description

Unrestricted User-Programmable I/O Pins

These pins can be configured to be input and/or output after configuration is completed.

Before configuration is completed, these pins have an internal high-value pull-up resis-

tor (20 kΩ - 100 kΩ) that defines the logic level as High.

Weak

Pull-up

I/O

M1, and M0 inputs. There are three self-loading Master

modes, two Peripheral modes, and a Serial Slave mode,

Configuration

Configuration is the process of loading design-specific pro-

gramming data into one or more FPGAs to define the func-

tional operation of the internal blocks and their

interconnections. This is somewhat like loading the com-

mand registers of a programmable peripheral chip.

XC5200-Series devices use several hundred bits of config-

uration data per CLB and its associated interconnects.

Each configuration bit defines the state of a static memory

cell that controls either a function look-up table bit, a multi-

plexer input, or an interconnect pass transistor. The devel-

opment system translates the design into a netlist file. It

automatically partitions, places and routes the logic and

generates the configuration data in PROM format.

Table 10: Configuration Modes

Mode

M2 M1 M0 CCLK

Data

Master Serial

Slave Serial

0

1

0

1

0

1

0

output

input

Bit-Serial

Master

Parallel Up

output

Byte-Wide,

increment

from 00000

Master

Parallel Down

1

0

output

Byte-Wide,

decrement

from 3FFFF

Peripheral

Synchronous*

0

1

0

1

input

Byte-Wide

Special Purpose Pins

Peripheral

output

Byte-Wide

Asynchronous

Three configuration mode pins (M2, M1, M0) are sampled

prior to configuration to determine the configuration mode.

After configuration, these pins can be used as auxiliary I/O

connections. The development system does not use these

resources unless they are explicitly specified in the design

entry. This is done by placing a special pad symbol called

MD2, MD1, or MD0 instead of the input or output pad sym-

bol.

Express

0

1

0

1

input

Byte-Wide

Reserved

—

Note :*Peripheral Synchronous can be considered byte-wide

Slave Parallel

which is used primarily for daisy-chained devices. The sev-

enth mode, called Express mode, is an additional slave

mode that allows high-speed parallel configuration. The

coding for mode selection is shown in Table 10.

In XC5200-Series devices, the mode pins have weak

pull-up resistors during configuration. With all three mode

pins High, Slave Serial mode is selected, which is the most

popular configuration mode. Therefore, for the most com-

mon configuration mode, the mode pins can be left uncon-

nected. (Note, however, that the internal pull-up resistor

value can be as high as 100 kΩ.) After configuration, these

pins can individually have weak pull-up or pull-down resis-

tors, as specified in the design. A pull-down resistor value

of 3.3kΩ is recommended.

Note that the smallest package, VQ64, only supports the

Master Serial, Slave Serial, and Express modes.A detailed

description of each configuration mode, with timing infor-

mation, is included later in this data sheet. During configu-

ration, some of the I/O pins are used temporarily for the

configuration process. All pins used during configuration

are shown in Table 13 on page 124.

Master Modes

These pins are located in the lower left chip corner and are

near the readback nets. This location allows convenient

routing if compatibility with the XC2000 and XC3000 family

conventions of M0/RT, M1/RD is desired.

The three Master modes use an internal oscillator to gener-

ate a Configuration Clock (CCLK) for driving potential slave

devices. They also generate address and timing for exter-

nal PROM(s) containing the configuration data.

Configuration Modes

Master Parallel (Up or Down) modes generate the CCLK

signal and PROM addresses and receive byte parallel

data. The data is internally serialized into the FPGA

data-frame format. The up and down selection generates

starting addresses at either zero or 3FFFF, for compatibility

with different microprocessor addressing conventions. The

XC5200 devices have seven configuration modes. These

modes are selected by a 3-bit input code applied to the M2,

7-104

November 5, 1998 (Version 5.2)

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XC5200 Series Field Programmable Gate Arrays

Master Serial mode generates CCLK and receives the con-

figuration data in serial form from a Xilinx serial-configura-

tion PROM.

Multi-Family Daisy Chain

All Xilinx FPGAs of the XC2000, XC3000, XC4000, and

XC5200 Series use a compatible bitstream format and can,

therefore, be connected in a daisy chain in an arbitrary

sequence. There is, however, one limitation. If the chain

contains XC5200-Series devices, the master normally can-

not be an XC2000 or XC3000 device.

CCLK speed is selectable as 1 MHz (default), 6 MHz, or 12

MHz. Configuration always starts at the default slow fre-

quency, then can switch to the higher frequency during the

first frame. Frequency tolerance is -50% to +50%.

The reason for this rule is shown in Figure 25 on page 109.

Since all devices in the chain store the same length count

value and generate or receive one common sequence of

CCLK pulses, they all recognize length-count match on the

same CCLK edge, as indicated on the left edge of

Figure 25. The master device then generates additional

CCLK pulses until it reaches its finish point F. The different

families generate or require different numbers of additional

CCLK pulses until they reach F. Not reaching F means that

the device does not really finish its configuration, although

DONE may have gone High, the outputs became active,

and the internal reset was released. For the

XC5200-Series device, not reaching F means that read-

back cannot be initiated and most boundary scan instruc-

tions cannot be used.

Peripheral Modes

The two Peripheral modes accept byte-wide data from a

bus. A RDY/BUSY status is available as a handshake sig-

nal. In Asynchronous Peripheral mode, the internal oscilla-

tor generates a CCLK burst signal that serializes the

byte-wide data. CCLK can also drive slave devices. In the

synchronous mode, an externally supplied clock input to

CCLK serializes the data.

Slave Serial Mode

In Slave Serial mode, the FPGA receives serial configura-

tion data on the rising edge of CCLK and, after loading its

configuration, passes additional data out, resynchronized

on the next falling edge of CCLK.

Multiple slave devices with identical configurations can be

wired with parallel DIN inputs. In this way, multiple devices

can be configured simultaneously.

The user has some control over the relative timing of these

events and can, therefore, make sure that they occur at the

proper time and the finish point F is reached. Timing is con-

trolled using options in the bitstream generation software.

7

Serial Daisy Chain

XC5200 devices always have the same number of CCLKs

in the power up delay, independent of the configuration

mode, unlike the XC3000/XC4000 Series devices. To guar-

antee all devices in a daisy chain have finished the

power-up delay, tie the INIT pins together, as shown in

Figure 27.

Multiple devices with different configurations can be con-

nected together in a “daisy chain,” and a single combined

bitstream used to configure the chain of slave devices.

To configure a daisy chain of devices, wire the CCLK pins

of all devices in parallel, as shown in Figure 28 on page

114. Connect the DOUT of each device to the DIN of the

next. The lead or master FPGA and following slaves each

passes resynchronized configuration data coming from a

single source. The header data, including the length count,

is passed through and is captured by each FPGA when it

recognizes the 0010 preamble. Following the length-count

data, each FPGA outputs a High on DOUT until it has

received its required number of data frames.

XC3000 Master with an XC5200-Series Slave

Some designers want to use an XC3000 lead device in

peripheral mode and have the I/O pins of the

XC5200-Series devices all available for user I/O. Figure 22

provides a solution for that case.

This solution requires one CLB, one IOB and pin, and an

internal oscillator with a frequency of up to 5 MHz as a

clock source. The XC3000 master device must be config-

ured with late Internal Reset, which is the default option.

After an FPGA has received its configuration data, it

passes on any additional frame start bits and configuration

data on DOUT. When the total number of configuration

clocks applied after memory initialization equals the value

of the 24-bit length count, the FPGAs begin the start-up

sequence and become operational together. FPGA I/O are

normally released two CCLK cycles after the last configura-

tion bit is received. Figure 25 on page 109 shows the

start-up timing for an XC5200-Series device.

One CLB and one IOB in the lead XC3000-family device

are used to generate the additional CCLK pulse required by

the XC5200-Series devices.

When the lead device

removes the internal RESET signal, the 2-bit shift register

responds to its clock input and generates an active Low

output signal for the duration of the subsequent clock

period. An external connection between this output and

CCLK thus creates the extra CCLK pulse.

The daisy-chained bitstream is not simply a concatenation

of the individual bitstreams. The PROM file formatter must

be used to combine the bitstreams for a daisy-chained con-

figuration.

November 5, 1998 (Version 5.2)

7-105

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XC5200 Series Field Programmable Gate Arrays

Pseudo Daisy Chain

Multiple devices with different configurations can be con-

nected together in a pseudo daisy chain, provided that all of

the devices are in Express mode. A single combined bit-

stream is used to configure the chain of Express mode

devices, but the input data bus must drive D0-D7 of each

device. Tie High the CS1 pin of the first device to be config-

ured, or leave it floating in the XC5200 since it has an inter-

nal pull-up. Connect the DOUT pin of each FPGA to the

CS1 pin of the next device in the chain. The D0-D7 inputs

are wired to each device in parallel. The DONE pins are

wired together, with one or more internal DONE pull-ups

activated. Alternatively, a 4.7 kΩ external resistor can be

used, if desired. (See Figure 37 on page 122.) CCLK pins

are tied together.

OE/T

Output

Connected

to CCLK

Reset

0

1

0

1

Active Low Output

Active High Output

etc

.

X5223

Figure 22: CCLK Generation for XC3000 Master

Driving an XC5200-Series Slave

The requirement that all DONE pins in a daisy chain be

wired together applies only to Express mode, and only if all

devices in the chain are to become active simultaneously.

All devices in Express mode are synchronized to the DONE

pin. User I/O for each device become active after the

DONE pin for that device goes High. (The exact timing is

determined by options to the bitstream generation soft-

ware.) Since the DONE pin is open-drain and does not

drive a High value, tying the DONE pins of all devices

together prevents all devices in the chain from going High

until the last device in the chain has completed its configu-

ration cycle.

Express Mode

Express mode is similar to Slave Serial mode, except the

data is presented in parallel format, and is clocked into the

target device a byte at a time rather than a bit at a time. The

data is loaded in parallel into eight different columns: it is

not internally serialized. Eight bits of configuration data are

loaded with every CCLK cycle, therefore this configuration

mode runs at eight times the data rate of the other six

modes. In this mode the XC5200 family is capable of sup-

porting a CCLK frequency of 10 MHz, which is equivalent to

an 80 MHz serial rate, because eight bits of configuration

data are being loaded per CCLK cycle. An XC5210 in the

Express mode, for instance, can be configured in about 2

ms. The Express mode does not support CRC error check-

ing, but does support constant-field error checking. A

length count is not used in Express mode.

The status pin DOUT is pulled LOW two internal-oscillator

cycles (nominally 1 MHz) after INIT is recognized as High,

and remains Low until the device’s configuration memory is

full. Then DOUT is pulled High to signal the next device in

the chain to accept the configuration data on the D7-D0

bus. All devices receive and recognize the six bytes of pre-

amble and length count, irrespective of the level on CS1;

but subsequent frame data is accepted only when CS1 is

High and the device’s configuration memory is not already

full.

In the Express configuration mode, an external signal

drives the CCLK input(s). The first byte of parallel configu-

ration data must be available at the D inputs of the FPGA

devices a short set-up time before the second rising CCLK

edge. Subsequent data bytes are clocked in on each con-

secutive rising CCLK edge. See Figure 38 on page 123.

Setting CCLK Frequency

Bitstream generation currently generates a bitstream suffi-

cient to program in all configuration modes except Express.

Extra CCLK cycles are necessary to complete the configu-

ration, since in this mode data is read at a rate of eight bits

per CCLK cycle instead of one bit per cycle. Normally the

entire start-up sequence requires a number of bits that is

equal to the number of CCLK cycles needed. An additional

five CCLKs (equivalent to 40 extra bits) will guarantee com-

pletion of configuration, regardless of the start-up options

chosen.

For Master modes, CCLK can be generated in one of three

frequencies. In the default slow mode, the frequency is

nominally 1 MHz. In fast CCLK mode, the frequency is

nominally 12 MHz. In medium CCLK mode, the frequency

is nominally 6 MHz. The frequency range is -50% to +50%.

The frequency is selected by an option when running the

bitstream generation software. If an XC5200-Series Master

is driving an XC3000- or XC2000-family slave, slow CCLK

mode must be used. Slow mode is the default.

Table 11: XC5200 Bitstream Format

Multiple slave devices with identical configurations can be

wired with parallel D0-D7 inputs. In this way, multiple

devices can be configured simultaneously.

Data Type

Value

Occurrences

Fill Byte

11111111

11110010

COUNT(23:0)

11111111

Once per bit-

stream

Preamble

Length Counter

Fill Byte

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November 5, 1998 (Version 5.2)

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XC5200 Series Field Programmable Gate Arrays

Table 11: XC5200 Bitstream Format

CCLK and address signals continue to operate externally.

The user must detect INIT and initialize a new configuration

by pulsing the PROGRAM pin Low or cycling Vcc.

Data Type

Value

Occurrences

Start Byte

11111110

Once per data

frame

Data Frame *

DATA(N-1:0)

Table 12: Internal Configuration Data Structure

Cyclic Redundancy Check or

Constant Field Check

CRC(3:0) or

0110

PROM

Size

(bits)

Xilinx

Serial PROM

Needed

Fill Nibble

1111

VersaBlock

Array

Device

Extend Write Cycle

Postamble

FFFFFF

11111110

FFFF…FF

FF

Once per de-

vice

Fill Bytes (30)

Start-Up Byte

XC5202

XC5204

XC5206

XC5210

XC5215

8 x 8

42,416

XC1765D

Once per bit-

stream

10 x 12

14 x 14

18 x 18

22 x 22

70,704

XC17128D

XC17256D

106,288

165,488

237,744

*Bits per Frame (N) depends on device size, as described for

table 11.

Data Stream Format

Bits per Frame = (34 x number of Rows) + 28 for the top + 28 for

the bottom + 4 splitter bits + 8 start bits + 4 error check bits + 4 fill

^bits* + 24 extended write bits

The data stream (“bitstream”) format is identical for all con-

figuration modes, with the exception of Express mode. In

Express mode, the device becomes active when DONE

goes High, therefore no length count is required. Addition-

ally, CRC error checking is not supported in Express mode.

= (34 x number of Rows) + 100

* In the XC5202 (8 x 8), there are 8 fill bits per frame, not 4

Number of Frames = (12 x number of Columns) + 7 for the left

edge + 8 for the right edge + 1 splitter bit

= (12 x number of Columns) + 16

The data stream formats are shown in Table 11. Express

mode data is shown with D0 at the left and D7 at the right.

For all other modes, bit-serial data is read from left to right,

and byte-parallel data is effectively assembled from this

serial bitstream, with the first bit in each byte assigned to

D0.

Program Data = (Bits per Frame x Number of Frames) + 48

header bits + 8 postamble bits + 240 fill bits + 8 start-up bits

= (Bits per Frame x Number of Frames) + 304

PROM Size = Program Data

7

Cyclic Redundancy Check (CRC) for

Configuration and Readback

The configuration data stream begins with a string of eight

ones, a preamble code, followed by a 24-bit length count

and a separator field of ones (or 24 fill bits, in Express

mode). This header is followed by the actual configuration

data in frames. The length and number of frames depends

on the device type (see Table 12). Each frame begins with

a start field and ends with an error check. In all modes

except Express mode, a postamble code is required to sig-

nal the end of data for a single device. In all cases, addi-

tional start-up bytes of data are required to provide four

clocks for the startup sequence at the end of configuration.

Long daisy chains require additional startup bytes to shift

the last data through the chain. All startup bytes are

don’t-cares; these bytes are not included in bitstreams cre-

ated by the Xilinx software.

The Cyclic Redundancy Check is a method of error detec-

tion in data transmission applications. Generally, the trans-

mitting system performs a calculation on the serial

bitstream. The result of this calculation is tagged onto the

data stream as additional check bits. The receiving system

performs an identical calculation on the bitstream and com-

pares the result with the received checksum.

Each data frame of the configuration bitstream has four

error bits at the end, as shown in Table 11. If a frame data

error is detected during the loading of the FPGA, the con-

figuration process with a potentially corrupted bitstream is

terminated. The FPGA pulls the INIT pin Low and goes into

a Wait state.

During Readback, 11 bits of the 16-bit checksum are added

to the end of the Readback data stream. The checksum is

computed using the CRC-16 CCITT polynomial, as shown

in Figure 23. The checksum consists of the 11 most signifi-

cant bits of the 16-bit code. A change in the checksum indi-

cates a change in the Readback bitstream. A comparison

to a previous checksum is meaningful only if the readback

data is independent of the current device state. CLB out-

puts should not be included (Read Capture option not

used). Statistically, one error out of 2048 might go undetec-

ted.

In Express mode, only non-CRC error checking is sup-

ported. In all other modes, a selection of CRC or non-CRC

error checking is allowed by the bitstream generation soft-

ware. The non-CRC error checking tests for a designated

end-of-frame field for each frame. For CRC error checking,

the software calculates a running CRC and inserts a unique

four-bit partial check at the end of each frame. The 11-bit

CRC check of the last frame of an FPGA includes the last

seven data bits.

Detection of an error results in the suspension of data load-

ing and the pulling down of the INIT pin. In Master modes,

November 5, 1998 (Version 5.2)

7-107

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XC5200 Series Field Programmable Gate Arrays

Initialization

X2

X15

This phase clears the configuration memory and estab-

lishes the configuration mode.

X16

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14

15

The configuration memory is cleared at the rate of one

frame per internal clock cycle (nominally 1 MHz). An

open-drain bidirectional signal, INIT, is released when the

configuration memory is completely cleared. The device

then tests for the absence of an external active-low level on

INIT. The mode lines are sampled two internal clock cycles

later (nominally 2 µs).

SERIAL DATA IN

Polynomial: X16 + X15 + X2 + 1

1

0

15 14 13 12 11 10

9

8

7

6

5

LAST DATA FRAME

CRC – CHECKSUM

X1789

Readback Data Stream

The master device waits an additional 32 µs to 256 µs

(nominally 64-128 µs) to provide adequate time for all of the

slave devices to recognize the release of INIT as well. Then

the master device enters the Configuration phase.

Figure 23: Circuit for Generating CRC-16

Configuration Sequence

There are four major steps in the XC5200-Series power-up

configuration sequence.

V

No

Boundary Scan

Instructions

Available:

CC

3V

•

Power-On Time-Out

Initialization

Configuration

Start-Up

Yes

Generate

One Time-Out Pulse

of 4 ms

PROGRAM

= Low

Yes

EXTEST*

SAMPLE/PRELOAD*

BYPASS

The full process is illustrated in Figure 24.

Completely Clear

Configuration

Memory

~1.3 µs per Frame

CONFIGURE*

Power-On Time-Out

(*only when PROGRAM = High)

INIT

High? if

Master

No

An internal power-on reset circuit is triggered when power

is applied. When V_CCreaches the voltage at which portions

Yes

of the FPGA begin to operate (i.e., performs

a

Sample

write-and-read test of a sample pair of configuration mem-

ory bits), the programmable I/O buffers are 3-stated with

active high-impedance pull-up resistors. A time-out delay

— nominally 4 ms — is initiated to allow the power-supply

voltage to stabilize. For correct operation the power supply

must reach V_CC(min) by the end of the time-out, and must

not dip below it thereafter.

Mode Lines

Master CCLK

Goes Active after

50 to 250 µs

Load One

Configuration

Data Frame

Yes

Frame

Error

Pull INIT Low

and Stop

No

There is no distinction between master and slave modes

with regard to the time-out delay. Instead, the INIT line is

used to ensure that all daisy-chained devices have com-

pleted initialization. Since XC2000 devices do not have this

signal, extra care must be taken to guarantee proper oper-

ation when daisy-chaining them with XC5200 devices. For

proper operation with XC3000 devices, the RESET signal,

which is used in XC3000 to delay configuration, should be

connected to INIT.

SAMPLE/PRELOAD

BYPASS

Config-

uration

memory

Full

No

Yes

Pass

Configuration

Data to DOUT

CCLK

Count Equals

Length

No

Count

Yes

Start-Up

Sequence

If the time-out delay is insufficient, configuration should be

delayed by holding the INIT pin Low until the power supply

has reached operating levels.

F

Operational

EXTEST

SAMPLE PRELOAD

BYPASS

If Boundary Scan

is Selected

USER 1

USER 2

CONFIGURE

READBACK

This delay is applied only on power-up. It is not applied

when reconfiguring an FPGA by pulsing the PROGRAM

pin Low. During all three phases — Power-on, Initialization,

and Configuration — DONE is held Low; HDC, LDC, and

INIT are active; DOUT is driven; and all I/O buffers are dis-

abled.

X9017

Figure 24: Configuration Sequence

7-108

November 5, 1998 (Version 5.2)

R

XC5200 Series Field Programmable Gate Arrays

Length Count Match

CCLK Period

CCLK

F

DONE

I/O

XC2000

Global Reset

F = Finished, no more

configuration clocks needed

F

DONE

I/O

Daisy-chain lead device

must have latest F

XC3000

Heavy lines describe

default timing

Global Reset

F

DONE

I/O

C1

C2

C3

C4

XC4000E/EX

XC5200/

CCLK_NOSYNC

GSR Active

C2

C3

C4

7

DONE IN

F

DONE

I/O

C1, C2 or C3

Di

XC4000E/EX

XC5200/

CCLK_SYNC

Di+1

GSR Active

Di

F

DONE

I/O

C1

U2

U3

U4

XC4000E/EX

XC5200/

UCLK_NOSYNC

U4

GSR Active

U2

U3

U4

DONE IN

F

DONE

I/O

C1

U2

XC4000E/EX

XC5200/

Di

Di+1

Di+2

UCLK_SYNC

GSR Active

Di Di+1

Synchronization

Uncertainty

UCLK Period

X6700

Figure 25: Start-up Timing

November 5, 1998 (Version 5.2)

7-109

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XC5200 Series Field Programmable Gate Arrays

Start-Up

Configuration

Start-up is the transition from the configuration process to

the intended user operation. This transition involves a

change from one clock source to another, and a change

from interfacing parallel or serial configuration data where

most outputs are 3-stated, to normal operation with I/O pins

active in the user-system. Start-up must make sure that

the user-logic ‘wakes up’ gracefully, that the outputs

become active without causing contention with the configu-

ration signals, and that the internal flip-flops are released

from the global Reset at the right time.

The length counter begins counting immediately upon entry

into the configuration state. In slave-mode operation it is

important to wait at least two cycles of the internal 1-MHz

clock oscillator after INIT is recognized before toggling

CCLK and feeding the serial bitstream. Configuration will

not begin until the internal configuration logic reset is

released, which happens two cycles after INIT goes High.

A master device’s configuration is delayed from 32 to 256

µs to ensure proper operation with any slave devices driven

by the master device.

Figure 25 describes start-up timing for the three Xilinx fam-

ilies in detail. Express mode configuration always uses

either CCLK_SYNC or UCLK_SYNC timing, the other con-

figuration modes can use any of the four timing sequences.

The 0010 preamble code, included for all modes except

Express mode, indicates that the following 24 bits repre-

sent the length count. The length count is the total number

of configuration clocks needed to load the complete config-

uration data. (Four additional configuration clocks are

required to complete the configuration process, as dis-

cussed below.) After the preamble and the length count

have been passed through to all devices in the daisy chain,

DOUT is held High to prevent frame start bits from reaching

any daisy-chained devices. In Express mode, the length

count bits are ignored, and DOUT is held Low, to disable

the next device in the pseudo daisy chain.

To access the internal start-up signals, place the STARTUP

library symbol.

Start-up Timing

Different FPGA families have different start-up sequences.

The XC2000 family goes through a fixed sequence. DONE

goes High and the internal global Reset is de-activated one

CCLK period after the I/O become active.

A specific configuration bit, early in the first frame of a mas-

ter device, controls the configuration-clock rate and can

increase it by a factor of eight. Therefore, if a fast configu-

ration clock is selected by the bitstream, the slower clock

rate is used until this configuration bit is detected.

The XC3000A family offers some flexibility. DONE can be

programmed to go High one CCLK period before or after

the I/O become active. Independent of DONE, the internal

global Reset is de-activated one CCLK period before or

after the I/O become active.

Each frame has a start field followed by the frame-configu-

ration data bits and a frame error field. If a frame data error

is detected, the FPGA halts loading, and signals the error

by pulling the open-drain INIT pin Low. After all configura-

tion frames have been loaded into an FPGA, DOUT again

follows the input data so that the remaining data is passed

on to the next device. In Express mode, when the first

device is fully programmed, DOUT goes High to enable the

next device in the chain.

The XC4000/XC5200 Series offers additional flexibility.

The three events — DONE going High, the internal Reset

being de-activated, and the user I/O going active — can all

occur in any arbitrary sequence. Each of them can occur

one CCLK period before or after, or simultaneous with, any

of the others. This relative timing is selected by means of

software options in the bitstream generation software.

The default option, and the most practical one, is for DONE

to go High first, disconnecting the configuration data source

and avoiding any contention when the I/Os become active

one clock later. Reset is then released another clock period

later to make sure that user-operation starts from stable

internal conditions. This is the most common sequence,

shown with heavy lines in Figure 25, but the designer can

modify it to meet particular requirements.

Delaying Configuration After Power-Up

To delay master mode configuration after power-up, pull

the bidirectional INIT pin Low, using an open-collector

(open-drain) driver. (See Figure 12.)

Using an open-collector or open-drain driver to hold INIT

Low before the beginning of master mode configuration

causes the FPGA to wait after completing the configuration

memory clear operation. When INIT is no longer held Low

externally, the device determines its configuration mode by

capturing its mode pins, and is ready to start the configura-

tion process. A master device waits up to an additional 250

µs to make sure that any slaves in the optional daisy chain

have seen that INIT is High.

Normally, the start-up sequence is controlled by the internal

device oscillator output (CCLK), which is asynchronous to

the system clock.

XC4000/XC5200 Series offers another start-up clocking

option, UCLK_NOSYNC. The three events described

above need not be triggered by CCLK. They can, as a con-

figuration option, be triggered by a user clock. This means

that the device can wake up in synchronism with the user

system.

7-110

November 5, 1998 (Version 5.2)

R

XC5200 Series Field Programmable Gate Arrays

When the UCLK_SYNC option is enabled, the user can

externally hold the open-drain DONE output Low, and thus

stall all further progress in the start-up sequence until

DONE is released and has gone High. This option can be

used to force synchronization of several FPGAs to a com-

mon user clock, or to guarantee that all devices are suc-

cessfully configured before any I/Os go active.

ship between CCLK and the user clock. This arbitration

causes an unavoidable one-cycle uncertainty in the timing

of the rest of the start-up sequence.

DONE Goes High to Signal End of Configuration

In all configuration modes except Express mode,

XC5200-Series devices read the expected length count

from the bitstream and store it in an internal register. The

length count varies according to the number of devices and

the composition of the daisy chain. Each device also

counts the number of CCLKs during configuration.

If either of these two options is selected, and no user clock

is specified in the design or attached to the device, the chip

could reach a point where the configuration of the device is

complete and the Done pin is asserted, but the outputs do

not become active. The solution is either to recreate the

bitstream specifying the start-up clock as CCLK, or to sup-

ply the appropriate user clock.

Two conditions have to be met in order for the DONE pin to

go high:

•

the chip's internal memory must be full, and

the configuration length count must be met, exactly.

Start-up Sequence

This is important because the counter that determines

when the length count is met begins with the very first

CCLK, not the first one after the preamble.

The Start-up sequence begins when the configuration

memory is full, and the total number of configuration clocks

received since INIT went High equals the loaded value of

the length count.

Therefore, if a stray bit is inserted before the preamble, or

the data source is not ready at the time of the first CCLK,

the internal counter that holds the number of CCLKs will be

one ahead of the actual number of data bits read. At the

end of configuration, the configuration memory will be full,

but the number of bits in the internal counter will not match

the expected length count.

The next rising clock edge sets a flip-flop Q0, shown in

Figure 26. Q0 is the leading bit of a 5-bit shift register. The

outputs of this register can be programmed to control three

events.

•

The release of the open-drain DONE output

The change of configuration-related pins to the user

function, activating all IOBs.

7

As a consequence, a Master mode device will continue to

send out CCLKs until the internal counter turns over to

•

The termination of the global Set/Reset initialization of

all CLB and IOB storage elements.

zero, and then reaches the correct length count a second

24

time. This will take several seconds [2

CCLK period]

The DONE pin can also be wire-ANDed with DONE pins of

other FPGAs or with other external signals, and can then

be used as input to bit Q3 of the start-up register. This is

called “Start-up Timing Synchronous to Done In” and is

selected by either CCLK_SYNC or UCLK_SYNC.

— which is sometimes interpreted as the device not config-

uring at all.

If it is not possible to have the data ready at the time of the

first CCLK, the problem can be avoided by increasing the

number in the length count by the appropriate value.

When DONE is not used as an input, the operation is called

“Start-up Timing Not Synchronous to DONE In,” and is

selected by either CCLK_NOSYNC or UCLK_NOSYNC.

In Express mode, there is no length count. The DONE pin

for each device goes High when the device has received its

quota of configuration data. Wiring the DONE pins of sev-

eral devices together delays start-up of all devices until all

are fully configured.

As a configuration option, the start-up control register

beyond Q0 can be clocked either by subsequent CCLK

pulses or from an on-chip user net called STARTUP.CLK.

These signals can be accessed by placing the STARTUP

library symbol.

Note that DONE is an open-drain output and does not go

High unless an internal pull-up is activated or an external

pull-up is attached. The internal pull-up is activated as the

default by the bitstream generation software.

Start-up from CCLK

If CCLK is used to drive the start-up, Q0 through Q3 pro-

vide the timing. Heavy lines in Figure 25 show the default

timing, which is compatible with XC2000 and XC3000

devices using early DONE and late Reset. The thin lines

indicate all other possible timing options.

Release of User I/O After DONE Goes High

By default, the user I/O are released one CCLK cycle after

the DONE pin goes High. If CCLK is not clocked after

DONE goes High, the outputs remain in their initial state —

3-stated, with a 20 kΩ - 100 kΩ pull-up. The delay from

Start-up from a User Clock (STARTUP.CLK)

When, instead of CCLK, a user-supplied start-up clock is

selected, Q1 is used to bridge the unknown phase relation-

November 5, 1998 (Version 5.2)

7-111

R

XC5200 Series Field Programmable Gate Arrays

DONE High to active user I/O is controlled by an option to

the bitstream generation software.

Q3

Q2

Q1/Q4

DONE

IN

STARTUP

IOBs OPERATIONAL PER CONFIGURATION

*

GLOBAL RESET OF

ALL CLB FLIP-FLOPS/LATCHES

1

0

GR ENABLE

GR INVERT

STARTUP.GR

CONTROLLED BY STARTUP SYMBOL

IN THE USER SCHEMATIC (SEE

LIBRARIES GUIDE)

STARTUP.GTS

GTS INVERT

GTS ENABLE

0

1

GLOBAL 3-STATE OF ALL IOBs

Q

S

R

DONE

" FINISHED "

ENABLES BOUNDARY

SCAN, READBACK AND

CONTROLS THE OSCILLATOR

*

1

0

1

0

Q0

Q1

Q2

Q3

Q4

1

FULL

LENGTH COUNT

S

Q

D

Q

D

Q

D

Q

D

Q

0

M

K

*

CLEAR MEMORY

CCLK

0

1

STARTUP.CLK

USER NET

M

CONFIGURATION BIT OPTIONS SELECTED BY USER

X9002

*

Figure 26: Start-up Logic

Release of Global Reset After DONE Goes High

Configuration Through the Boundary Scan

Pins

By default, Global Reset (GR) is released two CCLK cycles

after the DONE pin goes High. If CCLK is not clocked twice

after DONE goes High, all flip-flops are held in their initial

reset state. The delay from DONE High to GR inactive is

controlled by an option to the bitstream generation soft-

ware.

XC5200-Series devices can be configured through the

boundary scan pins.

For detailed information, refer to the Xilinx application note

XAPP017, “Boundary Scan in XC4000 and XC5200

Devices.”

Configuration Complete After DONE Goes High

Readback

Three full CCLK cycles are required after the DONE pin

goes High, as shown in Figure 25 on page 109. If CCLK is

not clocked three times after DONE goes High, readback

cannot be initiated and most boundary scan instructions

cannot be used.

The user can read back the content of configuration mem-

ory and the level of certain internal nodes without interfer-

ing with the normal operation of the device.

Readback not only reports the downloaded configuration

bits, but can also include the present state of the device,

represented by the content of all flip-flops and latches in

CLBs.

7-112

November 5, 1998 (Version 5.2)

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XC5200 Series Field Programmable Gate Arrays

Note that in XC5200-Series devices, configuration data is

not inverted with respect to configuration as it is in XC2000

and XC3000 families.

The readback signals are located in the lower-left corner of

the device.

Read Abort

Readback of Express mode bitstreams results in data that

does not resemble the original bitstream, because the bit-

stream format differs from other modes.

When the Read Abort option is selected, a High-to-Low

transition on RDBK.TRIG terminates the readback opera-

tion and prepares the logic to accept another trigger.

XC5200-Series Readback does not use any dedicated

pins, but uses four internal nets (RDBK.TRIG,

RDBK.DATA, RDBK.RIP and RDBK.CLK) that can be

routed to any IOB. To access the internal Readback sig-

nals, place the READBACK library symbol and attach the

appropriate pad symbols, as shown in Figure 27.

After an aborted readback, additional clocks (up to one

readback clock per configuration frame) may be required to

re-initialize the control logic. The status of readback is indi-

cated by the output control net RDBK.RIP. RDBK.RIP is

High whenever a readback is in progress.

Clock Select

After Readback has been initiated by a Low-to-High transi-

tion on RDBK.TRIG, the RDBK.RIP (Read In Progress)

output goes High on the next rising edge of RDBK.CLK.

Subsequent rising edges of this clock shift out Readback

data on the RDBK.DATA net.

CCLK is the default clock. However, the user can insert

another clock on RDBK.CLK. Readback control and data

are clocked on rising edges of RDBK.CLK. If readback

must be inhibited for security reasons, the readback control

nets are simply not connected.

Readback data does not include the preamble, but starts

with five dummy bits (all High) followed by the Start bit

(Low) of the first frame. The first two data bits of the first

frame are always High.

Violating the Maximum High and Low Time

Specification for the Readback Clock

Each frame ends with four error check bits. They are read

back as High. The last seven bits of the last frame are also

read back as High. An additional Start bit (Low) and an

11-bit Cyclic Redundancy Check (CRC) signature follow,

before RDBK.RIP returns Low.

The readback clock has a maximum High and Low time

specification. In some cases, this specification cannot be

met. For example, if a processor is controlling readback,

an interrupt may force it to stop in the middle of a readback.

This necessitates stopping the clock, and thus violating the

specification.

7

IF UNCONNECTED,

DEFAULT IS CCLK

The specification is mandatory only on clocking data at the

end of a frame prior to the next start bit. The transfer mech-

anism will load the data to a shift register during the last six

clock cycles of the frame, prior to the start bit of the follow-

ing frame. This loading process is dynamic, and is the

source of the maximum High and Low time requirements.

DATA

RIP

READ_DATA

X1786

CLK

MD1

READBACK

OBUF

READ_TRIGGER

TRIG

MD0

IBUF

Figure 27: Readback Schematic Example

Therefore, the specification only applies to the six clock

cycles prior to and including any start bit, including the

clocks before the first start bit in the readback data stream.

At other times, the frame data is already in the register and

the register is not dynamic. Thus, it can be shifted out just

like a regular shift register.

Readback Options

Readback options are: Read Capture, Read Abort, and

Clock Select. They are set with the bitstream generation

software.

The user must precisely calculate the location of the read-

back data relative to the frame. The system must keep

track of the position within a data frame, and disable inter-

rupts before frame boundaries. Frame lengths and data for-

mats are listed in Table 11 and Table 12.

Read Capture

When the Read Capture option is selected, the readback

data stream includes sampled values of CLB and IOB sig-

nals. The rising edge of RDBK.TRIG latches the inverted

values of the CLB outputs and the IOB output and input sig-

nals.

Note that while the bits describing configuration

Readback with the XChecker Cable

(interconnect and function generators) are not inverted, the

CLB and IOB output signals are inverted.

The XChecker Universal Download/Readback Cable and

Logic Probe uses the readback feature for bitstream verifi-

cation. It can also display selected internal signals on the

PC or workstation screen, functioning as a low-cost in-cir-

cuit emulator.

When the Read Capture option is not selected, the values

of the capture bits reflect the configuration data originally

written to those memory locations.

November 5, 1998 (Version 5.2)

7-113

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XC5200 Series Field Programmable Gate Arrays

There is an internal delay of 0.5 CCLK periods, which

means that DOUT changes on the falling CCLK edge, and

the next FPGA in the daisy chain accepts data on the sub-

sequent rising CCLK edge.

Configuration Timing

The seven configuration modes are discussed in detail in

this section. Timing specifications are included.

Figure 28 shows

XC5200-Series device in Slave Serial mode should be con-

nected as shown in the third device from the left.

a

full master/slave system. An

Slave Serial Mode

In Slave Serial mode, an external signal drives the CCLK

input of the FPGA. The serial configuration bitstream must

be available at the DIN input of the lead FPGA a short

setup time before each rising CCLK edge.

Slave Serial mode is selected by a <111> on the mode pins

(M2, M1, M0). Slave Serial is the default mode if the mode

pins are left unconnected, as they have weak pull-up resis-

tors during configuration.

The lead FPGA then presents the preamble data—and all

data that overflows the lead device—on its DOUT pin.

NOTE:

M2, M1, M0 can be shorted

to VCC if not used as I/O

M2, M1, M0 can be shorted

to Ground if not used as I/O

VCC

3.3 KΩ

N/C

3.3 KΩ

M0 M1

3.3 KΩ

M0 M1

M2

M0 M1

M2

PWRDN

DOUT

M2

N/C

DOUT

DIN

DOUT

DIN

CCLK

VCC

4.7 KΩ

XC5200

MASTER

SERIAL

Spartan,

XC1700E

+5 V

XC3100A

SLAVE

XC4000E/EX,

XC5200

CLK

DATA

CE

VPP

CEO

CCLK

SLAVE

DIN

LDC

INIT

PROGRAM

DONE

PROGRAM

RESET

D/P

RESET/OE

DONE

INIT

(Low Reset Option Used)

PROGRAM

X9003_01

Figure 28: Master/Slave Serial Mode Circuit Diagram

DIN

Bit n

Bit n + 1

1

2

5

T

CCL

DCC

CCD

CCLK

4

3

T

CCH

CCO

DOUT

(Output)

Bit n - 1

Bit n

X5379

Description

DIN setup

Symbol

Min

20

0

Max

30

Units

ns

1

2

3

4

5

T_DCC

T_CCD

T_CCO

T_CCH

T_CCL

F_CC

DIN hold

ns

DIN to DOUT

High time

Low time

ns

CCLK

45

ns

Frequency

10

MHz

Note: Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.

Figure 29: Slave Serial Mode Programming Switching Characteristics

7-114

November 5, 1998 (Version 5.2)

R

XC5200 Series Field Programmable Gate Arrays

The value increases from a nominal 1 MHz, to a nominal 12

MHz. Be sure that the serial PROM and slaves are fast

enough to support this data rate. The Medium ConfigRate

option changes the frequency to a nominal 6 MHz.

XC2000, XC3000/A, and XC3100A devices do not support

the Fast or Medium ConfigRate options.

Master Serial Mode

In Master Serial mode, the CCLK output of the lead FPGA

drives a Xilinx Serial PROM that feeds the FPGA DIN input.

Each rising edge of the CCLK output increments the Serial

PROM internal address counter. The next data bit is put on

the SPROM data output, connected to the FPGA DIN pin.

The lead FPGA accepts this data on the subsequent rising

CCLK edge.

The SPROM CE input can be driven from either LDC or

DONE. Using LDC avoids potential contention on the DIN

pin, if this pin is configured as user-I/O, but LDC is then

restricted to be a permanently High user output after con-

figuration. Using DONE can also avoid contention on DIN,

provided the DONE before I/O enable option is invoked.

The lead FPGA then presents the preamble data—and all

data that overflows the lead device—on its DOUT pin.

There is an internal pipeline delay of 1.5 CCLK periods,

which means that DOUT changes on the falling CCLK

edge, and the next FPGA in the daisy chain accepts data

on the subsequent rising CCLK edge.

Figure 28 on page 114 shows a full master/slave system.

The leftmost device is in Master Serial mode.

Master Serial mode is selected by a <000> on the mode

pins (M2, M1, M0).

In the bitstream generation software, the user can specify

Fast ConfigRate, which, starting several bits into the first

frame, increases the CCLK frequency by a factor of twelve.

CCLK

(Output)

T

2

CKDS

T

DSCK

1

Serial Data In

n

n + 1

n + 2

7

Serial DOUT

(Output)

n – 3

n – 2

n – 1

n

X3223

Description

DIN setup

DIN hold

Symbol

Min

20

0

Max

Units

ns

1

2

T

DSCK

CCLK

T_CKDS

ns

Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAM

Low until Vcc is valid.

2. Master Serial mode timing is based on testing in slave mode.

Figure 30: Master Serial Mode Programming Switching Characteristics

In the two Master Parallel modes, the lead FPGA directly

addresses an industry-standard byte-wide EPROM, and

accepts eight data bits just before incrementing or decre-

menting the address outputs.

The PROM address pins can be incremented or decre-

mented, depending on the mode pin settings. This option

allows the FPGA to share the PROM with a wide variety of

microprocessors and microcontrollers. Some processors

must boot from the bottom of memory (all zeros) while oth-

ers must boot from the top. The FPGA is flexible and can

load its configuration bitstream from either end of the mem-

ory.

The eight data bits are serialized in the lead FPGA, which

then presents the preamble data—and all data that over-

flows the lead device—on its DOUT pin. There is an inter-

nal delay of 1.5 CCLK periods, after the rising CCLK edge

that accepts a byte of data (and also changes the EPROM

address) until the falling CCLK edge that makes the LSB

(D0) of this byte appear at DOUT. This means that DOUT

changes on the falling CCLK edge, and the next FPGA in

the daisy chain accepts data on the subsequent rising

CCLK edge.

Master Parallel Up mode is selected by a <100> on the

mode pins (M2, M1, M0). The EPROM addresses start at

00000 and increment.

Master Parallel Down mode is selected by a <110> on the

mode pins. The EPROM addresses start at 3FFFF and

decrement.

November 5, 1998 (Version 5.2)

7-115

R

XC5200 Series Field Programmable Gate Arrays

TO DIN OF OPTIONAL

DAISY-CHAINED FPGAS

HIGH

or

3.3 K

N/C

M2

LOW

N/C

M0 M1

TO CCLK OF OPTIONAL

DAISY-CHAINED FPGAS

CCLK

DOUT

NOTE:M0 can be shorted

to Ground if not used

as I/O.

M0 M1 M2

. . .

A17

A16

A15

A14

A13

A12

A11

A10

A9

XC5200

Master

Parallel

DIN

DOUT

VCC

EPROM

(8K x 8)

(OR LARGER)

CCLK

4.7K

XC5200/

XC4000E/EX/

Spartan

USER CONTROL OF HIGHER

ORDER PROM ADDRESS BITS

CAN BE USED TO SELECT BETWEEN

ALTERNATIVE CONFIGURATIONS

INIT

A12

A11

A10

A9

SLAVE

PROGRAM

DONE

INIT

D7

D6

D5

D4

D3

D2

D1

D0

A8

A7

D7

D6

D5

D4

D3

D2

D1

D0

A6

A5

A4

A3

A2

A1

A0

DONE

OE

CE

DATA BUS

8

PROGRAM

X9004_01

Figure 31: Master Parallel Mode Circuit Diagram

7-116

November 5, 1998 (Version 5.2)

R

XC5200 Series Field Programmable Gate Arrays

.

A0-A17

(output)

Address for Byte n

Address for Byte n + 1

1

T

RAC

D0-D7

Byte

3

T

2

T

RCD

DRC

RCLK

(output)

7 CCLKs

CCLK

(output)

DOUT

(output)

D6

D7

Byte n - 1

X6078

Description

Delay to Address valid

Data setup time

Symbol

T_RAC

Min

Max

200

Units

1

2

3

0

60

0

ns

CCLK

T_DRC

Data hold time

T_RCD

7

Note: 1. At power-up, V_CCmust rise from 2.0 V to V_CCmin in less then 25 ms, otherwise delay configuration by pulling PROGRAM

Low until V_CCis Valid.

2. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).

This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than

500 ns. EPROM data output has no hold-time requirements.

Figure 32: Master Parallel Mode Programming Switching Characteristics

November 5, 1998 (Version 5.2)

7-117

R

XC5200 Series Field Programmable Gate Arrays

Synchronous Peripheral Mode

for test purposes. Note that RDY/BUSY is pulled High with

a high-impedance pullup prior to INIT going High.

Synchronous Peripheral mode can also be considered

Slave Parallel mode. An external signal drives the CCLK

input(s) of the FPGA(s). The first byte of parallel configura-

tion data must be available at the Data inputs of the lead

FPGA a short setup time before the rising CCLK edge.

Subsequent data bytes are clocked in on every eighth con-

secutive rising CCLK edge.

The lead FPGA serializes the data and presents the pre-

amble data (and all data that overflows the lead device) on

its DOUT pin. There is an internal delay of 1.5 CCLK peri-

ods, which means that DOUT changes on the falling CCLK

edge, and the next FPGA in the daisy chain accepts data

on the subsequent rising CCLK edge.

In order to complete the serial shift operation, 10 additional

CCLK rising edges are required after the last data byte has

been loaded, plus one more CCLK cycle for each

daisy-chained device.

The same CCLK edge that accepts data, also causes the

RDY/BUSY output to go High for one CCLK period. The pin

name is a misnomer. In Synchronous Peripheral mode it is

really an ACKNOWLEDGE signal. Synchronous operation

does not require this response, but it is a meaningful signal

Synchronous Peripheral mode is selected by a <011> on

the mode pins (M2, M1, M0).

NOTE:

M2 can be shorted to Ground

if not used as I/O

N/C

3.3 kΩ

M0 M1

M2

M0 M1

CCLK

M2

CCLK

CLOCK

OPTIONAL

DAISY-CHAINED

FPGAs

8

DATA BUS

D

0-7

DIN

DOUT

V

CC

XC5200

SYNCHRO-

NOUS

PERIPHERAL

XC5200E/EX

SLAVE

4.7 kΩ

RDY/BUSY

CONTROL

SIGNALS

DONE

INIT

DONE

INIT

3.3 kΩ

PROGRAM

X9005

Figure 33: Synchronous Peripheral Mode Circuit Diagram

7-118

November 5, 1998 (Version 5.2)

R

XC5200 Series Field Programmable Gate Arrays

T

CCL

CCLK

INIT

1

T

IC

T

CD

3

2

T

DC

BYTE

0

BYTE

1

D0 - D7

BYTE 0 OUT

BYTE 1 OUT

1

0

1

2

3

4

5

6

7

DOUT

RDY/BUSY

X6096

Description

INIT (High) setup time

D0 - D7 setup time

D0 - D7 hold time

CCLK High time

Symbol

Min

5

Max

Units

µs

1

2

3

T_IC

T_DC

T_CD

60

0

ns

CCLK

T_CCH

T_CCL

F_CC

50

60

ns

CCLK Low time

ns

CCLK Frequency

8

MHz

7

Notes: 1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the

first data byte on the second rising edge of CCLK after INIT goes high. Subsequent data bytes are clocked in on every

eighth consecutive rising edge of CCLK.

2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does

not require such a response.

3. The pin name RDY/BUSY is a misnomer. In synchronous peripheral mode this is really an ACKNOWLEDGE signal.

4.Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore,

additional CCLK pulses are clearly required after the last byte has been loaded.

Figure 34: Synchronous Peripheral Mode Programming Switching Characteristics

November 5, 1998 (Version 5.2)

7-119

R

XC5200 Series Field Programmable Gate Arrays

The READY/BUSY handshake can be ignored if the delay

from any one Write to the end of the next Write is guaran-

teed to be longer than 10 CCLK periods.

Asynchronous Peripheral Mode

Write to FPGA

Asynchronous Peripheral mode uses the trailing edge of

the logic AND condition of WS and CS0 being Low and RS

and CS1 being High to accept byte-wide data from a micro-

processor bus. In the lead FPGA, this data is loaded into a

Status Read

The logic AND condition of the CS0, CS1 and RS inputs

puts the device status on the Data bus.

double-buffered UART-like parallel-to-serial converter and

is serially shifted into the internal logic.

•

D7 High indicates Ready

D7 Low indicates Busy

D0 through D6 go unconditionally High

The lead FPGA presents the preamble data (and all data

that overflows the lead device) on its DOUT pin. The

RDY/BUSY output from the lead FPGA acts as a hand-

shake signal to the microprocessor. RDY/BUSY goes Low

when a byte has been received, and goes High again when

the byte-wide input buffer has transferred its information

into the shift register, and the buffer is ready to receive new

data. A new write may be started immediately, as soon as

the RDY/BUSY output has gone Low, acknowledging

receipt of the previous data. Write may not be terminated

until RDY/BUSY is High again for one CCLK period. Note

that RDY/BUSY is pulled High with a high-impedance

pull-up prior to INIT going High.

It is mandatory that the whole start-up sequence be started

and completed by one byte-wide input. Otherwise, the pins

used as Write Strobe or Chip Enable might become active

outputs and interfere with the final byte transfer. If this

transfer does not occur, the start-up sequence is not com-

pleted all the way to the finish (point F in Figure 25 on page

109).

In this case, at worst, the internal reset is not released. At

best, Readback and Boundary Scan are inhibited. The

length-count value, as generated by the software, ensures

that these problems never occur.

Although RDY/BUSY is brought out as a separate signal,

microprocessors can more easily read this information on

one of the data lines. For this purpose, D7 represents the

RDY/BUSY status when RS is Low, WS is High, and the

two chip select lines are both active.

The length of the BUSY signal depends on the activity in

the UART. If the shift register was empty when the new

byte was received, the BUSY signal lasts for only two

CCLK periods. If the shift register was still full when the

new byte was received, the BUSY signal can be as long as

nine CCLK periods.

Asynchronous Peripheral mode is selected by a <101> on

the mode pins (M2, M1, M0).

Note that after the last byte has been entered, only seven

of its bits are shifted out. CCLK remains High with DOUT

equal to bit 6 (the next-to-last bit) of the last byte entered.

N/C

M0

N/C

3.3 kΩ

M1

M0

CCLK

DIN

M1

M2

8

DATA

BUS

CCLK

D0–7

OPTIONAL

DAISY-CHAINED

FPGAs

DOUT

VCC

ADDRESS

DECODE

LOGIC

CS0

XC5200

ADDRESS

BUS

ASYNCHRO-

NOUS

PERIPHERAL

XC5200/

XC4000E/EX

SLAVE

4.7 kΩ

CS1

RS

WS

CONTROL

SIGNALS

RDY/BUSY

INIT

DONE

REPROGRAM

PROGRAM

3.3 kΩ

X9006

Figure 35: Asynchronous Peripheral Mode Circuit Diagram

7-120

November 5, 1998 (Version 5.2)

R

XC5200 Series Field Programmable Gate Arrays

Write to LCA

Read Status

RS, CS0

WS/CS0

RS, CS1

WS, CS1

1

T

CA

3

T

4

7

CD

2

T

DC

READY

BUSY

D7

D0-D7

CCLK

4

T

WTRB

6

T

BUSY

RDY/BUSY

DOUT

Previous Byte D6

D7

D0

D1

D2

X6097

Description

Symbol

Min

Max

Units

Effective Write time

1

T

100

ns

CA

(CSO, WS=Low; RS, CS1=High

Write

DIN setup time

DIN hold time

2

3

4

T

60

0

ns

DC

CD

7

RDY/BUSY delay after end of

Write or Read

T

60

9

WTRB

RDY/BUSY active after beginning

of Read

7

6

ns

RDY

RDY/BUSY Low output (Note 4)

T

2

CCLK

BUSY

periods

Notes: 1. Configuration must be delayed until INIT pins of all daisy-chained FPGAs are high.

2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte processing

and the phase of internal timing generator for CCLK.

3. CCLK and DOUT timing is tested in slave mode.

4. T_BUSYindicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest T_BUSY

occurs when a byte is loaded into an empty parallel-to-serial converter. The longest T_BUSYoccurs when a new word is

loaded into the input register before the second-level buffer has started shifting out data.

This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS. RDY/BUSY will

go active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but write

may not be terminated until RDY/BUSY has been High for one CCLK period.

Figure 36: Asynchronous Peripheral Mode Programming Switching Characteristics

November 5, 1998 (Version 5.2)

7-121

R

XC5200 Series Field Programmable Gate Arrays

Express Mode

ration memory is not already full. The status pin DOUT is

pulled Low two internal-oscillator cycles after INIT is recog-

nized as High, and remains Low until the device’s configu-

ration memory is full. DOUT is then pulled High to signal

the next device in the chain to accept the configuration data

on the D0-D7 bus.

Express mode is similar to Slave Serial mode, except that

data is processed one byte per CCLK cycle instead of one

bit per CCLK cycle. An external source is used to drive

CCLK, while byte-wide data is loaded directly into the con-

figuration data shift registers. A CCLK frequency of 10

MHz is equivalent to an 80 MHz serial rate, because eight

bits of configuration data are loaded per CCLK cycle.

Express mode does not support CRC error checking, but

does support constant-field error checking.

The DONE pins of all devices in the chain should be tied

together, with one or more active internal pull-ups. If a

large number of devices are included in the chain, deacti-

vate some of the internal pull-ups, since the Low-driving

DONE pin of the last device in the chain must sink the cur-

rent from all pull-ups in the chain. The DONE pull-up is

activated by default. It can be deactivated using an option

in the bitstream generation software.

In Express mode, an external signal drives the CCLK input

of the FPGA device. The first byte of parallel configuration

data must be available at the D inputs of the FPGA a short

setup time before the second rising CCLK edge. Subse-

quent data bytes are clocked in on each consecutive rising

CCLK edge.

XC5200 devices in Express mode are always synchronized

to DONE. The device becomes active after DONE goes

High. DONE is an open-drain output. With the DONE pins

tied together, therefore, the external DONE signal stays low

until all devices are configured, then all devices in the daisy

chain become active simultaneously. If the DONE pin of a

device is left unconnected, the device becomes active as

soon as that device has been configured.

If the first device is configured in Express mode, additional

devices may be daisy-chained only if every device in the

chain is also configured in Express mode. CCLK pins are

tied together and D0-D7 pins are tied together for all

devices along the chain. A status signal is passed from

DOUT to CS1 of successive devices along the chain. The

lead device in the chain has its CS1 input tied High (or float-

ing, since there is an internal pullup). Frame data is

accepted only when CS1 is High and the device’s configu-

Express mode is selected by a <010> on the mode pins

(M2, M1, M0).

VCC

NOTE:

M2, M1, M0 can be shorted

to Ground if not used as I/O

3.3 kΩ

8

To Additional

Optional

Daisy-Chained

Devices

M0

M1

M2

M0

M1

M2

CS1

D0-D7

CS1

D0-D7

DOUT

8

DATA BUS

Optional

Daisy-Chained

XC5200

VCC

XC5200

4.7KΩ

PROGRAM

INIT

PROGRAM

INIT

PROGRAM

INIT

DONE

CCLK

To Additional

Optional

Daisy-Chained

Devices

CCLK

X6611_01

Figure 37: Express Mode Circuit Diagram

7-122

November 5, 1998 (Version 5.2)

R

XC5200 Series Field Programmable Gate Arrays

CCLK

INIT

1

T

IC

T

3

CD

2

T

DC

BYTE

0

BYTE

1

BYTE

2

BYTE

3

D0-D7

Serial Data Out

(DOUT)

FPGA Filled

Internal INIT

RDY/BUSY

CS1

X5087

Description

Symbol

1 T_IC

Min

5

Max

Units

µs

INIT (High) Setup time required

DIN Setup time required

DIN hold time required

CCLK High time

2

3

T_DC

T_CD

30

0

ns

7

CCLK

T

30

ns

CCH

CCLK Low time

T

ns

CCL

CCLK frequency

F

10

MHz

CC

Note: If not driven by the preceding DOUT, CS1 must remain high until the device is fully configured.

Figure 38: Express Mode Programming Switching Characteristics

November 5, 1998 (Version 5.2)

7-123

R

XC5200 Series Field Programmable Gate Arrays

Table 13. Pin Functions During Configuration

CONFIGURATION MODE: <M2:M1:M0>

USER

OPERATION

SLAVE

<1:1:1>

MASTER-SER SYN.PERIPH ASYN.PERIPH MASTER-HIGH MASTER-LOW

EXPRESS

<0:1:0>

<0:0:0>

<0:1:1>

<1:0:1>

<1:1:0>

<1:0:0>

A16

A17

TDI

A16

A17

TDI

GCK1-I/O

I/O

TDI-I/O

TCK-I/O

TMS-I/O

I/O

TDI

TCK

TMS

TDI

TCK

TMS

TDI

TCK

TMS

TDI

TCK

TMS

TDI

TCK

TMS

TCK

TMS

TCK

TMS

M1 (HIGH) (I)

M0 (HIGH) (I)

M2 (HIGH) (I)

M1 (LOW) (I)

M0 (LOW) (I)

M2 (LOW) (I)

M1 (HIGH) (I)

M0 (HIGH) (I)

M2 (LOW) (I)

M1 (LOW) (I)

M0 (HIGH) (I)

M2 (HIGH) (I)

M1 (HIGH) (I)

M0 (LOW) (I)

M2 (HIGH) (I)

M1 (LOW) (I)

M0 (LOW) (I)

M2 (HIGH) (I)

M1 (HIGH) (I)

M0 (LOW) (I)

M2 (LOW) (I)

I/O

GCK2-I/O

I/O

HDC (HIGH)

LDC (LOW)

INIT-ERROR

HDC (HIGH)

LDC (LOW)

INIT-ERROR

HDC (HIGH)

LDC (LOW)

INIT-ERROR

HDC (HIGH)

LDC (LOW)

INIT-ERROR

HDC (HIGH)

LDC (LOW)

INIT-ERROR

HDC (HIGH)

LDC (LOW)

INIT-ERROR

HDC (HIGH)

LDC (LOW)

INIT-ERROR

I/O

DONE

PROGRAM

I/O

PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I)

DATA 7 (I)

GCK3-I/O

I/O

DATA 6 (I)

DATA 5 (I)

DATA 6 (I)

DATA 5 (I)

CSO (I)

DATA 6 (I)

DATA 5 (I)

DATA 6 (I)

DATA 5 (I)

DATA 6 (I)

DATA 5 (I)

I/O

DATA 4 (I)

DATA 3 (I)

DATA 4 (I)

DATA 3 (I)

RS (I)

DATA 4 (I)

DATA 3 (I)

DATA 4 (I)

DATA 3 (I)

DATA 4 (I)

DATA 3 (I)

I/O

DATA 2 (I)

DATA 1 (I)

RDY/BUSY

DATA 0 (I)

DOUT

DATA 2 (I)

DATA 1 (I)

RDY/BUSY

DATA 0 (I)

DOUT

DATA 2 (I)

DATA 1 (I)

RCLK

DATA 0 (I)

DOUT

CCLK (O)

TDO

A0

DATA 2 (I)

DATA 1 (I)

RCLK

DATA 0 (I)

DOUT

CCLK (O)

TDO

A0

DATA 2 (I)

DATA 1 (I)

I/O

DIN (I)

DOUT

CCLK (I)

TDO

DIN (I)

DOUT

DATA 0 (I)

DOUT

I/O

CCLK (O)

TDO

CCLK (I)

TDO

CCLK (O)

TDO

CCLK (I)

TDO

CCLK (I)

TDO-I/O

I/O

WS (I)

A1

GCK4-I/O

I/O

CS1 (I)

A2

CS1 (I)

A3

I/O

A4

I/O

A5

I/O

A6

I/O

A7

I/O

A8

I/O

A9

I/O

A10

I/O

A11

I/O

A12

I/O

A13

I/O

A14

I/O

A15

I/O

ALL OTHERS

Notes: 1. A shaded table cell represents a 20-kΩ to 100-kΩ pull-up resistor before and during configuration.

2. (I) represents an input (O) represents an output.

3. INIT is an open-drain output during configuration.

7-124

November 5, 1998 (Version 5.2)

R

XC5200 Series Field Programmable Gate Arrays

Configuration Switching Characteristics

T

Vcc

PROGRAM

INIT

POR

RE-PROGRAM

>300 ns

T

PI

T

ICCK

CCLK

CCLK OUTPUT or INPUT

<300 ns

M0, M1, M2

(Required)

DONE RESPONSE

I/O

VALID

X1532

Master Modes

Description

Symbol

Min

Max

Units

Power-On-Reset

Program Latency

CCLK (output) Delay

period (slow)

T

2

15

70

ms

POR

T

6

µs per CLB column

PI

T

40

640

100

375

3000

375

µs

ns

7

ICCK

CCLK

T

period (fast)

Slave and Peripheral Modes

Description

Power-On-Reset

Symbol

Min

2

Max

15

Units

ms

T

POR

Program Latency

T

6

70

µs per CLB column

PI

CCLK (input) Delay (required)

period (required)

T

5

100

µs

ns

ICCK

T

CCLK

Note:

At power-up, V_CCmust rise from 2.0 to V_CCmin in less than 15 ms, otherwise delay configuration using PROGRAM until

V_CCis valid.

November 5, 1998 (Version 5.2)

7-125

R

XC5200 Series Field Programmable Gate Arrays

XC5200 Program Readback Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%

functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns

that are taken at device introduction, prior to any process improvements.

The following guidelines reflect worst-case values over the recommended operating conditions.

Finished

Internal Net

3

T

RTL

rdbk.TRIG

rdclk.I

T

RCRT

T

2

RTRC

1

5

6

T

RCH

4

RCL

rdbk.RIP

T

RCRR

DUMMY

VALID

rdbk.DATA

T

RCRD

7

X1790

Description

Symbol

Min

Max

Units

rdbk.TRIG

rdclk.1

rdbk.TRIG setup to initiate and abort Readback

rdbk.TRIG hold to initiate and abort Readback

1

2

T

200

50

-

ns

RTRC

RCRT

rdbk.DATA delay

rdbk.RIP delay

High time

7

6

5

4

T

-

250

500

ns

RCRD

RCRR

T

RCL

250

RCH

Low time

Note 1: Timing parameters apply to all speed grades.

Note 2: rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback

7-126

November 5, 1998 (Version 5.2)

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XC5200 Series Field Programmable Gate Arrays

XC5200 Switching Characteristics

Definition of Terms

In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as

follows:

Advance:

Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device

families. Use as estimates, not for production.

Preliminary: Based on preliminary characterization. Further changes are not expected.

Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.

1

XC5200 Operating Conditions

Symbol

Description

Supply voltage relative to GND Commercial: 0°C to 85°C junction

Supply voltage relative to GND Industrial: -40°C to 100°C junction

High-level input voltage — TTL configuration

Low-level input voltage — TTL configuration

High-level input voltage — CMOS configuration

Low-level input voltage — CMOS configuration

Input signal transition time

Min

4.75

4.5

2.0

0

Max

5.25

5.5

Units

V

V_CC

V

V_IHT

V_ILT

V_IHC

V_ILC

T_IN

V_CC

V

0.8

V

70%

0

100%

20%

250

V_CC

ns

XC5200 DC Characteristics Over Operating Conditions

Symbol

V_OH

V_OL

Description

High-level output voltage @ I_OH= -8.0 mA, V_CCmin

Low-level output voltage @ I_OL= 8.0 mA, V_CCmax

Quiescent FPGA supply current (Note 1)

Leakage current

Min

Max

Units

V

7

3.86

0.4

15

V

I_CCO

I_IL

mA

µA

pF

-10

+10

15

C_IN

Input capacitance (sample tested)

I_RIN

Pad pull-up (when selected) @ V_IN= 0V (sample tested)

0.02

0.30

mA

Note: 1. With no output current loads, all package pins at Vcc or GND, either TTL or CMOS inputs, and the FPGA configured with a

tie option.

XC5200 Absolute Maximum Ratings

Symbol

V_CC

Description

Supply voltage relative to GND

Units

V

-0.5 to +7.0

-0.5 to V_CC+0.5

-65 to +150

+260

V_IN

Input voltage with respect to GND

V

V_TS

T_STG

T_SOL

T_J

Voltage applied to 3-state output

V

Storage temperature (ambient)

°C

Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)

Junction temperature in plastic packages

Junction temperature in ceramic packages

+125

+150

Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended

Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may

affect device reliability.

1. Notwithstanding the definition of the above terms, all specifications are subject to change without notice.

November 5, 1998 (Version 5.2)

7-127

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XC5200 Series Field Programmable Gate Arrays

XC5200 Global Buffer Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%

functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark

timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more

detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used

in the simulator.

Speed Grade

-6

-5

-4

-3

Max

(ns)

Max

(ns)

Max

(ns)

Max

(ns)

Description

Symbol

T_BUFG

Device

Global Signal Distribution

From pad through global buffer, to any clock (CK)

XC5202

XC5204

XC5206

XC5210

XC5215

9.1

9.3

8.5

8.7

8.8

9.9

8.0

8.2

8.3

8.5

9.8

6.9

7.6

7.7

9.6

9.4

10.5

XC5200 Longline Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%

functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark

timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more

detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used

in the simulator.

Speed Grade

-6

-5

-4

-3

Max

(ns)

Max

(ns)

Max

(ns)

Max

(ns)

Description

Symbol Device

TBUF driving a Longline

TS

T_IO

XC5202

XC5204

XC5206

XC5210

XC5215

6.0

6.4

6.6

7.3

3.8

4.1

4.2

4.6

3.0

3.2

3.3

3.8

2.0

2.3

2.7

2.9

3.2

I

O

TBUF

I to Longline, while TS is Low; i.e., buffer is constantly ac-

tive

TS going Low to Longline going from floating High or Low

to active Low or High

T_ON

XC5202

XC5204

XC5206

XC5210

XC5215

XC52xx

7.8

8.3

8.4

8.9

3.0

5.6

5.9

6.0

6.3

2.8

4.7

4.9

5.0

5.3

2.6

4.0

4.3

4.4

4.5

2.4

TS going High to TBUF going inactive, not driving

Longline

T_OFF

Note: 1. Die-size-dependent parameters are based upon XC5215 characterization. Production specifications will vary with array

size.

7-128

November 5, 1998 (Version 5.2)

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XC5200 Series Field Programmable Gate Arrays

XC5200 CLB Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%

functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark

timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more

detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used

in the simulator.

Speed Grade

Symbol

-6

-5

-4

-3

Min

(ns)

Max

(ns)

Min

(ns)

Max

(ns)

Min

(ns)

Max

(ns)

Min

(ns)

Max

(ns)

Description

Combinatorial Delays

F inputs to X output

T_ILO

T_ITO

T_IDO

5.6

8.0

4.3

4.6

6.6

3.5

3.8

5.4

2.8

3.0

4.3

2.4

F inputs via transparent latch to Q

DI inputs to DO output (Logic-Cell

Feedthrough)

F inputs via F5_MUX to DO output

Carry Delays

T_IMO

7.2

5.8

5.0

4.3

Incremental delay per bit

Carry-in overhead from DI

Carry-in overhead from F

Carry-out overhead to DO

Sequential Delays

T_CY

T_CYDI

T_CYL

T_CYO

0.7

1.8

3.7

4.0

0.6

1.6

3.2

0.5

1.5

2.9

2.5

0.5

1.4

2.4

2.1

Clock (CK) to out (Q) (Flip-Flop)

T_CKO

5.8

9.2

4.9

7.4

4.0

5.9

4.0

5.5

Gate (Latch enable) going active to out (Q)

Set-up Time Before Clock (CK)

F inputs

T_GO

7

T_ICK

T_MICK

T_DICK

T_EICK

2.3

3.8

0.8

1.6

1.8

3.0

0.5

1.2

1.4

2.5

0.4

0.9

1.3

2.4

0.4

0.9

F inputs via F5_MUX

DI input

CE input

Hold Times After Clock (CK)

F inputs

T_CKI

T_CKMI

T_CKDI

T_CKEI

0

F inputs via F5_MUX

DI input

CE input

Clock Widths

Clock High Time

T_CH

T_CL

6.0

Clock Low Time

Toggle Frequency (MHz) (Note 3)

Reset Delays

F_TOG

83

Width (High)

T_CLRW

T_CLR

6.0

Delay from CLR to Q (Flip-Flop)

Delay from CLR to Q (Latch)

Global Reset Delays

Width (High)

7.7

6.5

6.3

5.2

5.1

4.2

4.0

3.0

T_CLRL

T_GCLRW

T_GCLR

Delay from internal GR to Q

14.7

12.1

9.1

8.0

Note: 1. The CLB K to Q output delay (T

CKO

) of any CLB, plus the shortest possible interconnect delay, is always longer than the

) of any CLB on the same die.

Data In hold-time requirement (T

CKDI

2. Timing is based upon the XC5215 device. For other devices, see Timing Calculator.

3. Maximum flip-flop toggle rate for export control purposes.

November 5, 1998 (Version 5.2)

7-129

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XC5200 Series Field Programmable Gate Arrays

XC5200 Guaranteed Input and Output Parameters (Pin-to-Pin)

All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also be

derived indirectly from the Global Buffer specifications. The delay calculator uses this indirect method, and may

overestimate because of worst-case assumptions. When there is a discrepancy between these two methods, the values

listed below should be used, and the derived values should be considered conservative overestimates.

Speed Grade

-6

-5

-4

-3

Max

(ns)

Max

(ns)

Max

(ns)

Max

(ns)

Description

Symbol Device

Global Clock to Output Pad (fast)

T_ICKOF

(Max)

XC5202

XC5204

XC5206

XC5210

XC5215

XC5202

XC5204

XC5206

XC5210

XC5215

XC5202

XC5204

XC5206

XC5210

XC5215

XC5202

XC5204

XC5206

XC5210

XC5215

XC5202

XC5204

XC5206

XC5210

XC5215

XC5202

XC5204

XC5206

XC5210

XC5215

XC52xx

16.9

17.1

17.2

19.0

21.4

21.6

21.7

24.3

2.5

15.1

15.3

15.4

17.0

18.7

18.9

19.0

21.2

2.0

10.9

11.3

11.9

12.8

12.6

13.3

13.6

15.0

1.9

9.8

9.9

10.8

11.2

11.7

11.5

11.9

12.5

12.9

13.1

1.9

1.8

1.7

3.5

3.6

4.3

4.8

5.6

6.6

6.3

6.0

5.7

7.5

7.4

7.3

7.2

0

CLB

Q

Direct IOB

Connect

BUFG

.

FAST

Global Clock-to-Output Delay

Global Clock to Output Pad (slew-limited)

T_ICKO

CLB

Q

Direct IOB

Connect

(Max)

BUFG

.

Global Clock-to-Output Delay

Input Set-up Time (no delay) to CLB Flip-Flop

T_PSUF

(Min)

Direct

IOB(NODELAY)

CLB

F,DI

2.3

1.9

Connect

Input

Set-up

& Hold

Time

2.2

1.9

2.2

1.9

BUFG

2.0

1.8

1.7

Input Hold Time (no delay) to CLB Flip-Flop

T_PHF

3.8

3.5

Direct

IOB(NODELAY)

CLB

3.9

3.8

Connect

Input

(Min)

F,DI

4.4

Set-up

& Hold

Time

5.1

4.9

BUFG

5.8

5.7

Input Set-up Time (with delay) to CLB Flip-Flop DI Input

T_PSU

7.3

6.6

Direct

IOB

CLB

DI

7.3

6.6

Connect

Input

Set-up

& Hold

Time

7.2

6.5

6.4

7.2

6.5

6.0

BUFG

6.8

5.7

Input Set-up Time (with delay) to CLB Flip-Flop F Input

T_PSUL

(Min)

8.8

7.7

7.5

Direct

IOB

CLB

F

8.6

7.5

Connect

Input

Set-up

& Hold

Time

8.5

7.4

8.5

7.4

BUFG

8.5

7.4

Input Hold Time (with delay) to CLB Flip-Flop

T_PH

0

Direct

IOB

CLB

F,DI

Connect

Input

Set-up

& Hold

Time

(Min)

BUFG

Note: 1. These measurements assume that the CLB flip-flop uses a direct interconnect to or from the IOB. The INREG/ OUTREG

properties, or XACT-Performance, can be used to assure that direct connects are used. t_PSUapplies only to the CLB input

DI that bypasses the look-up table, which only offers direct connects to IOBs on the left and right edges of the die. t_PSUL

applies to the CLB inputs F that feed the look-up table, which offers direct connect to IOBs on all four edges, as do the CLB

Q outputs.

2. When testing outputs (fast or slew-limited), half of the outputs on one side of the device are switching.

7-130

November 5, 1998 (Version 5.2)

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XC5200 Series Field Programmable Gate Arrays

XC5200 IOB Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%

functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark

timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more

detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used

in the simulator.

Speed Grade

Symbol

-6

-5

-4

-3

Max

(ns)

Max

(ns)

Max

(ns)

Max

(ns)

Description

Input

Propagation Delays from CMOS or TTL Levels

Pad to I (no delay)

T_PI

5.7

5.0

4.8

3.3

9.5

Pad to I (with delay)

T_PID

11.4

10.2

Output

Propagation Delays to CMOS or TTL Levels

Output (O) to Pad (fast)

T_OPF

T_OPS

4.6

9.5

4.5

8.4

9.3

4.5

8.0

8.3

3.5

5.0

7.5

Output (O) to Pad (slew-limited)

From clock (CK) to output pad (fast), using direct connect between Q

and output (O)

T_OKPOF

10.1

From clock (CK) to output pad (slew-limited), using direct connect be-

tween Q and output (O)

T_OKPOS

14.9

13.1

11.8

10.0

3-state to Pad active (fast)

T_TSONF

T_TSONS

T_GTS

5.6

5.2

9.0

4.9

8.3

4.6

6.0

3-state to Pad active (slew-limited)

Internal GTS to Pad active

10.4

17.7

7

15.9

14.7

13.5

Note: 1. Timing is measured at pin threshold, with 50-pF external capacitance loads. Slew-limited output rise/fall times are

approximately two times longer than fast output rise/fall times.

2. Unused and unbonded IOBs are configured by default as inputs with internal pull-up resistors.

3. Timing is based upon the XC5215 device. For other devices, see Timing Calculator.

November 5, 1998 (Version 5.2)

7-131

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XC5200 Series Field Programmable Gate Arrays

XC5200 Boundary Scan (JTAG) Switching Characteristic Guidelines

The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units

of nanoseconds and apply to all XC5200 devices unless otherwise noted.

Speed Grade

Symbol

-6

-5

-4

-3

Description

Setup and Hold

Min

Max

Min

Max

Min

Max

Min

Max

Input (TDI) to clock (TCK)

setup time

Input (TDI) to clock (TCK)

hold time

T

30.0

0

30.0

0

30.0

0

30.0

0

TDITCK

TCKTDI

Input (TMS) to clock (TCK)

setup time

Input (TMS) to clock (TCK)

hold time

T

15.0

0

15.0

0

15.0

0

15.0

0

TMSTCK

TCKTMS

Propagation Delay

Clock (TCK) to Pad (TDO)

T

30.0

10.0

30.0

10.0

30.0

10.0

30.0

10.0

TCKPO

Clock

Clock (TCK) High

Clock (TCK) Low

T

30.0

TCKH

TCKL

F

(MHz)

F

MAX

Note 1:

Input pad setup and hold times are specified with respect to the internal clock.

7-132

November 5, 1998 (Version 5.2)

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XC5200 Series Field Programmable Gate Arrays

Device-Specific Pinout Tables

Device-specific tables include all packages for each XC5200-Series device. They follow the pad locations around the die,

and include boundary scan register locations.

Pin Locations for XC5202 Devices

The following table may contain pinout information for unsupported device/package combinations. Please see the

availability charts elsewhere in the XC5200 Series data sheet for availability information.

Description

VQ64*

PC84

PQ100

VQ100

TQ144

PG156

Boundary Scan Order

VCC

-

57

58

-

2

3

92

93

94

95

96

97

98

-

89

90

91

92

93

94

95

-

128

129

130

131

132

133

134

137

138

139

142

143

144

1

H3

H1

-

1.

2.

3.

4.

5.

6.

I/O (A8)

I/O (A9)

I/O

51

4

G1

G2

G3

F1

54

-

57

I/O

-

63

I/O (A10)

I/O (A11)

GND

-

5

66

59

-

6

F2

69

-

F3

-

7.

I/O (A12)

I/O (A13)

I/O (A14)

I/O (A15)

VCC

60

61

62

63

64

-

7

99

100

1

96

97

98

99

100

1

E3

78

8.

8

C1

81

9.

9

B1

90

10.

10

11

12

13

14

15

16

-

2

B2

93

3

C3

-

GND

4

C4

-

11.

12.

13.

14.

GCK1 (A16, I/O)

I/O (A17)

I/O (TDI)

I/O (TCK)

GND

1

5

2

B3

102

105

111

114

-

2

6

3

A1

7

3

7

4

6

B4

4

8

5

7

A3

-

8

C6

15.

16.

17.

18.

19.

20.

I/O (TMS)

I/O

5

17

18

-

9

6

11

12

13

14

15

16

17

18

19

20

21

22

23

24

27

28

29

32

33

34

35

36

37

38

39

A5

117

123

126

129

135

138

-

6

10

-

7

C7

I/O

-

B7

I/O

-

11

12

13

14

15

16

17

18

-

8

A6

I/O

-

19

20

21

22

23

24

-

9

A7

I/O

7

10

11

12

13

14

15

-

A8

GND

8

C8

VCC

9

B8

-

21.

22.

23.

24.

25.

26.

I/O

-

C9

141

147

150

153

159

162

-

I/O

10

B9

I/O

A9

I/O

-

B10

C10

A10

C11

B12

A13

B13

B14

A15

C13

A16

C14

B15

B16

I/O

-

25

26

-

19

20

-

16

17

-

I/O

11

GND

27.

28.

29.

30.

31.

I/O

12

27

-

21

22

23

24

25

26

27

28

29

30

18

19

20

21

22

23

24

25

26

27

165

171

174

177

186

-

I/O

13

14

15

-

28

29

30

31

32

33

34

35

I/O

M1 (I/O)

GND

32.

M0 (I/O)

VCC

16

-

189

-

33.

34.

M2 (I/O)

GCK2 (I/O)

17

18

192

195

November 5, 1998 (Version 5.2)

7-133

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XC5200 Series Field Programmable Gate Arrays

Description

VQ64*

PC84

PQ100

VQ100

TQ144

PG156

Boundary Scan Order

35.

36.

37.

I/O (HDC)

I/O

19

-

36

-

31

32

33

-

28

29

30

-

40

43

44

45

48

49

50

51

52

53

54

55

56

57

58

59

60

61

64

65

66

69

70

71

72

73

74

75

76

79

80

81

84

85

86

87

88

89

90

91

92

93

94

95

96

97

100

101

102

D14

E14

C16

F14

F16

G14

G15

G16

H16

H15

H14

J14

J15

J16

K16

K15

K14

L16

L14

P16

M14

N14

R16

P14

R15

P13

R14

T16

T15

T14

T13

P11

T10

P10

R10

T9

204

207

210

-

I/O (LDC)

GND

I/O

20

-

37

-

38.

39.

40.

41.

42.

43.

-

38

39

-

34

35

36

37

38

39

40

41

42

43

44

45

46

47

-

31

32

33

34

35

36

37

38

39

40

41

42

43

44

-

216

219

222

228

231

234

-

I/O

21

-

I/O

-

I/O

22

23

24

25

26

27

-

40

41

42

43

44

45

-

I/O (ERR, INIT)

VCC

GND

I/O

-

44.

45.

46.

47.

48.

49.

240

243

246

252

255

258

-

I/O

-

I/O

28

29

-

46

47

-

I/O

GND

I/O

50.

51.

52.

53.

-

48

49

50

51

52

53

54

55

56

57

58

-

48

49

50

51

52

53

54

55

56

57

58

59

-

45

46

47

48

49

50

51

52

53

54

55

56

-

264

267

276

279

-

I/O

30

-

I/O

31

-

GND

DONE

VCC

32

33

34

35

36

37

-

PROG

I/O (D7)

GCK3 (I/O)

I/O (D6)

I/O

-

54.

55.

56.

57.

288

291

300

303

-

GND

I/O (D5)

I/O (CS0)

I/O

-

58.

59.

60.

61.

62.

63.

38

-

59

60

-

60

61

62

63

64

65

66

67

68

69

70

-

57

58

59

60

61

62

63

64

65

66

67

-

306

312

315

318

324

327

-

I/O

-

I/O (D4)

I/O

39

-

61

62

63

64

65

66

-

R9

P9

VCC

40

41

42

43

-

R8

GND

I/O (D3)

I/O (RS)

I/O

P8

-

64.

65.

66.

67.

68.

69.

T8

336

339

342

348

351

360

-

T7

T6

I/O

-

R7

I/O (D2)

I/O

44

-

67

68

-

71

72

-

68

69

-

P7

T5

GND

I/O (D1)

-

P6

70.

71.

45

-

69

70

73

74

70

71

T3

363

366

I/O

P5

(RCLK-BUSY/RDY)

72.

73.

I/O (D0, DIN)

I/O (DOUT)

46

47

71

72

75

76

72

73

105

106

P4

T2

372

375

7-134

November 5, 1998 (Version 5.2)

R

XC5200 Series Field Programmable Gate Arrays

Description

VQ64*

PC84

PQ100

VQ100

TQ144

PG156

Boundary Scan Order

CCLK

48

-

73

74

75

76

77

78

79

80

-

77

78

79

80

81

82

83

84

-

74

75

76

77

78

79

80

81

-

107

108

109

110

111

112

115

116

118

121

122

123

124

125

126

127

R2

P3

T1

N3

R1

P2

P1

N1

L3

K3

K2

K1

J1

-

VCC

-

74.

I/O (TDO)

GND

49

-

0

-

75.

76.

77.

78.

I/O (A0, WS)

GCK4 (A1, I/O)

I/O (A2, CS1)

I/O (A3)

GND

50

51

52

-

9

15

18

21

-

79.

80.

81.

82.

83.

84.

I/O (A4)

I/O (A5)

I/O

-

81

82

-

85

86

87

88

89

90

91

82

83

84

85

86

87

88

27

30

33

39

42

45

-

53

-

I/O

-

I/O (A6)

I/O (A7)

GND

54

55

56

83

84

1

J2

J3

H2

* VQ64 package supports Master Serial, Slave Serial, and Express configuration modes only.

Additional No Connect (N.C.) Connections on TQ144 Package

TQ144

135

136

140

141

4

9

41

42

46

47

62

63

67

68

77

78

82

83

98

117

10

25

26

30

31

99

119

120

103

104

113

114

7

5

Notes: Boundary Scan Bit 0 = TDO.T

Boundary Scan Bit 1 = TDO.O

Boundary Scan Bit 1056 = BSCAN.UPD

Pin Locations for XC5204 Devices

The following table may contain pinout information for unsupported device/package combinations. Please see the

availability charts elsewhere in the XC5200 Series data sheet for availability information.

Description

VCC

PC84

PQ100 VQ100

TQ144

128

129

130

131

132

133

134

135

136

137

-

PG156 PQ160

Boundary Scan Order

2

3

4

-

92

93

94

95

96

97

98

-

89

90

91

92

93

94

95

-

H3

H1

G1

G2

G3

F1

F2

E1

E2

F3

D1

D2

E3

C1

C2

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

-

1.

2.

3.

4.

5.

6.

7.

8.

I/O (A8)

I/O (A9)

I/O

78

81

87

I/O

-

90

I/O (A10)

I/O (A11)

I/O

5

6

-

93

99

102

105

-

I/O

-

GND

-

9.

I/O

-

111

114

117

123

126

10.

11.

12.

13.

I/O

-

I/O (A12)

I/O (A13)

I/O

7

8

-

99

100

-

96

97

-

138

139

140

November 5, 1998 (Version 5.2)

7-135

R

XC5200 Series Field Programmable Gate Arrays

14.

15.

16.

Description

PC84

-

PQ100 VQ100

TQ144

141

142

143

144

1

PG156 PQ160

Boundary Scan Order

I/O

-

1

-

98

99

100

1

D3

B1

157

158

159

160

1

129

138

141

-

I/O (A14)

I/O (A15)

VCC

GND

GCK1 (A16, I/O)

I/O (A17)

I/O

9

10

11

12

13

14

-

2

B2

3

C3

4

C4

-

17.

18.

19.

20.

21.

22.

5

2

B3

2

150

153

159

162

165

171

-

6

3

A1

3

-

4

A2

4

I/O

-

5

C5

5

I/O (TDI)

I/O (TCK)

GND

I/O

15

16

-

7

4

6

B4

6

8

5

7

A3

7

-

8

C6

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

23.

24.

25.

26.

27.

28.

29.

30.

-

9

B5

174

177

180

183

186

189

195

198

-

I/O

-

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

-

B6

I/O (TMS)

I/O

17

18

-

9

6

A5

10

-

7

C7

I/O

-

B7

I/O

-

11

12

13

14

15

16

17

18

-

8

A6

I/O

19

20

21

22

23

24

-

9

A7

I/O

10

11

12

13

14

15

-

A8

GND

VCC

I/O

C8

B8

-

31.

32.

33.

34.

35.

36.

37.

38.

C9

201

207

210

213

219

222

225

231

-

I/O

B9

I/O

A9

I/O

-

B10

C10

A10

A11

B11

C11

B12

A13

A14

C12

B13

B14

A15

C13

A16

C14

B15

B16

D14

C15

D15

E14

C16

E15

D16

F14

F15

I/O

25

26

-

19

20

-

16

17

-

I/O

-

GND

I/O

-

39.

40.

41.

42.

43.

44.

45.

27

-

21

22

-

18

19

-

234

237

240

243

246

249

258

-

I/O

-

I/O

-

I/O

28

29

30

31

32

33

34

35

36

-

23

24

25

26

27

28

29

30

31

-

20

21

22

23

24

25

26

27

28

-

I/O

M1 (I/O)

GND

M0 (I/O)

VCC

M2 (I/O)

GCK2 (I/O)

I/O (HDC)

I/O

46.

261

-

47.

48.

49.

50.

51.

52.

53.

54.

55.

264

267

276

279

282

288

291

294

300

-

I/O

-

I/O

-

32

33

-

29

30

-

I/O (LDC)

I/O

37

-

I/O

-

GND

I/O

-

45

46

56.

-

303

7-136

November 5, 1998 (Version 5.2)

R

XC5200 Series Field Programmable Gate Arrays

57.

58.

59.

60.

61.

62.

63.

Description

PC84

-

PQ100 VQ100

TQ144

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

-

PG156 PQ160

Boundary Scan Order

I/O

-

E16

F16

G14

G15

G16

H16

H15

H14

J14

J15

J16

K16

K15

K14

L16

M16

L15

L14

N16

M15

P16

M14

N15

P15

N14

R16

P14

R15

P13

R14

T16

T15

R13

P12

T14

T13

P11

R11

T11

T10

P10

R10

T9

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

306

312

315

318

324

327

330

-

38

39

-

34

35

36

37

38

39

40

41

42

43

44

45

46

47

-

31

32

33

34

35

36

37

38

39

40

41

42

43

44

-

40

41

42

43

44

45

-

I/O (ERR, INIT)

VCC

GND

I/O

-

64.

65.

66.

67.

68.

69.

70.

71.

336

339

348

351

354

360

363

366

-

I/O

-

I/O

46

47

-

I/O

-

GND

I/O

-

72.

73.

74.

75.

76.

77.

78.

79.

-

372

375

378

384

387

390

396

399

-

I/O

-

I/O

48

49

-

48

49

-

45

46

-

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

I/O

-

7

I/O

50

51

52

53

54

55

56

57

-

50

51

52

53

54

55

56

57

-

47

48

49

50

51

52

53

54

-

I/O

GND

DONE

VCC

PROG

I/O (D7)

GCK3 (I/O)

I/O

-

80.

81.

82.

83.

84.

85.

408

411

420

423

426

432

-

I/O

-

I/O (D6)

I/O

58

-

58

59

-

55

56

-

GND

I/O

-

86.

87.

88.

89.

90.

91.

92.

93.

-

435

438

444

447

450

456

459

462

-

I/O

-

I/O (D5)

I/O (CS0)

I/O

59

60

-

60

61

62

63

64

65

66

67

68

69

70

-

57

58

59

60

61

62

63

64

65

66

67

-

I/O

-

I/O (D4)

I/O

61

62

63

64

65

66

-

R9

P9

VCC

GND

I/O (D3)

I/O (RS)

I/O

R8

P8

-

94.

95.

96.

97.

98.

T8

468

471

474

480

483

T7

T6

I/O

-

R7

I/O (D2)

67

71

68

P7

November 5, 1998 (Version 5.2)

7-137

R

XC5200 Series Field Programmable Gate Arrays

99.

Description

PC84

PQ100 VQ100

TQ144

97

PG156 PQ160

Boundary Scan Order

I/O

68

-

72

-

69

-

T5

R6

T4

P6

T3

P5

107

108

109

110

113

114

486

492

495

-

100.

101.

98

-

99

GND

-

100

101

102

102.

103.

I/O (D1)

69

70

73

74

70

71

498

504

I/O

(RCLK-BUSY/RDY)

104.

105.

106.

107.

I/O

-

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

-

R4

R3

P4

T2

R2

P3

T1

N3

R1

P2

N2

M3

P1

N1

M2

M1

L3

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

137

138

139

140

141

507

510

516

519

-

I/O

-

I/O (D0, DIN)

I/O (DOUT)

CCLK

71

72

73

74

75

76

77

78

-

75

76

77

78

79

80

81

82

-

72

73

74

75

76

77

78

79

-

VCC

-

108.

I/O (TDO)

GND

0

-

109.

110.

111.

112.

113.

114.

115.

116.

I/O (A0, WS)

GCK4 (A1, I/O)

I/O

9

15

18

21

27

30

33

39

-

I/O

-

I/O (A2, CS1)

I/O (A3)

I/O

79

80

-

83

84

-

80

81

-

I/O

-

GND

-

118

119

120

121

122

123

124

125

126

127

117.

118.

119.

120.

121.

122.

123.

124.

I/O

-

L2

42

45

51

54

57

63

66

69

-

I/O

-

L1

I/O (A4)

I/O (A5)

I/O

81

82

-

85

86

87

88

89

90

91

82

83

84

85

86

87

88

K3

K2

K1

J1

I/O

-

I/O (A6)

I/O (A7)

GND

83

84

1

J2

J3

H2

Additional No Connect (N.C.) Connections for PQ160 Package

PQ160

8

9

30

31

89

90

111

112

136

Notes: Boundary Scan Bit 0 = TDO.T

Boundary Scan Bit 1 = TDO.O

Boundary Scan Bit 1056 = BSCAN.UPD

7-138

November 5, 1998 (Version 5.2)

R

XC5200 Series Field Programmable Gate Arrays

Pin Locations for XC5206 Devices

The following table may contain pinout information for unsupported device/package combinations. Please see the

availability charts elsewhere in the XC5200 Series data sheet for availability information.

Description

VCC

PC84

PQ100

VQ100

TQ144

128

129

130

131

132

-

PQ160

142

143

144

145

146

-

TQ176

155

156

157

158

159

160

161

162

163

164

165

166

168

169

170

171

172

173

174

175

176

1

PG191

J4

PQ208 Boundary Scan Order

2

3

92

93

94

95

96

-

89

90

91

92

93

-

183

184

185

186

187

188

189

190

191

192

193

194

197

198

199

200

201

202

203

204

205

2

-

1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

I/O (A8)

I/O (A9)

I/O

J3

87

4

J2

90

-

J1

93

I/O

-

H1

H2

H3

G1

G2

F1

99

I/O

-

102

105

111

114

117

123

-

I/O

-

I/O (A10)

I/O (A11)

I/O

5

97

98

-

94

95

-

133

134

135

136

137

-

147

148

149

150

151

152

153

154

155

156

157

158

159

160

1

6

-

I/O

-

E1

G3

C1

E2

F3

GND

I/O

-

11.

12.

13.

14.

15.

16.

17.

18.

-

126

129

138

141

150

153

162

165

-

I/O

-

I/O (A12)

I/O (A13)

I/O

7

99

100

-

96

97

-

138

139

140

141

142

143

144

1

8

D2

B1

E3

C2

B2

D3

D4

C3

C4

B3

C5

A2

B4

C6

A3

C7

A4

A5

B7

A6

C8

A7

B8

A8

B9

C9

D9

D10

C10

B10

A9

A10

A11

-

I/O

-

I/O (A14)

I/O (A15)

VCC

GND

GCK1 (A16, I/O)

I/O (A17)

I/O

9

1

98

99

100

1

10

11

12

13

14

-

2

7

3

4

-

19.

20.

21.

22.

23.

24.

25.

26.

5

2

4

174

177

183

186

189

195

198

201

-

6

3

5

-

4

6

I/O

-

5

7

I/O (TDI)

I/O (TCK)

I/O

15

16

-

7

4

6

8

5

7

9

-

8

10

I/O

-

9

11

GND

I/O

-

8

10

11

12

13

14

-

10

14

27.

28.

29.

30.

31.

32.

33.

34.

35.

36.

-

9

11

15

207

210

213

219

222

225

234

237

246

249

-

I/O

-

10

11

12

-

12

16

I/O (TMS)

I/O

17

18

-

9

6

13

17

10

-

7

14

18

I/O

-

15

19

I/O

-

16

20

I/O

-

13

14

15

16

17

18

19

20

21

22

-

15

16

17

18

19

20

21

22

23

24

-

17

21

I/O

-

11

12

13

14

15

16

17

18

-

8

18

22

I/O

19

20

21

22

23

24

-

9

19

23

I/O

10

11

12

13

14

15

-

20

24

GND

VCC

I/O

21

25

22

26

-

37.

38.

39.

40.

41.

23

27

255

258

261

267

270

I/O

24

28

I/O

25

29

I/O

-

26

30

I/O

-

27

31

November 5, 1998 (Version 5.2)

7-139

R

XC5200 Series Field Programmable Gate Arrays

42.

43.

44.

45.

46.

Description

I/O

PC84

-

PQ100

-

VQ100

-

TQ144

-

PQ160

-

TQ176

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

PG191

C11

B11

A12

B12

A13

C12

A15

C13

B14

A16

B15

C14

A17

B16

C15

D15

A18

D16

C16

B17

E16

C17

D17

B18

E17

F16

C18

G16

E18

F18

G17

G18

H16

H17

H18

J18

PQ208 Boundary Scan Order

32

33

34

35

36

37

40

41

42

43

44

45

46

47

48

49

50

55

56

57

58

59

60

61

62

63

64

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

93

273

279

282

285

291

-

I/O

25

26

-

19

20

-

16

17

-

23

24

25

26

27

-

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

-

I/O

-

GND

I/O

-

47.

48.

49.

50.

51.

52.

53.

54.

55.

-

294

297

303

306

309

315

318

321

330

-

I/O

-

I/O

27

-

21

22

-

18

19

-

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

-

I/O

-

I/O

-

I/O

28

29

30

31

32

33

34

35

36

-

23

24

25

26

27

28

29

30

31

-

20

21

22

23

24

25

26

27

28

-

I/O

M1 (I/O)

GND

M0 (I/O)

VCC

M2 (I/O)

GCK2 (I/O)

I/O (HDC)

I/O

56.

333

-

57.

58.

59.

60.

61.

62.

63.

64.

65.

336

339

348

351

354

360

363

372

375

-

I/O

-

I/O

-

32

33

-

29

30

-

I/O (LDC)

I/O

37

-

I/O

-

GND

I/O

-

45

46

47

48

49

-

66.

67.

68.

69.

70.

71.

72.

73.

74.

75.

-

378

384

387

390

396

399

402

408

411

414

-

I/O

-

I/O

38

39

-

34

35

-

31

32

-

I/O

-

I/O

-

36

37

38

39

40

41

42

43

44

45

-

33

34

35

36

37

38

39

40

41

42

-

50

51

52

53

54

55

56

57

58

59

-

56

57

58

59

60

61

62

63

64

65

-

I/O

-

I/O

40

41

42

43

44

45

-

J17

I/O (ERR, INIT)

VCC

GND

I/O

J16

J15

K15

K16

K17

K18

L18

L17

L16

M18

M17

N18

P18

M16

T18

-

76.

77.

78.

79.

80.

81.

82.

83.

84.

85.

420

423

426

432

435

438

444

447

450

456

-

I/O

-

I/O

-

I/O

-

I/O

46

47

-

46

47

-

43

44

-

60

61

62

63

64

-

66

67

68

69

70

71

I/O

-

GND

I/O

-

86.

-

459

7-140

November 5, 1998 (Version 5.2)

R

XC5200 Series Field Programmable Gate Arrays

87.

88.

89.

90.

91.

92.

93.

Description

PC84

-

PQ100

-

VQ100

-

TQ144

-

PQ160

72

TQ176

80

PG191

P17

N16

T17

R17

P16

U18

T16

R16

U17

R15

V18

T15

U16

T14

U15

V17

V16

T13

U14

T12

U13

V13

U12

V12

T11

U11

V11

V10

U10

T10

R10

R9

PQ208 Boundary Scan Order

I/O

94

468

471

480

483

486

492

495

-

I/O

48

49

-

48

49

-

45

46

-

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

-

73

81

95

I/O

74

82

96

I/O

75

83

97

I/O

-

76

84

98

I/O

50

51

52

53

54

55

56

57

-

50

51

52

53

54

55

56

57

-

47

48

49

50

51

52

53

54

-

77

85

99

I/O

78

86

100

101

103

106

108

109

110

111

112

113

114

115

116

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

145

146

147

148

GND

DONE

VCC

PROG

I/O (D7)

GCK3 (I/O)

I/O

79

87

80

88

-

81

89

-

82

90

-

94.

95.

96.

97.

98.

99.

83

91

504

507

516

519

522

528

531

534

-

84

92

85

93

I/O

-

86

94

I/O (D6)

I/O

58

-

58

59

-

55

56

-

87

95

88

96

100. I/O

101. I/O

-

89

97

-

90

98

GND

-

81

82

83

84

85

-

91

99

102. I/O

103. I/O

104. I/O (D5)

105. I/O (CS0)

106. I/O

107. I/O

108. I/O

109. I/O

110. I/O (D4)

111. I/O

VCC

-

92

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

540

543

552

555

558

564

567

570

576

579

-

93

59

60

-

60

61

-

57

58

-

94

95

7

-

62

63

64

65

66

67

68

69

70

-

59

60

61

62

63

64

65

66

67

-

86

87

88

89

90

91

92

93

94

95

-

96

-

97

61

62

63

64

65

66

-

98

99

100

101

102

103

104

105

-

GND

-

112. I/O (D3)

113. I/O (RS)

114. I/O

115. I/O

116. I/O

117. I/O

118. I/O (D2)

119. I/O

120. I/O

121. I/O

GND

T9

588

591

600

603

612

615

618

624

627

630

-

U9

V9

-

V8

-

U8

-

T8

67

68

-

71

72

-

68

69

-

96

97

98

99

100

-

106

107

108

109

110

111

112

113

114

V7

U7

V6

-

U6

-

T7

122. I/O

123. I/O

124. I/O (D1)

125. I/O

-

U5

636

639

642

648

-

T6

69

70

73

74

70

71

101

102

V3

V2

(RCLK-BUSY/RD

Y)

126. I/O

-

103

104

105

106

115

116

117

118

127

128

129

130

U4

T5

U3

T4

149

150

151

152

651

654

660

663

127. I/O

-

128. I/O (D0, DIN)

129. I/O (DOUT)

71

72

75

76

72

73

November 5, 1998 (Version 5.2)

7-141

R

XC5200 Series Field Programmable Gate Arrays

Description

CCLK

VCC

PC84

73

74

75

76

77

78

-

PQ100

77

78

79

80

81

82

-

VQ100

74

75

76

77

78

79

-

TQ144

107

108

109

110

111

112

113

114

115

116

117

-

PQ160

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

-

TQ176

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

PG191

V1

R4

U2

R3

T3

PQ208 Boundary Scan Order

153

154

159

160

161

162

163

164

165

166

167

168

171

172

173

174

175

176

177

178

179

180

181

182

-

130. I/O (TDO)

GND

-

131. I/O (A0, WS)

132. GCK4 (A1, I/O)

133. I/O

9

U1

P3

R2

T2

15

18

21

27

30

33

42

-

134. I/O

-

135. I/O (A2, CS1)

136. I/O (A3)

137. I/O

79

80

-

83

84

-

80

81

-

N3

P2

T1

138. I/O

-

GND

-

118

119

120

121

122

-

M3

P1

N1

M2

M1

L3

139. I/O

-

45

51

54

57

63

66

69

75

78

81

-

140. I/O

-

141. I/O (A4)

142. I/O (A5)

143. I/O

81

82

-

85

86

-

82

83

-

144. I/O

-

136

137

138

139

140

141

L2

145. I/O

-

87

88

89

90

91

84

85

86

87

88

123

124

125

126

127

L1

146. I/O

-

K1

K2

K3

K4

147. I/O (A6)

148. I/O (A7)

GND

83

84

1

Additional No Connect (N.C.) Connections for PQ208 and TQ176 Packages

PQ208

TQ176

167

195

196

206

207

208

1

39

51

52

53

54

65

66

104

105

107

117

118

143

144

155

156

157

158

169

170

3

12

13

38

91

92

102

Notes: Boundary Scan Bit 0 = TDO.T

Boundary Scan Bit 1 = TDO.O

Boundary Scan Bit 1056 = BSCAN.UPD

Pin Locations for XC5210 Devices

The following table may contain pinout information for unsupported device/package combinations. Please see the

availability charts elsewhere in the XC5200 Series data sheet for availability information.

Boundary Scan

Description

PC84 TQ144 PQ160 TQ176 PQ208 PG223 BG225 PQ240

Order

VCC

I/O (A8)

I/O (A9)

I/O

2

3

4

-

128

129

130

131

132

-

142

143

144

145

146

-

155

156

157

158

159

160

161

183

184

185

186

187

188

189

J4

J3

J2

J1

H1

H2

H3

VCC*

E8

212

213

214

215

216

217

218

-

1.

111

114

117

123

126

129

2.

3.

4.

5.

6.

B7

A7

I/O

-

C7

I/O

-

D7

I/O

-

E7

7-142

November 5, 1998 (Version 5.2)

R

XC5200 Series Field Programmable Gate Arrays

Boundary Scan

7.

Description

PC84 TQ144 PQ160 TQ176 PQ208 PG223 BG225 PQ240

Order

135

138

-

I/O (A10)

I/O (A11)

VCC

I/O

5

6

-

133

134

-

147

148

-

162

163

-

190

191

-

G1

G2

-

A6

B6

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

1

8.

VCC*

C6

9.

-

H4

G4

F1

E1

G3

F2

D1

C1

E2

F3

D2

F4

E4

B1

E3

C2

B2

D3

D4

C3

C4

B3

C5

A2

B4

C6

A3

B5

B6

D5

D6

C7

A4

A5

B7

A6

-

141

150

153

162

-

10.

11.

12.

I/O

-

F7

I/O

-

135

136

137

-

149

150

151

-

164

165

166

-

192

193

194

195

196

197

198

199

200

-

A5

I/O

-

B5

GND

I/O

-

GND*

D6

13.

14.

15.

16.

17.

18.

19.

20.

21.

22.

23.

24.

-

165

171

174

177

183

186

189

195

198

201

210

213

-

I/O

-

167

168

169

170

171

-

C5

I/O

-

152

153

154

155

-

A4

I/O

-

E6

I/O (A12)

I/O (A13)

I/O

7

8

-

138

139

-

B4

D5

A3

I/O

-

C4

I/O

-

140

141

142

143

144

1

156

157

158

159

160

1

172

173

174

175

176

1

201

202

203

204

205

2

B3

I/O

-

F6

I/O (A14)

I/O (A15)

VCC

GND

GCK1 (A16, I/O)

I/O (A17)

I/O

9

10

11

12

13

14

-

A2

C3

VCC*

GND*

D4

-

25.

26.

27.

28.

29.

30.

31.

32.

33.

34.

35.

36.

2

4

2

222

225

231

234

237

243

246

249

255

258

261

267

-

7

3

5

B1

3

4

6

C2

4

I/O

-

5

7

E5

5

I/O (TDI)

I/O (TCK)

I/O

15

16

-

6

8

D3

6

7

9

C1

7

-

8

10

11

12

13

-

D2

8

I/O

-

9

G6

E4

9

I/O

-

10

I/O

-

D1

11

I/O

-

E3

12

I/O

-

E2

13

GND

I/O

-

8

10

11

12

13

14

-

10

11

12

13

14

-

14

15

16

17

18

-

GND*

F5

14

37.

38.

39.

40.

-

9

15

270

273

279

282

-

I/O

-

10

11

12

-

E1

16

I/O (TMS)

I/O

17

18

-

F4

17

F3

18

VCC

I/O

VCC*

F2

19

41.

42.

43.

44.

45.

46.

47.

48.

-

D7

D8

C8

A7

B8

A8

B9

C9

D9

D10

C10

20

285

291

294

297

306

309

318

321

-

I/O

-

F1

21

I/O

-

15

16

17

18

19

20

21

22

23

19

20

21

22

23

24

25

26

27

G4

G3

G2

G1

G5

H3

23

I/O

-

24

I/O

-

13

14

15

16

17

18

19

15

16

17

18

19

20

21

25

I/O

-

26

I/O

19

20

21

22

23

27

I/O

28

GND

VCC

I/O

GND*

VCC*

H4

29

30

-

49.

31

327

November 5, 1998 (Version 5.2)

7-143

R

XC5200 Series Field Programmable Gate Arrays

Boundary Scan

Order

Description

PC84 TQ144 PQ160 TQ176 PQ208 PG223 BG225 PQ240

50.

51.

52.

53.

54.

55.

56.

I/O

24

-

20

21

22

-

22

23

24

-

24

25

26

27

28

-

28

29

30

31

32

-

B10

A9

H5

J2

32

33

34

35

36

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

84

330

333

339

342

345

351

354

-

I/O

-

A10

A11

C11

D11

D12

-

J1

I/O

-

J3

I/O

-

J4

I/O

-

J5

I/O

-

K1

VCC

I/O

-

VCC*

K2

57.

58.

59.

60.

25

26

-

23

24

25

26

27

-

25

26

27

28

29

-

29

30

31

32

33

-

33

34

35

36

37

-

B11

A12

B12

A13

C12

D13

D14

B13

A14

A15

C13

B14

A16

B15

C14

A17

B16

C15

D15

A18

D16

C16

B17

E16

C17

D17

B18

E17

F16

C18

D18

F17

E15

F15

G16

E18

F18

G17

G18

-

357

363

366

369

-

I/O

K3

I/O

J6

I/O

-

L1

GND

I/O

-

GND*

L2

61.

62.

63.

64.

65.

66.

67.

68.

69.

70.

71.

72.

73.

-

375

378

381

387

390

393

399

402

405

411

414

417

426

-

I/O

-

K4

I/O

-

38

39

40

41

42

43

44

45

46

47

48

49

50

55

56

57

58

59

60

61

62

63

64

65

66

-

L3

I/O

-

M1

K5

I/O

-

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

-

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

-

I/O

-

M2

L4

I/O

27

-

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

-

I/O

N1

M3

N2

K6

I/O

-

I/O

-

I/O

28

29

30

31

32

33

34

35

36

-

I/O

P1

M1 (I/O)

GND

M0 (I/O)

VCC

M2 (I/O)

N3

GND*

P2

74.

429

-

VCC*

M4

R2

P3

75.

76.

77.

78.

79.

80.

81.

82.

83.

84.

85.

86.

87.

432

435

444

447

450

456

459

462

468

471

474

480

483

-

GCK2 (I/O)

I/O (HDC)

I/O

L5

I/O

-

N4

R3

P4

I/O

-

I/O (LDC)

I/O

37

-

K7

I/O

-

M5

R4

N5

P5

I/O

-

I/O

-

I/O

-

I/O

-

L6

GND

I/O

-

45

46

47

48

49

-

51

52

53

54

55

-

55

56

57

58

59

-

67

68

69

70

71

-

GND*

R5

M6

N6

P6

88.

89.

90.

91.

-

486

492

495

504

-

I/O

-

I/O

38

39

-

I/O

VCC

I/O

VCC*

R6

M7

N7

92.

93.

94.

-

60

61

-

72

73

-

H16

H17

G15

507

510

516

I/O

-

I/O

-

7-144

November 5, 1998 (Version 5.2)

R

XC5200 Series Field Programmable Gate Arrays

Boundary Scan

Description

PC84 TQ144 PQ160 TQ176 PQ208 PG223 BG225 PQ240

Order

519

522

528

531

534

-

95.

96.

97.

98.

99.

I/O

-

H15

H18

J18

J17

J16

J15

K15

K16

K17

K18

L18

L17

L16

L15

M15

-

P7

R7

85

86

50

51

52

53

54

55

56

57

58

59

-

56

57

58

59

60

61

62

63

64

65

-

62

63

64

65

66

67

68

69

70

71

72

73

-

74

75

76

77

78

79

80

81

82

83

84

85

-

L7

87

40

41

42

43

44

45

-

N8

88

I/O (ERR, INIT)

VCC

GND

I/O

P8

89

VCC*

GND*

L8

90

91

-

100.

101.

102.

103.

104.

105.

106.

107.

92

540

543

546

552

555

558

564

567

-

I/O

P9

93

I/O

R9

94

I/O

-

N9

95

I/O

-

M9

96

I/O

-

L9

97

I/O

-

R10

P10

VCC*

N10

K9

99

I/O

-

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

VCC

I/O

-

108.

109.

110.

111.

46

47

-

60

61

62

63

64

-

66

67

68

69

70

-

74

75

76

77

78

-

86

87

88

89

90

-

M18

M17

N18

P18

M16

N15

P15

N17

R18

T18

P17

N16

T17

R17

P16

U18

T16

R16

U17

R15

V18

T15

U16

T14

U15

R14

R13

V17

V16

T13

U14

V15

V14

T12

R12

570

576

579

588

-

I/O

R11

P11

GND*

M10

N11

R12

L10

P12

M11

R13

N12

P13

K10

R14

N13

GND*

P14

VCC*

M12

P15

N14

L11

M13

N15

M14

J10

I/O

-

GND

I/O

-

112.

113.

114.

115.

116.

117.

118.

119.

120.

121.

122.

123.

-

591

600

603

606

612

615

618

624

627

630

636

639

-

I/O

-

7

I/O

-

91

92

93

94

95

96

97

98

99

100

101

103

106

108

109

110

111

112

-

I/O

-

I/O

-

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

-

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

-

I/O

-

I/O

48

49

-

65

66

67

68

69

70

71

72

73

74

75

76

77

78

-

I/O

-

I/O

50

51

52

53

54

55

56

57

-

I/O

GND

DONE

VCC

PROG

I/O (D7)

GCK3 (I/O)

I/O

-

124.

125.

126.

127.

128.

129.

130.

131.

132.

133.

134.

135.

648

651

660

663

666

672

675

678

684

687

690

696

-

I/O

-

I/O

-

I/O

-

I/O (D6)

I/O

58

-

79

80

-

87

88

89

90

-

95

96

97

98

-

113

114

115

116

117

118

119

-

L12

M15

L13

L14

K11

GND*

L15

I/O

-

I/O

-

I/O

-

I/O

-

GND

I/O

-

81

-

91

-

99

-

136.

-

699

November 5, 1998 (Version 5.2)

7-145

R

XC5200 Series Field Programmable Gate Arrays

Boundary Scan

Order

Description

PC84 TQ144 PQ160 TQ176 PQ208 PG223 BG225 PQ240

137.

138.

139.

I/O

-

82

83

-

R11

U13

V13

-

K12

K13

K14

VCC*

K15

J12

137

138

139

140

141

142

144

145

146

147

148

149

150

151

152

153

154

155

156

157

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

708

711

714

-

I/O

92

100

101

-

120

121

-

I/O

-

93

VCC

I/O (D5)

-

140.

141.

142.

143.

144.

145.

146.

147.

59

60

-

84

85

-

94

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

-

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

-

U12

V12

T11

U11

V11

V10

U10

T10

R10

R9

T9

720

723

726

732

735

738

744

747

-

I/O (CS0)

95

I/O

-

J13

I/O

-

J14

I/O

-

86

87

88

89

90

91

92

93

94

95

-

96

J15

I/O

-

97

J11

I/O (D4)

61

62

63

64

65

66

-

98

H13

H14

VCC*

GND*

H12

H11

G14

G15

G13

G12

G11

F15

VCC*

F14

F13

G10

E15

GND*

E14

F12

E13

D15

F11

D14

E12

C15

D13

C14

F10

B15

C13

VCC*

A15

GND*

A14

B13

E11

C12

A13

B12

F9

I/O

99

VCC

100

101

102

103

104

105

-

GND

-

148.

149.

150.

151.

152.

153.

154.

155.

I/O (D3)

756

759

768

771

780

783

786

792

-

I/O (RS)

U9

V9

V8

U8

T8

I/O

-

I/O

-

I/O

-

I/O (D2)

67

68

-

96

97

-

106

107

-

V7

U7

-

I/O

VCC

156.

157.

158.

159.

I/O

-

98

99

-

108

109

-

120

121

-

140

141

-

V6

U6

R8

R7

T7

795

798

804

807

-

I/O

-

I/O

-

I/O

-

GND

-

100

-

110

-

122

-

142

-

160.

161.

162.

163.

164.

165.

166.

167.

168.

169.

170.

171.

I/O

-

R6

R5

V5

V4

U5

T6

810

816

819

822

828

831

834

840

843

846

855

858

-

I/O

-

I/O

-

143

144

145

146

147

148

149

150

151

152

153

154

159

160

161

162

163

164

165

166

-

I/O

-

I/O

-

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

-

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

-

I/O

-

I/O (D1)

I/O (RCLK-BUSY/RDY)

I/O

69

70

-

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

-

V3

V2

U4

T5

I/O

-

I/O (D0, DIN)

I/O (DOUT)

CCLK

71

72

73

74

75

76

77

78

-

U3

T4

V1

R4

U2

R3

T3

VCC

-

172.

I/O (TDO)

GND

-

173.

174.

175.

176.

177.

178.

179.

I/O (A0, WS)

GCK4 (A1, I/O)

I/O

9

U1

P3

R2

T2

15

18

I/O

-

21

I/O (CS1, A2)

I/O (A3)

I/O

79

80

-

27

N3

P4

30

33

7-146

November 5, 1998 (Version 5.2)

R

XC5200 Series Field Programmable Gate Arrays

Boundary Scan

Description

PC84 TQ144 PQ160 TQ176 PQ208 PG223 BG225 PQ240

Order

39

42

45

51

54

-

180.

181.

182.

183.

184.

I/O

-

117

-

N4

P2

T1

R1

N2

-

D11

A12

C11

B11

E10

GND*

-

190

191

192

193

194

129

130

-

141

142

-

167

168

169

170

-

GND

I/O

VCC

-

118

119

120

-

131

132

133

-

143

144

145

-

171

172

173

-

M3

P1

N1

M4

L4

-

196

197

198

199

200

201

202

203

205

206

207

208

209

210

211

-

185.

186.

187.

188.

-

A11

D10

C10

B10

VCC*

A10

D9

57

66

69

75

-

189.

190.

191.

192.

193.

194.

195.

196.

I/O (A4)

I/O (A5)

I/O

81

82

-

121

122

-

134

135

-

146

147

148

149

150

151

152

153

154

174

175

176

177

178

179

180

181

182

M2

M1

L3

L2

L1

K1

K2

K3

K4

78

81

87

90

93

99

102

105

-

C9

I/O

-

136

137

138

139

140

141

B9

I/O

-

123

124

125

126

127

A9

I/O

-

E9

I/O (A6)

I/O (A7)

GND

83

84

1

C8

B8

GND*

7

Additional No Connect (N.C.) Connections for PQ208 and PQ240 Packages

PQ208

105

PQ240

143

1

3

53

54

157

158

206

207

208

22

37

83

98

219

107

158

51

52

102

104

155

195

156

204

Notes: * Pins labeled VCC* are internally bonded to a VCC plane within the BG225 package. The external pins are: B2, D8, H15, R8,

B14, R1, H1, and R15.

Pins labeled GND* are internally bonded to a ground plane within the BG225 package. The external pins are: A1, D12, G7,

G9, H6, H8, H10, J8, K8, A8, F8, G8, H2, H7, H9, J7, J9, M8.

Boundary Scan Bit 0 = TDO.T

Boundary Scan Bit 1 = TDO.O

Boundary Scan Bit 1056 = BSCAN.UPD

Pin Locations for XC5215 Devices

The following table may contain pinout information for unsupported device/package combinations. Please see the

availability charts elsewhere in the XC5200 Series data sheet for availability information.

Description

PQ160

142

143

144

145

146

-

HQ208

183

HQ240

212

213

214

215

216

217

218

220

PG299

K1

BG225

VCC*

E8

BG352

VCC*

D14

Boundary Scan Order

VCC

-

1.

I/O (A8)

I/O (A9)

I/O

184

K2

138

141

147

150

153

159

162

2.

3.

4.

5.

6.

7.

185

K3

B7

C14

186

K5

A7

A15

I/O

187

K4

C7

B15

I/O

188

J1

D7

C15

I/O

-

189

J2

E7

D15

I/O (A10)

147

190

H1

A6

A16

November 5, 1998 (Version 5.2)

7-147

R

XC5200 Series Field Programmable Gate Arrays

8.

Description

I/O (A11)

PQ160

HQ208

HQ240

221

-

PG299

J3

BG225

B6

-

BG352

B16

C17

B18

VCC*

C18

D17

A20

B19

GND*

C19

D18

A21

B20

C20

B21

B22

C21

D20

A23

D21

C22

B24

C23

D22

C24

VCC*

GND*

D23

C25

D24

E23

C26

E24

F24

Boundary Scan Order

148

191

-

165

171

174

-

9.

I/O

-

H2

G1

E1

H3

G2

H4

F2

10.

I/O

-

VCC

I/O

-

222

223

224

225

226

227

-

VCC*

C6

F7

A5

B5

GND*

-

11.

12.

13.

14.

-

177

183

186

189

-

I/O

-

I/O

149

192

193

194

-

I/O

150

GND

I/O

151

F1

15.

16.

17.

18.

19.

20.

21.

22.

23.

24.

25.

26.

27.

28.

29.

30.

-

H5

G3

D1

G4

E2

F3

195

198

201

207

210

213

219

222

225

234

237

243

246

249

258

261

-

I/O

-

I/O

-

195

196

197

198

199

200

-

228

229

230

231

232

233

-

D6

C5

A4

E6

B4

D5

-

I/O

-

I/O

152

I/O

153

I/O (A12)

I/O (A13)

I/O

154

G5

C1

F4

155

-

I/O

-

E3

D2

C2

F5

-

I/O

-

234

235

236

237

238

239

240

1

A3

C4

B3

F6

A2

C3

VCC*

GND*

D4

B1

C2

E5

D3

C1

-

I/O

-

I/O

156

157

158

159

160

1

201

202

203

204

205

2

I/O

E4

D3

C3

A2

B1

D4

B2

B3

E6

D5

C4

A3

D6

E7

B4

C5

A4

D7

C6

E8

B5

A5

B6

D8

C7

B7

A6

C8

E9

B8

I/O (A14)

I/O (A15)

VCC

GND

GCK1 (A16, I/O)

I/O (A17)

I/O

-

31.

32.

33.

34.

35.

36.

37.

38.

39.

40.

41.

42.

43.

44.

45.

46.

2

4

2

270

273

279

282

285

294

297

303

306

309

315

318

321

327

330

333

-

3

5

3

4

6

4

I/O

5

7

5

I/O (TDI)

I/O (TCK)

I/O

6

8

6

7

9

7

-

I/O

-

E25

D26

G24

F25

I/O

8

10

11

12

13

-

8

D2

G6

E4

D1

E3

E2

-

I/O

9

I/O

-

10

11

12

13

-

I/O

-

F26

I/O

-

H23

H24

G25

G26

GND*

J23

I/O

-

I/O

-

I/O

-

GND

I/O

10

11

12

13

14

-

14

15

16

17

18

-

14

15

16

17

18

19

20

21

-

GND*

F5

E1

F4

F3

VCC*

F2

F1

-

47.

48.

49.

50.

339

342

345

351

-

I/O

J24

I/O (TMS)

I/O

H25

K23

VCC*

L24

VCC

I/O

51.

52.

53.

-

354

357

363

I/O

-

K25

L25

I/O

-

7-148

November 5, 1998 (Version 5.2)

R

XC5200 Series Field Programmable Gate Arrays

54.

Description

PQ160

-

HQ208

-

HQ240

-

PG299

A8

BG225

-

BG352

L26

Boundary Scan Order

I/O

366

369

375

378

381

390

393

-

55.

56.

57.

58.

59.

60.

-

19

20

21

22

23

24

25

26

27

28

29

30

31

32

-

23

24

25

26

27

28

29

30

31

32

33

34

35

36

-

C9

G4

G3

G2

G1

G5

H3

GND*

VCC*

H4

H5

J2

M23

-

B9

M24

15

16

17

18

19

20

21

22

23

24

-

E10

A9

M25

M26

D10

C10

A10

A11

B10

B11

C11

E11

D11

A12

B12

A13

E12

B13

A16

A14

C13

B14

D13

A15

B15

E13

C14

A17

D14

B16

C15

E14

A18

D15

C16

B17

B18

E15

D16

C17

A20

A19

C18

B20

D17

B19

C19

F16

E17

D18

C20

N24

N25

GND

VCC

I/O

VCC

I/O

GND

I/O

GND*

VCC*

N26

-

61.

62.

63.

64.

65.

66.

67.

68.

69.

70.

399

402

405

411

414

417

423

426

429

435

-

P25

P23

J1

P24

J3

R26

-

J4

R25

-

R24

-

R23

-

38

39

40

41

42

43

44

45

-

J5

T26

-

K1

VCC*

K2

K3

J6

T25

-

VCC*

U24

71.

72.

73.

74.

25

26

27

28

29

-

33

34

35

36

37

-

438

441

447

450

-

V25

V24

L1

U23

7

GND*

-

GND*

Y26

75.

76.

77.

78.

79.

80.

81.

82.

83.

84.

85.

86.

87.

88.

89.

90.

91.

453

459

462

465

471

474

477

483

486

489

495

498

501

507

510

513

522

-

W25

W24

V23

-

46

47

48

49

50

51

-

L2

-

K4

L3

-

38

39

40

41

-

AA26

Y25

-

M1

K5

M2

-

30

31

-

Y24

AA25

AB25

AA24

Y23

-

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

42

43

44

45

46

47

48

49

50

55

56

57

58

59

60

61

62

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

L4

N1

M3

N2

K6

P1

N3

GND*

P2

VCC*

M4

R2

P3

L5

AC26

AA23

AB24

AD25

AC24

AB23

GND*

AD24

VCC*

AC23

AE24

AD23

AC22

AF24

AD22

AE23

M1 (I/O)

GND

92.

M0 (I/O)

VCC

525

-

93.

94.

95.

96.

97.

98.

99.

M2 (I/O)

GCK2 (I/O)

I/O (HDC)

I/O

528

531

540

543

546

552

555

I/O

N4

R3

P4

I/O

I/O (LDC)

November 5, 1998 (Version 5.2)

7-149

R

XC5200 Series Field Programmable Gate Arrays

100.

101.

102.

103.

104.

105.

106.

107.

108.

109.

Description

PQ160

HQ208

-

HQ240

-

PG299

F17

G16

D19

E18

D20

G17

F18

H16

E19

F19

E20

H17

G18

G19

H18

F20

J16

BG225

-

BG352

AE22

AF23

AD20

AE21

AF21

AC19

AD19

AE20

AF20

AC18

GND*

AD18

AE19

AC17

AD17

VCC*

AE17

AE16

AF16

AC15

AD15

AE15

AF15

AD14

AE14

AF14

VCC*

GND*

AE13

AC13

AD13

AF12

AE12

AD12

AC12

AF11

AE11

AD11

VCC*

AE9

Boundary Scan Order

I/O

GND

I/O

VCC

I/O

-

558

564

567

570

576

579

582

588

591

594

-

49

50

-

63

64

65

66

-

69

70

71

72

73

74

-

K7

M5

R4

N5

P5

-

L6

-

51

52

53

54

55

-

67

68

69

70

71

-

75

76

77

78

79

80

81

82

-

GND*

R5

M6

N6

P6

110.

111.

112.

113.

600

603

606

612

-

VCC*

R6

M7

-

114.

115.

116.

117.

118.

119.

120.

121.

122.

123.

-

72

73

-

615

618

624

627

630

636

639

642

648

651

-

G20

H20

J18

-

84

85

86

87

88

89

90

91

92

93

94

95

96

97

-

J19

N7

P7

-

K16

J20

56

57

58

59

60

61

62

63

64

65

-

74

75

76

77

78

79

80

81

82

83

84

85

-

R7

L7

K17

K18

K19

L20

K20

L19

L18

L16

L17

M20

M19

N20

M18

N19

P20

T20

N18

P19

N17

R19

R20

N16

P18

U20

P17

T19

R18

P16

V20

N8

P8

I/O (ERR, INIT)

VCC

GND

I/O

VCC*

GND*

L8

-

124.

125.

126.

127.

128.

129.

130.

131.

132.

133.

660

663

672

675

678

684

687

690

696

699

-

I/O

P9

I/O

R9

N9

M9

L9

I/O

-

I/O

-

I/O

-

I/O

-

99

100

101

102

103

104

105

106

-

R10

P10

VCC*

N10

K9

I/O

-

VCC

I/O

-

134.

135.

136.

137.

66

67

68

69

70

-

86

87

88

89

90

-

702

708

711

714

-

I/O

AD9

I/O

R11

P11

GND*

-

AC10

AF7

I/O

GND

I/O

GND*

AE8

138.

139.

140.

141.

142.

143.

144.

145.

720

723

726

732

735

738

744

747

I/O

-

AD8

I/O

-

107

108

109

110

111

112

M10

N11

R12

L10

P12

M11

AC9

I/O

-

AF6

I/O

-

91

92

93

94

AE7

I/O

-

AD7

I/O

71

72

AE6

I/O

AE5

7-150

November 5, 1998 (Version 5.2)

R

XC5200 Series Field Programmable Gate Arrays

146.

147.

148.

149.

150.

151.

152.

153.

Description

PQ160

-

HQ208

-

HQ240

-

PG299

R17

T18

U19

V19

R16

T17

U18

X20

W20

V18

X19

U17

W19

W18

T15

U16

V17

X18

U15

T14

W17

V16

X17

U14

V15

T13

W16

W15

X16

U13

V14

W14

V13

X15

T12

X14

X13

V12

W12

T11

X12

U11

V11

W11

X10

X11

W10

V10

T10

U10

X9

BG225

-

BG352

AD6

AC7

AF4

AF3

AD5

AE3

AD4

AC5

GND*

AD3

VCC*

AC4

AD2

AC3

AB4

AD1

AA4

AA3

AB2

AC1

Y3

Boundary Scan Order

I/O

750

756

759

768

771

774

780

783

-

73

74

75

76

77

78

79

80

81

82

83

84

85

86

-

95

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

-

R13

N12

P13

K10

R14

N13

GND*

P14

VCC*

M12

P15

N14

L11

M13

N15

M14

-

96

97

98

99

100

101

103

106

108

109

110

111

112

-

GND

DONE

VCC

-

PROG

-

154.

155.

156.

157.

158.

159.

160.

161.

162.

163.

164.

165.

166.

167.

168.

169.

I/O (D7)

GCK3 (I/O)

I/O

792

795

804

807

810

816

819

828

831

834

840

843

846

852

855

858

-

I/O

-

I/O

-

I/O

-

I/O (D6)

I/O

87

88

89

90

-

113

114

115

116

117

118

-

129

130

131

132

133

134

-

J10

L12

M15

L13

L14

K11

-

AA2

AA1

W4

I/O

7

I/O

W3

I/O

-

Y2

I/O

-

Y1

I/O

-

V4

GND

I/O

91

-

119

-

135

136

137

138

139

140

141

142

-

GND*

L15

K12

K13

K14

VCC*

K15

J12

-

GND*

V3

170.

171.

172.

173.

864

867

870

876

-

I/O

-

W2

I/O

92

93

-

120

121

-

U4

I/O

U3

VCC

I/O (D5)

I/O (CS0)

I/O

VCC*

V2

174.

175.

176.

177.

178.

179.

180.

181.

182.

183.

94

95

-

122

123

-

879

882

888

891

894

900

903

906

912

915

-

V1

T1

I/O

-

R4

I/O

-

124

125

126

127

128

129

130

131

132

133

134

135

136

137

144

145

146

147

148

149

150

151

152

153

154

155

156

157

J13

J14

J15

J11

H13

H14

VCC*

GND*

H12

H11

G14

G15

G13

G12

R3

I/O

-

R2

I/O

96

97

98

99

100

101

102

103

104

105

-

R1

I/O

P3

I/O (D4)

I/O

P2

P1

VCC

GND

I/O (D3)

I/O (RS)

I/O

VCC*

GND*

N2

-

184.

185.

186.

187.

188.

189.

924

927

936

939

942

948

N4

N3

I/O

M1

I/O

M2

I/O

-

W9

M3

November 5, 1998 (Version 5.2)

7-151

R

XC5200 Series Field Programmable Gate Arrays

190.

191.

192.

193.

Description

PQ160

HQ208

-

HQ240

-

PG299

X8

V9

W8

X7

X5

V8

W7

U8

W6

X6

T8

BG225

-

BG352

M4

L1

Boundary Scan Order

I/O

-

951

954

960

963

-

I/O (D2)

106

107

-

138

139

-

159

160

161

162

163

164

165

166

-

G11

F15

VCC*

F14

F13

G10

E15

GND*

-

J1

I/O

K3

VCC

VCC*

J2

194.

195.

196.

197.

I/O

108

109

-

140

141

-

966

972

975

978

I/O

J3

I/O

K4

I/O

-

G1

GND*

H2

GND

110

-

142

-

198.

199.

200.

201.

202.

203.

204.

205.

206.

207.

208.

209.

210.

211.

212.

213.

I/O

984

987

990

996

999

1002

1008

1011

1014

1020

1023

1032

1035

1038

1044

1047

-

I/O

-

V7

X4

U7

W5

V6

T7

-

H3

I/O

-

167

168

169

170

171

172

173

174

-

E14

F12

E13

D15

F11

D14

E12

C15

-

J4

I/O

-

F1

I/O

-

143

144

145

146

147

148

-

G2

G3

F2

I/O

-

I/O

111

112

113

114

-

I/O

X3

U6

V5

W4

W3

T6

E2

I/O (D1)

F3

I/O (RCLK-BUSY/RDY)

G4

D2

I/O

-

F4

I/O

115

116

117

118

119

120

121

122

123

124

125

126

127

128

-

149

150

151

152

153

154

159

160

161

162

163

164

165

166

-

175

176

177

178

179

180

181

182

183

184

185

186

187

188

-

D13

C14

F10

B15

C13

VCC*

A15

GND*

A14

B13

E11

C12

A13

B12

-

E3

I/O

U5

V4

X1

V3

W1

U4

X2

W2

V2

R5

T4

C2

I/O (D0, DIN)

D3

I/O (DOUT)

E4

CCLK

C3

VCC

VCC*

D4

-

214.

I/O (TDO)

0

GND

GND*

B3

-

215.

216.

217.

218.

219.

220.

221.

222.

223.

224.

225.

226.

227.

228.

229.

230.

I/O (A0, WS)

9

GCK4 (A1, I/O)

C4

15

I/O

D5

18

I/O

A3

21

I/O (A2, CS1)

I/O (A3)

I/O

U3

V1

R4

P5

U2

T3

D6

27

C6

30

B5

33

I/O

-

A4

39

I/O

-

189

190

191

192

193

194

195

-

F9

C7

42

I/O

-

D11

A12

C11

B11

E10

-

B6

45

I/O

129

130

-

167

168

169

170

-

U1

P4

R3

N5

T2

A6

51

I/O

D8

54

I/O

B7

57

I/O

-

A7

63

I/O

-

D9

66

I/O

-

R2

T1

-

C9

69

GND

I/O

131

132

133

-

171

172

173

-

196

197

198

199

200

201

GND*

A11

D10

C10

B10

VCC*

GND*

B8

-

231.

232.

233.

234.

N4

P3

P2

N3

R1

75

I/O

D10

C10

B9

78

I/O

81

I/O

-

87

VCC

-

VCC*

-

7-152

November 5, 1998 (Version 5.2)

R

XC5200 Series Field Programmable Gate Arrays

235.

236.

237.

238.

239.

240.

241.

242.

243.

244.

Description

PQ160

-

HQ208

-

HQ240

-

PG299

M5

P1

BG225

-

BG352

B11

Boundary Scan Order

I/O

90

93

-

A11

I/O (A4)

I/O (A5)

I/O

134

135

-

174

175

176

177

178

179

180

181

182

202

203

205

206

207

208

209

210

211

N1

M3

M2

L5

A10

D9

D12

C12

B12

99

102

105

111

114

117

126

129

-

C9

I/O

136

137

138

139

140

141

B9

A12

I/O

M1

L4

A9

C13

B13

I/O

E9

I/O (A6)

I/O (A7)

GND

L3

C8

A13

L2

B8

B14

L1

GND*

Additional No Connect (N.C.) Connections for HQ208 and HQ240 Packages

HQ208

HQ240

219

22

206

207

208

1

102

104

105

107

155

156

157

158

-

37

83

3

98

51

52

53

54

143

158

204

-

7

Notes: * Pins labeled VCC* are internally bonded to a VCC plane within the BG225 and BG352 packages. The external pins for the

BG225 are: B2, D8, H15, R8, B14, R1, H1, and R15. The external pins for the BG352 are: A10, A17, B2, B25, D13, D19, D7,

G23, H4, K1, K26, N23, P4, U1, U26, W23, Y4, AC14, AC20, AC8, AE2, AE25, AF10, and AF17.

Pins labeled GND* are internally bonded to a ground plane within the BG225 and BG352 packages. The external pins for the

BG225 are: A1, D12, G7, G9, H6, H8, H10, J8, K8, A8, F8, G8, H2, H7, H9, J7, J9, M8. The external pins for the BG352 are:

A1, A2, A5, A8, A14, A19, A22, A25, A26, B1, B26, E1, E26, H1, H26, N1, P26, W1, W26, AB1, AB26, AE1, AE26, AF1,

AF13, AF19, AF2, AF22, AF25, AF26, AF5, AF8.

Boundary Scan Bit 0 = TDO.T

Boundary Scan Bit 1 = TDO.O

Boundary Scan Bit 1056 = BSCAN.UPD

November 5, 1998 (Version 5.2)

7-153

R

XC5200 Series Field Programmable Gate Arrays

Product Availability

PINS

64

84

100

144

156

160

176

191

208

223

225

240

299

352

TYPE

CODE

-6

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

-5

-4

-3

-6

-5

-4

-3

-6

-5

-4

-3

-6

-5

-4

-3

-6

-5

-4

-3

XC5202

XC5204

XC5206

XC5210

C

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

CI

C

XC5215

C

7/8/98

C = Commercial T_J= 0° to +85°C

I= Industrial T_J= -40°C to +100°C

* VQ64 package supports Master Serial, Slave Serial, and Express configuration modes only.

User I/O Per Package

Package Type

Max

I/O

Device

VQ64

52

PC84 PQ100 VQ100 TQ144 PG156 PQ160 TQ176 PG191 HQ208 PQ208 PG223 BG225 HQ240 PQ240 PG299 BG352

84

65

81

84

XC5202

XC5204

XC5206

XC5210

124

148

196

244

117

124

133

148

149

148

164

196

164

197

244

XC5215

7/8/98

Ordering Information

Example:

XC5210-6PQ208C

Temperature Range

Number of Pins

Package Type

Device Type

Speed Grade

7-154

November 5, 1998 (Version 5.2)

R

XC5200 Series Field Programmable Gate Arrays

Revisions

Version

12/97

7/98

Description

Rev 5.0 added -3, -4 specification

Rev 5.1 added Spartan family to comparison, removed HQ304

11/98

Rev 5.2 All specifications made final.

7

November 5, 1998 (Version 5.2)

7-155


型号：	XC5206-3VQ100I
厂家：	ETC
描述：	Field Programmable Gate Array (FPGA) 现场可编程门阵列（FPGA）的\n 现场可编程门阵列可编程逻辑栅时钟
文件：	总73页 (文件大小：583K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XC5206-3VQ100I [ETC]

相关型号：

XC5206-3VQ64C

XC5206-3VQG100I

XC5206-4BG225C

XC5206-4BG352C

XC5206-4HQ208C

XC5206-4HQ240C

XC5206-4PC84C

XC5206-4PC84I

XC5206-4PG156C

XC5206-4PG191C

XC5206-4PG191I

XC5206-4PG223C