XC95144XLSERIES [ETC]
High Performance CPLD ; 高性能CPLD\n
| 型号： | XC95144XLSERIES |
| 厂家： | 
ETC |
| 描述： | High Performance CPLD
|
| 文件： | 总9页 (文件大小：86K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XC95144XL High Performance
CPLD
Preliminary Product Specification
November 13, 1998 (Version 1.2)
Features
Power Estimation
•
•
•
•
5 ns pin-to-pin logic delays
Power dissipation in CPLDs can very substantially depend-
ing on the system frequency, design application, and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
System frequency up to 178 MHz
144 macrocells with 3,200 usable gates
Available in small footprint packages
-
-
-
100-pin TQFP (81 user I/O pins)
144-pin TQFP (117 user I/O pins)
144-pin CSP (117 user I/O pins)
•
•
Optimized for high-performance 3.3 V systems
For a general estimate of I , the following equation may
CC
-
-
Low power operation
5 V tolerant I/O pins accept 5 V, 3.3 V, and 2.5 V
signals
be used:
ICC (mA) = MCHP(0.5) + MCLP(0.3) + MC(0.0045 mA/MHz) f
-
-
3.3 V or 2.5 V output capability
Advanced 0.35 micron feature size CMOS
FastFLASH™ technology
Where:
MC = Macrocells in high-performance (default) mode
HP
Advanced system features
MC = Macrocells in low-power mode
LP
-
-
In-system programmable
MC = Total number of macrocells used
f = Clock frequency (MHz)
Superior pin-locking and routability with
FastCONNECT II™ switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with individual
product-term allocation
Local clock inversion with 3 global and one product-
term clocks
Individual output enable per output pin with local
inversion
Input hysteresis on all user and boundary-scan pin
inputs
Bus-hold ciruitry on all user pin inputs
Full IEEE Standard 1149.1 boundary-scan (JTAG)
-
-
This calculation is based on typical operating conditions
using a pattern of 16-bit up/down counters in each Function
Block with no output loading. The actual I
with the design application and should be verified during
normal system operation.
value varies
CC
-
-
-
Figure 1 shows the above estimation in graphical form.
200
178 MHz
-
-
•
•
•
•
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
150
Performance
High
104 MHz
100
-
-
-
Endurance exceeding 10,000 program/erase cycles
20 year data retention
ESD protection exceeding 2,000 V
ower
50
P
Low
50
0
•
Pin-compatible with 5 V-core XC95144 device in the
100-pin TQFP package
150
Clock Frequency (MHz)
100
200
Description
X5898C
The XC95144XL is a 3.3 V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of eight
54V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 5 ns. See Figure 2 for architecture
overview.
Figure 1: Typical Icc vs. Frequency for XC95144XL
November 13, 1998 (Version 1.2)
1
XC95144XL High Performance CPLD
3
JTAG
In-System Programming Controller
1
JTAG Port
Controller
54
Function
18
18
18
18
Block 1
I/O
Macrocells
1 to 18
I/O
I/O
I/O
54
54
54
Function
Block 2
Macrocells
1 to 18
I/O
Blocks
I/O
I/O
Function
Block 3
Macrocells
1 to 18
I/O
I/O
3
I/O/GCK
I/O/GSR
I/O/GTS
Function
Block 4
1
4
Macrocells
1 to 18
54
Function
Block 8
18
Macrocells
1 to 18
X5922B
Figure 2: XC95144XL Architecture
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.
2
November 13, 1998 (Version 1.2)
Absolute Maximum Ratings
Symbol
Description
Value
Units
V
Supply voltage relative to GND
-0.5 to 4.0
V
CC
V
Input voltage relative to GND (Note 1)
Voltage applied to 3-state output (Note 1)
Storage temperature (ambient)
-0.5 to 5.5
-0.5 to 5.5
-65 to +150
+260
V
V
IN
V
TS
o
T
T
C
STG
SOL
o
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)
Junction temperature
C
o
T
+150
C
J
Note 1: Maximum DC undershoot below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During
transitions, the device pins may undershoot to -2.0 V or overshoot to +7.0 V, provided this over- or undershoot lasts less
than 10 ns and with the forcing current being limited to 200 mA.
Note 2: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating
Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device
reliability.
Recommended Operation Conditions
Symbol
Parameter
Commercial T = 0 C to 70 C
Min
3.0
3.0
3.0
2.3
0
Max
3.6
Units
o
o
V
Supply voltage for internal logic
and input buffers
V
V
V
V
V
V
V
CCINT
A
o
o
Industrial T = -40 C to +85 C
3.6
A
V
Supply voltage for output drivers for 3.3 V operation
Supply voltage for output drivers for 2.5 V operation
Low-level input voltage
3.6
CCIO
2.7
V
0.80
5.5
IL
V
High-level input voltage
2.0
0
IH
V
Output voltage
V
CCIO
O
Quality and Reliability Characteristics
Symbol
Parameter
Min
20
Max
Units
t
Data Retention
-
-
-
Years
Cycles
Volts
DR
N
Program/Erase Cycles (Endurance)
Electrostatic Discharge (ESD)
10,000
2,000
PE
V
ESD
DC Characteristics Over Recommended Operating Conditions
Symbol
Parameter
Test Conditions
Min
Max
Units
V
Output high voltage for 3.3 V outputs
Output high voltage for 2.5 V outputs
I
I
= -4.0 mA
2.4
V
V
OH
OH
OH
= -500 µA
90% V
CCIO
V
I
Output low voltage for 3.3 V outputs
Output low voltage for 2.5 V outputs
Input leakage current
I
I
= 8.0 mA
0.4
0.4
V
V
OL
OL
= 500 µA
OL
V
V
= Max
CC
= GND or VCC
± 10.0
µA
IL
IN
I
I/O high-Z leakage current
I/O capacitance
V
V
= Max
= GND or V
± 10.0
10.0
µA
pF
ma
IH
CC
IN
CC
C
V
= GND
IN
IN
f = 1.0 MHz
I
Operating Supply Current
(low power mode, active)
V = GND, No load
f = 1.0 MHz
45
CC
I
November 13, 1998 (Version 1.2)
3
XC95144XL High Performance CPLD
AC Characteristics
XC95144XL-5
XC95144XL-7
XC95144XL-10
Symbol
Parameter
Units
Min1
Max1
Min
Max
Min
Max
t
t
I/O to output valid
5.0
7.5
10.0
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PD
I/O setup time before GCK
I/O hold time after GCK
3.7
0.0
4.8
0.0
6.5
0.0
SU
t
H
t
GCK to output valid
3.5
4.5
5.8
CO
SYSTEM
f
Multiple FB internal operating frequency
I/O setup time before p-term clock input
I/O hold time after p-term clock input
P-term clock output valid
178.6
125.0
100.0
t
1.7
2.0
1.6
3.2
2.1
4.4
PSU
t
PH
t
5.5
4.0
7.7
5.0
10.2
7.0
PCO
t
GTS to output valid
OE
t
GTS to output disable
4.0
5.0
7.0
OD
t
Product term OE to output enabled
Product term OE to output disabled
GSR to output valid
7.0
9.5
11.0
11.0
14.5
15.3
POE
POD
t
7.0
9.5
t
10.0
10.5
12.0
12.6
AO
t
P-term S/R to output valid
GCK pulse width (High or Low)
P-term clock pulse width (High or Low)
PAO
t
2.8
5.0
4.0
6.5
4.5
7.0
WLH
t
PLH
Advance
Preliminary
Note 1:Please contact Xilinx for up-to-date information on advance specifications.
V
TEST
R
1
Output Type
V
V
R
R
2
C
L
CCIO
TEST
1
Device Output
3.3 V
2.5 V
3.3 V
2.5 V
320 Ω
250 Ω
360 Ω
660 Ω
35 pF
35 pF
R
C
L
2
X5906A
Figure 3: AC Load Circuit
4
November 13, 1998 (Version 1.2)
Internal Timing Parameters
XC95144XL-5
XC95144XL-7
XC95144XL-10
Symbol
Parameter
Units
Min1
Max1
Min
Max
Min
Max
Buffer Delays
t
Input buffer delay
1.5
1.1
2.0
4.0
2.0
0.0
2.3
1.5
3.1
5.0
2.5
0.0
3.5
1.8
4.5
7.0
3.0
0.0
ns
ns
ns
ns
ns
ns
IN
t
t
GCK buffer delay
GCK
GSR buffer delay
GSR
t
t
GTS buffer delay
GTS
Output buffer delay
Output buffer enable/disable delay
OUT
t
EN
Product Term Control Delays
t
t
Product term clock delay
Product term set/reset delay
Product term 3-state delay
1.6
1.0
5.5
2.4
1.4
7.2
2.7
1.8
7.5
ns
ns
ns
PTCK
PTSR
t
PTTS
Internal Register and Combinatorial Delays
t
t
Combinatorial logic propagation delay
Register setup time
0.5
1.3
1.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PDI
2.3
1.4
2.3
1.4
2.6
2.2
2.6
2.2
3.0
3.5
3.0
3.5
SUI
t
Register hold time
HI
t
Register clock enable setup time
Register clock enable hold time
Register clock to output valid time
Register async. S/R to output delay
Register async. S/R recover before clock
Internal logic delay
ECSU
t
ECHO
t
0.4
6.0
0.5
6.4
1.0
7.0
COI
t
t
AOI
RAI
5.0
7.5
10.0
t
1.0
5.0
1.4
6.4
1.8
7.3
LOGI
t
Internal low power logic delay
LOGILP
Feedback Delays
FastCONNECT II™ feedback delay
Time Adders
t
1.9
3.5
4.2
ns
F
t
Incremental product term allocator delay
Slew-rate limited delay
0.7
3.0
0.8
4.0
1.0
4.5
ns
ns
PTA
t
SLEW
Advance
Preliminary
Note 1: Please contact Xilinx for up-to-date information on advance specifications.
November 13, 1998 (Version 1.2)
5
XC95144XL High Performance CPLD
XC95144XL I/O Pins
Function
Block
BScan
Order
Function
Block
BScan
Order
Macrocell TQ100 TQ144 CS144
Notes
Macrocell TQ100 TQ144 CS144
Notes
1
1
2
–
11
12
–
23
16
17
25
19
20
-
H3
F1
G2
J1
G3
G4
-
429
426
423
420
417
414
411
408
405
402
399
396
393
390
387
384
381
378
375
372
369
366
363
360
357
354
351
348
345
342
339
336
333
330
327
324
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
2
–
23
–
39
32
M3
L1
K4
N4
L2
L3
L5
N2
N3
N5
M4
K5
-
321
318
315
312
309
306
303
300
297
294
291
288
285
282
279
276
273
270
267
264
261
258
255
252
249
246
243
240
237
234
231
228
225
222
219
216
1
[1]
1
3
3
41
1
4
4
–
44
1
5
13
14
-
5
24
25
–
33
1
6
6
34
1
7
7
46
1
8
15
16
–
21
22
31
24
26
-
H1
H2
K3
H4
J2
-
8
27
28
–
38
[1]
1
9
9
40
1
10
11
12
13
14
15
16
17
18
1
10
11
12
13
14
15
16
17
18
1
48
1
17
18
–
29
30
–
43
1
45
1
-
1
19
20
–
27
28
35
30
–
J3
J4
M1
K2
-
32
33
–
49
K6
L6
-
1
50
1
-
1
22
–
[1]
[1]
34
–
51
M6
-
1
–
2
–
142
143
-
C3
A2
-
–
118
126
133
-
C9
A7
A5
-
2
2
99
–
2
87
–
2
3
3
2
4
–
4
C1
B1
C2
-
4
–
2
5
1
2
[1]
[1]
5
89
90
–
128
129
-
D7
A6
-
2
6
2
3
6
2
7
–
-
7
2
8
3
5
D4
D3
D2
E4
E3
E1
E2
F4
F3
F2
-
[1]
[1]
8
91
92
–
130
131
135
132
134
137
136
138
139
140
-
B6
C6
C5
D6
B5
A4
D5
B4
C4
A3
-
2
9
4
6
9
2
10
11
12
13
14
15
16
17
18
–
7
10
11
12
13
14
15
16
17
18
2
6
9
93
94
–
2
7
10
12
11
13
14
15
–
2
–
2
8
95
96
–
2
9
2
–
2
10
–
97
-
2
Note 1: Global control pin.
6
November 13, 1998 (Version 1.2)
XC95144XL (Continued)
Function
BScan
Order
Function
Block
BScan
Order
Macrocell TQ100 TQ144 CS144
Block
Notes
Macrocell TQ100 TQ144 CS144
Notes
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
1
2
-
-
-
N6
L8
-
213
210
207
204
201
198
195
192
189
186
183
180
177
174
171
168
165
162
159
156
153
150
147
144
141
138
135
132
129
126
123
120
117
114
111
108
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
1
2
–
50
–
–
71
75
-
-
105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
35
–
52
59
-
N12
L12
-
3
3
4
–
4
–
5
36
37
–
53
54
66
56
57
68
58
60
70
61
64
-
M7
N7
M10
K7
N8
N11
M8
K8
L11
N9
K9
-
5
52
53
–
74
76
77
78
80
79
82
85
81
86
87
83
88
–
M13
L13
K10
K11
K13
K12
J11
H10
J10
H11
H12
J12
H13
-
6
6
7
7
8
39
40
–
8
54
55
–
9
9
10
11
12
13
14
15
16
17
18
1
10
11
12
13
14
15
16
17
18
1
41
42
–
56
58
–
43
46
–
59
60
–
49
–
69
–
M11
-
61
–
–
–
-
–
–
-
2
74
–
106
-
C11
-
2
63
–
91
95
97
92
93
-
G11
F11
E13
G10
F13
-
3
3
4
–
111
110
112
-
B11
A12
A11
-
4
–
5
76
77
–
5
64
65
–
6
6
7
7
8
78
79
–
113
116
115
119
120
-
D10
A10
B10
B9
A9
-
8
66
67
–
94
96
101
98
100
103
102
104
107
105
–
F12
F10
D13
E12
E10
D11
D12
C13
B13
C12
-
9
9
10
11
12
13
14
15
16
17
18
10
11
12
13
14
15
16
17
18
80
81
–
68
70
–
82
85
–
121
124
117
125
–
D8
A8
D9
B7
-
71
72
–
6
86
–
73
–
3
0
November 13, 1998 (Version 1.2)
7
XC95144XL High Performance CPLD
XC95144XL Global, JTAG and Power Pins
Pin Type
I/O/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GTS3
I/O/GTS4
I/O/GSR
TCK
TQ100
TQ144
CS144
22
30
K2
23
32
L1
27
38
N2
3
5
D4
4
6
D3
1
2
B1
2
3
C2
99
143
A2
48
67
L10
TDI
45
83
63
122
L9
C8
TDO
TMS
47
65
N10
V
3.3 V
5, 57, 98
26, 38, 51, 88
8, 42, 84, 141
B3, D1, J13, L4
CCINT
V
2.5 V/3.3 V
1, 37, 55, 73, 109, 127 A1, A13, C7, L7, N1, N13
CCIO
21, 31, 44, 62, 69, 75, 84, 18, 29, 36, 47, 62, 72, 89, B2, B8, B12, C10, E11,
GND
100
90, 99, 108, 114, 123, 144 G1, G12, G13, K1, M2,
M5, M9, M12
No Connects
-
–
–
Ordering Information
Example:
XC95144XL -7 TQ 100 C
Device Type
Temperature Range
Number of Pins
Package Type
Speed Grade
Speed Options
Packaging Options
-10 10 ns pin-to-pin delay
-7 7.5 ns pin-to-pin delay
-5 5 ns pin-to-pin delay
TQ100 100-Pin Thin Quad Flat Pack (TQFP)
TQ144 144-Pin Thin Quad Flat Pack (TQFP)
CS144 144-Pin Chip Scale Package (CSP)
Temperature Options
o
o
C= Commercial T = 0 C to +70 C
I = Industrial
A
o
o
T = -40 C to +85 C
A
8
November 13, 1998 (Version 1.2)
Component Availability
Pins
100
144
144
Type
Plastic
TQFP
Plastic
TQFP
Chip Scale Package
CSP
Code
TQ100
C, I
C
TQ144
C, I
C
CS144
-10
-
(C)
-
XC95144XL
-7
-5
(C)
(C)
C = Commercial (TA = 0oC to +70oC) I = Industrial (TA = -40oC to +85oC)
( ) Parenthesis indicate future planned products. Please contact Xilinx for up-to-date availability
information.
Revision History
Date
Revision
10/30/98
11/13/98
Minor corrections in CS144 pinout table.
V1.2 Minor correction in CS144 pinout table.
November 13, 1998 (Version 1.2)
9
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