XCR3064XLSERIES [ETC]
64 Macrocell CPLD ; 64宏单元CPLD\n
| 型号： | XCR3064XLSERIES |
| 厂家： | 
ETC |
| 描述： | 64 Macrocell CPLD
|
| 文件： | 总9页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
R
XCR3064XL 64 Macrocell CPLD
0
14
DS017 (v1.6) January 8, 2002
Product Specification
Features
Description
•
•
•
•
•
Lowest power 64 macrocell CPLD
The XCR3064XL is a 3.3V, 64-macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of four function blocks provide
1,500 usable gates. Pin-to-pin propagation delays are
6.0 ns with a maximum system frequency of 145 MHz.
6.0 ns pin-to-pin logic delays
System frequencies up to 145 MHz
64 macrocells with 1,500 usable gates
Available in small footprint packages
TotalCMOS Design Technique for Fast
Zero Power
-
-
-
-
-
44-pin PLCC (36 user I/O pins)
44-pin VQFP (36 user I/O pins)
48-ball CS BGA (40 user I/O pins)
56-ball CP BGA (48 user I/O pins)
100-pin VQFP (68 user I/O pins)
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
•
•
Optimized for 3.3V systems
-
-
-
Ultra-low power operation
5V tolerant I/O pins with 3.3V core supply
Figure 1 and Table 1 showing the I vs. Frequency of our
CC
Advanced 0.35 micron five layer metal EEPROM
process
XCR3064XL TotalCMOS CPLD (data taken with four
resetable up/down, 16-bit counters at 3.3V, 25°C).
-
Fast Zero Power™ (FZP) CMOS design
technology
35.0
30.0
25.0
20.0
15.0
10.0
5.0
Advanced system features
-
-
-
-
-
-
-
-
In-system programming
Input registers
Predictable timing model
Up to 23 available clocks per function block
Excellent pin retention during design changes
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Four global clocks
Eight product term control terms per function block
•
•
•
Fast ISP programming times
Port Enable pin for dual function of JTAG ISP pins
0.0
2.7V to 3.6V supply voltage at industrial temperature
range
0
20
40
60
80
100 120 140
Frequency (MHz)
•
•
•
Programmable slew rate control per macrocell
Security bit prevents unauthorized access
DS017_01_102401
Figure 1: I vs. Frequency at V = 3.3V, 25°C
Refer to XPLA3 family data sheet (DS012) for
CC
CC
architecture description
Table 1: I vs. Frequency (V = 3.3V, 25°C)
CC
CC
Frequency (MHz)
0
1
5
10
20
40
60
11.3
80
100
18.5
120
140
Typical I (mA)
0
0.2
1.0
2.0
3.9
7.6
14.8
22.1
25.6
CC
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS017 (v1.6) January 8, 2002
www.xilinx.com
1
Product Specification
1-800-255-7778
R
XCR3064XL 64 Macrocell CPLD
DC Electrical Characteristics Over Recommended Operating Conditions(1)
Symbol
Parameter
Output High voltage
Test Conditions
= –8 mA
Min.
Max.
-
Unit
V
(2)
V
I
I
2.4
OH
OL
OH
OL
V
Output Low voltage for 3.3V outputs
Input leakage current
= 8 mA
-
0.4
10
10
100
0.5
15
8
V
I
I
I
I
V
V
V
= GND or V
= GND or V
–10
µA
µA
µA
mA
mA
pF
pF
pF
IL
IN
CC
CC
I/O High-Z leakage current
Standby current
–10
IH
IN
= 3.6V
-
-
-
-
-
-
CCSB
CC
CC
(3,4)
Dynamic current
f = 1 MHz
f = 50 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
(5)
C
C
C
Input pin capacitance
IN
(5)
Clock input capacitance
12
10
CLK
I/O
(5)
I/O pin capacitance
Notes:
1. See XPLA3 family data sheet (DS012) for recommended operating conditions.
2. See Figure 2 for output drive characteristics of the XPLA3 family.
3. See Table 1, Figure 1 for typical values.
4. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and
unloaded. Inputs are tied to V or ground. This parameter guaranteed by design and characterization, not testing.
CC
5. Typical values, not tested.
100
90
I
(3.3V)
OL
80
70
60
50
40
30
I
(3.3V)
OH
I
(2.7V)
OH
20
10
0
0
0.5
1
1.5
2
2.5
Volts
3
3.5
4
4.5
5
DS012_10_041901
Figure 2: Typical I/V Curve for the XPLA3 Family
2
www.xilinx.com
DS017 (v1.6) January 8, 2002
1-800-255-7778
Product Specification
R
XCR3064XL 64 Macrocell CPLD
AC Electrical Characteristics Over Recommended Operating Conditions(1,2)
-6
-7
-10
Symbol
Parameter
Min.
Max.
5.5
6.0
4.0
-
Min.
Max.
7.0
7.5
5.0
-
Min.
Max.
9.1
10.0
6.5
-
Unit
ns
T
T
T
T
T
T
T
T
Propagation delay time (single p-term)
-
-
-
PD1
PD2
CO
(3)
Propagation delay time (OR array)
-
-
-
ns
Clock to output (global synchronous pin clock)
Setup time (fast input register)
Setup time (single p-term)
Setup time (OR array)
-
-
-
ns
2.5
2.5
3.0
ns
SUF
(4)
3.5
-
4.3
-
5.4
-
ns
SU1
4.0
-
4.8
-
6.3
-
ns
SU2
(4)
H
Hold time
0
-
0
-
0
-
ns
(4)
Global Clock pulse width (High or Low)
P-term clock pulse width
Input rise time
2.5
-
3.0
-
4.0
-
ns
WLH
(4)
Tt
4.0
-
5.0
-
6.0
-
ns
PLH
(4)
T
T
-
-
-
-
-
-
-
-
-
20
20
145
60
60
7.5
7.5
6.5
8.0
-
-
-
-
-
-
-
-
-
20
20
119
60
60
9.3
9.3
8.3
9.3
-
-
-
-
-
-
-
-
-
20
20
95
60
60
11.2
11.2
10.7
11.2
ns
R
(4)
Input fall time
ns
L
(4)
(4)
f
Maximum system frequency
MHz
µs
µs
ns
SYSTEM
(5)
T
T
T
T
T
T
Configuration time
CONFIG
(4)
ISP initialization time
INIT
(4)
P-term OE to output enabled
POE
POD
PCO
(4)
(4)
(6)
P-term OE to output disabled
ns
P-term clock to output
ns
(4)
P-term set/reset to output valid
ns
PAO
Notes:
1. Specifications measured with one output switching.
2. See XPLA3 family data sheet (DS012) for recommended operating conditions.
3. See Figure 4 for derating.
4. These parameters guaranteed by design and/or characterization, not testing.
5. Typical current draw during configuration is 6 mA at 3.6V.
6. Output C = 5 pF.
L
DS017 (v1.6) January 8, 2002
www.xilinx.com
3
Product Specification
1-800-255-7778
R
XCR3064XL 64 Macrocell CPLD
Internal Timing Parameters(2)
-6
-7
-10
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Buffer Delays
T
T
T
T
T
Input buffer delay
-
-
-
-
-
1.3
2.3
0.8
2.2
4.2
-
-
-
-
-
1.6
3.0
1.0
2.7
5.0
-
-
-
-
-
2.2
3.1
1.3
3.6
5.7
ns
ns
ns
ns
ns
IN
Fast Input buffer delay
FIN
GCK
OUT
EN
Global Clock buffer delay
Output buffer delay
Output buffer enable/disable delay
Internal Register and Combinatorial Delays
T
T
T
T
T
T
Latch transparent delay
-
1.0
0.3
2.0
3.0
-
1.3
-
-
1.0
0.5
2.5
4.5
-
1.6
-
-
1.2
0.7
3.0
5.5
-
2.0
-
LDI
Register setup time
ns
ns
ns
ns
ns
ns
ns
ns
ns
SUI
Register hold time
-
-
-
HI
Register clock enable setup time
Register clock enable hold time
Register clock to output delay
Register async. S/R to output delay
Register async. recovery
-
-
-
ECSU
ECHO
COI
-
-
-
1.0
2.5
4.0
2.0
2.5
1.3
2.3
5.0
2.7
3.2
1.6
2.1
6.0
3.3
4.2
T
-
-
-
AOI
T
-
-
-
RAI
T
T
Internal logic delay (single p-term)
Internal logic delay (PLA OR term)
-
-
-
LOGI1
LOGI2
-
-
-
Feedback Delays
ZIA delay
Time Adders
T
-
2.4
-
2.9
-
3.5
ns
F
T
T
T
Fold-back NAND delay
Universal delay
-
-
-
6.0
1.5
4.0
-
-
-
7.5
2.0
5.0
-
-
-
9.5
2.5
6.0
ns
ns
ns
LOGI3
UDA
Slew rate limited delay
SLEW
Notes:
1. These parameters guaranteed by design and/or characterization, not testing.
2. See XPLA3 family data sheet (DS012) for timing model.
4
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DS017 (v1.6) January 8, 2002
1-800-255-7778
Product Specification
R
XCR3064XL 64 Macrocell CPLD
Switching Characteristics
V
CC
S1
Component
Values
R1
R2
C1
390Ω
390Ω
35 pF
R1
V
IN
V
OUT
Measurement
S1
S2
Open
Closed
Open
T
(High)
(Low)
POE
R2
C1
T
Closed
Closed
POE
T
Closed
P
Note: For T
, C1 = 5 pF. Delay measured at
POD
output level of V + 300 mV, V
– 300 mV.
OL
OH
S2
DS017_03_102401
Figure 3: AC Load Circuit
5.6
5.5
5.4
5.3
5.2
5.1
5.0
4.9
+3.0V
0V
90%
10%
T
T
L
R
1.5 ns
1.5 ns
Measurements:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
1
2
4
8
16
DS017_05_042800
Number of Adjacent Outputs Switching
DS017_04_042800
Figure 5: Voltage Waveform
Figure 4: Derating Curve for T
PD2
DS017 (v1.6) January 8, 2002
Product Specification
www.xilinx.com
1-800-255-7778
5
R
XCR3064XL 64 Macrocell CPLD
Pin Descriptions
Table 3: XCR3064XL I/O Pins
Function Macro-
Table 2: XCR3064XL User I/O Pins
Block
cell
15
16
1
PC44 VQ44 CS48 CP56 VQ100
PC44
VQ44
CS48
CP56 VQ100
48 68
2
12
-
6
-
D1
-
F1
-
13
14
Total User
I/O Pins
36
36
40
2
(1)
(1)
(1)
(1)
(1)
3
32
26
E5
F10
G8
-
62
3
2
31
-
25
-
E7
-
61
60
58
57
56
54
52
48
47
46
45
44
42
41
40
Table 3: XCR3064XL I/O Pins
3
3
Function Macro-
Block
cell
PC44 VQ44 CS48 CP56 VQ100
3
4
29
-
23
-
F7
-
H10
-
1
1
41
40
-
35
34
-
C5
A6
-
C8
A8
-
85
84
83
81
80
79
76
75
3
5
1
2
3
6
-
-
-
-
1
3
3
7
-
-
F6
-
K8
K10
K9
J10
H8
H7
H6
-
1
4
-
-
-
A9
A5
A10
-
3
8
-
-
1
5
-
-
-
3
9
28
27
26
25
24
-
22
21
20
19
18
-
G7
G6
F5
G5
F4
-
1
6
-
-
A7
-
3
10
11
12
13
14
15
16
1
1
7
-
-
3
1
8
39
33
B6
B10
3
(1)
(1)
(1)
(1)
(1)
1
9
38
32
B7
C10
D8
E8
-
73
3
1
10
11
12
13
14
15
16
1
37
36
-
31
30
-
D4
C6
-
71
69
68
67
65
64
63
92
93
94
96
97
98
99
100
3
1
3
-
-
-
K7
-
1
3
-
-
-
(1)
(1)
(1)
(1)
(1)
1
-
-
-
-
4
13
7
D2
G1
15
1
34
33
-
28
27
-
D6
D7
-
F8
E10
-
4
2
14
-
8
-
E1
-
F3
-
16
17
19
20
21
23
25
29
30
31
32
33
35
36
37
1
4
3
1
4
4
16
17
-
10
11
-
F1
G1
-
G3
J1
-
2
4
42
43
44
-
A2
A1
C4
-
C4
C3
A1
-
4
5
2
2
5
4
6
2
3
6
4
7
-
-
-
-
2
4
-
4
8
-
-
-
K1
K4
K2
K3
H3
H4
-
2
5
-
-
-
B1
-
4
9
18
19
20
21
-
12
13
14
15
-
E4
F2
G2
F3
G3
-
2
6
-
-
-
4
10
11
12
13
14
15
16
2
7
-
-
-
A2
A3
4
2
8
-
-
B2
4
(1)
(1)
(1)
(1)
(1)
2
9
7
1
B1
C1
D1
4
4
2
10
11
12
13
14
8
9
2
3
-
C2
C1
-
6
8
4
-
-
2
D3
-
4
-
-
-
K5
-
2
-
9
4
-
-
-
2
-
-
-
-
10
12
Notes:
1. JTAG pins
2
11
5
D3
E3
6
www.xilinx.com
DS017 (v1.6) January 8, 2002
1-800-255-7778
Product Specification
R
XCR3064XL 64 Macrocell CPLD
Table 4: XCR3064XL Global, JTAG, Port Enable, Power, and No connect Pins
Pin Type
IN0 / CLK0
IN1 / CLK1
IN2 / CLK2
IN3 / CLK3
TCK
PC44
2
VQ44
40
39
38
37
26
1
CS48
A3
CP56
C5
VQ100
90
1
B4
C6
89
44
43
32
7
A4
C7
88
B5
A6
87
E5
F10
C1
62
TDI
B1
4
TDO
38
13
32
7
B7
C10
G1
73
TMS
D2
15
(1)
(1)
(1)
(1)
(1)
PORT_EN
10
4
C3
E1
11
V
3, 15, 23, 35
9, 17, 29, 41
B3, C7, E2,
G4
A4, D10, H1,
H5
3, 18, 34, 39,
51, 66, 82, 91
CC
GND
22, 30, 42
-
16, 24, 36
-
A5, E3, E6
A7, G10, K6
26, 38, 43, 59,
74, 86, 95
No Connects
-
-
1, 2, 5, 7, 22,
24, 27, 28, 49,
50, 53, 55, 70,
72, 77, 78
Notes:
1. Port Enable is brought High to enable JTAG pins when JTAG pins are used as I/O. See family data sheet
(DS012) for more information.
DS017 (v1.6) January 8, 2002
www.xilinx.com
7
Product Specification
1-800-255-7778
R
XCR3064XL 64 Macrocell CPLD
Ordering Information
Example:
XCR3064XL -7 VQ 44 C
Device Type
Temperature Range
Number of Pins
Package Type
Speed Grade
Device Ordering Options
Speed
Package
Temperature
T = 0°C to + 70°C
-10 10 ns pin-to-pin delay
PC44 44-pin Plastic Leaded Chip Carrier
C = Commercial
I = Industrial
A
V
= 3.0V to 3.6V
CC
-7 7.5 ns pin-to-pin delay
-6 6 ns pin-to-pin delay
VQ44 44-pin Very Thin Quad Flat Pack
CS48 48-ball Chip Scale Package
T = –40°C to + 85°C
A
V
= 2.7V to 3.6V
CC
CP56 56-ball Chip Scale Package
VQ100 100-pin Very Thin Quad Flat Package
Component Availability
Pins
100
56
48
44
44
Type
Code
Plastic VQFP
Plastic BGA
Plastic BGA
Plastic VQFP Plastic PLCC
VQ100
C
CP56
C
CS48
C
VQ44
C
PC44
C
XCR3064XL
-6
-7, -10
C,I
C,I
C,I
C,I
C,I
8
www.xilinx.com
DS017 (v1.6) January 8, 2002
1-800-255-7778
Product Specification
R
XCR3064XL 64 Macrocell CPLD
Revision History
The following table shows the revision history for this document..
Date
Version
1.0
Revision
06/01/00
08/30/00
11/18/00
Initial Xilinx release.
1.1
Added 48-ball CS BGA package.
1.2
Updated to full production data sheet; corrected note in Table 4 to read: "port enable pin is
brought High".
12/08/00
04/11/01
04/19/01
01/08/02
1.3
1.4
1.5
1.6
Added PC44 package.
Added Typical I/V curve, Figure 2; added Table 2: Total User I/O; changed V spec.
OH
Updated Typical I/V curve, Figure 2: added voltage levels.
Moved I vs. Freq Figure 1 and Table 1 to page 1. Added single p-term setup time (T
)
SU1
CC
to AC Table, renamed T to T
for setup time through the OR array. Updated T
and
SU
SU2
SUF
T
spec to match software timing. Added T
spec. Updated T
spec. Updated T
FIN
INIT
CONFIG HI
spec to correct a typo. Updated AC Load Circuit diagram to more closely resemble true test
conditions, added note for T delay measurement. Updated note 5 in AC Characteristics
POD
table lowering typical current draw during configuration.
DS017 (v1.6) January 8, 2002
www.xilinx.com
9
Product Specification
1-800-255-7778
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