XE88LC05RI000_技术文档

XE88LC05

Data Sheet

XE88LC05

16 + 10 bit Data Acquisition

Ultra Low-Power Microcontroller

General Description

Key product Features

The XE88LC05 is an ultra low-power microcontroller unit

(MCU) associated with a versatile analog-to-digital con-

verter (ADC) including a programmable offset and gain

pre-amplifier (PGA) and digital-to-analog converters

(DACs).

•

Low-power, high resolution ZoomingADC

•

0.5 to 1000 gain with offset cancellation

up to 16 bits ADC

up to 13 input multiplexer

•

Buffered signal-DAC (up to 16 bits)

Buffered bias-DAC (up to 10 mA drive)

Low-voltage low-power controller operation

XE88LC05 is available with on chip Multiple-Time-Pro-

grammable (MTP) Flash program memory and ROM.

•

2 MIPS at 2.4 V to 5.5 V supply voltage

•

300 µA at 1 MIPS, 2.4 V to 5.5 V supply

Applications

•

22 kByte (8 kInstruction) MTP, 520 Byte RAM

RC and crystal oscillators

5 reset, 18 interrupt, 8 event sources

•

Internet connected appliances

Portable, battery operated instruments

Piezoresistive bridge sensors

4-20 mA bus sensors

0.5 - 4.5 V sensors

HVAC control

Ordering Information

Reference

XE88LC05MI000 MTP Flash

XE88LC05MI028 MTP Flash

Memory type Temperature

Package

die

-40°C to 85°C

-40°C to 125°C

LQFP64

die

Motor control

XE88LC05RI000

XE88LC05RI028

ROM

LQFP64

cool solutions for short-range wireless connectivity

XEMICS SA, Switzerland. Tel: +41 32 720 5511 Fax: +41 32 720 5770 email: info@xemics.com web: www.xemics.com

Data Acquisition Microcontroller

XE88LC05

1 Detailed Pin Description

63

61

59

57

55

53

51

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

PA(0)

PA(1)

PA(2)

PA(3)

PA(4)

PA(5)

PA(6)

PA(7)

PC(0)

PC(1)

PC(2)

PC(3)

PC(4)

PC(5)

PC(6)

PC(7)

1

2

3

AC_R(0)

AC_R(1)

AC_A(0)

AC_A(1)

AC_A(2)

AC_A(3)

AC_A(4)

AC_A(5)

AC_A(6)

AC_A(7)

AC_R(2)

AC_R(3)

4

5

6

7

packaging date

8

9

10

11

12

13

14

15

16

production

lot identification

device type

TEST

18

20

22

24

26

28

30

Figure 1.1:

Pinout of the XE88LC05 in LQFP64 package

Second

function

name

Description

Function

name

Position

Type

Input of Port A/

1

2

PA(0)

Input

Data input for MTP programming/

Counter A input

Input of Port A/

Data clock for MTP programming/

Counter B input

PA(1)

Input of Port A/

Counter C input/ Counter capture input

3

4

PA(2)

PA(3)

Input

Input of Port A/

Counter D input/ Counter capture input

5

6

PA(4)

PA(5)

PA(6)

PA(7)

PC(0)

PC(1)

PC(2)

PC(3)

PC(4)

PC(5)

PC(6)

PC(7)

Input

Input of Port A

7

Input of Port A

8

Input of Port A

9

Input/Output

Input-Output of Port C

10

11

12

13

14

15

16

Table 1.1:

Pin-out of the XE88LC05 in LQFP64

(see Table “IO pins performances” on page 17 for drive capabilities of the pins)

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Data Acquisition Microcontroller

XE88LC05

Second

function

name

Description

Function

name

Position

17

Type

Input-Output-Analog of Port B/

Data output for MTP programming/

PWM output

PB(0)

Input/Output/Analog

Input-Output-Analog of Port B/

PWM output

18

19

20

PB(1)

PB(2)

PB(3)

Input/Output/Analog

Input-Output-Analog of Port B

Input-Output-Analog of Port B,

Output pin of USRT

SOUT

SCL

SIN

Tx

Input-Output-Analog of Port B/

Clock pin of USRT

21

22

23

24

PB(4)

PB(5)

PB(6)

PB(7)

Input/Output/Analog

Input-Output-Analog of Port B/

Data input or input-output pin of USRT

Input-Output-Analog of Port B/

Emission pin of UART

Input-Output-Analog of Port B/

Reception pin of UART

Rx

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47-50

51

52

53

54

55

56

57

58

59

60

61

DAB_R_p

DAB_R_m

DAB_Out

Analog

Positive reference of bias DAC

Negative reference of bias DAC

Output of bias DAC

Analog

DAB_AO_p

DAB_AO_m

DAB_AI_p

DAB_AI_m

Analog

Highest potential output of bias DAC buffer

Lowest potential output of bias DAC buffer

Positive input of bias DAC buffer

Negative input of bias DAC buffer

Spare pins to be connected to negative power supply

Test mode/High voltage for MTP programming

Spare pins to be connected to negative power supply

Highest potential node for 2nd reference of ADC

Lowest potential node for 2nd reference of ADC

ADC input node

Analog

Not connected

Special

Not connected

Analog

VPP

TEST/Vhigh

AC_R(3)

AC_R(2)

AC_A(7)

AC_A(6)

AC_A(5)

AC_A(4)

AC_A(3)

AC_A(2)

AC_A(1)

AC_A(0)

AC_R(1)

AC_R(0)

Analog

ADC input node

Analog

ADC input node

Analog

ADC input node

Analog

ADC input node

Analog

ADC input node

Analog

ADC input node

Analog

ADC input node

Analog

Highest potential node for 1st reference of ADC

Lowest potential node for 1st reference of ADC

Spare pins to be connected to negative power supply

Output of signal DAC

Analog

Not connected

Analog

DAS_Out

DAS_AI_p

DAS_AI_m

DAS_AO

Vbat

Analog

Positive input of signal DAC buffer

Negative input of signal DAC buffer

Output of signal DAC buffer

Analog

VDD

Power

Positive power supply

Vss

Power

Negative power supply, connected to substrate

Digital negative power supply, must be equal to Vss

Regulated supply

Vss_Reg

Vreg

Power

Analog

Not connected

Analog

Spare pins to be connected to negative power supply

Pad for optional voltage multiplier capacitor

Reset pin (active high)

Vmult

RESET

Input

Connection to Xtal/

Peripheral clock for MTP programming

62

Xout

OscOut/ptck

OscIn/crck

Analog/Input

Connection to Xtal/

CoolRISC clock for MTP programming

63

64

Xin

-

Analog/Input

-

Do not connect, or VSS

Table 1.1:

Pin-out of the XE88LC05 in LQFP64

(see Table “IO pins performances” on page 17 for drive capabilities of the pins)

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Data Acquisition Microcontroller

XE88LC05

2 Absolute maximum ratings

Stresses beyond these listed in this chapter may cause permanent damage to the device. No

functional operation is implied at or beyond these conditions. Exposure to these conditions for

an extended period may affect the device reliability.

Parameter

VBAT with respect to VSS

Value

-0.3V to 6.0V

Remarks

Input voltage on any input pin

Storage temperature

VSS-0.3V to VBAT+0.3V

-55°C to 125°C

-40°C to 85°C

1

Storage temperature for programmed MTP devices

Table 2.1:

Note:

Absolute maximum ratings

1) For unprogrammed MTP devices. Blocking bits and software must be rewritten in MTP de-

vices if storage temperature exceedes storage temperature for programmed devices.

These devices are ESD sensitive. Although these devices feature proprietary ESD protection

structures, permanent damage may occur on devices subjected to high energy electrostatic

discharges. Proper ESD precautions have to be taken to avoid performance degradation or

loss of functionality.

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Data Acquisition Microcontroller

XE88LC05

3 Electrical Characteristics

All specification are -40°C to 85°C unless otherwise noted. ROM operates up to 125°C.

Operation conditions

min

2.4

typ

max

5.5

2

Unit

V

Remarks

ROM version

Power supply

MTP version

2.4 V to 5.5 V

any instruction

2.4

V

Operating speed

Instruction cycle

0.032

MHz

ns

500

7

1

CPU running

at 1 MIPS

310

10

uA

CPU running

at 32 kHz

on Xtal,

uA

1

RC off

CPU halt,

timer on Xtal,

RC off

1

uA

1

Current requirement

CPU halt,

timer on Xtal,

RC ready

1.7

CPU halt,

Xtal off

timer on RC

at 100 kHz

1.4

uA

1

CPU halt,

ADC 16 bits

at 4 kHz

190

460

4,6

CPU halt,

ADC 12 bits

at 4 kHz,

PGA gain 100

CPU at 1 MIPS,

ADC 12 bits and DAC

10 bits

670

790

uA

3,4,6

at 4 kHz

CPU at 1 MIPS,

ADC 12 bits and DAC

10 bits

Current requirement

at 4 kHz,

PGA gain 10

CPU at 1 MIPS,

ADC 12 bits and DAC

10 bits

940

uA

3,4,6

at 4 kHz,

PGA gain 100

CPU at 1 MIPS,

ADC 12 bits and DAC

10 bits

1100

uA

at 4 kHz,

PGA gain 1000

Voltage level

detection

15

Prog. voltage

Erase time

10.3

0.2

10

10.8

1

V

s

8

5

2

MTP Flash

instruction memory

Write/Erase cycles

Data retention

100

10

year

Table 3.1:

Note:

Specifications and current requirement of the XE88LC05

1) Power supply: 2.4 V - 5.5 V, temperature is 27°C.

2) Temperature < 85°C, < 10 erase cycles.

3) Output not loaded.

4) Current requirement can be divided by a factor of 2 or 4 by reducing the speed accordingly.

5) More cycles possible during development, with restraint retention

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Data Acquisition Microcontroller

XE88LC05

6) Power supply: 3.0V, at 27°C; see chapter Power Consumption on page 30 for variation of

current with voltage and clock speed variation

7) With 2 MHz clock, all instructions are using exactly 1 clock cycle

8) Longer erase time may degrade retention

4 CPU

The XE88LC05 CPU is a low power RISC core. It has 16 internal registers for efficient imple-

mentation of the C compiler. Its instruction set is made of 35 generic instructions, all coded on

22 bits, with 8 addressing modes. All instructions are executed in one clock cycle, including

conditional jumps and 8x8 multiplication.

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Data Acquisition Microcontroller

XE88LC05

5 Memory organization

The CPU uses a Harvard architecture, so that memory is organized in two separated fields:

program memory and data memory. As both memories are separated, the central processing

unit can read/write data at the same time it loads an instruction. Peripherals and system control

registers are mapped on data memory space.

Program memory is made in one page. Data is made of several 256 bytes pages.

0h1FFF / 01hBFF

0h027F

0h0080

RAM

512 Bytes

Program

memory

8k instructions MTP

or

CPU

6k instructions ROM

Peripherals

0h0010

0h0000

CPU

registers

Instruction

pipeline

LP RAM

0h0000

22 bits wide

Memory organization

8 bits wide

Figure 5.1:

5.1 Program memory

The program memory is implemented as Multiple Time Programmable (MTP) Flash memory

or ROM. The power consumption of MTP memory is linear with the access frequency (no sig-

nificant static current).

Size of the MTP Flash memory is 8192 x 22 bits (= 22 kBytes)

Size of the ROM memory is 6144 x 22 bits (= 17 kBytes)

block

MTP

size

8192 x 22

6144 x 22

address

H0000 - H1FFF

H0000 - H1BFF

ROM

Table 5.1:

Program addresses for MTP or ROM memory

5.2 Data memory

The data memory is implemented as static Random-Access Memory (RAM). The RAM size is

512 x 8 bits plus 8 low power RAM bytes that require very low current when addressed. Pro-

grams using the low-power RAM instead of RAM will use even less current.

block

LP RAM

RAM

size

8 x 8

address

H0000 - H0007

H0080 - H027F

512 x 8

Table 5.2:

RAM addresses

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Data Acquisition Microcontroller

XE88LC05

6

Registers list

Left column include register name and address.

Right columns include bit name, access (r: read, r0: always 0 when read, w: write, c: cleared

by writing any value, c1: cleared by writing 1), and reset status (0 or 1) and signal. Empty bits

are reserved for future use and should not be written, neither should their read value be used

for any purpose as it may change without notice.

6.1 Peripherals mapping

block

LP RAM

System control

Port A

size

8x8

16x8

8x8

4x8

8x8

12x8

8x8

address

Page

H0000-H0007

H0010-H001F

H0020-H0027

H0028-H002F

H0030-H0033

H0034-H0037

H0038-H003B

H003C-H003F

H0040-H0047

H0048-H004F

H0050-H0057

H0058-H005F

H0060-H0067

H0068-H0073

H0074-H007B

Port B

Port C

Reserved

MTP

Event

Interrupts control

reserved

UART

Page 0

Counters

Zooming ADC

Reserved

DACs

Other

(VLD)

4x8

H007C-H007F

RAM1

RAM2

RAM3

128x8

256x8

128x8

H0080 - H00FF

H0100 - H01FF

H0200 - H027F

Page 1

Page 2

Table 6.1:

Peripherals addresses

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Data Acquisition Microcontroller

XE88LC05

6.2

Resets

The reset source name is simplified in the following registers description. Name mapping is in

the next table.

name in this

reset source

document

resetsystem

global

resetSynch

resetPOR

resetCold

resetPad

cold

resetPconf

resetSleep

pconf

sleep

Table 6.2:

Reset signal name mapping

6.3

Low power RAM

Low power RAM is a small additionnal RAM area with extremely low power requirement.

Name

7

6

5

4

3

2

1

0

Address

h0000

h0001

h0002

h0003

h0004

h0005

h0006

rw

h0007

Table 6.3:

Low power RAM

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Data Acquisition Microcontroller

XE88LC05

6.4

System, oscillators, prescaler and watchdog

Name

Address

RegSysCtrl

7

6

5

4

3

2

1

0

EnRes-

PConf

SleepEn

rw, 0 por

Sleep

EnBus-Error EnResWD

h0010, type 1

RegSysReset

rw, 0 cold

ResWD

ResBus-

Error

ResPor

ResPortA ResPad-Deb ResPad

w, 0 cold

CpuSel

r, 0

rc, 0 cold

EnExtClk

rw, 0 cold

rc, 0 cold

BiasRC

rc, 0 cold

ColdXtal

r, 1 sleep

rc, 0 cold

ColdRC

rc, 0 cold

h0011, type 1

RegSysClock

ExtClk

r, 0 cold

EnableXtal EnableRC

rw, 0 sleep rw, 1 sleep

rw, 0 sleep

rw, 1 cold

r, 1 sleep

h0012, type 1

Output-

CkXtal

Output-

CkCPU

RegSysMisc

RCOnPA0

DebFast

rw, 0 sleep rw, 0 sleep rw, 0 sleep rw, 0 sleep

WatchDog(3) WatchDog(2) WatchDog(1) WatchDog(0)

h0013, type 1

RegSysWD

h0014

special

ResPre

RegSysPre0

ClearLow-

Prescal (*)

h0015

w, 0 cold

RCFreq-

Range

RCFreq-

Coarse(3)

RCFreq-

Coarse(2)

RCFreq-

Coarse(1)

RCFreq-

Coarse(0)

RegSysRCTrim1

h001B

rw, 0 cold

RCFreq-

Fine(5)

RCFreq-

Fine(4)

RCFreq-

Fine(3)

RCFreq-

Fine(2)

RCFreq-

Fine(1)

RCFreq-

Fine(0)

RegSysRCTrim2

h001C

rw, 1 cold

rw, 0 cold

Table 6.4:

System control registers

6.5

PortA

Name

Address

RegPAIn

h0020

RegPADebounce

h0021

RegPAEdge

h0022

RegPAPullup

h0023, type 1

RegPARes0

h0024

7

6

5

4

3

2

1

0

PAIn(7)

r

RegPAIn(6)

r

PAIn(5)

r

PAIn(4)

r

PAIn(3)

r

PAIn(2)

r

PAIn(1)

r

PAIn(0)

r

PADeb(7)

PADeb(6)

PADeb(5)

PADeb(4)

PADeb(3)

PADeb(2)

PADeb(1)

PADeb(0)

rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf

PAEdge(7) PAEdge(6) PAEdge(5) PAEdge(4) PAEdge(3) PAEdge(2) PAEdge(1) PAEdge(0)

rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global

PAPullUp(7) PAPullUp(6) PAPullUp(5) PAPullUp(4) PAPullUp(3) PAPullUp(2) PAPullUp(1) PAPullUp(0)

rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf

PARes0(7) PARes0(6) PARes0(5) PARes0(4) PARes0(3) PARes0(2) PARes0(1) PARes0(0)

rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global

PARes1(7) PARes1(6) PARes1(5) PARes1(4) PARes1(3) PARes1(2) PARes1(1) PARes1(0)

rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global

RegPARes1

h0025

Table 6.5:

Port A registers

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Data Acquisition Microcontroller

XE88LC05

6.6

PortB

Name

Address

RegPBOut

h0028

RegPBIn

h0029

RegPBDir

h002A

RegPBOpen

h002B

RegPBPullup

h002C

RegPBAna

h002D

7

6

5

4

3

2

1

0

PBOut(7)

PBOut(6)

PBOut(5)

PBOut(4)

PBOut(3)

PBOut(2)

PBOut(1)

PBOut(0)

rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf

PBIn(7)

r

PBIn(6)

r

PBIn(5)

r

PBIn(4)

r

PBIn(3)

r

PBIn(2)

r

PBIn(1)

r

PBIn(0)

r

PBDir(7)

PBDir(6)

PBDir(5)

PBDir(4)

PBDir(3)

PBDir(2)

PBDir(1)

PBDir(0)

rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf

PBOpen(7) PBOpen(6) PBOpen(5) PBOpen(4) PBOpen(3) PBOpen(2) PBOpen(1) PBOpen(0)

rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf

PBPullUp(7) PBPullUp(6) PBPullUp(5) PBPullUp(4) PBPullUp(3) PBPullUp(2) PBPullUp(1) PBPullUp(0)

rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf

PBAna(3)

PBAna(2)

PBAna(1)

PBAna(0)

rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf

Table 6.6:

Port B registers

6.7

PortC

Name

Address

RegPCOut

h0030

RegPCIn

h0031

RegPCDir

7

6

5

4

3

2

1

0

PCOut(7)

PCOut(6)

PCOut(5)

PCOut(4)

PCOut(3)

PCOut(2)

PCOut(1)

PCOut(0)

rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf

PCIn(7)

r

PCIn(6)

r

PCIn(5)

r

PCIn(4)

r

PCIn(3)

r

PCIn(2)

r

PCIn(1)

r

PCIn(0)

r

PCDir(7)

PCDir(6)

PCDir)

PCDir(4)

PCDir(3)

PCDir(2)

PCDir(1)

PCDir(0)

rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf

h0032

Table 6.7:

Port C registers

6.8

MTP

Name

Address

RegEEP

h0038

RegEEP1

h0039

RegEEP2

h003A

RegEEP3

7

6

5

4

3

2

1

0

rw

special

h003B

Table 6.8:

MTP control registers

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Data Acquisition Microcontroller

XE88LC05

6.9

Events

Name

Address

RegEvn

h003C

RegEvnEn

h003D

RegEvnPriority

h003E

RegEvnEvn

h003F

7

6

5

4

3

2

1

0

EvnCntA

EvnCntC

EvnPre1

EvnPA(1)

EvnCntB

EvnCntD

EvnPre2

EvnPA(0)

rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global

EvnEnCntA

rw, 0 global

EvnEnCntC

rw, 0 global

EvnEnPre1 EvnEnPA(1) EvnEnCntB EvnEnCntD

rw, 0 global rw, 0 global rw, 0 global rw, 0 global

EvnEnPre2 EvnEnPA(0)

rw, 0 global rw, 0 global

EvnPriority(7) EvnPriority(6) EvnPriority(5) EvnPriority(4) EvnPriority(3) EvnPriority(2) EvnPriority(1) EvnPriority(0)

r,1 global

EvnHigh

r, 0 global

r,1 global

EvnLow

r, 0 global

Table 6.9:

Events control registers

6.10 Interrupts

Name

7

6

5

4

3

2

1

0

Address

RegIrqHig

h0040

RegIrqMid

h0041

RegIrqLow

h0042

RegIrqEnHig

h0043

RegIrqEnMid

h0044

RegIrqEnLow

h0045

RegIrqPriority

h0046

RegIrqIrq

h0047

IrqAc

IrqPre1

IrqCntA

IrqCntC

IrqUartTx

IrqUartRx

rc1, 0 global rc1, 0 global

IrqPA(4) IrqPre2

rc1, 0 global rc1, 0 global

IrqPA(1) IrqPA(0)

IrqPA(5)

IrqVld

rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global

IrqCntB IrqCntD IrqPA(3) IrqPA(2)

rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global

IrqPA(7)

IrqPA(6)

IrqEnAc

IrqEnPre1

IrqEnCntA

rw, 0 global

IrqEnPA(4)

rw, 0 global

IrqEnCntD

rw, 0 global

IrqEnCntC

rw, 0 global

IrqEnPre2

rw, 0 global

IrqEnPA(3)

rw, 0 global

IrqEnUartTx IrqEnUartRx

rw, 0 global

IrqEnPA(1)

rw, 0 global

IrqEnPA(0)

rw, 0 global

IrqEnPA(5)

rw, 0 global

IrqEnCntB

rw, 0 global

IrqEnVld

rw, 0 global

IrqEnPA(2)

rw, 0 global

IrqEnPA(7)

rw, 0 global

IrqEnPA(6)

rw, 0 global

IrqPriority(7) IrqPriority(6) IrqPriority(5) IrqPriority(4) IrqPriority(3) IrqPriority(2) IrqPriority(1) IrqPriority(0)

r, 1 global

IrqHig

r, 1 global

IrqMid

r, 1 global

IrqLow

r, 0 global

Table 6.10:

Interrupts control registers

6.11 USRT

Name

Address

RegUsrtSin

h0048

7

6

5

4

3

2

1

0

UsrtSin

rw, 1 global

UsrtScl

RegUsrtScl

rw, 1 global

h0049

UsrtEnWait-

Cond1

RegUsrtCtrl

UsrtWaitS0

r, 0 global

UsrtEnWaitS0 UsrtEnable

h004A

rw, 0 global

UsrtData

r

RegUsrtData

h004D

RegUsrtEdgeScl

h004E

UsrtEdgeScl

r, 0 global

Table 6.11:

USRT control registers

12

D0109-40

Data Acquisition Microcontroller

XE88LC05

6.12 UART

Name

Address

RegUartCtrl

h0050

7

6

5

4

3

2

1

0

UartEcho

rw, 0 global

SelXtal

UartEnRx

UartEnTx

UartXRx

UartXTx

UartBR(2)

rw, 1 global

UartPM

UartBR(1)

rw, 0 global

UartPE

UartBR(0)

rw, 1 global

UartWL

rw, 0 global

RegUartCmd

UartWakeup UartRCSel(2) UartRCSel(1) UartRCSel(0)

rw, 0 global

UartTx(7)

rw, 0 global

UartTx(6)

rw, 0 global

UartTx(5)

rw, 0 global

UartTx(4)

rw, 0 global

UartTx(3)

rw, 0 global

UartTx(2)

rw, 0 global

UartTx(1)

rw, 0 global

UartTxBusy

r, 0 global

UartRx(1)

r

rw, 1 global

UartTx(0)

rw, 0 global

UartTxFull

r, 0 global

UartRx(0)

r

h0051

RegUartTx

h0052

RegUartTxSta

h0053

RegUartRx

h0054

rw, 0 global

UartRx(7)

r

UartRx(6)

r

UartRx(5)

UartRx(4)

UartRx(3)

UartRx(2)

r

RegUartRxSta

h0055

UartRxSErr

r

UartRxPErr

r

UartRxFErr

r

UartRxOErr UartRxBusy

UartRxFull

r

c

r

Table 6.12:

UART control registers

6.13 Counters

Name

7

6

5

4

3

2

1

0

Address

RegCntA

h0058

RegCntB

h0059

RegCntC

h005A

RegCntD

h005B

RegCntCtrlCk

h005C

RegCntConfig1

h005D

RegCntConfig2

h005E

RegCntOn

h005F

CounterA(7) CounterA(6) CounterA(5) CounterA(4) CounterA(3) CounterA(2) CounterA(1) CounterA(0)

rw rw rw rw rw rw rw rw

CounterB(7) CounterB(6) CounterB(5) CounterB(4) CounterB(3) CounterB(2) CounterB(1) CounterB(0)

rw rw rw rw rw rw rw rw

CounterC(7) CounterC(6) CounterC(5) CounterC(4) CounterC(3) CounterC(2) CounterC(1) CounterC(0)

rw rw rw rw rw rw rw rw

CounterD(7) CounterD(6) CounterD(5) CounterD(4) CounterD(3) CounterD(2) CounterD(1) CounterD(0)

rw

CntDSel(1)

rw

CntDSel(0)

rw

CntCSel(1)

rw

CntCSel(0)

rw

CntBSel(1)

rw

CntBSel(0)

rw

CntASel(1)

rw

CntASel(0)

rw

CntDDownUp CntCDownUp CntBDownUp CntADownUp CascadeCD CascadeAB

CntPWM1

rw, 0 global

CntPWM0

rw, 0 global

rw

CapSel(1)

rw, 0 global

CapSel(0)

rw, 0 global

CapFunc(1) CapFunc(0) PWM1Size(1) PWM1Size(0) PWM0Size(1) PWM0Size(0)

rw, 0 global rw, 0 global rw rw rw rw

CntDEnable CntCEnable CntBEnable CntAEnable

rw, 0 global

Table 6.13:

Counters control registers

13

D0109-40

Data Acquisition Microcontroller

XE88LC05

6.14 Acquisition chain

Name

Address

RegAcOutLsb

h0060

RegAcOutMsb

h0061

RegAcCfg0

h0062

RegAcCfg1

h0063

RegAcCfg2

h0064

RegAcCfg3

h0065

RegAcCfg4

h0066

RegAcCfg5

h0067

7

6

5

4

3

2

1

0

AdcOutL(7)

r

AdcOutL(6)

r

AdcOutL(5)

r

AdcOutL(4)

r

AdcOutL(3)

r

AdcOutL(2)

r

AdcOutL(1)

r

AdcOutL(0)

r

AdcOutM(7) AdcOutM(6) AdcOutM(5) AdcOutM(4) AdcOutM(3) AdcOutM(2) AdcOutM(1) AdcOutM(0)

r

Start

NelConv(1)

NelConv(0)

rw, 1 global

OSR(2)

OSR(1)

OSR(0)

Cont

r0w, 0 global rw, 0 global

rw, 0 global

rw, 1 global

Enable(3)

rw, 0 global

Enable(2)

rw, 0 global

Pga2Off(2)

rw, 0 global

Enable(1)

rw, 0 global

Pga2Off(1)

rw, 0 global

IbAmpADC(1) IbAmpAdc(0) IbAmpPga(1) IbAmpPga(0)

Enable(0)

rw, 1 global

Pga2Off(0)

rw, 0 global

rw, 1 global

Fin(1)

rw, 1 global

Fin(0)

rw, 1 global

Pga2Gain(1) Pga2Gain(0) Pga2Off(3)

rw, 0 global rw, 0 global rw, 0 global

rw, 0 global

Pga1Gain

rw, 0 global

Pga3Gain(6) Pga3Gain(5) Pga3Gain(4) Pga3Gain(3) Pga3Gain(2) Pga3Gain(1) Pga3Gain(0)

rw, 0 global

Pga3Off(6)

rw, 0 global

Def

rw, 0 global

Pga3Off(5)

rw, 0 global

AMux(4)

rw, 0 global

Pga3Off(4)

rw, 0 global

AMux(3)

rw, 1 global

Pga3Off(3)

rw, 0 global

AMux(2)

rw, 1 global

Pga3Off(2)

rw, 0 global

AMux(1)

rw, 0 global

Pga3Off(1)

rw, 0 global

AMux(0)

rw, 0 global

Pga3Off(0)

rw, 0 global

VMux

Busy

r, 0 global

wr0

rw, 0 global

Table 6.14:

Acquisition chain control registers

6.15 DACs

Name

Address

7

6

5

4

3

2

1

0

RegDasInLsb

DasInLSB(7) DasInLSB(6) DasInLSB(5) DasInLSB(4) DasInLSB(3) DasInLSB(2) DasInLSB(1) DasInLSB(0)

h0074

w

RegDasInMsb

h0075

RegDasCfg0

h0076

RegDasCfg1

h0077

RegDab1In

h0078

DasInMSB(7) DasInMSB(6) DasInMSB(5) DasInMSB(4) DasInMSB(3) DasInMSB(2) DasInMSB(1) DasInMSB(0)

w

Fin

NSOrder(1)

rw, 0 global

NSOrder(0) CodeIMax(2) CodeIMax(1) CodeIMax(0) DasEnable(1) DasEnable(0)

rw, 0 global

BW

rw, 0 global

Inv

rw, 0 global

DabIn(1)

w

rw, 0 global

DabIn(0)

w

DabIn(7)

w

DabIn(6)

w

DabIn(5)

w

DabIn(4)

w

DabIn(3)

w

DabIn(2)

w

Dab1-

Enable(1)

Dab1-

Enable(0)

RegDab1Cfg

h0079

rw, 0 global

Table 6.15:

DACs control registers

6.16 Vmult and Vld registers

Name

Address

RegVmultCfg0

h007C

RegVldCtrl

h007E

RegVldStat

h007F

7

6

5

4

3

2

1

0

Enable

rw, 0 global

VldTune(2)

rw, 0 cold

VldIrq

Fin(1)

Fin(0)

rw, 0 global

VldTune(1)

rw, 0 cold

VldValid

rw, 0 global

VldTune(0)

rw, 0 cold

VldEn

VldMult

rw, 0 cold

r, 0 global

rw, 0 global

Table 6.16:

Vmult and Vld control registers

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Data Acquisition Microcontroller

XE88LC05

7 Peripherals

The XE88LC05 includes usual microcontroller peripherals and some other blocks more spe-

cific to low-voltage or mixed-signal operation. There are 3 parallel ports, one input port (A), one

IO and analog port (B) with analog switching capabilities and one general purpose IO port (C).

A watchdog is available, connected to a prescaler. Four 8-bit counters, with capture, PWM and

chaining capabilities are available. The UART can handle transmission speeds as high as

115kbaud.

Low-power low-voltage blocks include a voltage level detector, two oscillators (one internal

0.1-2 MHz RC oscillator and a 32 kHz crystal oscillator) and a specific regulation scheme that

largely uncouples current requirement from external power supply (usual CMOS ASICs re-

quire much more current at 5.5 V than they need at 2.4 V. This is not the case for the

XE88LC05).

Analog blocks (ZoomingADC (acquisition path), bias DAC and signal DAC) are defined below.

All these blocks operate on 2.4 - 5.5 V power supply range.

7.1 Counters

7.2 Prescaler

•

4 8-bit counters

Daisy chain on 16 bits

PWM on 8-16 bits

Capture - compare on 16 bits

Events and interrupts generation

•

Interrupt generated with 8 millisecond or 1 second period for ultra low power hiberna-

tion mode

7.3 Watchdog

7.4 UART

2 seconds watchdog

•

full duplex operation with buffered receiver and transmitter.

internal baud rate generator with programmable baud rate (300 - 115000 bauds).

7 or 8 bits word length.

even, odd, or no-parity bit generation and detection

1 stop bit

error receive detection: Start, Parity, Frame and Overrun

receiver echo mode

2 interrupts (receive full and transmit empty)

enable receive and/or transmit

invert pad Rx and/or Tx

7.5 Xtal clock

The Xtal Oscillator operates with an external crystal of 32’768 Hz.

15

D0109-40

Data Acquisition Microcontroller

XE88LC05

symbol

f_clk32k

st_x32k

description

nominal frequency

oscillator start-up time

min

typ

32768

1

max

unit

Hz

s

comments

2

for full precision

duty_clk32k duty cycle on the digital output

30

50

70

%

relative frequency deviation from

not included:

crystal frequency tolerance and aging

crystal frequency - temperature dependence

nominal, for a crystal with

fstab_1

-100

+300

ppm

CL=8.2 pF and temperature

between -40° and +85°C

Table 7.1:

Note:

Xtal oscillator specifications.

Board layout recommendations for safer crystal oscillation and lower current consumption:

Keep lines xtal_in and xtal_out short and insert a VSS line between them.

Connect package of the crystal to VSS.

No noisy or digital lines near xtal_in and xtal_out.

Insert guards at VSS where needed.

7.6 RC oscillator

The RC Oscillator is always turned on at power-on reset and can be turned off after the option-

al Xtal oscillator has been started. The RC oscillator has two frequency ranges: sub-MHz

(100KHz to 1MHz) and above-MHz (1MHz to max MCU frequency). Inside a range, the fre-

quency can be tuned by software for coarse and fine adjustment.

Note:

No external component is required for the RC oscillator.

The RC oscillator can be in 3 modes. In mode 1(RC on), the RC oscillator and its bias are on.

In mode 2 (RC ready), the RC oscillator is off and the bias is on. In mode 3 (RC off), the RC

oscillator and the bias are off. RC ready mode is a compromise between power consumption

and start-up time.

Figure 7.1:

RC frequencies programming example for low range (typical values)

symbol

F_st

description

frequency at start-up

range selection

min

50

1

typ

80

max

110

10

unit

kHz

comments

at 27°C

multiplies F_st

range

Table 7.2:

RC specifications

16

D0109-40

Data Acquisition Microcontroller

XE88LC05

symbol

mult[3:0]

description

coarse tuning range

fine tuning range

fine tuning step

min

1

typ

max

16

1.5

2

unit

comments

4 bits, multiplies F_st* range

6 bits, multiplies F_st* range * mult

0.65

tune[5:0]

1.4

30

%

ms

%

T_st

O_st

start-up time

50

5

bias current is off (RC off)

bias current is on (RC ready)

overshoot at start-up

wakeup time

T_wu

O_wu

3

ms

overshoot at wakeup

50

%

o

jit

jitter rms

2

/

oo

Tdf

temperature drift

0.1

%/°C

Table 7.2:

RC specifications

7.7 Parallel IO ports

•

8 bit input port A with interrupt, reset and event generation.

8 bit input-output-analog port B with analog switching capabilities.

8 bit input-output port C.

sym

description

Port A: low threshold limit

condition

min

typ

1

max

unit

V

Comments

Port A: high threshold limit

1.5

V

output drop when sinking 1 mA

output drop when sinking 8 mA

output drop when sourcing 1 mA

output drop when sourcing 8 mA

Port A: low threshold limit

V

Vbat =

2.4 V

0.4

V

2

3

V

Port A: high threshold limit

V

output drop when sinking 1 mA

output drop when sinking 8 mA

output drop when sourcing 1 mA

output drop when sourcing 8 mA

pull-up, pull-down resistor

V

Vbat =

5.0 V

0.4

V

0.4

V

50

150

kohm

Table 7.3:

IO pins performances

7.8 Voltage level detector

•

Can be switched off, on or simultaneously with CPU activities

•

Generates an interrupt if power supply is below a pre-determined level

17

D0109-40

Data Acquisition Microcontroller

XE88LC05

The Voltage Level Detector monitors the state of the system battery. It returns a logical high

value (an interrupt) in the status register if the supplied voltage drops below the user defined

level.

symbol

description

min

typ

max

unit

comments

trimming values:

Note 1

VldRange

VldTune

000

001

010

011

100

101

110

111

000

001

010

011

100

101

110

111

1.53

1.44

1.36

1.29

1.22

1.16

1.11

1.06

3.06

2.88

2.72

2.57

2.44

2.33

2.22

2.13

2.0

0

1

Vth

Threshold voltage

V

T_EOM

T_PW

duration of measurement

2.5

ms

us

Note 2

Minimum pulse width detected

875

1350

Table 7.4:

Voltage level detector operation

1) Absolute precision of the threshold voltage is ±10%.

Note:

2) This timing is respected in case the internal RC or crystal oscillators are selected. Refer to

the clock block documentation in case the external clock is used.

18

D0109-40

Data Acquisition Microcontroller

XE88LC05

8 ZoomingADC

The fully differential acquisition chain is formed of a programmable gain (0.5 - 1000) and offset

amplifier and a programmable speed and resolution ADC (example: 12 bits at 4 kHz, 16 bits

at 1 kHz). It can handle inputs with very low full scale signal and large offsets.

reference selection

AC_R(0)

AC_R(1)

AC_R(2)

AC_R(3)

AC_A(0)

AC_A(1)

AC_A(2)

AC_A(3)

ADC

AC_A(4)

AC_A(5)

AC_A(6)

gain1

mode output

code

gain2

gain3

AC_A(7)

offset2

offset3

input selection

Figure 8.1:

Acquisition channel block diagram

Input selection is made from 1 of 4 differential pair or 1 of seven single signal versus AC_A(0).

Reference is chosen from the 2 differential references.

The gain of each amplifier is programmed individually. Each amplifier is powered on and off on

command to minimize the total current requirement. All blocks can be set to low frequency op-

eration and lower their current requirement by a factor 2 or 4.

The ADC can run continuously (end of conversion signalled by an interrupt, event or by pooling

the ready bit), or it can be started on request.

8.1 PGA 1

symbol

GD1

description

PGA1 Signal Gain

min

1

typ

max

10

unit

-

Comments

GD1 = 1 or 10

GD_preci

GD_TC

fs

Precision on gain settings

Temperature dependency of gain settings

input sampling frequency

Input impedance

-5

+5

%

-5

+5

ppm/°C

kHz

kΩ

512

Zin1

150

1

Zin1p

Input impedance for gain 1

1500

kΩ

nV/

sqrt(Hz)

VN1

Input referred noise

28.6

2

Table 8.1:

Note:

PGA1 Performances

1) Measured with block connected to inputs through AMUX block. Normalized input sampling

frequency for input impedance is 512 kHz. This figure has to be multiplied by 2 for fs = 256 kHz

and 4 for fs = 128 kHz.

2) Input referred rms noise is 205 uV per input sample with gain = 1, 20.5 uV with gain = 10.

This corresponds to 28.6 nV/sqrt(Hz) for fs = 512 kHz and gain = 10.

19

D0109-40

Data Acquisition Microcontroller

XE88LC05

8.2 PGA2

sym

GD2

description

PGA2 Signal Gain

min

1

typ

0.2

max

10

unit

-

FS

Comments

GD2 = 1, 2, 5 or 10

GDoff2

GDoff2_step

GD_preci

GD_TC

fs

PGA2 Offset Gain

-1

1

GDoff2(code+1) – GDoff2(code)

Precision on gain settings

Temperature dependency of gain settings

Input sampling frequency

Input impedance

0.18

-5

0.22

+5

-

%

valid for GD2 and GDoff2

-5

+5

ppm/°C

kHz

kΩ

nV/

sqrt(Hz)

512

Zin2

150

1

2

VN2

Input referred noise

47.5

Table 8.2:

PGA2 Performances

Note:

1) Measured with block connected to inputs through AMUX block. Normalized input sampling

frequency for input impedance is 512 kHz. This figure has to be multiplied by 2 for fs = 256 kHz

and 4 for fs = 128 kHz.

2) Input referred rms noise is 340 uV per input sample with gain = 1, 34 uV with gain = 10.This

corresponds to 47.5 nV/sqrt(Hz) for fs = 512 kHz and gain = 10.

8.3 PGA3

sym

GD3

description

PGA3 Signal Gain

min

0

typ

max

10

unit

-

Comments

GDoff3

GD3_step

GDoff3_step

GD_preci

GD_TC

fs

PGA3 Offset Gain

-5

5

FS

GD3(code+1) - GD3(code)

GDoff2(code+1) – GDoff2(code)

Precision on gain settings

Temperature dependency of gain settings

Input sampling frequency

0.075

-5

0.08

0.085

+5

-

%

valid for GD3 and GDoff3

-5

+5

ppm/°C

kHz

512

Zin3

VN3

Input impedance

150

kΩ

1

2

nV/

sqrt(Hz)

Input referred noise

51.0

Table 8.3:

Note:

PGA3 Performances

1) Measured with block connected to inputs through AMUX block. Normalized input sampling

frequency for input impedance is 512 kHz. This figure has to be multiplied by 2 for fs = 256 kHz

and 4 for fs = 128 kHz.

2) Input referred rms noise is 365 uV per imput sample with gain = 1, 36.5 uV with gain = 10.

This corresponds to 51.0 nV/sqrt(Hz) for fs = 512 kHz.

20

D0109-40

Data Acquisition Microcontroller

XE88LC05

8.4 Analog to digital converter (ADC)

The whole analog to digital conversion sequence is basically made of an initialisation, a set of

Nelconv elementary incremental conversions and finally a termination phase(N is set

umCONV

by 2 bits on RegACCfg0). The result is a mean of the results of the elementary conversions.

input

1 2

smax 1 2

smax

1 2

smax

sample

1st elementary

conversion

2nd elementary

conversion

elementary

conversion

elementary

conversion

END

START

conversion

1

2

N

_umConv-1

N_umConv

index

Figure 8.2:

Conversion sequence. smax is the oversampling rate.

Note: N_umCONVelementary conversions are performed, each elementary conversion being made of

smax input samples.

N

_umCONV= 2^NELCONV

smax = 8*2^OSR

During the elementary conversions, the operation of the converter is the same as in a sigma

delta modulator. During one conversion sequence, the elementary conversions are alterna-

tively performed with direct and crossed PGA-ADC differential inputs, so that when two ele-

mentary conversions or more are performed, the offset of the converter is cancelled.

Some additional clock cycles (N

conversion properly.

+N

) clock cycles are used to initiate and terminate the

INIT

END

8.5 ADC performances

sym

VINR

Resol

NResol

DNL

description

Input range

min

-0.5

6

typ

max

0.5

16

unit

Vref

bits

LSB

kHz

-

Comments

Resolution

Numerical resolution

Differential non-linearity

Integral non-linearity

sampling frequency

Oversampling Ratio

16

3

-0.1

-3

0.1

2

LSB at 16 bits

2, LSB at 16 bits

INL

fs

10

8

512

1024

smax

1

Number of elementary conversions in

incremental mode

N_UMCONV

Ninit

1

8

5

-

Number of periods for incremental

conversion initialization

Number of periods for incremental

conversion termination

Nend

Table 8.4:

ADC Performances

1) Only powers of 2

Note:

2) INL is defined as the deviation of the DC transfer curve from the best fit straight line. This

21

D0109-40

Data Acquisition Microcontroller

XE88LC05

specification holds over 100% of the full scale.

3) NResol is the maximal readable resolution of the digital filter.

8.6

resolution

6

conditions

oversampling per conversion = 8

1 conversion (no offset rejection)

input frequency conversion time output frequency

512 kHz

40 us

50 us

25 kHz

20 kHz

6.7 kHz

3.6 kHz

2 kHz

oversampling per conversion = 16

1 conversion (no offset rejection)

8

oversampling per conversion = 64

1 conversion (no offset rejection)

12

13

16

150 us

275 us

500 us

1 ms

oversampling per conversion = 64

2 conversions (offset rejection)

oversampling per conversion = 256

1 conversion (no offset rejection)

oversampling per conversion = 256

2 conversions (offset rejection)

1 kHz

oversampling per conversion = 1024

8 conversion s(offset rejection)

16.5 ms

60 Hz

Table 8.5:

ADC performances examples

8.7 Linearity

To quantify linearity errors, Integral Non-Linearity (INL) and Differential Non-Linearity (DNL)

were measured for the ADC alone and for gains of 1, 5, 10, 20, 100, 1000, and a resolution of

12 bits and 16 bits.

INL is defined as the deviation (in LSB) of the DC transfer curve of each individual code from

the best-fit straight line. This specification holds over the full scale.

DNL is defined as the difference (in LSB) between the ideal (1 LSB) and measured code tran-

sitions for successive codes. INL and DNL are specified after gain and offset errors have been

removed.

8.8 Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) for 12-bit

resolution

12 bits - ADC converter (No PGA; ADC only) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV =

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

4

f

0.50

0.40

0.30

0.20

0.10

0.00

-0.10

-0.20

-0.30

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

0

500

1000

1500

2000

2500

0

500

1000

1500

2000

2500

V_IN[mV]

Figure 8.3:

NO GAIN (ONLY ADC), 12 bit ADC setting

22

D0109-40

Data Acquisition Microcontroller

XE88LC05

12 bits - ADC converter (GDtot = 1) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV =

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

4

f

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

2.0

1.5

0.50

0.40

0.30

0.20

0.10

0.00

-0.10

-0.20

-0.30

1.0

0.5

INL

0.0

-0.5

-1.0

-1.5

-2.0

0

500

1000

1500

2000

2500

0

500

1000

1500

2000

2500

V_IN[mV]

Figure 8.4:

GAIN=1, 12 bit ADC setting

12 bits - ADC converter (GDtot = 5) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

sweep = 1201; average on 4 samples

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4

^RC= 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

f

N

f

0.50

0.40

0.30

0.20

0.10

0.00

-0.10

-0.20

-0.30

1.0

0.5

0.0

-0.5

-1.0

-1.5

0

100

200

V_IN[mV]

300

400

500

0

100

200

300

400

500

V_IN[mV]

Figure 8.5:

GAIN=5, 12 bit ADC setting

12 bits - ADC converter (GDtot = 10) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4

^RC= 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

f

0.50

2.0

1.5

0.40

0.30

1.0

0.20

0.5

0.10

0.00

0.0

-0.10

-0.20

-0.30

-0.40

-0.50

-0.5

-1.0

-1.5

-2.0

0

50

100

150

200

250

0

50

100

150

200

250

V_IN[mV]

Figure 8.6:

GAIN=10, 12 bit ADC setting

23

D0109-40

Data Acquisition Microcontroller

XE88LC05

12 bits - ADC converter (GDtot = 20) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

f

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

0.60

0.40

0.8

0.6

0.4

0.20

0.2

0.00

0.0

-0.20

-0.40

-0.60

-0.80

-0.2

-0.4

-0.6

-0.8

0

20

40

60

V_IN[mV]

80

100

120

0

20

40

60

80

100

120

V_IN[mV]

Figure 8.7:

GAIN=20, 12 bit ADC setting

12 bits - ADC converter (GDtot = 100) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

Vbat

=

Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

f

1.00

0.50

4.0

3.0

2.0

1.0

0.00

0.0

-0.50

-1.00

-1.50

-1.0

-2.0

-3.0

-4.0

0

5

10

15

20

25

0

5

10

15

20

25

V_IN[mV]

Figure 8.8:

GAIN=100, 12 bit ADC setting

12 bits - ADC converter (GDtot = 1000) (version v5a)

Vbat

=

Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4

^RC= 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

f

6.0

4.0

2.0

1.5

1.0

2.0

0.5

0.0

-0.5

-1.0

-1.5

-2.0

-4.0

-6.0

0

5

10

15

20

25

0

5

10 15

10*V_IN[mV]

20

25

10*V_IN[mV]

Figure 8.9:

GAIN=1000, 12 bit ADC setting

24

D0109-40

Data Acquisition Microcontroller

XE88LC05

8.9 Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) for 16-bit

resolution

16 bits - ADC converter (No PGA; ADC only) (version v5a)

16 bits- ADC converter (No PGA; ADC only) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2

RC 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

sweep = 1201; average on 4 samples

f

=

f

N

3

2

0.10

0.05

1

0.00

0

-0.05

-0.10

-0.15

-1

-2

-3

0

500

1000

1500

2000

2500

0

500

1000

1500

2000

2500

V_IN[mV]

Figure 8.10:

NO GAIN (ONLY ADC), 16 bit ADC setting

16 bits - ADC converter (GDtot = 1) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV =

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

2

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

f

25.0

20.0

15.0

10.0

5.0

0.10

0.08

0.06

0.04

0.02

0.00

-0.02

-0.04

-0.06

-0.08

-0.10

0.0

-5.0

-10.0

-15.0

-20.0

-25.0

0

500

1000

1500

2000

2500

0

500

1000

1500

2000

2500

V_IN[mV]

Figure 8.11:

GAIN=1, 16 bit ADC setting

16 bits - ADC converter (GDtot = 5) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2

16 bits - ADC converter (GDtot = 5) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

f

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

f

N sweep = 1201; average on 4 samples

10.0

5.0

0.15

0.10

0.05

0.00

-0.05

-0.10

-0.15

0.0

-5.0

-10.0

-15.0

-20.0

0

100

200

300

400

500

0

100

200

300

400

500

V_IN[mV]

Figure 8.12:

GAIN=5, 16 bit ADC setting

25

D0109-40

Data Acquisition Microcontroller

XE88LC05

16 bits - ADC converter (GDtot = 10) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2

16 bits - ADC converter (GDtot = 10) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

f

^RC= 2MHz; IB_AMP(1:0) = 11; Vinn=0V

f

N sweep = 1201; average on 4 samples

30

20

10

0

0.25

0.20

0.15

0.10

0.05

0.00

-0.05

-0.10

-0.15

-0.20

-0.25

-10

-20

-30

0

50

100

150

200

250

0

50

100

V_IN[mV]

150

200

250

V_IN[mV]

Figure 8.13:

GAIN=10, 16 bit ADC setting

16 bits - ADC converter (GDtot = 20) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2

^RC= 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

f

0.6

0.4

10

8

6

4

0.2

2

0.0

0

-2

-4

-6

-8

-10

-0.2

-0.4

-0.6

0

20

40

60

V_IN[mV]

80

100

120

0

20

40

60

80

100

120

V_IN[mV]

Figure 8.14:

GAIN=20, 16 bit ADC setting

16 bits - ADC converter (GDtot = 100) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV =

RC 2MHz; IB_AMP(1:0) = 11; Vinn=0V

sweep = 1201; average on 4 samples

2

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2

RC

2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

f

=

f

=

N

40

30

0.8

0.6

0.4

20

0.2

10

0.0

0

-0.2

-0.4

-0.6

-0.8

-1.0

-10

-20

-30

-40

0

5

10

15

20

25

0

5

10

15

20

25

V_IN[mV]

Figure 8.15:

GAIN=100, 16 bit ADC setting

26

D0109-40

Data Acquisition Microcontroller

XE88LC05

16 bits - ADC converter (GDtot = 1000) (version v5a)

2

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV =

f

fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N

sweep = 1201; average on 4 samples

80

60

2.0

1.5

40

1.0

20

0.5

0

0.0

-20

-40

-60

-80

-0.5

-1.0

-1.5

-2.0

0

5

10

15

20

25

0

5

10 15

10*V_IN[mV]

20

25

10*V_IN[mV]

Figure 8.16:

GAIN=1000, 16 bit ADC setting

The gain settings of each PGA stage for the plots of above figure are those of the table below.

PGA Gain

PGA1 Gain

GD1

PGA2 Gain

GD2

PGA3 Gain

GD3

GD

TOT

(V/V)

1

bypassed

10

5

1

5

10

bypassed

20

2

100

1000

10

Table 8.6:

Table 8.7:

Individual PGA gains for INL & DNL measurements

8.10 Noise

Ideally, a constant input voltage V should result in a constant output code. However, because

IN

of circuit noise, the output code may vary for a fixed input voltage. The figure shows the distri-

bution for the ADC alone (PGA1, 2, and 3 bypassed) and of several configurations of the

PGAs. Quantization noise is dominant in this case of ADC only, and, thus, the ADC thermal

noise is negligible.

One has to considere two points when computing final noise of the acquisition chain:

•

this is a type of amplifier (switched-cap with constant capacitive load) that maintains its

output noise when changing the gain. Therefore input refered noise is lowered when

the gain of an amplifier is increased.

•

the ADC is oversampled, and the number of samples taken lowers the thermal noise

Total input refered noise can be computed using the following equation:

2

²



²



V_{n, out1}

gain1

V_{n, out2}

gain1 ⋅ gain2

V_{n, out3}

gain1 ⋅ gain2 ⋅ gain3









----------------- + ---------------------------------- + -----------------------------------------------------









V²_{n, in}= -----------------------------------------------------------------------------------------------------------------------------------------------

numconv ⋅ smax

27

D0109-40

Data Acquisition Microcontroller

XE88LC05

Where V

is the rms output noise of amplifier x.

n,outx

Typical output noise

Symbol

Amplifier

Unit

per over-sample

V_n,out1

V_n,out2

V_n,out3

PGA1

PGA2

PGA3

205

340

365

uVrms

Typical output noise of ZoomingADC preamplifiers

ADC only

PGA1: 1

PGA2: 10

PGA3: off

PGA1: off

PGA2: 1

PGA3: 10

PGA1: 1

PGA2: 10

PGA3: 10

PGA1: 10

PGA2: 10

PGA3: off

Figure 8.17:

Noise measured at the output of the ZoomingADC

As one can see on the figures above, increase the gain of the first amplifier lowers the output

noise for constant global gain. It also lowers sensitivity to temperature drift as offset is better

compensated on first amplifier.

8.11 Gain Error and Offset Error

Gain error is defined as the amount of deviation between the ideal transfer function and the

measured transfer function (with the offset error removed). The left figure shows gain error vs.

temperature for different PGA gains. The curves are expressed in% of Full-Scale Range (FSR)

normalized to 25°C.

Offset error is defined as the output code error for a zero volt input (ideally, output code = 0).

The measured offset errors vs. temperature curves for different PGA gains are depicted in the

right figure below. The output offset error, expressed in (LSB), is normalized to 25°C.

28

D0109-40

Data Acquisition Microcontroller

XE88LC05

0.2

0.1

100

1

5

20

100

80

60

40

20

0

0.0

-0.1

-0.2

-0.3

-0.4

1

5

20

100

-20

-40

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Temperature [°C]

Figure 8.18:

Gain and offset error vs temperature for several gains, normalized to 25°C, offset

cancellation disabled. When the offset cancellation is enabled, the offset of PGA1 and ADC

29

D0109-40

Data Acquisition Microcontroller

XE88LC05

8.12 Power Consumption

Left figure below plots the variation of quiescent current consumption with supply voltage V

,

DD

as well as the distribution between the 3 PGA stages and the ADC. As shown in the right figure,

quiescent current consumption is not greatly affected by sampling frequency. It can be seen

that the quiescent current varies by about 20% between 100kHz and 2MHz. Quiescent current

consumption vs. temperature is shown in the second set of figures, showing a relative increase

of nearly 40% between -45 and +85°C.

800

700

600

500

400

300

200

100

750

PGA1, 2 & 3

500kHz

250kHz

62.5kHz

Sampling Frequency f_S

:

700

650

600

550

500

PGA1 & 2 only

PGA1 only

No PGAs, ADC only

2.5

3.0

3.5

4.0

4.5

5.0

5.5

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Supply Voltage - V_DDA[V]

Figure 8.19:

Quiescent current versus supply voltage for different gains and clock speed (not using the

PGA and ADC low power modes)

20

15

10

5

900

850

800

750

700

650

600

550

0

-5

-10

-15

-20

-25

500

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature [°C]

Figure 8.20:

Table 8.8:

Absolute and (b) relative change in quiescent current consumption vs. temperature

Supply

V_DD= 5V

V_DD= 3V

ADC

250

PGA1

165

PGA2

130

PGA3

175

TOTAL

720

Unit

µA

190

150

120

160

620

µA

Typical quiescent current distributions in acquisition chain (n = 16 bits, f = 500kHz)

S

30

D0109-40

Data Acquisition Microcontroller

XE88LC05

15

10

5

850

800

750

700

650

600

550

500

0

-5

-10

-15

-20

0

500

1000

1500

2000

2500

3000

3500

0

500

1000

1500

2000

2500

3000

3500

Frequency - f_RC[kHz]

Figure 8.21:

Absolute and (b) relative change in quiescent current consumption vs. clock speed

8.13 Power Supply Rejection Ratio

Figure below shows power supply rejection ratio (PSRR) at 3V and 5V supply voltage, and for

various PGA gains. PSRR is defined as the ratio (in dB) of voltage supply change (in V) to the

change in the converter output (in V). PSRR depends on both PGA gain and supply voltage

V

.

DD

105

100

95

VDD=3V

VDD=5V

90

85

80

75

70

65

60

1

5

10

20

100

PGA Gain [V/V]

Figure 8.22:

Power supply rejection ratio (PSRR)

Supply

GAIN = 1

GAIN =5

78

GAIN = 10

100

GAIN = 20

GAIN =100

Unit

dB

V

_DD= 5V

79

72

99

90

97

86

V_DD= 3V

79

90

dB

Table 8.9:

PSRR (n = 16 bits, V = V

= 2.5V, f = 500kHz)

IN

REF S

8.14 Frequency Response

The incremental ADC of the XE88LC05 is an over-sampled converter with two main blocks:

an analog modulator and a low-pass digital filter. The main function of the digital filter is to re-

move the quantization noise introduced by the modulator. As shown below, this filter deter-

mines the frequency response of the transfer function between the output of the ADC and the

analog input V . Notice that the frequency axes are normalized to one elementary conversion

IN

31

D0109-40

Data Acquisition Microcontroller

XE88LC05

period OSR/f . The plots below also show that the frequency response changes with the

S

number of elementary conversions N

performed. In particular, notches appear for N

ELCONV

EL-

Š 2. These notches occur at:

CONV

i ⋅ f_S

OSR ⋅ N_ELCONV

f_NOTCH(i) =

i = 1,2,...,(N_ELCONV−1)

(Hz)for

and are repeated every f /OSR.

S

Information on the location of these notches is particularly useful when specific frequencies

must be filtered out by the acquisition system. For example, consider a 5Hz-bandwidth, 16-bit

sensing system where 50Hz line rejection is needed. Using the above equation and the plots

below, we set the 4th notch for N

= 4 to 50Hz, i.e. 1.25Þf /OSR = 50Hz. The sampling

ELCONV

S

frequency is then calculated as f = 20.48kHz for OSR = 512. Notice that this choice yields

S

also good attenuation of 50Hz harmonics.

1.2

1

1.2

1

N_ELCONV= 2

N_ELCONV= 1

0.8

0.6

0.4

0.2

0

0.8

0.6

0.4

0.2

0

1

2

3

4

0

1

2

3

4

Normalized Frequency - f *(OSR/f_S) [-]

1.2

1

1.2

1

N_{EL CONV}= 8

N_ELCONV= 4

0.8

0.6

0.4

0.2

0

0.8

0.6

0.4

0.2

0

1

2

3

4

0

1

2

3

4

Normalized Frequency - f *(OSR/f_S) [-]

Figure 8.23:

Frequency response: normalized magnitude vs. frequency for different N

ELCONV

32

D0109-40

Data Acquisition Microcontroller

XE88LC05

9 Digital to analog converters (DACs)

The XE88LC05 includes 2 DACs: a signal DAC and a bias DAC.

9.1 Bias DAC

The bias DAC is a low resolution (8 bits) DAC with a buffer perfectly adapted to sensor bridge

bias. It can be used to bias a bridge in current (figure) or in voltage by choosing the pins con-

nection.

Figure 9.1:

General block diagram of the bias DAC

The bias DAC itself is built of a series of resistors which two extremes are available outside

the chip, so that one can connect it to an external source when the output of the DAC should

not be ratiometric to the power supply.

9.2 The DAC of bias DAC

The DAC convertor is a resistive divider connected between pads DAB_R_m and DAB_R_p.

sym

wda

description

number of input bits

step response

min

typ

8

max

unit

bits

ms

Comments

tstep

range

INL

100

1

2

3

DAC output range

integral non-linearity

differential non-linearity

DAB_R_m

DAB_R_p

1

LSB

DNL

Table 9.1:

Note:

DAC performances

1) Time to reach the final value within 5%. Node not charged.

2) In most cases DAB_R_m will be connected to VSS and DAB_R_p to VDD.

3) For DAB_R_m connected to VSS and DAB_R_p to VDD, VDD > 2.4 V.

9.3 The amplifier of bias DAC

The amplifier can be used in several configurations as for biasing a bridge in voltage or current.

Application examples are given in application note AN8000.03.

sym

gain

description

gain at DC

min

60

typ

max

unit

dB

Comments

1

GBW

gain bandwidth product

100

Hz

Table 9.2:

Amplifier performances

33

D0109-40

Data Acquisition Microcontroller

XE88LC05

sym

fm

description

phase margin

min

60

typ

max

unit

°

Comments

1

rl

resistive load

300

100000

1

ohm

nF

4,5

cl

capacitive load

CMR

OR

common mode input range

output range

vss

vdd

V

vss+0.2

vss+2.3

vdd-0.2

vdd

V

3

outp vr

voff

outp pin voltage range

offset

V

±10

mV

uVrms

mA

dB

uA

noise

isourc

PSRR

ibias

ioff

integrated input noise

max source current

power supply rejection ratio

quiescent bias current

off current

100

10

4

2

5

40

2

5

1

Table 9.2:

Note:

Amplifier performances

1) For all possible combinations of resistive load and capacitive load.

2) At DC.

3) For voltage controlled bias control. For current controlled operation the voltage drop on the

pMOS output transistor has to be less than 200mV at maximum current.

4) Short circuit protection at ~80mA.

5) This amplifier must be loaded for correct operation. Ibias is without load current.

9.4 Signal DAC

The signal DAC is build around a programmable DAC and a buffer. It can generate fast (up to

64 kHz) or high resolution (resolution up to 16 bits) output. The output can be controlled in cur-

rent or voltage.

Figure 9.2:

General block diagram of the signal DAC

9.5 The amplifier of signal DAC

The amplifier can be used in several configurations. Therefore, it is not connected internally.

sym

gain

GBW0

cl0

description

gain at DC

min

80

typ

max

unit

dB

Comments

1

4

5

6

3

7

gain bandwidth product

capacitive load

25

kHz

nF

5

GBW1

cl1

gain bandwidth product

capacitive load

125

kHz

pF

200

fm

phase margin

55

5

°

rl

resistive load

kohm

kV/s

V

SR

slew rate

10

CMR

OR

common mode input range

output range

vss-0.2

vss+0.2

vdd-1.2

vdd-0.2

V

Table 9.3:

DAC signal amplifier performances

34

D0109-40

Data Acquisition Microcontroller

XE88LC05

sym

voff

description

offset

min

60

typ

200

max

±5

unit

mV

Comments

2

CMRR

noise

ibias

ioff

common mode rejection

integrated input noise

quiescent bias current

off current

dB

100

500

1

uVrms

uA

Table 9.3:

Note:

DAC signal amplifier performances

1) For the minimal resistive load and the maximal capacitive load

2) At DC

3) Short circuit protection at ~5mA.

4) GBW when the maximal load is cl0 and with the bit BW=0

5) GBW when the maximal load is cl1 and with the bit BW=1

6) In both cases BW=0 and BW=1 for the maximal capacitive load and the minimal resistive

load.

7) For maximal load cl0, BW=0 and maximal resistive load rl

9.6 The DAC of signal DAC

The DAC of signal DAC can be used as a regular PWM DAC (NSorder set to 00), or a sigma-

delta DAC (first or second order). The most efficient setting is the second order sigma-delta

(NSorder set to 10), and this is the mode that we describe below. In order to function according

to the following computation, it must be followed by a second order filter or larger with a given

cut-off frequency.

Note:

The DAC output is ratiometric to power supply. It is highly important to avoid parasitic on power

supply. It is recommended to have no heavy switching on output ports for precise DAC output.

The D/A resolution in bits is given by (second order filter):

resolution(bit) = – 0.226 + m + (NSorder ⋅ (q – 2.65))

with:

m = PWM resolution in bits (4 .. 11)

m

code_lmax

(PWM resolution in bits)

000

001

010

011

100

101

110

111

4

5

6

7

8

9

10

11

Table 9.4:

PWM resolution setting

NSorder = order of the noise shaper = (0 .. 2)

35

D0109-40

Data Acquisition Microcontroller

XE88LC05

ns_order(1:0)

Noise shaping order

00

01

1x

0

1

2

Table 9.5:

Noise shaper order setting

q = ratio between the pulse repetition frequency (fs) and the cut-off frequency of the external

low pass filter (fc)

q = log₂((fs) ⁄ (fc))

fs = PWM pulse repetition frequency

(frc) ⁄ (fdiv)

fs = ------------------------------

2^m

with frc the RC oscillator frequency; fdiv is the division factor of the frc as set by FIN.

FIN(1:0)

RC clock division factor: fdiv

0

1

2

Table 9.6:

RC clock division factor

_Example:f_RC

=2MHz, FIN=1, m=4, fc=1kHz, NSorder=2 and therefore, the resolution is:

fs 2MHz 2⁴125kHz

=

q

log (125kHz /1kHz) 6.96

=

2

=

resolution

0.226 4 2*(6.96 2.65) 12.4bit

+ +

= −

−

=

Settings

m

Performances

q

frc

fin

fc

ns

fs

resolution

Hz

4’000

Hz

bits

8.4

2’000’000

2’00’0000

2’000’000

1

2

4

2

125’000

62’500

31’250

977

4.97

5.97

6.97

7.97

8.97

5.97

4.97

1.97

5.97

4

2’000

1’000

500

10.4

12.4

14.4

16.0

11.4

10.4

9.4

4

250

5

1’000

250

6

11

4

1’000

62’500

10.4

Table 9.7:

Examples of resolution for different settings of the signal DAC and of the filter

36

D0109-40

Data Acquisition Microcontroller

XE88LC05

10 Physical description

10.1 LQFP64 package

Figure 10.1:

LQFP64 package, size in mm.

10.2 Die

pin 1

Figure 10.2:

Die. Chip size is 4.2 x 4.7mm2 for 0.3 mm thickness.

Physical chip size and exact pad positioning can change without notification.

37

D0109-40

Data Acquisition Microcontroller

XE88LC05

10.2.1 Bonding pad location

Coordinates start with a point near to the bottom left border (with respect to above picture). X

is horizontal, Y is vertical.

Pad size is 85 x 85 um.

Symbol

Pad

X

Y

Symbol

Pad

X

Y

um

1

PA(0)

PA(1)

52.6

4123.5

3908.5

3693.5

3478.5

3263.5

3048.5

2833.5

2618.5

2403.5

2188.5

1973.5

1758.5

1543.5

1328.5

1113.5

898.5

683.5

468.5

47.6

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

NC

DAB_AI_p

DAB_AI_n

TEST

3363.5

3498.5

3628.5

3958.4

3628.5

3458.5

3293.5

3114.6

1923.5

1753.5

1588.5

1418.5

1252.9

1088.5

923.5

47.6

2

52.6

47.6

3

PA(2)

52.6

47.6

4

PA(3)

52.6

508.5

5

NC

52.6

AC_R(3)

AC_R(2)

AC_A(7)

AC_A(6)

AC_A(5)

NC

768.5

6

PA(4)

52.6

1028.5

1283.5

1543.5

1798.5

2058.5

2313.5

2573.5

2828.5

3088.5

3343.5

3603.5

3858.5

4118.5

4453.4

7

PA(5)

52.6

8

PA(6)

52.6

9

PA(7)

52.6

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

PC(0)

PC(1)

PC(2)

PC(3)

NC

52.6

AC_A(4)

AC_A(3)

AC_A(2)

AC_A(1)

AC_A(0)

NC

52.6

PC(4)

PC(5)

PC(6)

PC(7)

PB(0)

52.6

AC_R(1)

AC_R(0)

DAS_Out

DAS_AI_p

DAS_AI_n

DAS_AO

Vbat

52.6

398.5

533.5

668.5

798.5

933.5

1063.5

1198.5

1328.5

1463.5

1593.5

1728.5

1858.5

2042.4

2683.3

PB(1)

47.6

PB(2)

47.6

PB(3)

47.6

PB(4)

47.6

NC

47.6

Vss

PB(5)

47.6

Vss_Vreg

Vreg

PB(6)

47.6

PB(7)

47.6

Vmult

DAB_R_p

DAB_R_n

DAB_Out

DAB_AO_p

DAB_AO_n

47.6

RESET

OscOut

NC

47.6

758.5

47.6

OscIn

593.5

47.6

Vss

428.5

Table 10.1:

Bonding pads location. Do not connect pads named NC. Pins 56, 57 and 64 must be

connected to VSS.

38

D0109-40

Data Acquisition Microcontroller

XE88LC05

11 Contacting XEMICS

11.1 Web site:

http://www.xemics.com

11.2 XEMICS Headquarter, Sales for Europe and Asia

XEMICS SA

Maladière 71

CH-2007 Neuchâtel

Switzerland

Tel: +41 32 720 5511

Fax: +41 32 720 5770

E-mail: info@xemics.com

11.3 Sales for USA

XEMICS USA Inc.

625 Ellis Street, #102

Mountain View, CA 94043

Phone: (650) 428 0600

Fax: (650) 938 1732

Toll free: 1-888-3XEMICS

email: xemicsus@xemics.com

You will find more information about the XE88LC05 and other XEMICS products, as well as

the addresses of our representatives and distributors for your region on www.xemics.com.

All rights are reserved. Reproduction whole or in part is prohibited without the prior written consent of the copyright owner. The

information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and

may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof

does not convey nor imply any license under patent- or other industrial or intellectual property rights.

39

D0109-40


型号：	XE88LC05RI000
厂家：	ETC
描述：	16 + 10 bit Data Acquisition Ultra Low-Power Microcontroller 16 + 10位数据采集超低功耗微控制器微控制器
文件：	总39页 (文件大小：1363K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XE88LC05RI000 [ETC]

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