XR-T5684IP [ETC]
CEPT/T1 Interface ; CEPT / T1接口\n
| 型号： | XR-T5684IP |
| 厂家： | 
ETC |
| 描述： | CEPT/T1 Interface
|
| 文件： | 总16页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XR-T5684
Low Power T1
Analog Interface
...the analog plus companyTM
June 1997-3
FEATURES
APPLICATIONS
D Fully Integrated T1 Transceiver
D Interfacing T1 Network Equipment such as
Multiplexers, Channel Banks and DSX-1 Switching
Systems
D Low Power Consumption (normally 225mW)
D Recovered Data and Clock Outputs
D Driver Performance Monitor
D Interfacing Customer Premises Equipment such as
CSUs, PBXs, T1 Measurement and Test Equipment
D Internal Transmit LBO for Line Lengths Between
0 to 655 Feet
D Compliance with TR-TSY-000499, 43802 and 43801
Input Jitter Tolerance Specifications
GENERAL DESCRIPTION
The XR-T5684 is a fully integrated PCM line transceiver
intended for DSX-1 digital cross-connect applications. It
combines both transmit and receive circuitry in a 28 pin
PLCC or PDIP package. The receiver extracts data from
AMI coded input signal, and outputs synchronized clock and
unipolar RPOS and RNEG data by means of an external 8X
or 16X oversampling clock. The oversampling clock is
necessary only for applications where the clock recovery
feature is required. The transmitter of the device pre-shapes
the transmit pulse internally, providing the appropriate pulse
shape at the cross-connect for line lengths ranging from 0 to
655 feet. The XR-T5684 is manufactured using advanced
CMOS technology and requires only a single +5V power
supply.
ORDERING INFORMATION
Operating
Temperature Range
Part No.
Package
XR-T5684IJ
XR-T5684IP
-40 to + 85°C
-40 to + 85°C
28 Lead PLCC
28 Lead 600 Mil PDIP
Rev. 1.01
E1997
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017
1
XR-T5684
BLOCK DIAGRAM
12
LOS
Loss of
Signal
Detection
Data
Comparators
6
7
+
–
RPOS
RNEG
19
RTIP
Data
Retiming
Circuit
Peak
Det.
20
RRING
+
–
8
Clock
Recovery
RCLK
1
5
9
LCLK
MODE
PD
10
21
22
CLKDIS
RVDD
+5
RGND
Figure 1. XR-T5684 Receive Side
Rev 1.01
2
XR-T5684
2
13
TTIIP
TCLK
TPOS
TNEG
Transmit
Control
Logic
Output
Pulse
Shaper
3
4
Output
Driver
16
TRING
26
28
TEST
TAOS
23
24
LEN0
LEN1
LEN2
25
17
18
11
Driver
Performance
Monitor
MTIP
DPM
MRING
15
14
27
+5
TVDD
GND
NC
Figure 2. XR-T5684 Transmit Side
Rev. 1.01
3
XR-T5684
PIN CONFIGURATION
1
2
28
27
26
25
24
23
22
21
LCLK
TCLK
TAOS
N/C
4
3
2
1
28 27 26
3
TPOS
TNEG
MODE
TEST
LEN2
LEN1
25
24
23
5
4
MODE
LEN2
5
6
RPOS
LEN1
LEN0
6
RPOS
RNEG
RCLK
PD
CLKDS
DPM
LEN0
RGND
RVDD
7
RNEG
7
22
8
8
RCLK
RGND
9
20 RRING
19
9
21
20
PD
RVDD
RTIP
MRING
10
11
10
CLKDS
RRING
18
11
19
DPM
RTIP
LOS 12
17 MTIP
TTIP
TRING
13
16
12 13 14 15 16 17 18
14
15
TGND
TVDD
28 Lead PLCC
28 Lead PDIP (0.600”)
PIN DESCRIPTION
Pin #
Symbol
Type Description
1
LCLK
I
Oversampling Clock. 8X or 16X input clock for receive clock recovery circuit.
8X=12.352MHz±200ppm with pin 9 set to low. 16X=24.704MHz ±200ppm with pin 9 set to high.
2
3
TCLK
TPOS
I
I
Transmit Clock. T1=1.544MHz±50ppm.
Transmit Positive Data. A positive NRZ data on this pin causes a positive pulse to be trans-
mitted on TTIP. TPOS is sampled on the falling edge of TCLK.
4
5
TNEG
MODE
I
I
Transmit Negative Data. A positive NRZ data on this pin causes a negative pulse to be
transmitted on TRING. TNEG is sampled on the falling edge of TCLK.
Receive Output Data Select. With this pin set to high, the extracted data at RPOS and
RNEG are re-timed using the recovered clock RCLK. With this pin set to low, the received
data have no relation to RCLK and are typically stretched by 80nS before being sent to the
output. This pin is pulled down internally.
6
7
8
9
RPOS
RNEG
RCLK
PD
O
O
O
I
Receive Positive Data Output. A positive pulse on this pin corresponds to a positive pulse
on RTIP.
Receive Negative Data Output. A positive pulse on this pin corresponds to a positive pulse
on RRING.
Receive Clock Output. Recovered clock using oversampling clock applied to pin 1. See
MODE select of pin 5 and PD of pin 9.
Programmable Divider. The state of this pin determines the oversampling clock applied to
pin 1. When LCLK=16X1.544MHz, set PD to high. When LCLK=8X1.544MHz, set PD to low.
This pin is pulled down internally.
10
11
CLKDS
DPM
I
Clock Disable. With this pin set to high, the recovered clock at pin 8 is disabled. This func-
tion is provided for applications where upon input data loss, the output clock can be inhibited
by connecting LOS to CLKDS externally. This pin is pulled down internally.
O
Driver Performance Monitor. Used as an early warning signal on non-functioning T1 links. If
no signal is present on MTIP and MRING for 63 clock cycles. DPM goes high until a next
pulse is detected.
Rev 1.01
4
XR-T5684
PIN DESCRIPTION (CONT’D)
Pin #
Symbol
Type Description
12
LOS
O
O
Loss of Signal. This pin goes high either when the input signal at RTIP and RRING drops to
below 0.4V peak or after 175 zeros are detected. The 175 zeros detection is active only when
LCLK is applied.
13
TTIP
Transmit Positive Data. Transmit AMI signal is driven to the line via a step-up transformer
from this pin.
14
15
16
TGND
TVDD
TRING
Transmitter Supply Ground. This pin can be connected to RGND externally.
5 V ±5% Transmitter Supply.
O
O
Transmit Negative Data. Transmit AMI signal is driven to the line via a step-up transformer
from this pin.
17
18
MTIP
I
I
Driver Performance Monitor Input. This pin is normally connected to TTIP for monitoring
the driver’s activity. It is pulled high internally.
MRING
Driver Performance Monitor Input. This pin is normally connected to TRING for monitoring
the driver’s activity. It is pulled high internally.
19
20
21
22
23
24
25
26
27
28
RTIP
RRING
RVDD
RGND
LEN0
LEN1
LEN2
TEST
N/C
I
I
Receive Tip Input. The AMI receive signal is input to this pin via a centre-tapped transformer.
Receive Ring Input. The AMI receive signal is input to this pin via a centre-tapped transformer.
5 V ±5% Receive Supply. This pin can be connected to TVDD externally.
Receive Supply Ground. This pin is also connected to the substrate of the device.
Pulse Shaper Select Pin. Least significant bit.
I
I
I
I
Pulse Shaper Select Pin. Second significant bit.
Pulse Shaper Select Pin. Most significant bit.
Factory Test Pin. This pin must be grounded for normal operation.
No Connection Pin. This pin can be grounded or left floating.
TAOS
I
Transmit All Ones Select. Setting TAOS high causes continuous AMI ones to be transmitted
to the line at the frequency set by TCLK.
Rev. 1.01
5
XR-T5684
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = -40 to + 85_C, RV and TV = 5V ± 5%, RGND and TGND = 0V.
DD
DD
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
DC ELECTRICAL CHARACTERISTICS
Recommended Operating Conditions
VDD/TVDD
PD
DC Supply Voltage
4.75
5
5.25
400
V
Total Power Disapation
mW
100% ones density & max. line
length @ 5.25V and with 16X over-
sampling clock running.
PD
Normal Power Dissipation
225
mW
50% ones density & 300 feet line
length @5.0V and with over-sam-
pling clock disabled.
Inputs
VIH
High Level Input1
Low Level Input1
2.0
V
V
VIL
0.8
IIL
Input Leakage Current
ꢀ10
mA
Pins = TCLK, TPOS, TNEG,
LEN0/1/2.
Outputs
VOH
High Level Output2
Low Level Output2
2.4
2.4
V
V
VOL
0.4
3.6
Analog Specifications
VPA
AMI Output Pulse Amplitudes
3.0
V
Measured at DSX-1 using a 1:1.36
step up transformer with all line
length select as shown in Table 1.
TXJA
Jitter added by the transmitter
10Hz - 40KHz3
Broad Band3
0.025
0.05
UI
UI
RXS
Receiver Sensitivity
Below DSX(0dB=2.4V)
6
dB
RLOS
Receiver Loss of Signal
Threshold
0.4
175
70
V
Number of Consecutive Zeros
before LOS
160
190
RTH
Receiver Data Slicing
Threshold
% of
peak
AC CHARACTERISTICS
TCLKf
Clock Frequency
1.544
50
MHz
%
TCLK Clock Duty Cycle
Frequency 8X
40
35
60
LCLKf
LCLKf
12.352
24.704
MHz
MHz
ppm
%
16X
LCLK Clock Tolerance
LCLK Clock Duty Cycle
ꢀ 200
50
65
Notes
1
2
3
4
All input pins except RTIP, RRING, MTIP and MRING.
All output pins except TTIP and TRING.
Input clock to TCLK is jitter free.
Pin 5 Set to low.
Rev 1.01
6
XR-T5684
ELECTRICAL CHARACTERISTICS (CONT’D)
Test Conditions: TA = -40 to + 85_C, RV and TV = 5V ± 5%, RGND and TGND = 0V.
DD
DD
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
tsu
TPOS/TNEG to TCLK Setup
Time
25
ns
tho
tdr
tdf
TCLK to TPOS/TNEG Hold
Time
25
15
60
ns
ns
ns
RTIP/RRING Rising to RPOS/
RNEG Rising4
30
120
250
RTIP/RRING Falling to RPOS/
RNEG Falling4
120
RCLK Duty Cycle
50
%
tsu
tho
RPOS/RNEG to RCLK Falling
Setup Time
300
ns
RCLK Falling to RPOS/RNEG
Hold Time
324
ns
Notes
1
2
3
4
All input pins except RTIP, RRING, MTIP and MRING.
All output pins except TTIP and TRING.
Input clock to TCLK is jitter free.
Pin 5 Set to low.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (continuous) . . . . . . . . . . . . -0.5V, +7V
Supply Current (continuous) . . . . . . . 20mA to -20mA
Storage Temperature . . . . . . . . . . . . -65°C to + 150°C
Rev. 1.01
7
XR-T5684
SYSTEM DESCRIPTION
The device consists of receiver and transmitter circuitry
with separate power supplies to reduce crosstalk
between the two sections.
A positive data at RPOS corresponds to a positive pulse
received at RTIP and a positive data at RNEG
corresponds to a positive pulse received at RRING.
With Mode Select (pin 5) set to high and an oversampling
clock applied to pin 1, the recovered data can be
synchronized with RCLK at pin 8. The clock recovery circuit
extracts the timing contents from the incoming data
transitions by means of an 8X or 16X divider. If there is no
data on the input, the divider operates in its free running
mode, generating a equal mark-and-space ratio output
clock. This free running mode will be interrupted if a positive
pulse is detected; the resultant mark-and-space ratio of the
output clock is then determined by the position of the
occurrence of the positive data relative to its free running
position. See timing diagram in Figure 3 and Figure 4.
RECEIVER
The receiver is sensitive to the entire cable length from
the cross-connect and requires no external equalization
networks. The receive AMI input signal is applied to RTIP
and RRING through a center-grounded transformer. The
positive pulse is input to RTIP and the negative pulse is
input to RRING.
Comparators are used to slice the data on RTIP and
RRING. The slicing level of the comparators are
dynamically set at around 70% of peak level of the input
signaltoensureoptimumsignal-to-noiseratio. WithMode
Select (pin 5) set to low, the clock recovery feature is
bypassed and the output data from the comparators are
typically stretched by 80nS before output to RPOS and
RNEG respectively.
In all cases, the output data RPOS and RNEG remains
stable on the falling edge of RCLK so as to be sampled
correctly. The input jitter tolerance with an 8X
oversampling clock is shown in Figure 6 and that with a
16X oversampling clock is shown in Figure 5.
8X OVERSAMPLING
RTIP
RRING
648nS
RCLK
RPOS
6 Clk Cycles
RNEG
tsu
tho
6 Clk Cycles
Figure 3. Receiver Clock and Data Switching Characteristics
16 X OVERSAMPLING
RTIP
RRING
RCLK
8 Clk Cycles
RPOS
RNEG
8 Clk Cycles
tsu
tho
Figure 4. Typical Receive Timing Diagram Using 8X Oversampling Clock.
Rev 1.01
8
XR-T5684
-20db / Decade
10 UI
10 UI
TR-TSY-000499
Issue 2 Dec., 1988
1.5 UI
0.6 UI
0.4 UI
0.3 UI
10 Hz
640 Hz
6430 Hz
20 KHz
40 KHz
Jitter Frequency
Figure 5. Typical Receive Timing Diagram Using 16X Oversampling Clock
-20db / Decade
10 UI
10 UI
TR-TSY-000499
Issue 2 Dec., 1988
1.9 UI
0.7 UI
0.5 UI
0.3 UI
10 Hz
640 Hz
6430 Hz
20 KHz
40 KHz
Jitter Frequency
Figure 6. XR-T5684 Input Jitter Tolerance Using 8X Oversampling Clock
Rev. 1.01
9
XR-T5684
Another function of the receiver is the signal quality
monitor that reports loss of signal when the input level on
RTIP and RRING falls below 0.4V or upon detection of
175 ± 15 consecutive zeros in the incoming data stream.
The zero detection circuit is active only when LCLK clock
is applied. In both cases, the receiver reports loss of
signal by setting LOS high, and at the same time, RPOS
and RNEG are forced to low. Under the loss of signal
conditions, the receiver will continue to recover data and
will return to its normal operation if a valid data is detected
on RTIP and RRING.
Pulse shaping is selectable through input control pins
LEN2, LEN1 and LEN0 for line lengths ranging from 0 to
655 feet of ABAM cable as illustrated in Table 1.
LEN2 LEN1 LEN0
Line Length Selected (ft.)
0 - 133
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
133 - 266
266 - 399
399 - 533
533 - 655
TRANSMITTER
Table 1. ABAM or ALVYN Cable Type
Line Length Selection
The transmitter is designed to take dual rail NRZ data, plus a
synchronized input clock and produces a bipolar signal with
the appropriate shape for transmission to the line.
The transmitter can be set to transmit a continuous AMI
encoded all ones signal to the line by forcing TAOS high. In
this mode, input data TPOS and TNEG are ignored and the
frequency of the transmitted signal is determined by TCLK.
After sampling by the falling edge of TCLK, TPOS and
TNEG data are processed by a digital to analog converter
together with a slew-control circuit to generate output
pulses at TTIP and TRING with the appropriate amplitude
and shape to meet the cross-connect template specified
in CB 119. A typical output pulse is shown in Figure 7. In
ordertomeettheamplituderequirementwithasingle+5V
supply, thetransmitsignalisdriventothelinedifferentially
via a 1:1.36 step-up transformer.
With TTIP connected to MTIP and TRING connected to
MRING, the driver monitor can detect a non-functional T1
transmitter by monitoring the activity at its input. If no signal
is presented on MTIP and MRING for 63 TCLK clock cycles,
DPM goes high until the next AMI signal is detected.
T5684 Output Pulse Shape
CB119 Specification
1.0
0.5
0
-0.5
250
500
750
1000
Time (Nanoseconds)
Figure 7. Receiver Clock and Data Switching Characteristics
Rev 1.01
10
XR-T5684
Rev. 1.01
11
XR-T5684
RRING, RTIP
RPOS, RNEG
tdr
tdf
Figure 2. Receiver Clock and Data Switching Characteristics
TCLK
tsu
tho
TPOS, TTNEG
Figure 3. Receiver Clock and Data Switching Characteristics
Rev 1.01
12
Preliminary
XR-T5684
28 LEAD PLASTIC LEADED CHIP CARRIER
(PLCC)
Rev. 1.00
D
C
Seating Plane
D
1
A
45° x H1
2
45° x H2
2
1
28
B
1
B
D
D
1
D
D
2
3
e
R
D
3
A
1
A
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
A
A
B
B
0.165
0.090
0.020
0.013
0.026
0.008
0.485
0.450
0.390
0.180
0.120
–––.
4.19
2.29
0.51
0.33
0.66
0.19
4.57
3.05
1
2
–––
0.021
0.032
0.013
0.495
0.456
0.430
0.53
0.81
1
C
D
D
D
D
e
0.32
12.32
11.43
9.91
12.57
11.58
10.92
1
2
3
0.300 typ.
0.050 BSC
7.62 typ.
1.27 BSC
H1
H2
R
0.042
0.056
0.048
0.045
1.07
1.42
1.22
1.14
0.042
0.025
1.07
0.64
Note: The control dimension is the inch column
Rev.
13
XR-T5684
28 LEAD PLASTIC DUAL-IN-LINE
(600 MIL PDIP)
Rev. 1.00
28
15
E
1
1
14
E
D
A
2
A
L
Seating
Plane
C
α
A
1
B
B
e
1
e
e
A
B
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.160
0.015
0.125
0.014
0.030
0.008
1.380
0.600
0.485
0.250
0.070
0.195
0.024
0.070
0.014
1.565
0.625
0.580
4.06
0.38
6.35
1.78
A
A
B
B
1
2
3.18
4.95
0.36
0.56
0.76
1.78
1
C
D
E
0.20
0.38
35.05
15.24
12.32
39.75
15.88
14.73
E
e
1
0.100 BSC
0.600 BSC
2.54 BSC
15.24 BSC
e
A
e
B
L
0.600
0.700
0.200
15.24
17.78
5.08
0.115
2.92
α
0°
15°
0°
15°
Note: The control dimension is the inch column
Rev 1.01
14
Preliminary
XR-T5684
Notes
Rev.
15
XR-T5684
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.
Copyright 1997 EXAR Corporation
Datasheet June 1997
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev 1.01
16
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