Z9960AL [ETC]
TWENTY-ONE DISTRIBUTED-OUTPUT CLOCK DRIVER|QFP|48PIN|PLASTIC ; 二十一分布式输出时钟驱动器| QFP | 48PIN |塑料\n
| 型号： | Z9960AL |
| 厂家： | 
ETC |
| 描述： | TWENTY-ONE DISTRIBUTED-OUTPUT CLOCK DRIVER|QFP|48PIN|PLASTIC
|
| 文件： | 总7页 (文件大小：72K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Z9960
2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer
Table 1. Frequency Table[1]
Features
• 2.5V or 3.3V operation
F
B
_
S
E
L
• Output frequency up to 200 MHz
• Supports PowerPC , and Pentium® processors
• 21 clock outputs: drive up to 42 clock lines
• LVPECL or LVCMOS/LVTTL clock input
• Output-to-output Sskew < 150 ps
• Split 2.5V/3.3V outputs
S
E
L
S
E
L
S
E
L
A
QA
VCO/2
VCO/4
B
QB
VCO/2
VCO/4
C
QC
VCO/2
VCO/4
FB_OUT
VCO/8
VCO/12
0
1
0
1
0
1
0
1
• Spread spectrum compatible
Note:
• Glitch-free output clocks transitioning
• Output disable control
1. Input frequency range: 16 MHz to 33 MHz (FB_SEL = 1), or 25 MHz to 50
MHz (FB_SEL = 0).
• Pin-compatible with MPC9600
• Industrial temperature range: –40°C to +85°C
• 48-pin LQFP package
Block Diagram
Pin Configuration
AVDD
A
REF_SEL
0
1
/2
/4
/8
0
1
PLL
D Q
0
1
TCLK
PECL_CLK
PECL_CLK#
0
1
REF
FB
/12
48 47 46 45 44 43 42 41 40 39 38 37
2
3
FB_IN
SELA
VSSA
FB_OUT
QB0
1
36
35
34
33
32
31
30
29
28
27
26
25
VSS
TCLK
4
5
2
3
PECL_CLK
PECL_CLK#
VDD
B
6
0
0
1
QB1
4
D Q
VDDB
QB2
1
5
2
3
6
SELB
REF_SEL
FB_SEL
AVDD
Z9960
QB3
7
4
5
VSSB
QB4
8
9
SELA
6
0
C
QB5
10
11
12
SELB
0
1
D Q
QB6
SELC
1
VDDB
VSSC
2
3
SELC
13 14 15 16 17 18 19 20 21 22 23 24
4
5
6
OE#
FB
0
1
FB_OUT
D Q
FB_SEL
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07087 Rev. *A
Revised October 31, 2001
Z9960
Pin Definitions
Pin
Pin Name
PECL_CLK
PECL_CLK#
TCLK
Pin No.
Type
Pin Description
3
4
2
I, PD
I, PU
I, PD
PECL Clock Input.
PECL Clock Input.
External Reference/Test Clock Input.
QA(6:0)
38, 39, 40,
O
Clock Outputs. See Table 1 for frequency selections.
42, 43, 45, 46
VDDA
QB(6:0)
QC(6:0)
FB_OUT
26, 27, 28,
30, 31, 33, 34
O
VDDB
Clock Outputs. See Table 1 for frequency selections.
Clock Outputs. See Table 1 for frequency selections.
15, 16, 18,
19, 21, 22, 23
O
VDDC
35
O
VDD
Feedback Clock Output. Connect to FB_IN for normal operation. The divider
ratio for this output is set by FB_SEL; see Table 1. A bypass delay capacitor
at this output will control Input Reference/ Output Banks phase relationships.
SELA
SELB
9
10
11
7
I, PU
I, PU
I, PU
I, PU
Frequency Select Inputs. These inputs select the divider ratio at QA(0:6)
outputs. See Table 1.
Frequency Select Inputs. These inputs select the divider ratio at QB(0:6)
outputs. See Table 1.
SELC
Frequency Select Inputs. These inputs select the divider ratio at QC(0:6)
outputs. See Table 1.
FB_SEL
Feedback Select Inputs. These inputs select the divide ratio at FB_OUT
output. See Table 1.
FB_IN
47
6
I, PD
I, PU
Feedback Clock Input. Connect to FB_OUT for accessing the PLL.
REF_SEL
Reference Select Input. When high, the PECL clock is selected. And when
low, TCLK is the reference clock.
OE#
14
I, PD
Output Enable Input. When asserted low, enables all of the outputs. When
pulled high, disables to high impedance all of the outputs except FB_OUT.
VDDA
VDDB
VDDC
VDD
37, 44
25, 32
13, 20
5
Power Supply for Bank A Clock Buffers
Power Supply for Bank B Clock Buffers
Power Supply for Bank C Clock Buffers
Power Supply for Core
AVDD
VSSA
VSSB
VSSC
VSS
8
Power Supply for PLL. When AVDD is set low, PLL is bypassed.
Common Ground for Bank A
36, 41
24, 29
12, 17
1, 48
Common Ground for Bank B
Common Ground for Bank C
Common Ground
A bypass capacitor (0.1µF) should be placed as close as
possible to each positive power pin (< 0.2”). If these bypass
capacitors are not close to the pins, their high-frequency
filtering characteristic will be cancelled by the lead inductance
of the traces.
Document #: 38-07087 Rev. *A
Page 2 of 7
Z9960
Function Table
Control Pin
REF_SEL
AVDD
0
1
TCLK
PECL_CLK
PLL Power
PLL Bypass, Outputs Controlled by OE#
Outputs Enabled
OE#
Outputs Disabled (except FB_OUT)
Output Bank A at VCO/4
SELA
Output Bank A at VCO/2
Output Bank B at VCO/2
Output Bank C at VCO/2
Feedback Output at VCO/8
SELB
Output Bank B at VCO/4
SELC
Output Bank C at VCO/4
FB_SEL
Feedback Output at VCO/12
works to align the output edge, with the input reference edge
thus producing a near-zero delay. The reference frequency
affects the static phase offset of the PLL and thus the relative
delay between the inputs and outputs. Because the static
phase offset is a function of the reference clock, the Tpd of the
Z9960 is a function of the configuration used.
Overview
The Z9960 has an integrated PLL that provides low skew and
low jitter clock outputs for high-performance microprocessors.
Three independent banks of seven outputs as well as an
independent PLL feedback output, FB_OUT, provide excep-
tional flexibility for possible output configurations. The PLL is
ensured stable operation given that the VCO is configured to
run between 200 MHz to 400 MHz. This allows a wide range
of output frequencies up to 200 MHz.
Absolute Maximum Ratings
Input Voltage Relative to VSS: ..............................VSS – 0.3V
Input Voltage Relative to VDD:..............................VDD + 0.3V
Storage Temperature:................................. -65°C to + 150°C
Operating Temperature: ............................... -40°C to + 85°C
Maximum ESD Protection ............................................... 2kV
Maximum Power Supply:................................................ 5.5V
Maximum Input Current: .................................................± 20mA
The phase detector compares the input reference clock to the
external feedback input. For normal operation, the external
feedback input, FB_IN, is connected to the feedback output,
FB_OUT. The internal VCO is running at multiples of the input
reference clock set by FB_SEL select inputs; refer to Table 1.
The VCO frequency is then divided down to provide the
required output frequencies.
Zero Delay Buffer
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, VIN and VOUT should be constrained to
the range
When used as a zero delay buffer the Z9960 will likely be in a
nested clock tree application. For these applications the
Z9960 offers a low-voltage PECL clock input as a PLL
reference. This allows the user to use LVPECL as the primary
clock distribution device to take advantage of its far-superior
skew performance. The Z9960 then can lock onto the LVPECL
reference and translate with near zero delay to low skew
outputs.
VSS < (VIN or VOUT) < VDD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
By using one of the outputs as a feedback to the PLL, the
propagation delay through the device is eliminated. The PLL
Document #: 38-07087 Rev. *A
Page 3 of 7
Z9960
DC Electrical Characteristics VDD = 2.5V ±5%, TA = –40°C to +85°C
Parameter
Description
Input Low Voltage
Test Condition
Min.
VSS
1.7
Typ.
Max.
0.7
Unit
V
[2]
VIL
-
-
-
[2]
VIH
Input High Voltage
VDD
1000
V
VPP
Peak-to-Peak Input Voltage
PECL_CLK
500
mV
VCMR[3]
Common Mode Range
PECL_CLK
VDD –1.4
-
VDD –0.6
V
[4]
IIL
Input Low Current (@ VIL = VSS
Input High Current (@ VIH = VDD
Output Low Voltage
)
–120
120
0.6
µA
µA
V
[4]
IIH
)
[5]
VOL
IOL = 15 mA
IOH = –15 mA
VDD and AVDD
[5]
VOH
Output High Voltage
1.8
V
IDD
CIN
Quiescent Supply Current
Input Pin Capacitance
-
-
10
4
13
-
mA
pF
DC Electrical Characteristics VDD = 3.3V +5%, TA = –40°C to +85°C
Parameter
Description
Input Low Voltage
Test Condition
Min.
VSS
2.0
Typ.
Max.
0.8
Unit
V
[2]
VIL
-
-
-
[2]
VIH
Input High Voltage
VDD
1000
V
VPP
Peak-to-Peak Input Voltage
PECL_CLK
500
mV
VCMR[3]
Common Mode Range PECL_CLK
VDD –1.4
-
VDD –0.6
–120
V
µA
µA
V
[4]
IIL
Input Low Current (@ VIL = VSS)
[4]
IIH
Input High Current (@ VIH = VDD
)
120
[5]
VOL
Output Low Voltage
IOL = 24 mA
IOH = –24 mA
VDD and AVDD
0.55
[5]
VOH
Output High Voltage
2.4
V
IDD
CIN
Quiescent Supply Current
Input Pin Capacitance
-
-
15
4
20
-
mA
pF
Notes:
2. The LVCMOS inputs threshold is at 30% of VDD
.
3. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when HIGH input is within the VCMR range
and the input lies within the VPP specification.
4. Inputs have pull-up/pull-down resistors that affect input current .
5. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines.
Document #: 38-07087 Rev. *A
Page 4 of 7
Z9960
AC Electrical Characteristics VDD = 2.5V ±5% or 3.3V ±5%, TA = –40°C to +85°C[6]
Symbol
Fref
Parameter
Test Condition
FB_SEL = 1
FB_SEL = 0
Min.
16
Typ.
Max.
33
Unit
Reference Input Frequency
MHz
25
50
FrefDC
Fvco
Reference Input Duty Cycle
PLL VCO Lock Range
25
75
%
MHz
ms
200
400
10
Tlock
Tr / Tf
Maximum PLL lock Time
Output Clocks Rise / Fall
Time[7],[8]
0.55V to 2.0V, VDD = 3.3V
0.5V to 1.8V, VDD = 2.5V
Q (÷2)
0.1
1.0
ns
Fout
Maximum Output Frequency
100
50
45
2
200
100
55
MHz
Q (÷4)
FoutDC
Output Duty Cycle[7],[8]
50
%
tpZL, tpZH Output Enable Time[7] (all out-
puts)
10
ns
tpLZ, tpHZ Output Disable Time[7] (all out-
puts)
2
8
ns
TCCJ
Tskew
Cycle to Cycle Jitter[7],[8]
+/- 100
ps
ps
Any Output to Any Output
Skew[7],[8]
Same frequency
Different frequency
150
300
400
450
200
225
Tskew
Bank to Bank Skew
Banks at different voltages
ps
ps
ps
Tskew(pp) Part to Part Skew[9]
Tpd
Phase Er-
ror[7],[8]
TCLK or
PECL_CLK to
FB_IN
V
DD = 3.3V
DD = 2.5V
0
100
125
V
25
Note:
6. Parameters are guaranteed by design and characterization. Not 100% tested in production.
7. Outputs loaded with 30pF each.
8. 50Ω transmission line terminated into VDD/2.
9. Part to Part skew at a given temperature and voltage
Ordering Information
Package
Name
Ordering Code
Package Type
Z9960AL
48 LQFP
Industrial, -40°C to +85°C
The ordering part number is formed by a combination
of device number, device revision, package style,
and screening, as shown below.
Example: Cypress
Z9960AL
Date Code, Lot #
Z9960AL
Package
L = LQFP
Revision
Device Number
Document #: 38-07087 Rev. *A
Page 5 of 7
Z9960
Package Diagram
D
D1
10°
A2
A1
b
A
L
e
D
D1
b
-
-
0.354
0.276
-
-
-
-
-
9.00
7.00
-
-
-
48 Pin LQFP Outline Dimensions
Inches
Millimeters
0.007
0.011 0.17
0.27
Symbol
Min.
-
0.002
0.053
Nom. Max.
Min. Nom. Max.
e
L
0.02 BSC
-
0.50 BSC
-
A
A1
A2
-
-
-
0.063
0.006 0.05
0.057 1.35
-
-
-
-
1.60
0.15
1.45
0.018
0.030 0.45
0.75
PowerPC is a trademark of IBM®. Pentium® is a trademark of Intel Corporation. All product or company names mentioned in this
document are the trademarks of their respective holders.
Document #: 38-07087 Rev. *A
Page 6 of 7
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Z9960
Document Title: Z9960 2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer
Document Number: 38-07087
Issue
Date
Orig. of
Change
Rev.
**
ECN No.
107123
108715
Description of Change
06/06/01
11/07/01
IKA
Convert from IMI to Cypress
Updated AVDD Pin Functionality.
*A
NDP
Document #: 38-07087 Rev. *A
Page 7 of 7
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