ZN428E8 [ETC]

8-BIT LATCHED INPUT D-A CONVERTER; 8位锁存输入D-A转换器


型号：	ZN428E8
厂家：	ETC
描述：	8-BIT LATCHED INPUT D-A CONVERTER 8位锁存输入D-A转换器转换器光电二极管输入元件
文件：	总9页 (文件大小：275K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

THIS DOCUMENT IS FOR MAINTENANCE

PURPOSES ONLY AND IS NOT

RECOMMENDED FOR NEW DESIGNS

AUGUST 1994

DS3007-2.1

ZN428E8/ZN428J8/ZN428D

8-BIT LATCHED INPUT D-A CONVERTER

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 7

BIT 8

The ZN428 is a monolithic 8-bit D-A converter with input

latches to facilitate updating from a data bus. The latch is

transparent when enable is LOW and the data is held when

enable is taken HIGH. The ZN428 also contains a 2.5V

reference the use of which is pin optional to retain ﬂexibility.

An external ﬁxed or varying reference may therefore be

substituted.

ENABLE

ZN428J8

ZN428E8

ANALOG OUTPUT

V_REFIN

BIT 1 (MSB)

V_REFOUT

+V_CC(+5V)

ANALOG GROUND

DIGITAL GROUND

FEATURES

■ Contains DAC with Data Latch and On-Chip

Reference

■ Guaranteed Monotonic over the Full Operating

Temperature Range

■ Single +5V Supply

■ Microprocessor Compatible

■ TTL and 5V CMOS Compatible

■ 800ns Settling Time

■ Complementary to ZN427 A to D Series

■ Commercial or Military Temperature Range

DC16

DP16

BIT 7

BIT 8

BIT 6

BIT 5

BIT 4

ENABLE

BIT 3

BIT 2

BIT 1 (MSB)

+V_CC(+5V)

ZN428D

ANALOG OUTPUT

V_REFIN

V_REFOUT

ANALOG GROUND

DIGITAL GROUND

MP16 WIDE BODY

ORDERING INFORMATION

DeviceType

ZN428D

ZN428E8

ZN428J8

Operating temperature

0°C to +70°C

Package

MP16W

DP16

Fig.1 Pin connections (not to scale) - top view

-55°C to +125°C

DC16

ZN428

ABSOLUTE MAXIMUM RATINGS

Supply voltage V

+7.0V

Max.voltage, logic and V

inputs

REF

Operating temperature range

0°C to +70°C (ZN428E8, ZN428D)

-55°C to +125°C (ZN428J8)

-55°C to +125°C

Storage temperature range

Analog ground to digital ground

±200mV

ELECTRICAL CHARACTERISTICS

(V = +5V, T

= 25°C unless otherwise speciﬁed)

amb

Parameter

Units

Conditions

Min.

Typ.

Max.

Internal Voltage Reference

Output voltage

2.475

2.550

0.5

2.625

Ω

= 390Ω

= 1µF

REF

Slope resistance

T.C.

ppm/°C

REF OUT

Reference current

Note 1

D-A Converter

Linearity error

±0.5

±3

±0.5

LSB

2.0V ≤V

≤3.0V

REF IN

Differential non-linearity

Linearity error T.C.

ppm/°C

Differential non-linearity T.C.

Offset voltage

±6

All bits off

Offset voltage T.C.

±6

µV/°C

Full-scale output

2.545

2.550

2.555

External reference

= 2.560V,

all bits ON

REF IN

Full-scale output T.C.

Analog output resistance

External reference voltage

Settling time to 0.5 LSB

ppm/°C

kΩ

3.0

800

1.25

1 LSB major transition

(Note 2)

All bits ON to OFF or

OFF to ON (Note 2)

µs

Operating temperature range:

ZN428D and ZN428 E8

ZN428J8

-55

125

°C

Supply voltage (V

Supply current

)

4.5

5.0

5.5

Note 3

Power consumption

Note 1: See REFERENCE

100

Note 2: R = 10MΩ, C = 10pF

Note 3: All inputs HIGH (V = 3.5V)

ZN428

ELECTRICAL CHARACTERISTICS (cont.)

Parameter

Units

Conditions

Min.

Typ.

Max.

Logic (over specified operating

temperature range)

High level input voltage

Low level input voltage

High level input current

2.0

0.8

µA

= 5.5V, V = Max.

= 2.4V, V = Max.

Low level input current

Input clamp diode voltage

Enable pulse width

Data set-up time

-5

µA

= 0.4V, V = Max.

-1.5

= -8mA

100

150

Note 4

Note 5

Data hold time

Note 4: Set up time before ENABLE goes high

Note 5: Hold time after ENABLE goes high

D-A CONVERTER

The converter is of the voltage switching type and uses

an R-2R ladder network as shown in Fig.3. Each 2R element

specially designed for low offset voltage (<1mV). A binary

weighted voltage is produced at the output of the R-2R

ladder.

is connected to 0V or V

by transistor voltage switches

REF IN

Fig.3 The R-2R ladder network

value of V

256

is typically 1mV. This offset will normally be

Analog output =

- V ) + V

REF IN OS OS

removed by the setting up procedure (see Operating Notes)

and because the offset temperature coefﬁcient is low

(±6µV/°C)the effect on accuracy is negligible.

where n is the digital input to the D-A from the data latch.

is a small offset voltage produced by the D-A switch

currents ﬂowing through the package lead resistance. The

ZN428

Fig.4 Analog output equivalent circuit

Fig.4 shows equivalent circuit of the output (ignoring

). The output resistance R has a temperature coefﬁcient

of +0.2% per °C.

REFERENCE

(a) Internal Reference

The internal reference is an active bandgap circuit which

is equivalent to a 2.5V Zener diode with very low slope

0.2R

R+R

The gain drift due to this is

% per °C.

impedance (Fig.5). A resistor (R

), should be connected

REF

between +V

(pin 10) and pin 7. The recommended value

of 390Ω will supply a nominal reference current of (5.0-

2.5)/0.39 = 6.4mA. A stabilising/decoupling capacitor C

R should be chosen as large as possible to make the

gain drift small. As an example if R = 400kΩ then the gain

REF

1µF is required between pins 7 and 8 for internal reference

option, V (pin 7) being connected to V (pin 6).

drift due to the T.C. of R for a 100°C change in ambient

temperature will be less than 0.2%. Alternatively the ZN428

can be buffered by an ampliﬁer (see Operating Notes).

REF OUT

REF IN

Fig.5 Internal voltage reference

ZN428

Up to ﬁve ZN428s may be driven from one internal

reference (there is no need to reduce R ). This useful

feature saves power and gives excellent gain tracking

between the converters.

LOGIC

REF

Input coding is binary for unipolar operation and offset

binary for bipolar operation. When the ENABLE input is low

the data inputs drive the D to A directly. When ENABLE goes

high the input data word is held in the data latch.

The equivalent circuit for the data and clock inputs is

shown in Fig.6.

The ZN428 is provided with separate analog and digital

ground connections. The circuit will operate correctly with as

much as ±200mV between the two grounds.

(b) External Reference

If required an external reference voltage may be connected

to V

.The slope resistance of such a reference should be

REF IN

2.5

less than

Ω, where n is the number of converters supplied.

can be varied from 0 to +3V for ratiometric

REF IN

operation. The ZN428 is guaranteed monotonic for V

above 2V.

REF IN

Fig.6 Equivalent circuit of all inputs

Using these relationships a table of nominal resistance

OPERATING NOTES

values for R and R can be constructed for V

= 2.5V.

REF IN

(1) Unipolar D-A Converter

The nominal output range of the ZN428 is 0 to V

through a 4Ω resistance. Other output ranges can readily be

obtained by using an external ampliﬁer.

The general scheme (Fig.7) is suitable for ampliﬁers

with input bias currents less than 1.5µA.

REF IN

Output Range

+5V

8kΩ

+10V

16kΩ

5.33kΩ

The resulting full-scale range is given by:

FS =( ^{1 + R1}) V

= G.V

REF IN REF IN

OUT

For gain setting R is adjusted about its nominal value.

Practical circuit realisations (including ampliﬁer stabilising

components) for +5 and +10V output ranges are given in

Fig.8. Settling time for a major transition is 1.5µs typical.

The impedance at the inverting input is R1//R2 and for

low drift with temperature this parallel combination should be

equal to the ladder resistance (4kΩ). The required nominal

values of R1 and R2 are given by R1 = 4GkΩ and R

4G/(G-1)kΩ.

ZN428

Fig.7 Unipolar operation - basic circuit

Fig.8 Unipolar operation - component values

ZN428

UNIPOLAR ADJUSTMENT PROCEDURE

UNIPOLAR LOGIC CODING

(i) Set all bits to OFF (low) with ENABLE low and adjust

Input Code

(Binary)

Analog Output

(Nominal Value)

zero until V

= 0.0000V.

OUT

(ii) Set all bits ON (high) and adjust gain until V

= FS

OUT

- 1LSB.

11111111

11111110

11000000

10000001

10000000

01111111

01000000

00000001

00000000

FS - 1LSB

FS - 2 LSB

UNIPOLAR SETTING UP POINTS

/ FS

Output Range, +FS

LSB

FS - 1LSB

4.9805V

9.9609V

/ FS + 1LSB

/ FS

/ FS - 1LSB

/ FS

+5V

19.5 mV

39.1mV

+10V

1LSB

1LSB = FS

256

Fig.9 Bipolar operation - basic circuit

(2) Bipolar D-A Converter

For bipolar operation the output from the ZN428 is offset

by half full-scale by connecting a resistor R3 between V

Output Range

+5V

REF

and the inverting input of the buffer ampliﬁer (Fig.9).

16kΩ

32kΩ

16kΩ

8kΩ

When the digital input to the ZN428 is zero the analog

output is zero and the ampliﬁer output should be -Full-scale.

An input of all ones to the D-A will give a ZN428 output of

+10V

10.66kΩ

and the ampliﬁer output required is +Full-scale. Also,

REF IN

to match the ladder resistance the parallel combination of

Minus full scale (0ffset) is set by adjusting R about its

R , R and R should be 4kΩ.

nominal value relative to R . Plus full-scale (gain) is set by

The nominal values of R , R and R which meet these

adjusting R relative to R .

conditions are given by

Practical circuit realisations are given in Fig.10.

R = 8GkΩ, R = 8G/(G-1)kΩ and R = 8kΩ.

where the resultant output range is ±G V

. A bipolar

Note that in the ±5V case R has been chosen as 7.5kΩ

REF IN

output range of ±V

unipolar range 0 to V

(which corresponds to the basic

(instead of 8.2kΩ) to get a more symmetrical range of

adjustment using standard potentiometers. Settling time for a

major transition is 1.5µs typical.

REF IN

) is obtained if R = R = 8kΩ and

REF IN

R = ∞.

Assuming that V

= 2.5V the nominal values of

REF IN

resistors for ±5 and ±10V output ranges are given in the

following table:

ZN428

Fig.10 Bipolar operation - component values

BIPOLAR ADJUSTMENT PROCEDURE

BIPOLAR LOGIC CODING

(i) Set all bits to OFF (low) with ENABLE low and adjust

offset until the ampliﬁer output reads -full-scale.

(ii) Set all bits ON (high) and adjust gain until the

ampliﬁer output reads +(full-scale - 1LSB).

Input Code

Analog Output

(Nominal Value)

(Offset Binary)

11111111

11111110

11000000

10000001

10000000

01111111

01000000

00000001

00000000

+(FS - 1LSB)

BIPOLAR SETTING UP POINTS

+(FS - 2 LSB)

+ / FS

Input Range,

LSB

-FS

+(FS -

1LSB)

+ 1LSB

± FS

-1 LSB

±5V

39.1 mV

78.1mV

-5.0000V

+4.9609V

9.9219V

- / FS

±10V

-10.0000V

-(FS - 1LSB)

-FS

1LSB = 2FS

256

HEADQUARTERS OPERATIONS

GEC PLESSEY SEMICONDUCTORS

Cheney Manor, Swindon,

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Tel: (0793) 518000

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These are supported by Agents and Distributors in major countries world-wide.

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ZN428E8 [ETC]

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