MC74VHC1GT00 [ETL]
2-Input NAND Gate / CMOS Logic Level Shifter with LSTTL-Compatible Inputs; 2输入与非门/ CMOS逻辑电平转换器与LSTTL兼容输入
| 型号： | MC74VHC1GT00 |
| 厂家： | 
E-TECH ELECTRONICS LTD |
| 描述： | 2-Input NAND Gate / CMOS Logic Level Shifter with LSTTL-Compatible Inputs |
| 文件： | 总4页 (文件大小：577K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2–Input NAND Gate / CMOS Logic Level Shifter
with LSTTL–Compatible Inputs
MC74VHC1GT00
The MC74VHC1GT00 is a single gate 2–input NAND fabricated with silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.
The device input is compatible with TTL–type input thresholds and the output has a full 5 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic–level translator from
3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high–voltage power
supply.
The MC74VHC1GT00 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT00 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when
V CC = 0 V. These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch,
battery backup, hot insertion, etc.
• Power Down Protection Provided on Inputs and Outputs
• High Speed: t PD = 3.1 ns (Typ) at V CC = 5 V
• Balanced Propagation Delays
• Low Power Dissipation: I CC = 2mA (Max) at T A = 25°C
• Pin and Function Compatible with Other Standard Logic
• TTL–Compatible Inputs: V IL = 0.8 V; V IH = 2.0 V
Families
• CMOS–Compatible Outputs: V OH > 0.8 V CC ; V OL < 0.1
• Chip Complexity: FETs = 64; Equivalent Gates = 14
V CC @Load
MARKING DIAGRAMS
5
4
1
2
VHd
3
SC–70/SC–88A/SOT–353
DF SUFFIX
CASE 419A
Pin 1
Y
d = Date Code
5
Figure 1. Pinout (Top View)
4
VHd
1
2
3
Figure 2. Logic Symbol
SOT–23/TSOP–5/SC–59
DT SUFFIX
Pin 1
CASE 483
d = Date Code
FUNCTION TABLE
Inputs
Output
PIN ASSIGNMENT
A
L
B
L
Y
H
H
H
L
1
2
3
4
5
IN B
IN A
L
H
L
GND
OUT Y
V CC
H
H
H
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 4 of this data sheet.
VHT0–1/4
MC74VHC1GT00
MAXIMUM RATINGS
Symbol
Parameter
Value
– 0.5 to + 7.0
– 0.5 to +7.0
– 0.5 to +7.0
–0.5 to V cc + 0.5
–20
Unit
V
V CC
V IN
DC Supply Voltage
DC Input Voltage
V
V OUT
DC Output Voltage
V CC=0
V
High or Low State
I IK
Input Diode Current
Output Diode Current
mA
mA
mA
mA
mW
°C/W
°C
I OK
I OUT
I CC
P D
θ JA
T L
V OUT < GND; V OUT > V CC
+20
DC Output Current, per Pin
DC Supply Current, V CC and GND
Power dissipation in still air
Thermal resistance
+ 25
+50
SC–88A, TSOP–5
SC–88A, TSOP–5
200
333
Lead Temperature, 1 mm from Case for 10 s
Junction Temperature Under Bias
Storage temperature
260
T J
+ 150
°C
T stg
V ESD
–65 to +150
>2000
°C
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
V
> 200
Charged Device Model (Note 4)
N/A
I LATCH–UP
Latch–Up Performance Above V CC and Below GND at 125°C (Note 5)
± 500
mA
1. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied. Functional operation should be restricted to the Recommended Operating Conditions.
2. Tested to EIA/JESD22–A114–A
3. Tested to EIA/JESD22–A115–A
4. Tested to JESD22–C101–A
5. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
V CC
Parameter
Min
3.0
0.0
0.0
0.0
– 55
0
Max
5.5
Unit
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V IN
5.5
V
V OUT
V CC=0
5.5
V
High or Low State
V CC
+ 125
100
20
T A
Operating Temperature Range
Input Rise and Fall Time
°C
t r ,t f
V CC = 3.3 ± 0.3 V
V CC = 5.0 ± 0.5 V
ns/V
0
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Time,
Hours
Time,
Years
117.8
47.9
20.4
9.4
Temperature °C
80
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
90
100
110
120
130
140
1
4.2
2.0
1
10
100
1000
1.0
TIME, YEARS
Figure 3. Failure Rate vs. Time Junction Temperature
VHT0–2/4
MC74VHC1GT00
DC ELECTRICAL CHARACTERISTICS
V CC
T A = 25°C
T A
<
85°C –55°C to 125°C
Symbol
Parameter
Test Conditions
(V) Min Typ Max Min Max Min Max Unit
V IH
Minimum High–Level
Input Voltage
V
3.0 1.4
4.5 2.0
5.5 2.0
1.4
2.0
2.0
1.4
2.0
2.0
V IL
Maximum Low–Level
Input Voltage
V
V
3.0
4.5
5.5
0.53
0.8
0.53
0.8
0.53
0.8
0.8
0.8
0.8
V OH
Minimum High–Level
Output Voltage
V IN = V IH or V IL
I OH = – 50 µA
3.0 2.9 3.0
4.5 4.4 4.0
2.9
4.4
2.9
4.4
V
IN = V IH or V IL
V IN = V IH or V IL
I OH = –4 mA
I OH = –8 mA
V IN = V IH or V IL
I OL = 50 µA
3.0 2.58
4.5 3.94
2.48
3.80
2.34
3.66
V OL
Maximum Low–Level
Output Voltage
V
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
IN = V IH or V IL
V IN = V IH or V IL
I OL = 4 mA
3.0
4.5
0.36
0.36
±0.1
0.44
0.44
±1.0
0.52
0.52
±1.0
I OL = 8 mA
I IN
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
Quiescent Supply
Current
V IN = 5.5 V or GND
0 to5.5
µA
µA
I CC
I CCT
I OPD
V IN = V CC or GND
Input: V IN = 3.4 V
V OUT = 5.5 V
5.5
5.5
0.0
2.0
1.35
0.5
20
1.50
5.0
40
1.65 mA
10 µA
Output Leakage
Current
AC ELECTRICAL CHARACTERISTICS C load = 50 pF, Input t r = t f = 3.0 ns
T A = 25°C
Min Typ Max Min Max Min Max Unit
T A
<85°C –55°C<TA<125°C
Symbol Parameter
Test Conditions
t PLH
t PHL
,
Maximum
V CC = 3.3± 0.3 V C L = 15 pF
C L = 50 pF
4.1
5.5
10.0
13.5
11.0
15.0
13.0 ns
17.5
Propagation Delay,
Input A or B to Y
V CC = 5.0± 0.5 V C L = 15 pF
C L = 50 pF
3.1
3.6
5.5
6.9
7.9
10
8.0
9.0
10
9.5
10.5
C IN
Maximum Input
Capacitance
10
pF
Typical @ 25°C, V CC = 5.0 V
C PD
Power Dissipation Capacitance (Note 6)
11
pF
6. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without
load. Average operating current can be obtained by the equation: I CC(OPR) = C PD • V CC • f in + I CC C PD is used to determine the no–
.
2
load dynamic power consumption; P D = C PD • V CC • f in + I CC • V CC
.
VHT0–3/4
MC74VHC1GT00
Y
*Includes all probe and jig capacitance.
A 1–MHz square input wave is recommended
for propagation delay tests.
Figure 4. Switching Waveforms
Figure 5. Test Circuit
DEVICE ORDERING INFORMATION
Device Nomenclature
Device
Package Type
(Name/SOT#/
Common Name)
Tape and
Reel Size
Device Order
Number
Logic
Temp
Package Tape and
Circuit
Range
Technology
Function Suffix
Reel Suffix
Indicator Identifier
MC74VHC1GT00DFT1 MC
MC74VHC1GY00DFT2 MC
MC74VHC1GT00DFT4 MC
MC74VHC1GT00DTT1 MC
MC74VHC1GT00DTT3 MC
74
74
74
74
74
VHC1G
VHC1G
VHC1G
VHC1G
VHC1G
T00
T00
T00
T00
T00
DF
DF
DF
DT
DT
T1
SC–70/SC–88A/
SOT–353
178 mm (7 in)
3000 Unit
T2
T4
T1
T3
SC–70/SC–88A/
SOT–353
178 mm (7 in)
3000 Unit
SC–70/SC–88A/
SOT–353
330 mm (13 in)
10,000 Unit
178 mm (7 in)
3000 Unit
SOT–23/TSOPS/
SC–59
SOT–23/TSOPS/
SC–59
330 mm (13 in)
10,000 Unit
VHT0–4/4
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