EMD3D256M16G2-150CBS1

EMD3D256M08BS1

EMD3D256M16BS1

256Mb ST-DDR3 Spin-transfer Torque

MRAM

FEATURES

• Non-volatile 256Mb (32Mb x 8, 16Mb x 16) DDR3

• Supports standard DDR3 SDRAM features

• V_DD= 1.5v +/- 0.075v

f

• Up to 667MHz CK (1333MT/sec/pin)

RoHS

• Page size of 512 bits (x8) or 1024 bits (x16)

• On-device termination

• On-Chip DLL aligns DQ, DQS, DQS transition with CK transition

• All addresses and control inputs are latched on rising edge of Clock

• Burst length of 8 with programmable Burst Chop length of 4

• Standard 10x13mm 78-Ball (x8) or 96-ball (x16) BGA Package

INTRODUCTION

The EMD3D256M08/16B 256Mb DDR3 Spin-transfer Torque MRAM (STT-MRAM) is a non-

volatile memory that oﬀers non-volatility and high endurance at DDR3 speeds. The device is

capable of DDR3 operation at rates of up to 1333MT/Sec/Pin. It is designed to comply with

all DDR3 DRAM features including on-device termination (ODT) and internal ZQ calibration

but with the beneﬁt of data persistence and extremely high write cycle endurance. With

Spin-Torque MRAM technology, cell refresh is not required, which greatly simpliﬁes system

design and reduces overhead.

All control and address inputs are synchronized with a pair of externally supplied diﬀerential

clocks, with input latching at clock crosspoints. I/Os are synchronized with a pair of bidirec-

tional strobes (DQS, DQS). The device uses a RAS/CAS multiplexing scheme and operates at

1.5V.

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DDR3 DRAM COMPATIBILITY

Everspin DDR3 Spin-Torque MRAMs are fully compatible with DDR3 standards for DRAM operation deﬁned

in JEDEC Standard JESD79-3F, with exceptions and improvements as noted and deﬁned in this data sheet.

•

The Spin-Torque MRAM is a non-volatile memory. All data in closed/precharged banks are retained in

memory whenever device power is removed for any reason.

•

Command timing will be diﬀerent in some cases. See “Table 11 – Timing Parameters”on page 20.

The DDR3 standard applies to densities higher than 256Mb resulting in addressing and page size dif-

ferences.

•

Burst Type/Burst Order supports only the sequential burst type for CA<2:0 = 000 or 100. See ”Burst

Length, Type and Order”on page 30.

This data sheet will make references to JESD79-3F when the function, timing, parameter or condition

is identical between the MRAM and this standard. The JESD79-3F standard is available on the JEDEC

website , registration is required.

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TABLE OF CONTENTS

DDR3 DRAM COMPATIBILITY .............................................................................................................2

FUNCTIONAL DESCRIPTION ...............................................................................................................6

Basic Functionality ..........................................................................................................................6

Figure 1 – Simpliﬁed State Diagram STT-MRAM ............................................................................................... 7

Figure 2 – Block Diagram (32Mb x 8) STT-MRAM.............................................................................................. 8

Figure 3 – Block Diagram (16Mb x 16) STT-MRAM ........................................................................................... 8

Table 1 – Addressing Scheme by I/O Width........................................................................................................ 9

PACKAGE BALL ASSIGNMENTS ....................................................................................................... 10

Table 2 – 32Mb x 8 in 78-Ball BGA - Top View...................................................................................................10

Table 3 – 16Mb x 16 in 96-Ball BGA - Top View.................................................................................................11

BALL FUNCTIONS AND DESCRIPTIONS.......................................................................................... 12

Table 4 – Ball Functions and Descriptions.........................................................................................................12

ABSOLUTE MAXIMUM RATINGS...................................................................................................... 15

Table 5 – Absolute Maximum Ratings.................................................................................................................15

THERMAL CHARACTERISTICS.......................................................................................................... 16

Table 6 – Thermal Characteristics 78-ball BGA Package...............................................................................16

Table 7 – Thermal Characteristics 96-ball BGA Package...............................................................................16

DC CHARACTERISTICS...................................................................................................................... 17

Table 8 – Power Supply and Input Leakage.....................................................................................................17

Table 9 – Input / Output Capacitance .................................................................................................................18

Table 10 – I_DDMaximum Limits ............................................................................................................................19

TIMING PARAMETERS ...................................................................................................................... 20

Table 11 – Timing Parameters................................................................................................................................20

TRUTH TABLES................................................................................................................................... 21

Command Truth Table.................................................................................................................. 21

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Table of Contents (Cont’d)

Table 12 – Command Truth Table .........................................................................................................................21

CKE Truth Table............................................................................................................................. 23

Table 13 – CKE Truth Table.......................................................................................................................................23

FUNCTIONAL PARAMETERS ............................................................................................................ 24

COMMAND DESCRIPTIONS.............................................................................................................. 25

ACTIVE Command......................................................................................................................... 25

t

Figure 4 – ACTIVE Command Example: Meeting RRD (MIN) and RCD (MIN)......................................26

PRECHARGE Command ................................................................................................................ 26

Figure 5 – PRECHARGE Command Timing ........................................................................................................26

READ Command ........................................................................................................................... 27

Figure 6 – READ Command Timing......................................................................................................................27

WRITE Command .......................................................................................................................... 28

Figure 7 – WRITE Burst Operation WL = 5 (AL = 0 CWL = 5, BL8)...............................................................29

Burst Length, Type and Order ..................................................................................................... 30

Table 14 – Burst Length, Type and Order...........................................................................................................30

PART NUMBER DECODER................................................................................................................. 31

Table 15 – 256Mb x8 / x16 STT-MRAM Ordering Part Number Decoder...............................................31

ORDERING PART NUMBERS............................................................................................................. 32

Table 16 – Ordering Part Numbers.......................................................................................................................32

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Table of Contents (Cont’d)

PACKAGE OUTLINE DRAWING......................................................................................................... 33

Figure 8 – 78-Ball BGA Package Outline (x8) ....................................................................................................33

Figure 9 – 78-Ball BGA Package Outline (x8) Dimensions............................................................................34

Figure 10 – 96-Ball BGA Package Outline (x16)................................................................................................35

Figure 11 – 96-Ball BGA Package Outline (x16) Dimensions.......................................................................36

Table 17 – Revision History .....................................................................................................................................37

HOW TO CONTACT US....................................................................................................................... 38

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FUNCTIONAL DESCRIPTION

Basic Functionality

The DDR3 STT-MRAM is a high-speed Spin-Torque Magnetoresistive Random Access Memory inter-

nally conﬁgured as an eight-bank RAM. It uses an 8n prefetch architecture to achieve high-speed

operation. The 8n prefetch architecture is combined with an interface designed to transfer two

data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 MRAM

consists of a single 8n-bit wide, four clock data transfer at the internal STT-MRAM core and two cor-

responding n-bit wide, one-half clock cycle data transfers at the I/O pins.

READ and write operations to the DDR3 STT-MRAM are burst oriented, start at a selected location,

and continue for a burst length of eight or a “chopped”burst of four in a programmed sequence.

Operation begins with the registration of an Active command, which is then followed by a READ

or WRITE command. The address bits registered coincident with the Active command are used to

select the bank and row to be activated ([BA0:BA2] select the bank; A0-A13 select the row); refer to

“Table 1 – Addressing Scheme by I/O Width”on page 9”for speciﬁc requirements. The address

bits registered coincident with the READ or WRITE command are used to select the starting column

location for the burst operation, determine if the auto precharge command is to be issued (via A10),

and select BC4 or BL8 mode ‘on the ﬂy’(via A12) if enabled in the mode register.

Prior to normal operation, the DDR3 STT-MRAM must be powered up and initialized in a predeﬁned

manner.

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Figure 1 – Simpliﬁed State Diagram STT-MRAM

This simpliﬁed State Diagram is intended to provide an overview of the possible state transitions and the

commands to control them. Situations involving more than one bank, the enabling or disabling of on-die

termination, and some other events are not captured in full detail.

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Figure 2 – Block Diagram (32Mb x 8) STT-MRAM

Figure 3 – Block Diagram (16Mb x 16) STT-MRAM

s 0, 1 and 2

15

128

18

32K

DQS, DQS#

(32,768 x 8 x 128)

15

128

1024

DQS, DQS#

(1, 2 )

A[14:0]

18

128

3

DM

6

3

0, 1 and 2

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Table 1 – Addressing Scheme by I/O Width

The addressing scheme is shown in the Table 1 below. The Bank and Row Address is presented during an

ACTIVE command. The Column Address is selected during a READ or WRITE command. Further explanation

is given in the COMMAND section.

Conﬁguration

# of Banks

32Mb x 8

8

16Mb x 16

8

Bank Address

Auto Precharge

BC Switch on the ﬂy

# Rows

BA0 - 2

A10/AP

A12/BC

64K

BA0 - 2

A10/AP

A12/BC

32K

Row Address

# Columns

A0 - A15

64

A0 - A14

64

Column Address

Page Size

A0 - A5

512 bits

A0 - A5

1024 bits

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PACKAGE BALL ASSIGNMENTS

256Mb x8 and x16 package ball assignments conform to JESD79-3F Standard DDR3 SDRAM footprints and

pin assignments.

Table 2 – 32Mb x 8 in 78-Ball BGA - Top View

Row

A

1

2

3

4

5

6

7

8

9

Row

A

NC

NF/TDQS

V

DD

SS

DD

SS

B

C

D

DQ0

DQS

DM/TDQS

DQ1

B

C

D

V

DDQ

SSQ

DQ2

DQ6

DQ3

V

DDQ

SSQ

V

SSQ

DD

SS

V

DDQ

E

F

DQ4

RAS

CAS

WE

BA2

A0

DQ7

CK

DQ5

E

F

V

REFDQ

NC

DDQ

NC

CKE

NC

V

SS

G

H

J

ODT

NC

CK

G

H

J

V

DD

CS

A10/AP

A15

ZQ

V

BA0

A3

V

REFCA

BA1

SS

K

L

A12/BC

A1

K

L

V

DD

A5

A2

A4

A6

V

SS

M

N

A7

A9

A11

M

N

V

DD

RESET

2

A13

3

A14

7

A8

8

V

SS

1

4

5

6

9

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Table 3 – 16Mb x 16 in 96-Ball BGA - Top View

Row

A

1

2

3

4

5

6

7

8

9

Row

A

DQU5

DQU7

DQU4

V

DDQ

SS

B

C

DQSU

DQU6

DQU2

B

C

V

SSQ

DD

SS

DQU3

DQU1

V

DDQ

D

E

DMU

DQL0

DQSL

DQU0

DML

D

E

V

SSQ

DDQ

SSQ

DD

V

SS

SSQ

DDQ

F

DQL2

DQL6

DQL1

DQL3

F

V

DDQ

SSQ

G

V

SSQ

DD

SS

SSQ

H

DQL4

DQL7

DQL5

H

V

DDQ

V

DDQ

REFDQ

NC

J

K

L

RAS

CAS

WE

BA2

A0

CK

NC

CKE

NC

J

K

L

V

SS

ODT

NC

V

DD

CS

BA0

A3

A10/AP

A15

ZQ

M

N

P

R

T

M

N

P

R

T

V

SS

REFCA

BA1

A12/BC

A1

V

DD

A5

A2

A4

A6

V

SS

A7

A9

A11

V

DD

RESET

2

A13

3

A14

7

A8

8

V

SS

1

4

5

6

9

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BALL FUNCTIONS AND DESCRIPTIONS

Table 4 – Ball Functions and Descriptions

Symbol

Type

Name

Description

Clock: CK and CK are diﬀerential clock inputs. All control and address input signals

are sampled on the crossing of the positive edge of CK and the negative edge of CK.

Output data strobe (DQS, DQS) is referenced to the crossings of CK and CK.

CK, CK

Input

Clock

Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal

circuitry and clocks on the STT-MRAM. The speciﬁc circuitry that is enabled/ dis-

abled is dependent upon the DDR3 STT-MRAM conﬁguration and operating mode.

CKE

Input

Clock Enable Taking CKE LOW provides PRECHARGE POWER-DOWN, or active power-down (row

active in any bank). CKE is synchronous for power-down entry and exit. Input buf-

fers (excluding CK, CK, CKE, RESET, and ODT) are disabled during POWER-DOWN.

CKE is referenced to V

.

REFCA

Chip Select: All commands are masked when CS is registered HIGH. CS provides for

CS

Input

Chip Select

external Rank selection on systems with multiple Ranks. CS is considered part of

the command code.

On Die Termination: ODT (registered HIGH) enables termination resistance internal

to the DDR3 STT-MRAM. When enabled, ODT is only applied to each DQ, DQS, DQS

and DM/TDQS, NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1)

signal for x8 conﬁgurations. The ODT pin will be ignored if MR1 is programmed to

disable ODT.

On-Die Termi-

nation

ODT

Command

Inputs

Command Inputs: RAS, CAS and WE (along with CS) deﬁne the command being

entered.

RAS, CAS, WE Input

Input Data Mask: DM is an input mask signal for write data. Input data is masked

when DM is sampled HIGH coincident with that input data during a WRITE access.

DM is sampled on both edges of DQS. For x8 device, the function of DM or TDQS/

TDQS is enabled by Mode Register A11 setting in MR1. For x16 DML is associated

with DQ0-7 while DMU is associated with DQ8-15.

Input Data

Mask

DM

Input

Bank address inputs: BA[2:0] deﬁne the bank to which an ACTIVE, READ, WRITE, or

Bank Address PRECHARGE command is being applied. BA[2:0] deﬁne which mode register (MR0,

BA0, BA1, BA2 Input

Inputs

MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are refer-

enced to V

.

REFCA

Address Inputs: Provide the row address for Active commands and the column

address for READ/WRITE commands to select one location out of the memory array

in the respective bank. (A10/AP and A12/BC have additional functions, see below).

The address inputs also provide the op-code during Mode Register Set commands.

In using the device in x16 mode A15 needs to be pulled to logic HIGH.

Address

Inputs

A0-A15

Input

Table continues on the next page.

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Ball Functions and Descriptions (Continued)

Symbol

Type

Name

Description

Auto-precharge: A10 is sampled during READ/WRITE commands to determine

whether Autoprecharge should be performed to the accessed bank after the READ/

WRITE operation. (HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled

during a Precharge command to determine whether the Precharge applies to one

bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the

bank is selected by bank addresses.

Auto Pre-

charge

A10/AP

Input

Burst Chop: A12 / BC is sampled during READ and WRITE commands to determine

if burst chop (on-the-ﬂy) will be performed. (HIGH, no burst chop; LOW: burst

chopped). See command truth table for details.

A12/BC

RESET

Input

Burst Chop

Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive

Acitve Low

Asynchro-

nous Reset

when RESET is HIGH. RESET must be HIGH during normal operation. RESET is a

CMOS rail-to-rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for

DC high and 0.30V for DC low.

Input

Input/

Output Output

Data Input/

Data Input/ Output: Bi-directional data bus. DQ0-7 (x8) and DQ8-15 (x16) are refer-

DQ

enced to V

.

REFDQ in

Data strobe: Output with read data. Edge-aligned with read data. Input with write

data. Center-aligned to write data. For x16 operation DQSL/DQSL is associated with

DQ0-7 and DQSU/DQSU is associated with DQ8-15.

Input/

DQS/DQS

Data Strobe

Output

Termination data strobe: Applies to the x8 conﬁguration only. When enabled via

Mode Register A11=1 in MR1, STT-MRAM will enable the same termination resis-

tance function on TDQS/TDQS that is applied to DQS/DQS. When disabled via

mode register A11=0 in MR1, DM/TDQS will provide the data mask function and

TDQS is not used.

Termination

Data Strobe

TDQS, TDQS

V_DD

Supply

Power Supply Power supply: 1.5V 0.075V.

V_DDQ

DQ Power

Supply

DQ power supply: 1.5V 0.075V. Isolated on the device for improved noise immu-

nity.

V_SS

Ground

V_SSQ

DQ Ground

DQ ground: Isolated on the device for improved noise immunity.

Reference

Voltage for

Control, Com-

mand and

Address

Reference voltage for control, command, and address: V

at all times for proper device operation.

must be maintained

REFCA

V_REFCA

Supply

Table continues on the next page.

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Ball Functions and Descriptions (Concluded)

Symbol

Type

Name

Description

Reference

Voltage for

Data

V

Reference voltage for data: V

device operation.

must be maintained at all times for proper

REFDQ

Supply

REFDQ

External Ref-

Refer-

ence

erence Ball for External reference ball for output drive calibration: This ball is tied to an external

Output Drive 240Ω resistor (RZQ), which is tied to V

Calibratoin

ZQ

.

SSQ

NC

NF

-

No Connect

No Function

No Connect: These balls should be left unconnected (the ball has no connection).

No Function

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ABSOLUTE MAXIMUM RATINGS

Table 5 – Absolute Maximum Ratings

Min

Symbol Parameter

Max

Unit

Notes

V_DD

V_DDsupply voltage relative to V_SS

V_DDQ

V_IN, V_OUT

T_OPER

-0.4

1.975

V

1

V_DDsupply voltage relative to V_SSQ

Voltage on any pin relative to V_SS

Normal operating temperature

Storage temperature

0

85

°C

2

-

T_STG

-55

150

H_max

Maximum magnetic ﬁeld during read, write, standby or

power oﬀ.

-

2,000

A/m

Notes:

1. V_DDand V_DDQmust be within 300mV of each other at all times, and V_REFmust not be greater than 0.6 × V_DDQ

V_DDQare <500mV, V_REFcan be ≤300mV.

.

When V_DDand

2. The normal temperature range speciﬁes the temperature at which all STT-MRAM speciﬁcations will be supported. During

operation, the STT-MRAM case temperature must be maintained between 0°C to 85°C under all operating conditions.

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THERMAL CHARACTERISTICS

Table 6 – Thermal Characteristics 78-ball BGA Package

Symbol Parameter

Value

Unit

T_OPER

Θ_JA

Maximum Operating Temperature

Thermal Resistance Junction to Ambient

Thermal Resistance Junction to Case

0 to 85

26.4

°C

°C/watt

Θ_JC

2.3

Table 7 – Thermal Characteristics 96-ball BGA Package

Symbol Parameter

Value

Unit

T_OPER

Θ_JA

Maximum Operating Temperature

0 to 85

25.6

°C

Thermal Resistance Junction to Ambient

Thermal Resistance Junction to Case

°C/watt

Θ_JC

2.3

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DC CHARACTERISTICS

DC Characteristics are deﬁned under standard measurement conditions speciﬁed in JEDEC Standard

JESD79-3F.

Table 8 – Power Supply and Input Leakage

All voltages referenced to V_SS

Symbol Parameter/Condition

Min

Nom

Max

Unit

Notes

V_DD

Supply Voltage

1.425

1.5

1.575

V

1, 2

V_DDQ

I/O supply voltage

Input leakage current

Any input 0V ≤ V_IN≤ V_DD, V_REFpin 0V ≤

V_IN≤ 1.1V

I_I

-2

-1

-

2

1

μA

3

(All other pins not under test = 0V)

V_REFsupply leakage current

I_VREF

V_REFDQ= V_DD/2 or V_REFCA= V_DD/2

(All other pins not under test = 0V)

3, 4

Notes:

1. V_DDand V_DDQmust track one another. V_DDQmust be ≤ V_DD. V_SS= V_SSQ

.

2. V_DDand V_DDQmay include AC noise of 50mV (250 kHz to 20 MHz) in addition to the DC (0 Hz to 250 kHz) speciﬁcations. V_DD

and V_DDQmust be at same level for valid AC timing parameters.

3. V_REF(see JESD79-3F Section 8, AC and DC Input Measurement Levels)

4. The minimum limit requirement is for testing purposes. The leakage current on the V_REFpin should be minimal.

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Table 9 – Input / Output Capacitance

Note 1 applies to the entire Table.

DDR3-All Bins

Unit

Symbol

Parameter

Min

Max

C_CK

CK and CK

0.8

1.6

pF

C_DCK

ΔC: CK to CK

0

1.5

0

0.15

3.0

0.2

0.3

1.5

0.3

0.5

3.0

Single-end I/O: DQ, DM

Diﬀerential I/O: DQS, DQS, TDQS, TDQS

ΔC: DQS to DQS, TDQS,TDQS

ΔC: DQ to DQS

2

3

4

5

6

7

C_IO

C_DQQS

C_DIO

-0.5

0.75

-0.5

-

C_I

Inputs (CTRL, CMD, ADDR)

ΔC: CTRL to CK

C_{DI_CTRL}

C_{DI_CMD_ADDR}

C_ZQ

ΔC: CMD_ADDR to CK

ZQ pin capacitance

Reset pin capacitance

C_RE

-

Notes:

1. V_DD= 1.5V 0.075mV, V_DDQ= V_DD, V_REF= V_SS, f = 100 MHz, T_C= 25°C. V_OUT(DC)= 0.5 × V_DDQ, V_OUT= 0.1V (peak-to-peak).

2. DM input is grouped with I/O pins, reﬂecting the fact that they are matched in loading.

3. Includes TDQS, TDQS. C_DDQSis for DQS vs. DQS and TDQS vs. TDQS separately.

4. C_DIO= C_IO(DQ)- 0.5 × (C_IO(DQS)+ C_IO(DQS)).

5. Excludes CK, CK; CTRL = ODT, CS, and CKE; CMD = RAS, CAS, and WE; ADDR = A[n:0], BA[2:0].

6. C_{DI_CTRL}= C_I(CTRL)- 0.5 × (C_CK(CK)+ C_CK(CK)).

7. C_{DI_CMD_ADDR}= C_{I(CMD_ADDR)}- 0.5 × (C_CK(CK)+ C_CK(CK)).

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Table 10 – I_DDMaximum Limits

2

1333MT/sec/pin

1

I_DD

Units

x8

x16

220

55

220

55

mA

I_DD0

I_DD1

I_DD2P0(slow)

I_DD2P1(fast)

I_DD2Q

60

90

I_DD2N

90

I_DD2NT

I_DD3P

60

90

I_DD3N

135

165

90

135

185

90

I_DD4R

I_DD4W

I_DD5B

45

I_DD6

2

490

45

667

45

I_DD7

I_DD8

Notes:

1. Refer to JESD79-3F Section 10, I_DDand I_DDQSpeciﬁcation Parameters and Test Conditions, with some patterns that are STT-

MRAM speciﬁc.

2

t

2. In order to limit power dissipation, I_DD7is speciﬁed with FAW = 190ns for the x8 and FAW = 230ns for the x16. The FAW can

be reduced per Table 11 but I_DD7will increase.

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TIMING PARAMETERS

Table 11 – Timing Parameters

Parameter

Symbol

I/O

Min

Max

Unit

Notes

t

Internal READ to ﬁrst data

AA

x8, x16

x8

14

95

-

ns

4

t

ACTIVE to internal READ or WRITE delay time

Precharge command period

RCD

x16

x8

190

66

t

RP

x16

134

x8

x16

170

332

103

198

30

-

ns

4

t

ACTIVE to ACTIVE command period

RC

x8

t

ACTIVE to Precharge command period

ACT to ACT Command Period, diﬀerent banks

Four ACTIVE Window

RAS

x16

t

RRD

x8, x16

x8

120

-

ns

4

t

FAW

x16

160

-

8.5

ns

V/ns

nCK

Unit

ns

4

Output slew rate

SRQ

x8, x16

4

t

DQS, DQS# Output high time for 1333 speed bin

DQS, DQS# Output low time for 1333 speed bin

QSH

-

.38

4

t

QSL

-

.38

4

Speed Bin

CL

CWL

CWL = 5

Symbol

Min

2.5

Max

3.3

Notes

t

CK (Avg)

2

3

2

3

2

3

800

CL = 6

CWL = 6,7,8,9

CWL = 6

Reserved

1.875

Reserved

1.5

CK (Avg)

< 2.5

ns

1

1066

CL = 8

CL=10

CWL= 5,7,8,9

CWL=7

<1.875

1

1333

CWL= 5,6,8,9

Reserved

6,8,10

5,6,7

Supported CL settings

Supported CWL settings

CK

1. The 1333 and 1066 speed grade ordering options are backward compatible with lower speed grade operation.

t

2. The CL and CWL settings result in CK requirements. When making a selection of CK, both CL and CWL requirement set-

tings need to be fulﬁlled.

3. Reserved settings are not allowed.

4. Parameter is diﬀerent than Standard DDR3 due to STT-MRAM design

Note: Dynamic ODT timings are intended to follow the JEDEC speciﬁcation but have not been characterized.

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TRUTH TABLES

Command Truth Table

Table 12 – Command Truth Table

Notes 1-5 apply to the entire Table.

CKE

BA

A13-

A15

A10/ A0-A9,

A12/

BC

Symbol

Notes

Function

CS RAS CAS WE

[2:0]

AP

A11

Prev.

Refresh

MRS

REF

H

L

BA

Op. Code

Self Refresh Entry

Self Refresh Exit

SRE

Not used for STT-MRAM

SRX

Single Bank Precharge

Precharge All Banks

Bank ACTIVE

PRE

H

L

H

L

H

L

BA

L

V

L

V

L

V

PREA

ACT

WR

H

L

BA

Row Address (RA)

WRITE (Fixed BL8 pr BC4)

WRITE (BC4 on the Fly)

WRITE (BL8 on the Fly)

H

BA RFU

V

L

V, CA

7

WRS4

WRS8

L

H

WRITE w/ Auto Precharge

(Fixed BL8 or BC4)

WRAP

H

L

H

L

BA RFU

V

L

H

V, CA

7

WRITE w/ Auto Precharge

(BC4 On the Fly)

WRAPS4

WRAPS8

WRITE w/ Auto Precharge

(BL8 On the Fly)

H

READ (Fixed BL8 or BC4)

READ (BC4, on the Fly)

READ (BL8, on the Fly)

RD

H

L

H

L

H

BA RFU

V

L

V, CA

7

RDS4

RDS8

H

Table continues with notes next page.

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Command Truth Table (Continued)

CKE

BA

[2:0]

A13- A12/ A10/ A0-A9,

Notes

Symbol

CS

RAS

CAS

WE

Function

A15

BC

AP

A11

Prev.

(Fixed BL8 or BC4)

RDAP

H

L

H

L

H

BA RFU

V

H

V, CA

7

READ with Auto Precharge

(BC4, on the Fly)

RDAPS4

H

L

H

L

H

L

H

V, CA

READ (BL8, on the Fly)

No Operation

RDAPS8

NOP

H

L

H

L

H

V

X

H

V

X

V, CA

7

8

9

H

V

X

V

X

V

X

Device Deselected

DES

H

L

X

H

V

H

V

X

H

V

H

V

X

H

V

H

V

Power Down Entry

PDE

PDX

H

L

V

H

L

Power Down Exit

H

6

H

ZQ Calibration Long

ZQCL

ZQCS

H

L

H

L

X

H

L

X

10

ZQ Calibration Short

Notes:

1. Commands are deﬁned by states of CS, RAS, CAS, WE, and CKE at the rising edge of the clock. The MSB of BA, RA, and CA

are device-, density-, and conﬁguration-dependent.

2. RESET is LOW enabled and used only for asynchronous reset. Thus, RESET must be held HIGH during any normal opera-

tion.

3. The state of ODT does not aﬀect the states described in this table.

4. Operations apply to the bank deﬁned by the bank address, BA[2:0]. For MRS, BA selects one of four mode registers.

5. “V” means “H” or “L” (a deﬁned logic level), and “X” means “Don’t Care.”

6. See the CKE Truth Table below for additional information on CKE transition.

7. Burst READ’s or WRITE’s cannot be terminated or interrupted. MRS (ﬁxed) and OTF BL/BC are deﬁned in MR0.

8. The purpose of the NOP command is to prevent the MRAM from registering any unwanted commands. A NOP will not termi-

nate an operation that is executing.

9. The DES and NOP commands perform similarly.

10. ZQ CALIBRATION LONG is used for either ZQinit (ﬁrst ZQCL command during initialization) or ZQoper (ZQCL command

after initialization).

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CKE Truth Table

Table 13 – CKE Truth Table

Notes 1,2 apply to the entire Table.

CKE

Previous Cycle

5

Command (RAS,

3

5

Current State

Action

Present Cycle

CAS, WE. CS)

4

(n-1)

(n)

L

H

L

X

Maintain Power Down

Power Down Exit

Power Down

L

DES or NOP

Bank(s) Active

Reading

H

Active Power Down Entry

Power Down Entry

Precharge Power Down Entry

-

Writing

Precharging

6

All Banks Idle

Notes:

X

1. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.

t

2.

CKE (MIN) means CKE must be registered at multiple consecutive positive clock edges. CKE must remain at the valid input

level the entire time it takes to achieve the required number of registration clocks. Thus, after any CKE transition, CKE may

not transition from its valid level during the time period of IS + CKE (MIN) + IH.

t

3. Current state = The state of the STT-MRAM immediately prior to clock edge n.

4. CKE (n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at the previous clock edge.

5. COMMAND is the command registered at the clock edge (must be a legal command as deﬁned in Table 12 on page 21)

Action is a result of COMMAND. ODT does not aﬀect the states described in this table and is not listed.

6. Idle state = All banks are closed, no data bursts are in progress, CKE is HIGH, and all timings from previous operations are

satisﬁed. All power-down exit parameters are also satisﬁed.

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FUNCTIONAL PARAMETERS

Functional

Parameter

Level

Description

It is expected that bit fails will be soft and distributed through-

out the address space so the system ECC built into your control-

ler should correct them. BER is after maximum page cycles, or at

the end of the endurance life.

Bit Error Rate (BER)

Limit to End of Life

-8

6.3 x 10

A cycle is deﬁned as a page access. After this number of cycles,

the bit error rate may start to increase above the BER limit. Sys-

tem level ECC is recommended.

10

Cycle Endurance

Data Retention

1 x10

The data retention time starts from the last read or write cycle

and does not diﬀer between powered up and powered down

conditions.

T_OPER= 70°C,

3 months

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COMMAND DESCRIPTIONS

The 256Mb STT-MRAM is fully compatible with the command descriptions of JESD79-3F, section 4, with the

following additional considerations:

1. Timing for Active, Precharge, Read, and Write commands are as described in JESD79-3F, with some

exceptions due to the timing diﬀerences between DRAM and MRAM. These exceptions are noted in the

description sections for each command.

2. To ensure the non-volatility of any data stored in the MRAM, it is necessary to close any open page by

issuing a PRECHARGE command to any open banks or all banks (PRE or PREA). The PRECHARGE must be

t

completed and RP met with V_DDwithin the speciﬁed operating range.

ACTIVE Command

Before any READ or WRITE commands can be issued to a bank within the MRAM, a row in that bank must be

opened (activated). This is accomplished via the ACTIVE command, which selects both the bank and the row

to be activated.

After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row,

t

subject to the RCD speciﬁcation. However, if the additive latency is programmed correctly, a READ or WRITE

t

command may be issued prior to RCD (MIN). In this operation, the MRAM enables a READ or WRITE com-

t

mand to be issued after the ACTIVE command for that bank, but prior to RCD (MIN) with the requirement

t

that (ACTIVE-to-READ/WRITE) + AL ≥ RCD (MIN) (see Posted CAS Additive Latency). RCD (MIN) should be

divided by the clock period and rounded up to the next whole number to determine the earliest clock edge

after the ACTIVE command on which a READ or WRITE command can be entered. The same procedure is

used to convert other speciﬁcation limits from time units to clock cycles.

When at least one bank is open, any READ-to-READ command delay or WRITE-to-WRITE command delay is

t

restricted to CCD (MIN).

A subsequent ACTIVE command to a diﬀerent row in the same bank can only be issued after the previous ac-

tive row has been closed (precharged). The minimum time interval between successive ACTIVE commands

t

to the same bank is deﬁned by RC. A subsequent ACTIVE command to another bank can be issued while

the ﬁrst bank is being accessed, which results in a reduction of total row-access overhead. The minimum

t

time interval between successive ACTIVE commands to diﬀerent banks is deﬁned by RRD. No more than

t

four bank ACTIVE commands may be issued in a given FAW (MIN) period, and the RRD (MIN) restriction still

t

applies. The FAW (MIN) parameter applies, regardless of the number of banks already opened or closed.

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t

Figure 4 – ACTIVE Command Example: Meeting RRD (MIN) and RCD (MIN)

T12

T13

T14

TT6467

T6478

T49

T68

T50

69

f

t

1. In this example, CK=533MHz, 1066 MT/sec/pin, CL - RCD - RP = 8- 47-36, a READ or WRITE command may be issued 47 nCK

(clock cycles) after the Bank is Activated.

t

2. The minimum time interval between successive ACTIVE commands to diﬀerent banks is deﬁned by RRD.

3. After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row, subject to the RCD

t

speciﬁcation.

PRECHARGE Command

Input A10 determines whether one bank or all banks are to be precharged and, in the case where only one

bank is to be precharged, inputs BA[2:0] select the bank.

When all banks are to be precharged, inputs BA[2:0] are treated as “Don’t Care.”After a bank is precharged, it

is in the idle state and must be activated prior to any READ or WRITE commands being issued.

Figure 5 – PRECHARGE Command Timing

T31

T19

T32

T20

T33

T21

t

PRCD (to next RD or WR), RPRAS (to next PRE)

Notes:

1. In this example, CK = 533MHz, 1066 MT/sec/pin, AL=0, CL=8 with BC4 selected.

2. The minimum READ command to PRECHARGE command spacing to the same bank is equal to AL+ RTP, with RTP being the

internal READ to PRECHARGE delay, 5 nCK (clock cycles).

f

t

3. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until RP is met. This is 36

nCK (clock cycles) from the PRECHARGE command.

t

4.

RAS min and RC min must be satisﬁed from the previous ACTIVE command.

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READ Command

READ bursts are initiated with a READ command. The starting column and bank addresses are provided

with the READ command and auto precharge is either enabled or disabled for that burst access. If auto

precharge is enabled, the row being accessed is automatically precharged at the completion of the burst. If

auto precharge is disabled, the row will be left open after the completion of the burst.

During READ bursts, the valid data-out element from the starting column address is available READ latency

(RL) clocks later. RL is deﬁned as the sum of posted CAS additive latency (AL) and CAS latency (CL) (RL = AL +

CL). The value of AL and CL is programmable in the mode register via the MRS command. Each subsequent

data-out element is valid nominally at the next positive or negative clock edge (that is, at the next crossing

of CK and CK.) Figure 6 below illustrates an example of RL based on a CL setting of 8 and an AL setting of 0.

Figure 6 – READ Command Timing

T10

T11

T12

Tꢀ

T8

Tꢁ

Notes:

1. Read Latency (RL) is deﬁned as the sum of POSTED CAS ADDITIVE latency (AL) and CAS latency (CL), (RL = AL + CL). -The value

f

of AL and CL is programmable in the mode register via the MRS command. In this example, CK = 533MHz, 1066 speed bin,

CL=8, AL=0.

2. DO n=data-out from column n. Subsequent elements of data-out appear in the programmed order following DO n. -The

burst length is selected by MR0 and A12 during the READ command.

3. Bank “a”was previously opened with an ACTIVE Command.

DQS, DQS is driven by the MRAM along with the output data. The initial LOW state on DQS and HIGH state

t

on DQS is known as the READ preamble ( RPRE). The LOW state on DQS and the HIGH state on DQS, coinci-

t

dent with the last data-out element, is known as the READ postamble ( RPST). Upon completion of a burst,

t

assuming no other commands have been initiated, the DQ goes High-Z. A detailed explanation of DQSQ

t

(valid data-out skew), QH (data-out window hold), and the valid data window are depicted in Section

t

4.13.2.1 of JESD79-3F. A detailed explanation of DQSCK (DQS transition skew to CK) is depicted in the same

section.

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Data from any READ burst may be concatenated with data from a subsequent READ command to provide a

continuous ﬂow of data. The ﬁrst data element from the new burst follows the last element of a completed

t

burst. The new READ command should be issued CCD cycles after the ﬁrst READ command. This is shown

t

for BL8 in Standard JESD79-3F Figure 33. If BC4 is enabled, CCD must still be met, which will cause a gap in

the data output, as shown in JESD79-3F Figure 34. The DDR3 MRAM does not allow interrupting or truncat-

ing any READ burst. Data from any READ burst must be completed before a subsequent WRITE burst is al-

lowed. An example of a READ burst followed by a WRITE burst for BL8 can be found in JESD79-3F Figure 35,

READ (BL8) to WRITE (BL8). READ to WRITE timing for BC4 can be found in JESD79-3F Figure 36, READ (BC4) to

WRITE (BC4) OTF. To ensure the READ data is completed before the WRITE data is on the bus, the minimum

t

READ-to-WRITE timing is RL + CCD - WL + 2 CK.

For additional information on the READ command, please refer to JESD79-3F Section 4.13. Please note that

t

in READ followed by a PRECHARGE, the MRAM RP needs to be observed for a given CL.

WRITE Command

WRITE bursts are initiated with a WRITE command. The starting column and bank addresses are provided

with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto-pre-

charge is selected, the row being accessed is precharged at the end of the WRITE burst. If auto-precharge is

not selected, the row will remain open for subsequent accesses. After a WRITE command has been issued,

the WRITE burst may not be interrupted.

During WRITE bursts, the ﬁrst valid data-in element is registered on the ﬁrst rising edge of DQS immediately

following the WRITE latency (WL) clock time. Data elements will continue to be registered on successive

edges of DQS.

WRITE latency (WL) is deﬁned as the sum of posted CAS additive latency (AL) and CAS WRITE latency (CWL):

WL = AL + CWL. The values of AL and CWL are programmed in the MR0 and MR2 registers respectively.

Only AL=0 is supported. Prior to the ﬁrst valid DQS edge, a full cycle is needed (including a dummy cross-

over of DQS, DQS) and speciﬁed as the WRITE preamble shown in “Figure 7 – WRITE Burst Operation WL =

5 (AL = 0 CWL = 5, BL8)”on page 29. The half cycle on DQS following the last data-in element is known as

the WRITE postamble.

t

The time between the WRITE command and the ﬁrst valid edge of DQS is WL clocks DQSS. Standard

t

JESD79-3F Figure 43 includes DQSS (MIN), DQSS (NOM) and DQSS (MAX) cases.

Data may be masked from completing a WRITE using data mask. The data mask occurs on the DM ball

aligned to the WRITE data. If DM is LOW, the WRITE completes normally. If DM is HIGH, that bit of data is

masked.

Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain High-Z,

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and any additional input data will be ignored.

Data for any WRITE burst may be concatenated with a subsequent WRITE command to provide a continuous

t

ﬂow of input data. The new WRITE command can be CCD clocks following the previous WRITE command.

The ﬁrst data element from the new burst is applied after the last element of a completed burst. Standard

JESD79-3F Figure 51, WRITE(BL8) to WRITE(BL8) and Figure 52, WRITE (BC4) to WRITE (BC4) OTF illustrate con-

catenated bursts.

t

Data for any WRITE burst may be followed by a subsequent READ command after WTR has been met (see

Standard JESD79-3F Figure 53, WRITE (BL8) to READ (BC4/BL8) OTF. ) Additional WRITE burst diagrams are

given in Section 4.14, WRITE Operation.

t

Data for any WRITE burst may be followed by a subsequent PRECHARGE command, providing WR has

been met, as shown in Standard JESD79-3F Figures 49 and 50. Please note that in Write followed by a PRE-

t

CHARGE, the MRAM RP needs to be observed for a given CL.

t

Both WTR and WR starting time may vary, depending on the mode register settings (ﬁxed BC4, BL8 versus

OTF).

Figure 7 – WRITE Burst Operation WL = 5 (AL = 0 CWL = 5, BL8)

Notes:

1. BL8, WL= 5; AL=0, CWL=5

2. D_INn = data-in from column n.

3. NOP commands are shown for ease of illustration; other commands may be valid at these times.

4. BL8 setting activated by either MR0 [A1:0= 00] or MR0 [ A1:0 = 01] and A12 = 1 during WRITE command at T0

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Burst Length, Type and Order

Accesses within a given burst may be programmed only in a sequential order which is selected via bit A3

of Mode Register MR0=0. The ordering of accesses within a burst is determined by the burst length and the

starting column address as shown in Table 14 below. The burst length is deﬁned by bits A1:A0 of Mode Reg-

ister MR0. Burst length options include ﬁxed BC4, ﬁxed BL8, and “on the ﬂy”which allows BC4 or BL8 to be

selected coincident with the registration of a Read or Write command via A12/BC_n.

Table 14 – Burst Length, Type and Order

Burst

Length

READ/

WRITE

Starting Column Address

A[2,1,0]

Burst Type = Sequencial

(Decimal)

000

100

0, 1, 2, 3, T, T, T, T

4, 5, 6, 7, T, T, T, T

0, 1, 2, 3, X, X, X, X

4, 5, 6, 7, X, X, X, X

0, 1, 2, 3, 4, 5, 6, 7

4, 5, 6, 7, 0, 1, 2, 3

0, 1, 2, 3, 4, 5, 6, 7

READ

BC4

BL8

0, V, V

1, V, V

000

WRITE

READ

100

WRITE

V, V, V

Burst Type/Burst Order supports only the sequential burst type for CA<2:0 = 000 or 100

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PART NUMBER DECODER

Table 15 – 256Mb x8 / x16 STT-MRAM Ordering Part Number Decoder

Note 1

Note 2

Device Version

Deﬁnition

First Version

Device Class

Deﬁnition

A

B

S1

Storage DEC

Second Version

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ORDERING PART NUMBERS

Table 16 – Ordering Part Numbers

Shipping

Container

Speed

Bin

Org

Temp Package

Part Number

Trays

EMD3D256M08G1-150CBS1

EMD3D256M08G1-150CBS1R

EMD3D256M16G2-150CBS1

EMD3D256M16G2-150CBS1R

10x13mm

78-ball

BGA

32Mb x 8 0 - 85°C

16Mb x 16 0 - 85°C

1333

Tape and

Reel

Trays

10x13mm

96-ball

BGA

1333

Tape and

Reel

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PACKAGE OUTLINE DRAWING

Figure 8 – 78-Ball BGA Package Outline (x8)

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Figure 9 – 78-Ball BGA Package Outline (x8) Dimensions

12.90

13.10

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Figure 10 – 96-Ball BGA Package Outline (x16)

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Figure 11 – 96-Ball BGA Package Outline (x16) Dimensions

12.90

13.10

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Table 17 – Revision History

Revision

Date

Description of Change

1.0

February 7, 2018

Published data sheet

1.1

1.2

1.3

March 6, 2018

March 16, 2018

October 15, 2018

Updated Table 15 and 16 to remove “T”OPN designation from tray parts

Updated OPN table to change T designation for tray to blank.

Added Figure 3 and included additional details for x16 device

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Everspin Technologies, Inc.

HOW TO CONTACT US

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able attorney fees arising out of, directly or indirectly, any claim

of personal injury or death associated with such unintended or

unauthorized use, even if such claim alleges that Everspin Tech-

nologies was negligent regarding the design or manufacture of

the part. Everspin™ and the Everspin logo are trademarks of Ever-

spin Technologies, Inc. All other product or service names are the

property of their respective owners.

Home Page:

www.everspin.com

World Wide Information Request

WW Headquarters - Chandler, AZ

5670 W. Chandler Blvd., Suite 100

Chandler, Arizona 85224

Tel: +1-877-480-MRAM (6726)

Local Tel: +1-480-347-1111

Fax: +1-480-347-1175

support@everspin.com

Europe, Middle East and Africa

Everspin Europe Support

support.europe@everspin.com

Japan

Everspin Japan Support

support.japan@everspin.com

Asia Paciﬁc

Everspin Asia Support

support.asia@everspin.com

EMD3D256M08BS1/16BS1 Revision 1.3 10/2018

38


型号：	EMD3D256M16G2-150CBS1
厂家：	Everspin Technologies
描述：	256Mb ST-DDR3 Spin-transfer Torque MRAM 双倍数据速率
文件：	总38页 (文件大小：2405K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EMD3D256M16G2-150CBS1 [EVERSPIN]

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