MR0A08BCSO35R_技术文档

MR0A08B

128K x 8 MRAM

FEATURES

• 3.3 Volt power supply

• Fast 35 ns read/write cycle

• SRAM compatible timing

• Native non-volatility

• Unlimited read & write endurance

• Data always non-volatile for >20 years at temperature

• Commercial and industrial temperatures

• All products meet MSL-3 moisture sensitivity level

• RoHS-Compliant TSOP2 and BGA packages

48-ball FBGA

44-pin TSOP2

BENEFITS

• One memory replaces FLASH, SRAM, EEPROM and

MRAM in system for simpler, more eﬃcient design

• Improves reliability by replacing battery-backed

SRAM

INTRODUCTION

The MR0A08B is a 1,048,576-bit magnetoresistive random access

memory (MRAM) device organized as 131,072 words of 8 bits. The

MR0A08B oﬀers SRAM compatible 35 ns read/write timing with unlim-

ited endurance.

RoHS

Data is always non-volatile for greater than 20-years. Data is automatically protected on

power loss by low-voltage inhibit circuitry to prevent writes with voltage out of speciﬁcation.

The MR0A08B is the ideal memory solution for applications that must permanently store and

retrieve critical data and programs quickly.

The MR0A08B is available in small footprint 400-mil, 44-lead plastic small-outline TSOP

type-2 package, 8 mm x 8 mm, or a 48-pin ball grid array (BGA) package with 0.75 mm ball

centers. (The 32-SOIC package options is obsolete and no longer available for new orders.)

These packages are compatible with similar low-power SRAM products and other non-vola-

tile RAM products.

The MR0A08B provides highly reliable data storage over a wide range of temperatures. The

product is oﬀered with commercial temperature range (0 to +70 °C) and industrial tempera-

ture range (-40 to +85 °C).

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MR0A08B Rev. 8.6, 3/2018

MR0A08B

TABLE OF CONTENTS

FEATURES .............................................................................................................................................1

BENEFITS...............................................................................................................................................1

INTRODUCTION ...................................................................................................................................1

BLOCK DIAGRAM AND PIN ASSIGNMENTS.......................................................................................4

Figure 1 – MR0A08B Block Diagram ...................................................................................................................... 4

Table 1 – Pin Functions............................................................................................................................................... 4

1 ...................................................................... 5

Figure 2 – Pin Diagrams for Available Packages (Top View)

OPERATING MODES.............................................................................................................................5

Table 2 – Operating Modes....................................................................................................................................... 5

ELECTRICAL SPECIFICATIONS ............................................................................................................6

Table 3 – Absolute Maximum Ratings................................................................................................................... 6

OPERATING CONDITIONS ...................................................................................................................7

Table 4 – Operating Conditions............................................................................................................................... 7

Power Up and Power Down Sequencing .......................................................................................8

Figure 3 – Power Up and Power Down Diagram............................................................................................... 8

DC CHARACTERISTICS.........................................................................................................................9

Table 5 – DC Characteristics...................................................................................................................................... 9

Table 6 – Power Supply Characteristics................................................................................................................ 9

TIMING SPECIFICATIONS ................................................................................................................. 10

Table 7 – Capacitance ...............................................................................................................................................10

Table 8 – AC Measurement Conditions ..............................................................................................................10

Figure 4 – Output Load Test Low and High.......................................................................................................10

Figure 5 – Output Load Test All Others...............................................................................................................10

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MR0A08B Rev. 8.6, 3/2018

MR0A08B

TABLE OF CONTENTS (CONT’D)

Read Mode .................................................................................................................................... 11

Table 9 – Read Cycle Timing ...................................................................................................................................11

Figure 6 – Read Cycle 1.............................................................................................................................................12

Figure 7 – Read Cycle 2.............................................................................................................................................12

Write Mode.................................................................................................................................... 13

Table 10 – Write Cycle Timing 1 ( W Controlled ).............................................................................................13

Figure 8 – Write Cycle Timing 1 (W Controlled) ...............................................................................................14

Table 11 – Write Cycle Timing 2 (E Controlled)................................................................................................15

Figure 9 – Write Cycle Timing 2 (E Controlled) ................................................................................................16

Table 12 – Write Cycle Timing 3 (Shortened t

, W and E Controlled).............................................17

, W and E Controlled)...........................................17

WHAX

Figure 10 – Write Cycle Timing 3 (Shortened t

WHAX

ORDERING INFORMATION ............................................................................................................... 18

Table 13 – Ordering Part Number System for Parallel I/O MRAM..............................................................18

1...............................................................................................18

Table 14 – MR0A08B Ordering Part Numbers

PACKAGE OUTLINE DRAWINGS....................................................................................................... 19

Figure 11 – 44-TSOP2 Package Outline...............................................................................................................19

Figure 12 – 48-BGA Package Outline...................................................................................................................20

1 ..............................................................................................................21

Figure 13 – 32-SOIC Package Outline

REVISION HISTORY ........................................................................................................................... 22

HOW TO CONTACT US....................................................................................................................... 23

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MR0A08B Rev. 8.6, 3/2018

MR0A08B

BLOCK DIAGRAM AND PIN ASSIGNMENTS

Figure 1 – MR0A08B Block Diagram

OUTPUT

ENABLE

BUFFER

G

OUTPUT ENABLE

7

A[16:0] ADDRESS

ROW

DECODER

10

BUFFER

COLUMN

DECODER

17

CHIP

ENABLE

BUFFER

E

8

OUTPUT

BUFFER

8

SENSE

AMPS

128k x 8

BIT

MEMORY

ARRAY

WRITE

ENABLE

BUFFER

W

FINAL

WRITE

DRIVERS

8

WRITE

DRIVER

8

DQ[7:0]

WRITE ENABLE

Table 1 – Pin Functions

Signal Name Function

A

E

Address Input

Chip Enable

Write Enable

Output Enable

Data I/O

W

G

DQ

V

Power Supply

Ground

DD

V

SS

DC

NC

Do Not Connect

No Connection - Pin 2, 40, 41,43 (TSOP2); Ball C2, C5, D3, F2, F5, G1, G2, G6, H1, H6

(BGA); Pin 30 (SOIC) Reserved For Future Expansion

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MR0A08B Rev. 8.6, 3/2018

MR0A08B

1

Figure 2 – Pin Diagrams for Available Packages ꢀTop Viewꢁ

DC

NC

Aꢀ

Aꢁ

1

2

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

DC

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

V

DD

DC

NC

DC

NC

Aꢁꢉ

A

2

A

15

16

14

12

1

2

3

4

5

6

3

NC

W

A

3

4

A₀

A₁

A₂

A

B

C

D

E

DC

G

DC

5

Aꢂ

4

6

Aꢃ

Aꢇ

E

A₃

A₅

A₄

A₆

A

5

A

NC

DQ₀

V_SS

DC

E

DC

DQ₄

V_DD

V_SS

7

6

5

4

3

2

1

0

1

2

13

7

Aꢁꢈ

8

A

6

A

8

G

DQ7

DQ6

NC

DQ₁

DQ₂

NC

DQ₅

DQ₆

9

DQ0

A

7

A

9

10

11

12

13

14

15

16

17

18

19

20

21

22

DQ1

8

A₇

11

NC

DC

A₁₄

A₁₂

VDD

V

SS

V

SS

G

A

V

DD

A

9

V_DD

DQ₃

A₁₆

A₁₅

A₁₃

A₁₀

DQ2

DQ3

W

DQ5

DQ4

DC

A

10

11

12

13

14

15

16

10

A

E

F

DQ₇

NC

A₈

NC

W

Aꢁꢇ

Aꢁꢃ

Aꢈ

Aꢉ

Aꢄ

Aꢅ

Aꢆ

DC

A

DQ

7

6

5

4

3

G

H

NC

DQ

V

Aꢁꢂ

Aꢁꢁ

Aꢁꢀ

A₉

A₁₁

DC

SS

1

44 Pin TSOP2

32 Pin SOIC

48 Pin FBGA

Note:

1. The 32-SOIC package is obsolete and shown for legacy reference only. This package option is no longer

available for new orders.

OPERATING MODES

Table 2 – Operating Modes

1

2

E

G

W

Mode

Not selected

Output disabled

Byte Read

V_DDCurrent

DQ[7:0]

Hi-Z

H

X

I

, I

SB1 SB2

L

H

L

H

L

I

Hi-Z

DDR

I

D

DDR

Out

X

Byte Write

I

D

DDW

in

Notes:

1. H = high, L = low, X = don’t care

2. Hi-Z = high impedance

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MR0A08B Rev. 8.6, 3/2018

MR0A08B

ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

This device contains circuitry to protect the inputs against damage caused by high static voltages or electric

ﬁelds; however, it is advised that normal precautions be taken to avoid application of any voltage greater

than maximum rated voltages to these high-impedance (Hi-Z) circuits.

The device also contains protection against external magnetic ﬁelds. Precautions should be taken o avoid

application of any magnetic ﬁeld more intense than the maximum ﬁeld intensity speciﬁed in the maximum

1

ratings.

Table 3 – Absolute Maximum Ratings

Parameter

Symbol

Value

Unit

2,3

Supply voltage

V

-0.5 to 4.0

V

DD

2,3

Voltage on any pin

V

-0.5 to V + 0.5

V

mA

W

IN

DD

Output current per pin

I

20

OUT

3

Package power dissipation

Temperature under bias

P

0.600

D

MR0A08B (Commercial)

MR0A08BC (Industrial)

-10 to 85

-45 to 95

T

°C

BIAS

Storage Temperature

T

-55 to 150

260

°C

stg

Lead temperature during solder (3 minute max)

T

Lead

Maximum magnetic ﬁeld during write

MR0A08B (All Temperatures)

H

2000

A/m

max_write

Maximum magnetic ﬁeld during read or standby

H

8000

A/m

max_read

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional opera-

tion should be restricted to recommended operating conditions. Exposure to excessive voltages or

magnetic ﬁelds could aﬀect device reliability.

2. All voltages are referenced to V .

SS

3. Power dissipation capability depends on package characteristics and use environment.

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MR0A08B Rev. 8.6, 3/2018

MR0A08B

OPERATING CONDITIONS

Table 4 – Operating Conditions

Parameter

Symbol

Min

Typical

Max

Unit

1

V

Power supply voltage

3.0

3.3

3.6

V

DD

1

V

Write inhibit voltage

Input high voltage

2.5

2.2

2.7

3.0

V

WI

2

V

-

V

+ 0.3

DD

IH

3

Input low voltage

V

-0.5

0.8

IL

Temperature under bias

MR0A08B (Commercial)

MR0A08BC (Industrial)

T

0

70

85

°C

A

-40

Notes:

1. There is a 2 ms startup time once V exceeds V (max). See “Figure 3 – Power Up and Power Down

DD

DD,

Diagram” .

2. V (max) = V + 0.3 V ; V (max) = V + 2.0 V (pulse width ≤ 10 ns) for I ≤ 20.0 mA.

IH

DD

DC

IH

DD

AC

3. V (min) = -0.5 V ; V (min) = -2.0 V (pulse width ≤ 10 ns) for I ≤ 20.0 mA.

IL

DC IL

AC

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MR0A08B Rev. 8.6, 3/2018

MR0A08B

Power Up and Power Down Sequencing

The MRAM is protected from write operations whenever V is less than V . As soon as V exceeds

DD

WI

DD

V

(min), there is a startup time of 2 ms before read or write operations can start. This time allows memory

DD

power supplies to stabilize.

The E and W control signals should track V on power up to V - 0.2 V or V (whichever is lower) and

DD

IH

remain high for the startup time. In most systems, this means that these signals should be pulled up with a

resistor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and

W should hold the signals high with a power-on reset signal for longer than the startup time.

During power loss or brownout where V goes below V , writes are protected and a startup time must be

DD

WI

observed when power returns above V (min).

DD

Figure 3 – Power Up and Power Down Diagram

VDD

V

WI

BROWNOUT or POWER LOSS

2 ms

STARTUP

RECOVER

NORMAL

OPERATION

NORMAL

OPERATION

READ/WRITE

INHIBITED

READ/WRITE

INHIBITED

VIH

E

W

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MR0A08B Rev. 8.6, 3/2018

MR0A08B

DC CHARACTERISTICS

Table 5 – DC Characteristics

Parameter

Symbol

Min

Typical

Max

Unit

Input leakage current

-

1

μA

I

lkg(I)

Output leakage current

Output low voltage

-

1

μA

V

I

lkg(O)

(I = +4 mA)

0.4

OL

V

OL

(I = +100 μA)

V

+ 0.2

OL

SS

Output high voltage

(I = -4 mA)

V

2.4

-

V

OL

OH

(I = -100 μA)

V

- 0.2

OL

DD

Table 6 – Power Supply Characteristics

Parameter

Symbol

Typical

Max

Unit

1

AC active supply current - read modes

(I = 0 mA, V = max)

25

30

mA

I

DDR

OUT

DD

1

AC active supply current - write modes

(V = max)

DD

MR0A08B (Commercial)

MR0A08BC (Industrial)

55

65

70

mA

I

DDW

AC standby current

(V = max, E = V )

6

7

I

DD

IH

SB1

no other restrictions on other inputs

CMOS standby current

( E ≥ V - 0.2 V and V ≤ V + 0.2 V or ≥ V - 0.2 V )

5

6

mA

I

DD

In

SS

DD

SB2

( V = max, f = 0 MHz )

DD

Notes:

1. All active current measurements are measured with one address transition per cycle and at minimum cycle time.

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MR0A08B Rev. 8.6, 3/2018

MR0A08B

TIMING SPECIFICATIONS

Table 7 – Capacitance

1

Parameter

Symbol

Typical

Max

Unit

C

Address input capacitance

Control input capacitance

-

6

pF

In

C

-

6

8

pF

In

C

Input/Output capacitance

I/O

Notes:

1. f = 1.0 MHz, dV = 3.0 V, T = 25 °C, periodically sampled rather than 100% tested.

A

Table 8 – AC Measurement Conditions

Parameter

Value

1.5

Unit

Logic input timing measurement reference level

Logic output timing measurement reference level

Logic input pulse levels

V

1.5

0 or 3.0

2

V

Input rise/fall time

ns

Output load for low and high impedance parameters

Output load for all other timing parameters

See Figure 4

See Figure 5

Figure 4 – Output Load Test Low and High

Z_D= 50 Ω

Output

R_L= 50 Ω

V_L= 1.5 V

Figure 5 – Output Load Test All Others

3.3 V

590 Ω

Output

5 pF

435 Ω

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MR0A08B Rev. 8.6, 3/2018

MR0A08B

Read Mode

Table 9 – Read Cycle Timing

1

Parameter

Symbol

Min

Max

Unit

t

Read cycle time

AVAV

35

-

ns

t

Address access time

AVQV

-

35

15

-

ns

2

t

Enable access time

ELQV

t

Output enable access time

Output hold from address change

GLQV

-

t

AXQX

3

0

3

t

Enable low to output active

ELQX

-

3

t

Output enable low to output active

GLQX

-

3

t

Enable high to output Hi-Z

EHQZ

15

10

3

t

Output enable high to output Hi-Z

GHQZ

Notes:

1. W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be

minimized or eliminated during read or write cycles.

2. Addresses valid before or at the same time E goes low.

3. This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage.

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MR0A08B Rev. 8.6, 3/2018

MR0A08B

Figure 6 – Read Cycle 1

t_AVAV

A (ADDRESS)

Q (DATA OUT)

t_AXQX

Previous Data Valid

Data Valid

t_AVQV

Note: Device is continuously selected (E≤V_IL, G≤V_IL).

Figure 7 – Read Cycle 2

t_AVAV

A (ADDRESS)

t_AVQV

t_ELQV

E (CHIP ENABLE)

t_EHQZ

t_ELQX

G (OUTPUT ENABLE)

Q (DATA OUT)

t_GHQZ

t_GLQV

t_GLQX

Data Valid

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MR0A08B Rev. 8.6, 3/2018

MR0A08B

Write Mode

Table 10 – Write Cycle Timing 1 ꢀ W Controlled ꢁ

1

Parameter

Symbol

Min

Max

Unit

2

t

Write cycle time

AVAV

35

-

ns

t

Address set-up time

AVWL

0

ns

t

Address valid to end of write (G high)

Address valid to end of write (G low)

AVWH

18

20

t

AVWH

-

t

WLWH

WLEH

Write pulse width (G high)

Write pulse width (G low)

15

ns

t

WLWH

WLEH

-

t

Data valid to end of write

Data hold time

DVWH

10

0

-

ns

t

WHDX

3

t

Write low to data Hi-Z

WLQZ

0

12

-

3

t

Write high to output active

WHQX

3

t

Write recovery time

Notes:

12

-

ns

WHAX

1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus

contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after

W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain

in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being as-

serted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.

2. All write cycle timings are referenced from the last valid address to the ﬁrst transition address.

3. This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. At any given

voltage or temperate, t

(max) < t

(min)

WLQZ

WHQX

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MR0A08B Rev. 8.6, 3/2018

MR0A08B

Figure 8 – Write Cycle Timing 1 ꢀW Controlledꢁ

t_AVAV

A (ADDRESS)

t_AVWH

t_WHAX

E (CHIP ENABLE)

t_WLEH

t_WLWH

W (WRITE ENABLE)

t_AVWL

t_DVWH

DATA VALID

t_WHDX

D (DATA IN)

t_WLQZ

Hi -Z

Q (DATA OUT)

t_WHQX

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MR0A08B Rev. 8.6, 3/2018

MR0A08B

Table 11 – Write Cycle Timing 2 ꢀE Controlledꢁ

1

Parameter

Symbol

Min

35

0

Max

Unit

ns

2

t

Write cycle time

AVAV

-

t

Address set-up time

AVEL

ns

t

AVEH

18

ns

Address valid to end of write (G high)

Address valid to end of write (G low)

t

AVEH

20

15

-

ns

t

ELEH

Enable to end of write (G high)

t

ELWH

t

ELEH

3

15

-

ns

Enable to end of write (G low)

t

ELWH

t

Data valid to end of write

Data hold time

DVEH

10

0

-

ns

t

EHDX

t

Write recovery time

Notes:

EHAX

12

1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus

contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or

after W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must re-

main in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being

asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.

2. All write cycle timings are referenced from the last valid address to the ﬁrst transition address.

3. If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the

same time or before W goes high, the output will remain in a high-impedance state.

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MR0A08B Rev. 8.6, 3/2018

MR0A08B

Figure 9 – Write Cycle Timing 2 ꢀE Controlledꢁ

t_AVAV

A (ADDRESS)

E (CHIP ENABLE)

t_EHAX

t_AVEH

t_ELEH

t_ELWH

t_AVEL

W (WRITE ENABLE)

t_EHDX

t_DVEH

D (DATA IN)

Data Valid

Hi-Z

Q (DATA OUT)

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MR0A08B Rev. 8.6, 3/2018

MR0A08B

Table 12 – Write Cycle Timing 3 ꢀShortened t_WHAX, W and E Controlledꢁ

1

Parameter

Symbol

Min

Max

Unit

2

t

Write cycle time

AVAV

35

-

ns

t

Address set-up time

AVWL

0

-

ns

t

AVWH

18

20

Address valid to end of write (G high)

Address valid to end of write (G low)

t

AVWH

t

WLWH

WLEH

Write pulse width

15

-

ns

t

Data valid to end of write

Data hold time

DVWH

10

0

-

ns

t

WHDX

t

Enable recovery time

EHAX

-2

6

3

t

Write recovery time

WHAX

3

t

Write to enable recovery time

WHEL

12

Notes:

1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus

contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or

after W goes low, the output will remain in a high impedance state. After W, or E has been brought high, the signal must re-

main in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being

asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.

2. All write cycle timings are referenced from the last valid address to the ﬁrst transition address.

3. If E goes low at the same time or after W goes low the output will remain in a high impedance state. If E goes high at the

same time or before W goes high the output will remain in a high impedance state. E must be brought high each cycle.

Figure 10 – Write Cycle Timing 3 ꢀShortened t_WHAX, W and E Controlledꢁ

t_AVAV

A (ADDRESS)

t_WHAX

t_AVWH

t_EHAX

E (CHIP ENABLE)

t _WLEH

t_WLWH

t_WHEL

t_WHDX

W (WRITE ENABLE)

t _AVWL

t _DVWH

D (DATA IN)

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MR0A08B Rev. 8.6, 3/2018

MR0A08B

ORDERING INFORMATION

Table 13 – Ordering Part Number System for Parallel I/O MRAM

Memory Density Type I/O Width

MR 08

Rev.

B

Temp Package Speed Packing Grade

MA 35

Example Ordering Part Number

0

A

C

R

MRAM

256 Kb

1 Mb

MR

256

0

4 Mb

2

16 Mb

Async 3.3v

4

A

D

Async 3.3v Vdd and 1.8v Vddq

DL

Async 3.3v Vdd and 1.8v Vddq with 2.7v min. Vdd

8-bit

08

16-bit

Rev A

Rev B

16

A

B

Commercial

Industrial

Extended

0 to 70°C

-40 to 85°C

-40 to 105°C

Blank

C

V

AEC Q-100 Grade 1 -40 to 125°C

44-TSOP-2

M

YS

48-FBGA

16-SOIC

MA

SC

32-SOIC

35 ns

SO

35

45 ns

45

Tray

Blank

R

ES

Blank

Tape and Reel

Engineering Samples

Customer Samples

Mass Producꢀon

1

Table 14 – MR0A08B Ordering Part Numbers

Temp Grade

Temp

Package

Shipping

Tray

Ordering Part Number

MR0A08BYS35

44-TSOP2

Tape and Reel

Tray

MR0A08BYS35R

MR0A08BMA35

Commercial

48-BGA

0 to +70 °C

Tape and Reel

Tray

MR0A08BMA35R

MR0A08BSO35 Obsolete

MR0A08BSO35R Obsolete

MR0A08BCYS35

1

32-SOIC

Tape and Reel

Tray

44-TSOP2

48-BGA

Tape and Reel

Tray

MR0A08BCYS35R

MR0A08BCMA35

Industrial

-40 to +85 °C

Tape and Reel

Tray

MR0A08BCMA35R

MR0A08BCSO35 Obsolete

MR0A08BCSO35R Obsolete

1

32-SOIC

Tape and Reel

1

The 32-SOIC package option is obsolete and no longer available. See PCN02895 here.

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MR0A08B Rev. 8.6, 3/2018

MR0A08B

PACKAGE OUTLINE DRAWINGS

Figure 11 – 44-TSOP2 Package Outline

Not To Scale

1. Dimensions and tolerances per ASME Y14.5M - 1994.

2. Dimensions in Millimeters.

3. Dimensions do not include mold protrusion.

4. Dimension does not include DAM bar protrusions.

5. DAM Bar protrusion shall not cause the lead width to

exceed 0.58.

44

19

MR0A08B Rev. 8.6, 3/2018

MR0A08B

Figure 12 – 48-BGA Package Outline

TOP VIEW

0.41

0.31

0.32

0.22

SIDE VIEW

BOTTOM VIEW

Not To Scale

1. Dimensions in Millimeters.

2. Dimensions and tolerances per ASME Y14.5M - 1994.

3. Maximum solder ball diameter measured parallel to DATUM A

4. DATUM A, the seating plane is determined by the spherical crowns

of the solder balls.

5.

surface of package.

20

MR0A08B Rev. 8.6, 3/2018

MR0A08B

1

Figure 13 – 32-SOIC Package Outline

PIN 1 ID

32

17

J

Reference JEDEC MO-119

K

1

16

A

I

G

D

C

H

E

F

B

Unit

A

B

C

D

E

F

G

H

I

J

K

mm - Min 20.574 1.00

- Max 20.878 1.50

0.355 0.66

0.508 0.81

0.101 2.286 Radius 0.533 0.152 7.416 10.287

0.254 2.540 0.101 1.041 0.304 7.594 10.642

inch - Min 0.810 0.04

- Max 0.822 0.06

0.14

0.02

0.026 0.004 0.09

0.032 0.010 0.10

Radius 0.021 0.006 0.292 0.405

0.0040 0.041 0.012 0.299 0.419

Note:

1. The 32-SOIC package is obsolete and shown for legacy reference only. This package option is no longer

available for new orders.

21

MR0A08B Rev. 8.6, 3/2018

MR0A08B

REVISION HISTORY

Revi-

sion

Date

Description of Change

0

Sep 12, 2008

Initial Advance Information Release

Revised format; Add Table 3.6 Write Timing Cycle 3; Add Figure 3.6 Write

Timing Cycle 3; Add TSOPII Lead Width Info; Changed to Preliminary from

Product Concept.

1

May 8, 2009

Changed from datasheet from Preliminary to Production except where

noted.

2

3

4

June 18, 2009

Apr 12, 2011

Added SOIC package option.

Corrected SOIC Pin 1 to read DC. Updated contact information. Revised

copyright year.

August 15, 2011

Changed TSOP-II to TSOP2. Changed logo to new EST Logo. Added In-

dustrial Temp Grade option in SOIC package, Table 4.1. Deleted Tape &

Reel pack option for all SOIC packaged parts. Figure 2.1 cosmetic update.

Figure 5.2 BGA package outline drawing revised for ball size.

5

Dec 16, 2011

July 9, 2013

6

7

MR0A08BCSO35 preliminary status removed. Now MP.

September 4, 2013 Added table of dimenstions to the SOIC package outline diagram.

Added Tape and Reel shipping option for SOIC packged versions. Refor-

matted to current standards.

8

October 11, 2013

8.1

8.2

8.3

8.4

8.5

8.6

May 18, 2015

Revised How to Contact Us information.

June 11, 2015

July 20, 2015

Correction to Japan Sales Oﬃce telephone number.

32-SOIC package options Not Recommended for New Designs.

32-SOIC package options are obsolete and no longer available.

October 17, 2015

December 9, 2015

March 22, 2018

Corrections to incorrect package pinouts and replaced missing 48-BGA

package outline drawing.

Updated Contact Us table

22

MR0A08B Rev. 8.6, 3/2018

MR0A08B

HOW TO CONTACT US

Home Page:

Everspin Technologies, Inc.

www.everspin.com

Information in this document is provided solely to enable system and

software implementers to use Everspin Technologies products. There are

no express or implied licenses granted hereunder to design or fabricate any

integrated circuit or circuits based on the information in this document.

Everspin Technologies reserves the right to make changes without further

notice to any products herein. Everspin makes no warranty, representa-

tion or guarantee regarding the suitability of its products for any particular

purpose, nor does Everspin Technologies assume any liability arising out of

the application or use of any product or circuit, and speciﬁcally disclaims

any and all liability, including without limitation consequential or inci-

dental damages. “Typical”parameters, which may be provided in Everspin

Technologies data sheets and/or speciﬁcations can and do vary in diﬀer-

ent applications and actual performance may vary over time. All operating

parameters including “Typicals”must be validated for each customer ap-

plication by customer’s technical experts. Everspin Technologies does not

convey any license under its patent rights nor the rights of others. Everspin

Technologies products are not designed, intended, or authorized for use

as components in systems intended for surgical implant into the body, or

other applications intended to support or sustain life, or for any other ap-

plication in which the failure of the Everspin Technologies product could

create a situation where personal injury or death may occur. Should Buyer

purchase or use Everspin Technologies products for any such unintended

or unauthorized application, Buyer shall indemnify and hold Everspin Tech-

nologies and its oﬃcers, employees, subsidiaries, aﬃliates, and distributors

harmless against all claims, costs, damages, and expenses, and reasonable

attorney fees arising out of, directly or indirectly, any claim of personal

injury or death associated with such unintended or unauthorized use, even

if such claim alleges that Everspin Technologies was negligent regarding

the design or manufacture of the part. Everspin™ and the Everspin logo

are trademarks of Everspin Technologies, Inc. All other product or service

World Wide Information Request

WW Headquarters - Chandler, AZ

5670 W. Chandler Blvd., Suite 100

Chandler, Arizona 85224

Tel: +1-877-480-MRAM (6726)

Local Tel: +1-480-347-1111

Fax: +1-480-347-1175

support@everspin.com

Europe, Middle East and Africa

Everspin Europe Support

support.europe@everspin.com

Japan

Everspin Japan Support

support.japan@everspin.com

Asia Paciﬁc

Everspin Asia Support

support.asia@everspin.com

names are the property of their respective owners.

Filename:

EST00183_MR0A08B_Datasheet_Rev8.6032218

23

MR0A08B Rev. 8.6, 3/2018


型号：	MR0A08BCSO35R
厂家：	Everspin Technologies
描述：	128K x 8 MRAM 静态存储器光电二极管内存集成电路
文件：	总23页 (文件大小：1279K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MR0A08BCSO35R [EVERSPIN]

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