MR25H128ACDFR [EVERSPIN]
128Kb Serial SPI MRAM;型号: | MR25H128ACDFR |
厂家: | Everspin Technologies |
描述: | 128Kb Serial SPI MRAM |
文件: | 总20页 (文件大小:1544K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MR25H128A
128Kb Serial SPI MRAM
FEATURES
• No write delays
• Unlimited write endurance
• Data retention greater than 20 years
• Automatic data protection on power loss
• Block write protection
• Fast, simple SPI interface with up to 40 MHz clock rate
• 2.7 to 3.6 Volt power supply range
• Low current sleep mode
Small Flag DFN
• Industrial and Automotive temperatures
• Available in 8-pin DFN Small Flag RoHS-compliant package.
• Direct replacement for serial EEPROM, Flash, FeRAM
• Industrial Grade and AEC-Q100 Grade 1 and Grade 3 options
• Moisture Sensitivity MSL-3
INTRODUCTION
The MR25H128A is a 128Kbit magnetoresistive random access memory (MRAM) device orga-
nized as 16,384 words of 8 bits. The MR25H128A offers serial EEPROM and serial
Flash compatible read/write timing with no write delays and unlimited read/write
endurance.
RoHS
Unlike other serial memories, both reads and writes can occur randomly in memo-
ry with no delay between writes. The MR25H128A is the ideal memory solution for applications that must
store and retrieve data and programs quickly using a small number of I/O pins.
The MR25H128A is available in a 5 mm x 6 mm 8-pin DFN Small Flag package compatible with serial EE-
PROM, Flash, and FeRAM products.
The MR25H128A provides highly reliable data storage over a wide range of temperatures. The product is
offered with industrial (-40° to +85 °C) and AEC-Q100 Grade 1 (-40°C to +125 °C) and AEC-Q100 Grade 3
(-40° to +85 °C) operating temperature range options.
CONTENTS
1. DEVICE PIN ASSIGNMENT......................................................................... 3
2. SPI COMMUNICATIONS PROTOCOL...................................................... 4
3. ELECTRICAL SPECIFICATIONS................................................................. 10
4. TIMING SPECIFICATIONS.......................................................................... 14
5. ORDERING INFORMATION....................................................................... 17
6. MECHANICAL DRAWING.......................................................................... 18
7. REVISION HISTORY...................................................................................... 19
How to Reach Us.......................................................................................... 20
MR25H128A Rev. 1.2 3/2018
Copyright © 2018 Everspin Technologies, Inc.
1
MR25H128A
1. DEVICE PIN ASSIGNMENT
Overview
The MR25H128A is a serial MRAM with memory array logically organized as 16Kx8 using the four pin inter-
face of chip select (CS), serial input (SI), serial output (SO) and serial clock (SCK) of the serial peripheral inter-
face (SPI) bus. Serial MRAM implements a subset of commands common to today’s SPI EEPROM and Flash
components allowing MRAM to replace these components in the same socket and interoperate on a shared
SPI bus. Serial MRAM offers superior write speed, unlimited endurance, low standby & operating power, and
more reliable data retention compared to available serial memory alternatives.
Figure 1.1 Block Diagram
Instruction Decode
Clock Generator
Control Logic
WP
CS
HOLD
SCK
Write Protect
16KB
MRAM ARRAY
Instruction Register
14
8
Address Register
Counter
SO
Data I/O Register
SI
4
Nonvolatile Status
Register
System Configuration
Single or multiple devices can be connected to the bus as shown in Figure 1.2. Pins SCK, SO and SI are com-
mon among devices. Each device requires CS and HOLD pins to be driven separately.
Figure 1.2 System Configuration
SCK
MOSI
MISO
SO
SI
SCK
SO
SI
SCK
SPI
EVERSPIN SPI MRAM 1
EVERSPIN SPI MRAM 2
Micro Controller
CS
HOLD
CS
HOLD
CS1
HOLD1
CS2
HOLD2
MOSI = Master Out Slave In
MISO = Master In Slave Out
MR25H128A Rev. 1.2 3/2018
Copyright © 2018 Everspin Technologies, Inc.
2
MR25H128A
DEVICE PIN ASSIGNMENT
Figure 1.3 Pin Diagrams (Top View)
1
8
CS
V
DD
2
3
4
7
6
5
HOLD
SCK
SI
SO
WP
V
SS
8-Pin DFN Small Flag Package
Table 1.1 Pin Functions
Signal Name Pin I/O
Function
Chip Select
Description
CS
1
Input
An active low chip select for the serial MRAM. When chip select is high, the
memory is powered down to minimize standby power, inputs are ignored
and the serial output pin is Hi-Z. Multiple serial memories can share a com-
mon set of data pins by using a unique chip select for each memory.
SO
2
3
Output Serial Output
The data output pin is driven during a read operation and remains Hi-Z at
all other times. SO is Hi-Z when HOLD is low. Data transitions on the data
output occur on the falling edge of SCK.
WP
Input
Write Protect
A low on the write protect input prevents write operations to the Status
Register.
VSS
SI
4
5
Supply Ground
Power supply ground pin.
Input
Input
Serial Input
All data is input to the device through this pin. This pin is sampled on the
rising edge of SCK and ignored at other times. SI can be tied to SO to create
a single bidirectional data bus if desired.
SCK
6
Serial Clock
Synchronizes the operation of the MRAM. The clock can operate up to 40
MHz to shift commands, address, and data into the memory. Inputs are
captured on the rising edge of clock. Data outputs from the MRAM occur
on the falling edge of clock. The serial MRAM supports both SPI Mode 0
(CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). In Mode 0, the clock is
normally low. In Mode 3, the clock is normally high. Memory operation is
static so the clock can be stopped at any time.
HOLD
VDD
7
8
Input
Hold
A low on the Hold pin interrupts a memory operation for another task.
When HOLD is low, the current operation is suspended. The device will
ignore transitions on the CS and SCK when HOLD is low. All transitions of
HOLD must occur while CS is low.
Supply Power Supply
Power supply voltage from +2.7 to +3.6 volts.
MR25H128A Rev. 1.2 3/2018
Copyright © 2018 Everspin Technologies, Inc.
3
MR25H128A
2. SPI COMMUNICATIONS PROTOCOL
MR25H128A can be operated in either SPI Mode 0 (CPOL=0, CPHA =0) or SPI Mode 3 (CPOL=1, CPHA=1).
For both modes, inputs are captured on the rising edge of the clock and data outputs occur on the falling
edge of the clock. When not conveying data, SCK remains low for Mode 0; while in Mode 3, SCK is high. The
memory determines the mode of operation (Mode 0 or Mode 3) based upon the state of the SCK when CS
falls.
All memory transactions start when CS is brought low to the memory. The first byte is a command code. De-
pending upon the command, subsequent bytes of address are input. Data is either input or output. There
is only one command performed per CS active period. CS must go inactive before another command can
be accepted. To ensure proper part operation according to specifications, it is necessary to terminate each
access by raising CS at the end of a byte (a multiple of 8 clock cycles from CS dropping) to avoid partial or
aborted accesses.
Table 2.1 Command Codes
Instruction
WREN
WRDI
Description
Write Enable
Binary Code
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
1011 1001
1010 1011
Hex Code
06h
Address Bytes
Data Bytes
0
0
0
0
2
2
0
0
0
Write Disable
04h
0
RDSR
Read Status Register
Write Status Register
Read Data Bytes
Write Data Bytes
Enter Sleep Mode
Exit Sleep Mode
05h
1
WRSR
01h
1
1 to ∞
1 to ∞
0
READ
03h
WRITE
SLEEP
WAKE
02h
B9h
ABh
0
Status Register and Block Write Protection
The status register consists of the 8 bits listed in table 2.2. Status register bits BP0 and BP1 define the mem-
ory block arrays that are protected as described in table 2.3. The Status Register Write Disable bit (SRWD)
is used in conjunction with bit 1 (WEL) and the Write Protection pin (WP) as shown in table 2.4 to enable
writes to status register bits. The fast writing speed of MR25H128A does not require write status bits. The
state of bits 6,5,4, and 0 can be user modified and do not affect memory operation. All bits in the status
register are pre-set from the factory to the “0”state.
Table 2.2 Status Register Bit Assignments
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRWD
Don’t Care Don’t Care Don’t Care
BP1
BP0
WEL
Don’t Care
MR25H128A Rev. 1.2 3/2018
Copyright © 2018 Everspin Technologies, Inc.
4
MR25H128A
SPI COMMUNICATIONS PROTOCOL
Table 2.3 Block Memory Write Protection
Memory Contents
Status Register
BP1 BP0
Protected Area
None
Unprotected Area
All Memory
0
0
0
1
1
1
0
1
Upper Quarter
Upper Half
All
Lower Three-Quarters
Lower Half
None
Table 2.4 Memory Protection Modes
Status
Register
WEL
SRWD
WP
Protected Blocks
Unprotected Blocks
0
1
1
1
X
0
1
1
X
X
Low
High
Protected
Protected
Protected
Protected
Protected
Writable
Writable
Writable
Protected
Writable
Protected
Writable
When WEL is reset to 0, writes to all blocks and the status register are protected. When WEL is set to 1,
BP0 and BP1 determine which memory blocks are protected. While SRWD is reset to 0 and WEL is set to 1,
status register bits BP0 and BP1 can be modified. Once SRWD is set to 1, WP must be high to modify SRWD,
BP0 and BP1.
Read Status Register (RDSR)
The Read Status Register (RDSR) command allows the Status Register to be read. The Status Register can
be read at any time to check the status of write enable latch bit, status register write protect bit, and block
write protect bits. For MR25H128A, the write in progress bit (bit 0) is not written by the memory because
there is no write delay. The RDSR command is entered by driving CS low, sending the command code, and
then driving CS high.
Figure 2.1 RDSR
CS
Mode 3
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Mode 0
SCK
0
0
0
0
0
1
0
1
SI
MSB
Status Register Out
High Impedance
High Z
SO
7
6
5
4
3
2
1
0
MSB
MR25H128A Rev. 1.2 3/2018
Copyright © 2018 Everspin Technologies, Inc.
5
MR25H128A
SPI COMMUNICATIONS PROTOCOL
Write Enable (WREN)
The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit in the status register to 1. The
WEL bit must be set prior to writing in the status register or the memory. The WREN command is entered
by driving CS low, sending the command code, and then driving CS high.
Figure 2.2 WREN
CS
Mode 3
Mode 0
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCK
Instruction (06h)
0
0
0
0
0
1
1
0
SI
High Impedance
SO
Write Disable (WRDI)
The Write Disable (WRDI) command resets the WEL bit in the status register to 0. This prevents writes to
status register or memory. The WRDI command is entered by driving CS low, sending the command code,
and then driving CS high.
The WEL bit is reset to 0 on power-up or completion of WRDI.
Figure 2.3 WRDI
CS
Mode 3
Mode 0
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCK
Instruction (04h)
0
0
0
0
0
1
0
0
SI
High Impedance
SO
Write Status Register (WRSR)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. The
WRSR command is not executed unless the Write Enable Latch (WEL) has been set to 1 by executing a
WREN command while pin WP and bit SRWD correspond to values that make the status register writable
as seen in table 2.4. Status Register bits are non-volatile with the exception of the WEL which is reset to 0
upon power cycling.
MR25H128A Rev. 1.2 3/2018
Copyright © 2018 Everspin Technologies, Inc.
6
MR25H128A
SPI COMMUNICATIONS PROTOCOL
The WRSR command is entered by driving CS low, sending the command code and status register write
data byte, and then driving CS high.
Figure 2.4 WRSR
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Instruction (01h)
Status Register In
0
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
SI
MSB
High Impedance
SO
Read Data Bytes (READ)
The Read Data Bytes (READ) command allows data bytes to be read starting at an address specified by the
16-bit address. Only address bits 0-13 are decoded by the memory. The data bytes are read out sequen-
tially from memory until the read operation is terminated by bringing CS high The entire memory can be
read in a single command. The address counter will roll over to 0000h when the address reaches the top of
memory.
The READ command is entered by driving CS low and sending the command code. The memory drives the
read data bytes on the SO pin. Reads continue as long as the memory is clocked. The command is termi-
nated by bring CS high.
Figure 2.5 READ
CS
0
1
2
3
4
5
6
7
8
9
10
20
21
22
23
24
25
26
27
28
29
30
31
SCK
Instruction (03h)
16-Bit Address
13
3
X
X
0
0
0
0
0
0
1
1
2
1
0
SI
MSB
High Impedance
Data Out 1
Data Out 2
7
6
5
4
3
2
1
0
7
SO
X = Don’t Care
MSB
MR25H128A Rev. 1.2 3/2018
Copyright © 2018 Everspin Technologies, Inc.
7
MR25H128A
SPI COMMUNICATIONS PROTOCOL
Write Data Bytes (WRITE)
The Write Data Bytes (WRITE) command allows data bytes to be written starting at an address specified by
the 16-bit address. Only address bits 0-13 are decoded by the memory. The data bytes are written sequen-
tially in memory until the write operation is terminated by bringing CS high. The entire memory can be
written in a single command. The address counter will roll over to 0000h when the address reaches the top
of memory.
Unlike EEPROM or Flash Memory, MRAM can write data bytes continuously at its maximum rated clock
speed without write delays or data polling. Back to back WRITE commands to any random location in mem-
ory can be executed without write delay. MRAM is a random access memory rather than a page, sector, or
block organized memory making it ideal for both program and data storage.
The WRITE command is entered by driving CS low, sending the command code, and then sequential write
data bytes. Writes continue as long as the memory is clocked. The command is terminated by bringing CS
high.
Figure 2.6 WRITE
CS
20
21
22
23
24
25
26
27
28
29
30
31
0
1
2
3
4
5
6
7
8
9
10
SCK
Data Byte 1
Instruction (02h)
16-Bit Address
13
3
X
X
0
0
0
0
0
0
1
0
2
1
0
7
6
5
4
3
2
1
0
SI
MSB
High Impedance
MSB
SO
X = Don’t Care
CS
Mode 3
Mode 0
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
SCK
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SI
MSB
MSB
High Impedance
SO
MR25H128A Rev. 1.2 3/2018
Copyright © 2018 Everspin Technologies, Inc.
8
MR25H128A
SPI COMMUNICATIONS PROTOCOL
Enter Sleep Mode (SLEEP)
The Enter Sleep Mode (SLEEP) command turns off all MRAM power regulators in order to reduce the overall
chip standby power to 3 μA typical. The SLEEP command is entered by driving CS low, sending the com-
mand code, and then driving CS high. The standby current is achieved after time, tDP. If power is removed
when the part is in sleep mode, upon power restoration, the part enters normal standby. The only valid
command following SLEEP mode entry is a WAKE command.
Figure 2.7 SLEEP
CS
t DP
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCK
Instruction (B9h)
1
0
1
1
1
0
0
1
SI
Active Current
Standby Current
Sleep Mode Current
SO
Exit Sleep Mode (WAKE)
The Exit Sleep Mode (WAKE) command turns on internal MRAM power regulators to allow normal operation.
The WAKE command is entered by driving CS low, sending the command code, and then driving CS high.
The memory returns to standby mode after tRDP. The CS pin must remain high until the tRDP period is over.
Figure 2.8 WAKE
CS
t RDP
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCK
Instruction (ABh)
1
0
1
0
1
0
1
1
SI
Sleep Mode Current
Standby Current
SO
MR25H128A Rev. 1.2 3/2018
Copyright © 2018 Everspin Technologies, Inc.
9
MR25H128A
3. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
This device contains circuitry to protect the inputs against damage caused by high static voltages or
electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage
greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.
The device also contains protection against external magnetic fields. Precautions should be taken to avoid
application of any magnetic field more intense than the field intensity specified in the maximum ratings.
Table 3.1 Absolute Maximum Ratings 1
Symbol
Parameter
Supply voltage 2
Conditions
Value
Unit
VDD
All
-0.5 to 4.0
V
VIN
IOUT
PD
Voltage on any pin 2
All
All
All
-0.5 to VDD + 0.5
V
mA
W
Output current per pin
Package power dissipation 3
20
0.600
Industrial
-45 to 95
°C
TBIAS
Temperature under bias
AEC-Q100 Grade 3
AEC-Q100 Grade 1
All
-45 to 95
-45 to 135
-55 to 150
°C
°C
°C
Tstg
Storage Temperature
Lead temperature during solder (3
minute max)
TLead
All
260
°C
Hmax_write
Hmax_read
Maximum magnetic field (Write)
During Write
12,000
12,000
A/m
A/m
Maximum magnetic field (Read or During Read or
Standby) Standby
1
2
3
Permanent device damage may occur if absolute maximum ratings are exceeded. Functional opera-
tion should be restricted to recommended operating conditions. Exposure to excessive voltages or
magnetic fields could affect device reliability.
All voltages are referenced to VSS. The DC value of VIN must not exceed actual applied VDD by more
than 0.5V. The AC value of VIN must not exceed applied VDD by more than 2V for 10ns with IIN limited
to less than 20mA.
Power dissipation capability depends on package characteristics and use environment.
MR25H128A Rev. 1.2 3/2018
Copyright © 2018 Everspin Technologies, Inc.
10
MR25H128A
ELECTRICAL SPECIFICATIONS
Table 3.2 Operating Conditions
Symbol Parameter
Grade
Min
2.7
2.7
3.0
Typical
Max
3.6
Unit
Industrial
-
-
-
-
V
VDD
Power supply voltage
AEC-Q100 Grade 3
AEC-Q100 Grade1
3.6
3.6
V
V
VIH
VIL
VDD + 0.3
Input high voltage
Input low voltage
All
2.2
All
-0.5
-40
-40
-40
-
-
-
-
0.8
85
V
Industrial
°C
°C
°C
TA
Temperature under bias AEC-Q100 Grade 3
AEC-Q100 Grade 1 1
85
125
Note 1: AEC-Q100 Grade 1 temperature profile assumes 10 percent duty cycle at maximum temperature (2
years out of 20-year life.)
Table 3.3 DC Characteristics
Symbol Parameter
Conditions
Min
Typical
Max
Unit
ILI
Input leakage current
All
-
-
1
μA
ILO
Output leakage current All
-
-
-
-
-
-
1
μA
V
IOL = +4 mA
IOL = +100 μA
IOH = -4 mA
-
0.4
VOL
Output low voltage
Output high voltage
-
V
VSS + 0.2v
-
2.4
V
VOH
IOH = -100 μA
VDD - 0.2
-
V
Table 3.4 Power Supply Characteristics
Symbol Parameter
Conditions
Typical
Max
Unit
@ 1 MHz
2.5
3
10
13
27
115
30
mA
IDDR
Active Read Current
@ 40 MHz
@ 1 MHz
@ 40 MHz
CS High 1
CS High
6
8
mA
mA
mA
μA
IDDW
Active Write Current
23
90
7
ISB
IZZ
Standby Current
Standby Sleep Mode Current
μA
1 ISB current is specified with CS high and the SPI bus inactive.
MR25H128A Rev. 1.2 3/2018
Copyright © 2018 Everspin Technologies, Inc.
11
MR25H128A
4. TIMING SPECIFICATIONS
Table 4.1 Capacitance1
Symbol Parameter
Typical
Max
Unit
pF
CIn
Control input capacitance
Input/Output capacitance
-
-
6
8
CI/O
pF
1
ƒ = 1.0 MHz, dV = 3.0 V, TA = 25 °C, periodically sampled rather than 100% tested.
Table 4.2 AC Measurement Conditions
Parameter
Value
1.5
Unit
Logic input timing measurement reference level
Logic output timing measurement reference level
Logic input pulse levels
V
V
1.5
0 or 3.0
2
V
Input rise/fall time
ns
Output load for low and high impedance parameters
Output load for all other timing parameters
See Figure 4.1
See Figure 4.2
Figure 4.1 Output Load for Impedance Parameter Measurements
ZD= 50 Ω
Output
RL = 50 Ω
VL = 1.5 V
Figure 4.2 Output Load for all Other Parameter Measurements
3.3 V
590 Ω
Output
30 pF
435 Ω
MR25H128A Rev. 1.2 3/2018
Copyright © 2018 Everspin Technologies, Inc.
12
MR25H128A
TIMING SPECIFICATIONS
Power-Up Timing
The MR25H128A is not accessible for a start-up time, t = 400 μs after power up. Users must wait this time
from the time when VDD (min) is reached until the first PCUS low to allow internal voltage references to become
stable. The CS signal should be pulled up to VDD so that the signal tracks the power supply during power-up
sequence.
Table 4.3 Power-Up
Symbol
Parameter
Min
Typical
Max
Unit
VWI
Write Inhibit Voltage
2.2
-
2.7
V
tPU
Startup Time
400
-
-
μs
Figure 4.3 Power-Up Timing
VDD
DD(max)
V
Chip Selection not allowed
DD(min)
V
Reset state
of the
Normal Operation
t PU
device
VWI
Time
MR25H128A Rev. 1.2 3/2018
Copyright © 2018 Everspin Technologies, Inc.
13
MR25H128A
TIMING SPECIFICATIONS
Synchronous Data Timing
Table 4.4 AC Timing Parameters
Over the Operating Temperature Range and CL= 30 pF
Symbol
fSCK
Parameter
Min
0
Max
40
50
50
-
Unit
MHz
ns
SCK Clock Frequency
Input Rise Time
Input Fall Time
SCK High Time
SCK Low Time
tRI
-
tRF
-
ns
tWH
11
11
ns
tWL
-
ns
Synchronous Data Timing (See figure 4.4)
tCS
tCSS
tCSH
tSU
tH
CS High Time
40
10
10
5
-
-
-
-
-
ns
ns
ns
ns
ns
CS Setup Time
CS Hold Time
Data In Setup Time
Data In Hold Time
5
VDD = 2.7 to 3.6v.
VDD = 3.0 to 3.6v.
VDD = 2.7 to 3.6v.
VDD = 3.0 to 3.6v.
VDD = 3.0 to 3.6v.
0
0
0
0
0
10
9
ns
ns
ns
ns
ns
Industrial Grade
tV
Output Valid
10
9
AEC Q-100 Grade 3
AEC Q-100 Grade 1
10
Table continues next page.
MR25H128A Rev. 1.2 3/2018
Copyright © 2018 Everspin Technologies, Inc.
14
MR25H128A
Table 4.4 (Cont’d) AC Timing Parameters
Symbol
Parameter
Min
Max
Unit
tHO
Output Hold Time
0
-
ns
HOLD Timing (See figure 4.5)
tHD
tCD
tLZ
HOLD Setup Time
HOLD Hold Time
10
10
-
-
ns
ns
ns
ns
-
HOLD to Output Low Impedance
HOLD to Output High Impedance
20
20
tHZ
-
Other Timing Specifications
tWPS
tWPH
tDP
WP Setup To CS Low
WP Hold From CS High
Sleep Mode Entry Time
Sleep Mode Exit Time
Output Disable Time
5
5
-
-
-
-
-
ns
ns
μs
μs
ns
3
tRDP
tDIS
400
12
MR25H128A Rev. 1.2 3/2018
Copyright © 2018 Everspin Technologies, Inc.
15
MR25H128A
TIMING SPECIFICATIONS
Figure 4.4 Synchronous Data Timing
Figure 4.5 HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
SO
tHZ
tLZ
MR25H128A Rev. 1.2 3/2018
Copyright © 2018 Everspin Technologies, Inc.
16
MR25H128A
5. ORDERING INFORMATION
Figure 5.1 Product Part Number Decoder Table
Memory
Speed
Voltage
Density
Revision Temp Package
DF
Ship
Grade
Example Ordering Part Number
MR
25
H
128
A
P
R
ES
Everspin MRAM
40 MHz
MR
25
H
3.0v. Vdd
128 Kb
128
A
Revision A
Industrial
-40 to 85°C
-40 to 85°C
-40 to 125°C
C
AEC-Q100 Grade 3
AEC-Q100 Grade 1
8-pin DFN Small Flag
Tray
P
M
DF
Blank
R
Tape and Reel
Mass Producꢀon
Customer Samples
Engineering Samples
Blank
CS
ES
Table 5.1 Ordering Part Numbers
Grade
Industrial
Temperature Package
-40 to +85 C 8-DFN Small Flag
Shipping Container Order Part Number
Trays
MR25H128ACDF
MR25H128ACDFR
MR25H128APDF
MR25H128APDFR
MR25H128AMDF
MR25H128AMDFR
Tape and Reel
Trays
AEC-Q100 Grade 3 -40 to +85 C
8-DFN Small Flag
Tape and Reel
Trays
AEC-Q100 Grade 1 -40 to +125 C 8-DFN Small Flag
Tape and Reel
MR25H128A Rev. 1.2 3/2018
Copyright © 2018 Everspin Technologies, Inc.
17
MR25H128A
6. MECHANICAL DRAWINGS
Figure 6.1 DFN Small Flag Package
Exposed metal Pad. Do not con-
nect anything except VSS
A
2X 0.10 C
5
8
2X 0.10 C
J
B
I
L
G
H
M
4
1
Pin 1 Index
C
Detail A
F
K
F
D
E
Detail A
Dimension
A
B
C
D
E
F
G
H
I
J
K
L
M
Max
5.10
6.10
6.00
5.90
0.90
-
0.45
0.05
1.54
0.70
2.10
2.10
0.210
-
-
1.27
BSC
Nominal
Min
5.00
4.90
0.85
0.80
0.40
0.35
-
1.40
1.26
0.60
0.50
2.00
1.90
2.00
1.90
0.200 C0.45 R0.20
0.190
-
0.00
-
-
NOTE:
1. All dimensions are in mm. Angles in degrees.
2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be
within 0.08 mm.
3. Refer to JEDEC MO-229-E
MR25H128A Rev. 1.2 3/2018
Copyright © 2018 Everspin Technologies, Inc.
18
MR25H128A
7. REVISION HISTORY
Revision Date
Description of Change
0.1
0.2
June 1, 2015
First Draft
Corrected address range and timing diagrams for READ and WRITE to
September 29, 2015 Address bits 0-13. Added Grade 3 parameters to Table 4.4 and refor-
matted the Table.
0.3
1.0
November 2, 2015
October 1, 2016
Revised Part Number Decoder Table.
Production release. Removed all Preliminary status statements and
indications. Added nominal values to DFN package outline dimen-
sions table.
t
t
1.1
1.2
February 1, 2017
March 23, 2018
Added HO and V relationship to Synchronous Data Timing
Updated the Contact Us table
MR25H128A Rev. 1.2 3/2018
Copyright © 2018 Everspin Technologies, Inc.
19
MR25H128A
Everspin Technologies, Inc.
Information in this document is provided solely to enable system and
software implementers to use Everspin Technologies products. There are
no express or implied licenses granted hereunder to design or fabricate any
integrated circuit or circuits based on the information in this document.
Everspin Technologies reserves the right to make changes without further
notice to any products herein. Everspin makes no warranty, representation
or guarantee regarding the suitability of its products for any particular pur-
pose, nor does Everspin Technologies assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and
all liability, including without limitation consequential or incidental dam-
ages. “Typical”parameters, which may be provided in Everspin Technologies
data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters
including “Typicals”must be validated for each customer application by
customer’s technical experts. Everspin Technologies does not convey any
license under its patent rights nor the rights of others. Everspin Technologies
products are not designed, intended, or authorized for use as components
in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the
failure of the Everspin Technologies product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Everspin
Technologies products for any such unintended or unauthorized applica-
tion, Buyer shall indemnify and hold Everspin Technologies and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising
out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that
Everspin Technologies was negligent regarding the design or manufacture
of the part. Everspin™ and the Everspin logo are trademarks of Everspin
Technologies, Inc. All other product or service names are the property of
their respective owners.
How to Reach Us:
Home Page:
www.everspin.com
World Wide Information Request
WW Headquarters - Chandler, AZ
5670 W. Chandler Blvd., Suite 100
Chandler, Arizona 85226
Tel: +1-877-480-MRAM (6726)
Local Tel: +1-480-347-1111
Fax: +1-480-347-1175
support@everspin.com
orders@everspin.com
sales@everspin.com
Europe, Middle East and Africa
Everspin Europe Support
support.europe@everspin.com
Japan
Everspin Japan Support
support.japan@everspin.com
Asia Pacific
Everspin Asia Support
support.asia@everspin.com
Filename:
EST02895_MR25H128A_Datasheet_Rev1.2032318
Copyright © Everspin Technologies, Inc. 2018
MR25H128A Rev. 1.2 3/2018
Copyright © 2018 Everspin Technologies, Inc.
20
相关型号:
©2020 ICPDF网 联系我们和版权申明