MR25H40CDFR [EVERSPIN]
50MHz/20ns tSCK 4Mb SPI Interface MRAM / 40MHz/25ns tSCK 4Mb SPI Interface MRAM;
| 型号： | MR25H40CDFR |
| 厂家： | 
Everspin Technologies |
| 描述： | 50MHz/20ns tSCK 4Mb SPI Interface MRAM / 40MHz/25ns tSCK 4Mb SPI Interface MRAM 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总30页 (文件大小：1649K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MR20H40 / MR25H40
t
MR20H40 - 50MHz/20ns SCK 4Mb SPI Interface MRAM
t
MR25H40 - 40MHz/25ns SCK 4Mb SPI Interface MRAM
For more information on product options, see “Table 16 – Ordering Part Numbers” on page 25.
FEATURES
•
•
•
•
•
•
•
•
No write delays
Unlimited write endurance
Data retention greater than 20 years
Automatic data protection on power loss
Fast, simple SPI interface, up to 50 MHz clock rate with MR20H40.
3.0 to 3.6 Volt power supply range
Low-current sleep mode
8-DFN
Commercial (0 to 70°C), Industrial (-40 to 85°C), Extended (-40 to 105°C), and
AEC-Q100 Grade 1 (-40 to 125°C) temperature range options.
8-DFN Small Flag
•
•
•
Available in 8-pin DFN or 8-pin DFN Small Flag, RoHS-compliant packages.
Direct replacement for serial EEPROM, Flash, and FeRAM
MSL Level 3
RoHS
DESCRIPTION
MR2xH40 is a family of 4,194,304-bit magnetoresistive random access memory (MRAM) devices
organized as 524,288 words of 8 bits. They are the ideal memory solution for applications that must
store and retrieve data and programs quickly using a small number of I/O pins. They have serial EE-
PROM and serial Flash compatible read/write timing with no write delays and unlimited read/write
endurance. Unlike other serial memories, with the MR2xH40 family both reads and writes can occur
randomly in memory with no delay between writes.
The MR2xH40 family provides highly reliable data storage over a wide range of temperatures. The
MR20H40 (50MHz) is offered with Industrial (-40° to 85 °C) range. The MR25H40 (40MHz) is offered
with Commercial (0 to 70°C), Industrial (-40° to 85 °C), Extended (-40 to 105°C), and AEC-Q100 Grade
1 (-40°C to 125 °C) operating temperature range options.
Both are available in a 5 x 6mm, 8-pin DFN package. The pinout is compatible with serial SRAM,
EEPROM, Flash, and FeRAM products.
1
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6, 8/2020
MR20H40 / MR25H40
TABLE OF CONTENTS
OVERVIEW ............................................................................................................................................5
Figure 1 – Block Diagram........................................................................................................................................... 5
System Configuration .....................................................................................................................5
Figure 2 – System Configuration............................................................................................................................. 5
Pin Functions ...................................................................................................................................6
Figure 3 – DFN Package Pin Diagram (Top View).............................................................................................. 6
Table 1 – Pin Functions............................................................................................................................................... 6
SPI COMMUNICATIONS PROTOCOL...................................................................................................7
Command Codes..............................................................................................................................7
Table 2 – Command Codes ....................................................................................................................................... 7
Status Register, Memory Protection and Block Write Protection................................................8
Table 3 – Status Register Bit Assignments........................................................................................................... 8
Memory Protection Modes.............................................................................................................8
Table 4 – Memory Protection Modes .................................................................................................................... 8
Block Protection Modes..................................................................................................................9
Table 5 – Block Memory Write Protection............................................................................................................ 9
Read Status Register (RDSR)........................................................................................................ 10
Figure 4 – Read Status Register (RDSR) Timing................................................................................................10
Write Enable (WREN).................................................................................................................... 10
Figure 5 – Write Enable (WREN) Timing..............................................................................................................10
Write Disable (WRDI).................................................................................................................... 11
Figure 6 – Write Disable (WRDI) Timing..............................................................................................................11
Write Status Register (WRSR) ...................................................................................................... 11
Figure 7 – Write Status Register (WRSR) Timing ..............................................................................................11
Read Data Bytes (READ) ............................................................................................................... 12
Figure 8 – Read Data Bytes (READ) Timing........................................................................................................12
2
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6 8/2020
MR20H40 / MR25H40
Table of Contents (Cont’d)
Write Data Bytes (WRITE)............................................................................................................. 12
Figure 9 – Write Data Bytes (WRITE) Timing......................................................................................................13
Enter Sleep Mode (SLEEP)............................................................................................................ 13
Figure 10 – Enter Sleep Mode (SLEEP) Timing..................................................................................................13
Exit Sleep Mode (WAKE)............................................................................................................... 14
Figure 11 – Exit Sleep Mode (WAKE) Timing.....................................................................................................14
ELECTRICAL SPECIFICATIONS ......................................................................................................... 15
Absolute Maximum Ratings ........................................................................................................ 15
Table 6 – Absolute Maximum Ratings ..............................................................................................................15
Table 7 – Operating Conditions.............................................................................................................................16
Table 8 – DC Characteristics....................................................................................................................................16
Table 9 – Power Supply Characteristics..............................................................................................................17
TIMING SPECIFICATIONS ................................................................................................................. 18
Capacitance................................................................................................................................... 18
Table 10 – Capacitance.............................................................................................................................................18
AC Measurement Conditions....................................................................................................... 18
Table 11 – AC Measurement Conditions............................................................................................................18
Figure 12 – Output Load for Impedance Parameter Measurements .......................................................18
Figure 13 – Output Load for all Other Parameter Measurements.............................................................18
Power Up Timing .......................................................................................................................... 19
Table 12 – Power-Up Timing...................................................................................................................................19
Figure 14 – Power-Up Timing................................................................................................................................19
AC Timing Parameters.................................................................................................................. 20
f
Table 13 – MR20H40 ( SCK = 50MHz) AC Timing Parameters.....................................................................20
f
Table 14 – MR25H40 ( SCK = 40MHz) AC Timing Parameters.....................................................................21
3
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6, 8/2020
MR20H40 / MR25H40
Table of Contents (Cont’d)
Figure 15 – Synchronous Data Timing................................................................................................................23
Figure 16 – HOLD Timing........................................................................................................................................23
PART NUMBERS AND ORDERING .................................................................................................... 24
Table 15 – Part Numbering System......................................................................................................................24
Table 16 – Ordering Part Numbers.......................................................................................................................25
PACKAGE OUTLINE DRAWINGS....................................................................................................... 26
Figure 17 – DFN Package Outline........................................................................................................................26
Figure 18 – DFN Small Flag Package....................................................................................................................27
REVISION HISTORY ........................................................................................................................... 28
HOW TO REACH US ........................................................................................................................... 29
4
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6 8/2020
MR20H40 / MR25H40
OVERVIEW
The MR2xH40 family is an SPI interface MRAM family with a memory array logically organized as 512Kx8
using the four pin interface of chip select (CS), serial input (SI), serial output (SO) and serial clock (SCK) of the
serial peripheral interface (SPI) bus. The MRAM implements a subset of commands common to SPI EEPROM
and SPI Flash components. This allows the SPI MRAM to replace these components in the same socket
and interoperate on a shared SPI bus. The SPI MRAM offers superior write speed, unlimited endurance, low
standby & operating power, and simple, reliable data retention compared to other serial memory alterna-
tives.
Figure 1 – Block Diagram
Instruction Decode
Clock Generator
Control Logic
WP
CS
HOLD
SCK
Write Protect
512Kb x 8
MRAM ARRAY
Instruction Register
19
8
Address Register
Counter
SO
Data I/O Register
SI
4
Nonvolatile Status
Register
System Configuration
Single or multiple devices can be connected to the bus as shown in Figure 2. Pins SCK, SO and SI are com-
mon among devices. Each device requires CS and HOLD pins to be driven separately.
Figure 2 – System Configuration
SCK
MOSI
MISO
SO
SI
SCK
SO
SI
SCK
SPI
EVERSPIN SPI MRAM 1
EVERSPIN SPI MRAM 2
Micro Controller
CS
HOLD
CS
HOLD
CS
1
HOLD
1
2
CS
2
HOLD
MOSI = Master Out Slave In
MISO = Master In Slave Out
5
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6, 8/2020
MR20H40 / MR25H40
Pin Functions
Figure 3 – DFN Package Pin Diagram (Top View)
1
8
CS
V
DD
2
3
4
7
6
5
HOLD
SCK
SI
SO
WP
V
SS
Table 1 – Pin Functions
Signal
Name
Pin I/O
Function
Description
An active low chip select for the serial MRAM. When chip select is high, the
memory is powered down to minimize standby power, inputs are ignored
and the serial output pin is Hi-Z. Multiple serial memories can share a com-
mon set of data pins by using a unique chip select for each memory.
CS
1
2
Input
Chip Select
The data output pin is driven during a read operation and remains Hi-Z at
all other times. SO is Hi-Z when HOLD is low. Data transitions on the data
output occur on the falling edge of SCK.
SO
Output
Input
Serial Output
A low on the write protect input prevents write operations to the Status
Register.
WP
3
4
Write Protect
Ground
Refer-
ence
V
Power supply ground pin.
SS
All data is input to the device through this pin. This pin is sampled on the
rising edge of SCK and ignored at other times. SI can be tied to SO to create
a single bidirectional data bus if desired.
SI
5
Input
Input
Serial Input
Synchronizes the operation of the MRAM. The clock can operate up to 50
MHz to shift commands, address, and data into the memory. Inputs are
captured on the rising edge of clock. Data outputs from the MRAM occur
on the falling edge of clock. The serial MRAM supports both SPI Mode 0
(CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). In Mode 0, the clock is
normally low. In Mode 3, the clock is normally high. Memory operation is
static so the clock can be stopped at any time.
SCK
6
Serial Clock
A low on the Hold pin interrupts a memory operation for another task.
When HOLD is low, the current operation is suspended. The device will
ignore transitions on the CS and SCK when HOLD is low. All transitions of
HOLD must occur while CS is low.
HOLD
7
8
Input
Hold
V
Supply
Power Supply
Power supply voltage from +3.0 to +3.6 volts.
DD
6
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6 8/2020
MR20H40 / MR25H40
SPI COMMUNICATIONS PROTOCOL
The MR2xH40 can be operated in either SPI Mode 0 (CPOL=0, CPHA =0) or SPI Mode 3 (CPOL=1, CPHA=1).
For both modes, inputs are captured on the rising edge of the clock and data outputs occur on the falling
edge of the clock. When not conveying data, SCK remains low for Mode 0; while in Mode 3, SCK is high.
The memory determines the mode of operation (Mode 0 or Mode 3) based upon the state of the SCK when
CS falls.
All memory transactions start when CS is brought low to the memory. The first byte is a command code.
Depending upon the command, subsequent bytes of address are input. Data is either input or output.
There is only one command performed per CS active period. CS must go inactive before another command
can be accepted. To ensure proper part operation according to specifications, it is necessary to terminate
each access by raising CS at the end of a byte (a multiple of 8 clock cycles from CS dropping) to avoid partial
or aborted accesses.
Command Codes
Table 2 – Command Codes
Instruction
Description
Binary Code
Hex Code
Address Bytes
Data Bytes
WREN
Write Enable
0000 0110
06h
0
0
WRDI
Write Disable
Read Status Register
Write Status Register
Read Data Bytes
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
1011 1001
1010 1011
04h
05h
01h
03h
02h
B9h
ABh
0
0
0
3
3
0
0
0
1
RDSR
1
WRSR
READ
WRITE
SLEEP
WAKE
1
1 to ∞
1 to ∞
0
Write Data Bytes
Enter Sleep Mode
Exit Sleep Mode
0
Note:
1. An RDSR command cannot immediately follow a READ command. If an RDSR command immediately follows a READ com-
mand, the output data will not be correct. Any other sequence of commands is allowed. If an RDSR command is required
immediately following a READ command, it is necessary that another command be inserted before the RDSR is executed.
Alternatively, two successive RDSR commands can be issued following the READ command. The second RDSR will output the
proper state of the Status Register.
7
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6, 8/2020
MR20H40 / MR25H40
Status Register, Memory Protection and Block Write Protection
The status register consists of the 8 bits listed in Table 3. As seen in Table 4, the Status Register Write Disable
bit (SRWD) is used in conjunction with bit 1 (WEL) and the Write Protection pin (WP) to provide hardware
memory block protection. Bits BP0 and BP1 define the memory block arrays that are protected as described
in Table 5. The fast writing speed of the MR2xH40 does not require write status bits. The state of bits 6,5,4,
and 0 can be user modified and do not affect memory operation. All bits in the status register are pre-set
from the factory in the “0”state.
Table 3 – Status Register Bit Assignments
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRWD
Don’t Care Don’t Care Don’t Care
BP1
BP0
WEL
Don’t Care
Memory Protection Modes
When WEL is reset to 0, writes to all blocks and the status register are protected. When WEL is set to 1, BP0
and BP1 determine which memory blocks are protected. While SRWD is reset to 0 and WEL is set to 1,
status register bits BP0 and BP1 can be modified. Once SRWD is set to 1, WP must be high to modify SRWD,
BP0 and BP1.
Table 4 – Memory Protection Modes
Status
WEL
SRWD
WP
Protected Blocks
Unprotected Blocks
Register
Protected
Writable
0
1
1
1
X
0
1
1
X
X
Protected
Protected
Protected
Protected
Protected
Writable
Writable
Writable
Low
High
Protected
Writable
8
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6 8/2020
MR20H40 / MR25H40
Block Protection Modes
The memory enters hardware block protection when the WP input is low and the Status Register Write Dis-
able (SRWD) bit is set to 1. The memory leaves hardware block protection only when the WP pin goes high.
While WP is low, the write protection blocks for the memory are determined by the status register bits BP0
and BP1 and cannot be modified without taking the WP signal high again.
If the WP signal is high (independent of the status of SRWD bit), the memory is in software protection mode.
This means that block write protection is controlled solely by the status register BP0 and BP1 block write pro-
tect bits and this information can be modified using the WRSR command.
Table 5 – Block Memory Write Protection
Status Register
Memory Contents
BP1
BP0
Protected Area
Unprotected Area
0
0
None
All Memory
0
1
Upper Quarter
Lower Three-Quarters
1
1
0
1
Upper Half
All
Lower Half
None
9
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6, 8/2020
MR20H40 / MR25H40
Read Status Register (RDSR)
The Read Status Register (RDSR) command allows the Status Register to be read. The Status Register can be
read to check the status of write enable latch bit, status register write protect bit, and block write protect
bits. For MR2xH40, the write in progress bit (bit 0) is not written by the memory because there is no write
delay. The RDSR command is entered by driving CS low, sending the command code, and then driving CS
high. An RDSR command cannot immediately follow a READ command. If an RDSR command immediately
follows a READ command, the output data will not be correct. Any other sequence of commands is allowed.
If an RDSR command is required immediately following a READ command, it is necessary that another com-
mand be inserted before the RDSR is executed. Alternatively, two successive RDSR commands can be issued
following the READ command. The second RDSR will output the proper state of the Status Register.
Figure 4 – Read Status Register (RDSR) Timing
CS
Mode 3
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Mode 0
SCK
0
0
0
0
0
1
0
1
SI
MSB
Status Register Out
High Impedance
High Z
SO
7
6
5
4
3
2
1
0
MSB
Write Enable (WREN)
Figure 5 – Write Enable (WREN) Timing
CS
Mode 3
Mode 0
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Instruction (06h)
SI
0
0
0
0
0
1
1
0
High Impedance
SO
The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit in the status register (bit 1). The
Write Enable Latch must be set prior to writing either bit in the status register or the memory. The WREN
command is entered by driving CS low, sending the command code, and then driving CS high.
10
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6 8/2020
MR20H40 / MR25H40
Write Disable (WRDI)
The Write Disable (WRDI) command resets the Write Enable Latch (WEL) bit in the status register (bit 1) to 0.
This prevents writes to status register or memory. The WRDI command is entered by driving CS low, sending
the command code, and then driving CS high.
The Write Enable Latch (WEL) is reset to 0 on power-up or when the WRDI command is completed.
Figure 6 – Write Disable (WRDI) Timing
CS
Mode 3
Mode 0
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCK
Instruction (04h)
0
0
0
0
0
1
0
0
SI
High Impedance
SO
Write Status Register (WRSR)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. The
WRSR command is not executed unless the Write Enable Latch (WEL) has been set to 1 by executing a WREN
command while pin WP and the Status Register SRWD (Bit 7) correspond to values that make the status reg-
ister writable as seen in Table 4 on page 8. Status Register bits are non-volatile with the exception of the
WEL which is reset to 0 upon power cycling.
The WRSR command is entered by driving CS low, sending the command code and status register write data
byte, and then driving CS high.
Figure 7 – Write Status Register (WRSR) Timing
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Instruction (01h)
Status Register In
0
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
SI
MSB
High Impedance
SO
11
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6, 8/2020
MR20H40 / MR25H40
Read Data Bytes (READ)
The Read Data Bytes (READ) command allows data bytes to be read starting at an address specified by the
24-bit address. Only address bits 0-18 are decoded by the memory. The data bytes are read out sequentially
from memory until the read operation is terminated by bringing CS high. The entire memory can be read in
a single command. The address counter will roll over to 0000H when the address reaches the top of memo-
ry.
The READ command is entered by driving CS low and sending the command code. The memory drives the
read data bytes on the SO pin. Reads continue as long as the memory is clocked. The command is termi-
nated by bringing CS high.
Figure 8 – Read Data Bytes (READ) Timing
CS
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
32
33
34
35
36
37
38
39
SCK
Instruction (03h)
24-Bit Address
3
0
0
0
0
0
0
1
1
23
MSB
High Impedance
22
21
2
1
0
SI
Data Out 1
Data Out 2
7
6
5
4
3
2
1
0
7
SO
MSB
Write Data Bytes (WRITE)
The Write Data Bytes (WRITE) command allows data bytes to be written starting at an address specified by
the 24-bit address. Only address bits 0-18 are decoded by the memory. The data bytes are written sequen-
tially in memory until the write operation is terminated by bringing CS high. The entire memory can be
written in a single command. The address counter will roll over to 0000H when the address reaches the top
of memory.
Unlike EEPROM or Flash Memory, MRAM can write data bytes continuously at its maximum rated clock speed
without write delays or data polling. Back to back WRITE commands to any random location in memory can
be executed without write delay. MRAM is a random access memory rather than a page, sector, or block
organized memory so it is ideal for both program and data storage.
The WRITE command is entered by driving CS low, sending the command code, and then sequential write
data bytes. Writes continue as long as the memory is clocked. The command is terminated by bringing CS
high.
12
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6 8/2020
MR20H40 / MR25H40
Figure 9 – Write Data Bytes (WRITE) Timing
CS
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
32
33
34
35
36
37
38
39
SCK
Instruction (02h)
24-Bit Address
3
0
0
0
0
0
0
1
0
23
MSB
High Impedance
22
21
2
1
0
7
6
5
4
3
2
1
0
SI
MSB
SO
CS
Mode 3
Mode 0
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
SCK
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SI
MSB
MSB
High Impedance
SO
Enter Sleep Mode (SLEEP)
The Enter Sleep Mode (SLEEP) command turns off all MRAM power regulators in order to reduce the overall
chip standby power to 15 μA typical. The SLEEP command is entered by driving CS low, sending the com-
t
mand code, and then driving CS high. The standby current is achieved after time, DP. If power is removed
when the part is in sleep mode, upon power restoration, the part enters normal standby. The only valid
command following SLEEP mode entry is a WAKE command.
Figure 10 – Enter Sleep Mode (SLEEP) Timing
CS
t DP
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCK
Instruction (B9h)
1
0
1
1
1
0
0
1
SI
Active Current
Standby Current
Sleep Mode Current
SO
13
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6, 8/2020
MR20H40 / MR25H40
Exit Sleep Mode (WAKE)
The Exit Sleep Mode (WAKE) command turns on internal MRAM power regulators to allow normal operation.
The WAKE command is entered by driving CS low, sending the command code, and then driving CS high.
t
t
The memory returns to standby mode after RDP. The CS pin must remain high until the RDP period is over.
WAKE must be executed after sleep mode entry and prior to any other command.
Figure 11 – Exit Sleep Mode (WAKE) Timing
CS
t RDP
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCK
Instruction (ABh)
1
0
1
0
1
0
1
1
SI
Sleep Mode Current
Standby Current
SO
14
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6 8/2020
MR20H40 / MR25H40
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
This device contains circuitry to protect the inputs against damage caused by high static voltages or electric
fields. However, it is advised that normal precautions be taken to avoid application of any voltage greater
than maximum rated voltages to these high-impedance (Hi-Z) circuits.
The device also contains protection against external magnetic fields. Precautions should be taken to avoid
application of any magnetic field more intense than the maximum field intensity specified in the maximum
ratings.
Table 6 – Absolute Maximum Ratings
Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to
recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability.
Symbol Parameter
Conditions
Value
Unit
2
V
Supply voltage
-0.5 to 4.0
V
DD
2
V
Voltage on any pin
-0.5 to V + 0.5
V
mA
W
IN
DD
I
Output current per pin
20
OUT
3
P
Package power dissipation
0.600
D
Commercial
-10 to 85
-45 to 95
°C
Industrial
°C
T
Temperature under bias
Storage Temperature
BIAS
Extended
-45 to 115
-45 to 135
-55 to 150
260
°C
°C
°C
°C
AEC-Q100 Grade 1
T
stg
T
Lead temperature during solder (3 minute max)
Lead
H
Maximum magnetic field during write
Write
12,000
12,000
A/m
A/m
max_write
Maximum magnetic field during read or
standby
H
Read or Standby
max_read
Notes:
1. All voltages are referenced to V . The DC value of V must not exceed actual applied V by more than 0.5V. The AC value of
SS
IN
DD
V
must not exceed applied V by more than 2V for 10ns with I limited to less than 20mA.
IN
DD IN
2. Power dissipation capability depends on package characteristics and use environment.
15
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6, 8/2020
MR20H40 / MR25H40
Table 7 – Operating Conditions
Symbol
Parameter
Temp Grade
Min
Max
Unit
V
Power supply voltage
3.0
3.6
V
DD
V
Input high voltage
Input low voltage
2.2
V
+ 0.3
V
V
IH
DD
V
-0.5
0.8
IL
Commercial
Industrial
0
70
85
°C
°C
°C
°C
-40
-40
-40
T
Ambient temperature under bias
A
Extended
105
125
1
AEC-Q100 Grade 1
Notes:
1. AEC-Q100 Grade 1 temperature profile assumes 10 percent duty cycle at maximum temperature (2 years out of 20-year life.)
Table 8 – DC Characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
I
Input leakage current
-
1
μA
LI
I
Output leakage current
Output low voltage
-
-
1
μA
V
LO
I
I
I
I
= +4 mA
0.4
OL
V
OL
= +100 μA
-
V
+ 0.2v
V
OL
SS
= -4 mA
2.4
-
-
V
OH
V
Output high voltage
OH
= -100 μA
V
- 0.2
V
OH
DD
16
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6 8/2020
MR20H40 / MR25H40
Table 9 – Power Supply Characteristics
Symbol Parameter
Conditions
Typical
Max
Unit
@ 1 MHz
5.0
11
mA
I
Active Read Current
@ 40 MHz
@ 50MHz
@ 1 MHz
12
13.8
9.0
28
17
18.5
25
mA
mA
mA
mA
mA
μA
DDR
I
Active Write Current
@ 40 MHz
@ 50 MHz
@ 40 MHz
@ 50 MHz
42
DDW
33
46.5
400
750
180
40
250
650
90
I
AC Standby Current (CS High)
SB1
μA
I
CMOS Standby Current (CS High)
μA
SB2
I
Standby Sleep Mode Current (CS High)
15
μA
ZZ
17
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6, 8/2020
MR20H40 / MR25H40
TIMING SPECIFICATIONS
Capacitance
Table 10 – Capacitance
Symbol Parameter
Typical
Max
Unit
1
1
C
Control input capacitance
-
6
pF
In
C
Input/Output capacitance
-
8
pF
I/O
Notes:
1. ƒ = 1.0 MHz, dV = 3.0 V, T = 25 °C, periodically sampled rather than 100% tested.
A
AC Measurement Conditions
Table 11 – AC Measurement Conditions
Parameter
Value
Unit
Logic input timing measurement reference level
Logic output timing measurement reference level
Logic input pulse levels
1.5
V
1.5
0 or 3.0
2
V
V
Input rise/fall time
ns
Output load for low and high impedance parameters
Output load for all other timing parameters
See Figure 12
See Figure 13
Figure 12 – Output Load for Impedance Parameter Measurements
ZD= 50 Ω
Output
RL = 50 Ω
VL = 1.5 V
Figure 13 – Output Load for all Other Parameter Measurements
3.3 V
590 Ω
Output
30 pF
435 Ω
18
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6 8/2020
MR20H40 / MR25H40
Power Up Timing
t
The MR2xH40 is not accessible for a start-up time, PU= 400 μs after power up. Users must wait this time
from the time when V (min) is reached until the first CS low to allow internal voltage references to become
DD
stable. The CS signal should be pulled up to V so that the signal tracks the power supply during power-up
DD
sequence.
Table 12 – Power-Up Timing
Symbol
Parameter
Min
Typical
Max
Unit
V
Write Inhibit Voltage
2.2
-
-
V
WI
t
PU
Startup Time
400
-
-
μs
Figure 14 – Power-Up Timing
VDD
DD(max)
V
Chip Selection not allowed
DD(min)
V
Reset state
of the
Normal Operation
t PU
device
VWI
Time
19
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6, 8/2020
MR20H40 / MR25H40
AC Timing Parameters
Table 13 – MR20H40 (fSCK = 50MHz) AC Timing Parameters
Industrial Temperature Range, V =3.0 to 3.6 V, C = 30 pF for all values.
DD
L
Symbol Parameter
Temp Range
Min
Typical
Max
Unit
f
SCK
SCK Clock Frequency
Industrial
Industrial
Industrial
Industrial
Industrial
0
-
50
MHz
t
RI
Input Rise Time
Input Fall Time
SCK High Time
SCK Low Time
-
-
-
-
-
-
50
50
-
ns
ns
ns
ns
t
RF
t
WH
7
7
t
WL
-
Synchronous Data Timing see Figure 15
t
CS
CS High Time
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
40
5
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
t
CSS
CS Setup Time
CS Hold Time
t
CSH
5
-
t
SU
Data In Setup Time
Data In Hold Time
Output Valid
2
-
t
H
5
-
t
V
0
9
-
t
HO
Output Hold Time
0
HOLD Timing see Figure 16
t
HD
HOLD Setup Time
Industrial
Industrial
Industrial
5
5
-
-
-
-
-
-
ns
ns
ns
t
CD
HOLD Hold Time
t
LZ
HOLD to Output Low Impedance
20
HOLD to Output High Imped-
ance
t
HZ
Industrial
-
-
20
ns
Other Timing Specifications
t
WPS
WP Setup To CS Low
WP Hold From CS High
Sleep Mode Entry Time
Sleep Mode Exit Time
Output Disable Time
Industrial
Industrial
Industrial
Industrial
Industrial
5
5
-
-
-
-
-
-
-
-
-
-
ns
ns
μs
μs
ns
t
WPH
t
DP
3
t
RDP
400
12
t
DIS
20
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6 8/2020
MR20H40 / MR25H40
Table 14 – MR25H40 (fSCK = 40MHz) AC Timing Parameters
Commercial Industrial, Extended and AEC-Q100 Grade 1 Temperature Ranges, V =3.0 to 3.6 V, C = 30 pF
DD
L
for all values.
Symbol Parameter
Temp Grade
Min
Typical
Max
Unit
f
SCK
SCK Clock Frequency
All
0
-
40
MHz
t
RI
Input Rise Time
Input Fall Time
SCK High Time
SCK Low Time
All
All
All
All
-
-
-
-
-
50
50
-
ns
ns
ns
ns
t
RF
-
t
WH
11
11
t
WL
-
Synchronous Data Timing see Figure 15
t
CS
CS High Time
All
40
10
10
5
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
t
CSS
CS Setup Time
CS Hold Time
All
t
CSH
All
-
t
SU
Data In Setup Time
Data In Hold Time
All
-
t
H
All
5
-
Comm./Ind./Ext.
AEC-Q100 Grade 1
All
0
9
10
-
t
V
Output Valid
0
t
HO
Output Hold Time
0
Table continues next page.
21
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6, 8/2020
MR20H40 / MR25H40
f
Table 14 (Cont’d) - MR25H40 ( SCK = 40MHz) AC Timing Parameters
Commercial, Industrial, Extended and AEC-Q100 Grade 1 Temperature Ranges, V =3.0 to 3.6 V, C = 30 pF
DD
L
for all values.
HOLD Timing see Figure 16
Symbol Parameter
Temp Grade
Min
Typical
Max
Unit
t
HD
HOLD Setup Time
All
10
-
-
ns
t
CD
HOLD Hold Time
All
All
All
10
-
-
-
-
-
ns
ns
ns
t
LZ
HOLD to Output Low Impedance
HOLD to Output High Impedance
20
20
t
HZ
-
Other Timing Specifications
t
WPS
WP Setup To CS Low
WP Hold From CS High
Sleep Mode Entry Time
Sleep Mode Exit Time
Output Disable Time
All
All
All
All
All
5
5
-
-
-
-
-
-
-
-
-
-
ns
ns
μs
μs
ns
t
WPH
t
DP
3
t
RDP
400
12
t
DIS
22
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6 8/2020
MR20H40 / MR25H40
Figure 15 – Synchronous Data Timing
Figure 16 – HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
SO
tHZ
tLZ
23
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6, 8/2020
MR20H40 / MR25H40
PART NUMBERS AND ORDERING
Table 15 – Part Numbering System
Product Family Number
MR
Memory
MR
25H
Interface
25H
40
Density
40
Revision Temp Package Grade
DC ES
Ordering Part Number
C
MRAM
MR
20H
25H
256
512
10
50 MHz Serial Family
40 MHz Serial Family
256 Kb
512 Kb
1 Mb
4 Mb
40
No Revision
Revision A
Revision B
Commercial
Industrial
Extended
Blank
A
B
Blank
C
V
0 to 70°C
-40 to 85°C
-40 to 105°C
AEC Q-100 Grade 1 -40 to 125°C
8-pin DFN in Tray
M
DC
8-pin DFN Tape and Reel
8-pin DFN (small flag) in Tray
8-pin DFN (small flag) Tape and Reel
Engineering Samples
DCR
DF
DFR
ES
Customer Samples
Mass Producꢀon
Blank
Blank
Product Family Number and Ordering Part Number given are for illustraꢀon only.
24
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6 8/2020
MR20H40 / MR25H40
Table 16 – Ordering Part Numbers
Speed
Grade
Tempera-
ture
Shipping Con-
tainer
Temp Grade
Package
Order Part Number
Trays
MR20H40CDF
8-DFN Small
Flag
50MHz
Industrial
-40 to +85 C
0 to +70 C
Tape and Reel MR20H40CDFR
Trays MR25H40DF
Tape and Reel MR25H40DFR
8-DFN Small
Flag
Commercial
Industrial
Extended
1
Trays
MR25H40CDC
1
8-DFN
1
Tape and Reel
Trays
MR25H40CDCR
MR25H40CDF
-40 to +85 C
8-DFN Small
Flag
40 MHz
Tape and Reel MR25H40CDFR
Trays MR25H40VDF
Tape and Reel MR25H40VDFR
Trays MR25H40MDF
Tape and Reel MR25H40MDFR
8-DFN Small
Flag
-40 to +105 C
8-DFN Small
Flag
AEC-Q100 Grade 1 -40 to +125 C
Note:
1. The DC pckage option (8-DFN) is not recommended for new designs. Please select the DF (8-DFN small
flag) option for new designs.
25
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6, 8/2020
MR20H40 / MR25H40
PACKAGE OUTLINE DRAWINGS
Figure 17 – DFN Package Outline
Exposed metal Pad. Do not
connect anything except V
SS
A
8
5
DAP Size
4.4 x 4.4
J
B
I
L
G
H
M
4
1
Pin 1 Index
Detail A
F
C
K
N
D
E
Detail A
Dimension
Max.
A
B
6.10
5.90
C
D
E
0.45
0.35
F
G
H
0.70
0.50
I
J
4.20
4.00
K
L
M
N
0.05
0.00
5.10
4.90
1.00 1.27
BSC
0.90
0.05
0.00
4.20
4.00
0.261
0.195
0.35
Ref.
C0.35 R0.20
Min.
Notes:
1. Reference JEDEC MO-229.
2. All dimensions are in mm. Angles in degrees.
3. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be within 0.08 mm.
4. Warpage shall not exceed 0.10 mm.
26
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6 8/2020
MR20H40 / MR25H40
Figure 18 – DFN Small Flag Package
Exposed metal Pad. Do not
connect anything except V
SS
A
2X 0.10 C
5
8
2X 0.10 C
J
B
I
L
G
H
M
4
K
1
Pin 1 Index
Detail A
F
C
N
D
E
Detail A
Dimension
Max.
A
5.10
B
6.10
C
0.90
D
E
F
G
1.60
H
0.70
I
J
K
.210
L
M
N
0.05
0.45 0.05
2.10 2.10
1.27
BSC
C0.45 R0.20
Min.
4.90
5.90
0.80
0.35 0.00
1.20
0.50
1.90 1.90
.196
0.00
Notes:
1. Reference JEDEC MO-229.
2. All dimensions are in mm. Angles in degrees.
3. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be within 0.08 mm.
4. Warpage shall not exceed 0.10 mm.
27
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6, 8/2020
MR20H40 / MR25H40
REVISION HISTORY
Revision
Date
Description of Change
0
0 .1
1
Jan 15, 2010
Feb. 23, 2010
May 5, 2010
Product Concept Release
Fixed typos in text.
Removed commercial specifications. All parts meet industrial specifications.
Preliminary Product Release. Updated description of status register non-volatility, WAKE
command, Table 3.4.
2
3
4
Jan 11, 2011
Apr 25, 2011
Removed DIP package part to seperate datasheet. Added inset detail for mechanical pack-
age drawings.
September 22,
2011
Added AEC-Q100 Grade 1 ordering option. Revised Table 3.1, Table 3.2, Table 3.4, Table 4.4
revised and Note 2 deleted, revised Figure 5.1 and Table 5.1.
Corrected V in Table 3.3 to read V Max = V + 0.2v. Corrected SI waveform in Figure 2.8.
OL
OL
SS
New Small Flag DFN package option added to Page 1 Features and available parts Table 5.1.
DFN Small Flag drawing and dimensions table added as Figure 6.2. Figure 6.1, DFN Pack-
age, cleaned up with better quality drawing and dimension table. No specifications were
changed in Figure 6.1.
5
6
Nov 18, 2011
CDF and CDFR options changed to Preliminary. Added Small Flag DFN illustrations. Refor-
matted all parametric tables. Revised 8-DFN package drawing to show correct proportion
for flag and package. Added MR20H40 as 50MHz speed option. Deleted large flag DFN
ordering option for AEC-Q100 products. Corrected errors in DFN package outline drawings.
August 23, 2012
January 17,
2013
7
8
Removed Preliminary status from MR25H40CDF, CDFR.
May 24, 2013
March 28, 2014
July 11, 2014
Removed Preliminary status from MR20H40CDF(R), and from MR20H40DF(R).
Removed Preliminary status from 25H40MDF(R). V max to unspecified from TBD. Added
WI
9
MSL-3 status to the Features list.
10
MR20H40DF and MR20H40DFR withdrawn from sales status.
11
August 13, 2014 Added Extended temperature grade offering.
11.1
11.2
12.0
May 19, 2015
June 11, 2015
Revised Everspin contact information.
Corrected Japan Sales Office telephone number.
Clarification of RDSR command operation.
December 9,
2015
Minor edits to the revised RDSR command operation. Corrected wrong bit number for the
WEL in the WRDI command description. Clarification of SRWD bit location in the Status Reg-
ister within the WRSR command description. Condensed Note 1 in Table 2, referring to RDSR
operation after a READ command.
December 18,
2015
12.1
28
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6 8/2020
MR20H40 / MR25H40
REVISION HISTORY - Cont’d
Revision
Date
Description of Change
Change all large flag DFN options to “The DC pckage option (8-DFN) is not recommended
for new designs. Please select the DF (8-DFN small flag) option for new designs.”
December 13,
2016
12.2
t
t
12.3
12.4
12.5
12.6
February 2, 2017 Added HO and V relationship to Synchronous Data Timing
March 23, 2018 Updated the Contact Us table
Corrected sentence in Block Protection Modes section on page 9 to ”The memory enters
hardware block protection when the WP input is low and the Status Register Write Disable
(SRWD) bit is set to 1”.
December 16,
2019
August 7, 2020
Added a Commercial temperature range product option to MR25H40 family.
29
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6, 8/2020
MR20H40 / MR25H40
HOW TO REACH US
Everspin Technologies, Inc.
Information in this document is provided solely to enable system and soft-
ware implementers to use Everspin Technologies products. There are no
express or implied licenses granted hereunder to design or fabricate any
integrated circuit or circuits based on the information in this document.
Everspin Technologies reserves the right to make changes without further
notice to any products herein. Everspin makes no warranty, representa-
tion or guarantee regarding the suitability of its products for any particu-
lar purpose, nor does Everspin Technologies assume any liability arising
out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential
or incidental damages. “Typical” parameters, which may be provided in
Everspin Technologies data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All
operating parameters including “Typicals” must be validated for each cus-
tomer application by customer’s technical experts. Everspin Technologies
does not convey any license under its patent rights nor the rights of oth-
ers. Everspin Technologies products are not designed, intended, or au-
thorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or
for any other application in which the failure of the Everspin Technologies
product could create a situation where personal injury or death may oc-
cur. Should Buyer purchase or use Everspin Technologies products for any
such unintended or unauthorized application, Buyer shall indemnify and
hold Everspin Technologies and its officers, employees, subsidiaries, affili-
ates, and distributors harmless against all claims, costs, damages, and ex-
penses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that Everspin Technologies
was negligent regarding the design or manufacture of the part. Everspin™
and the Everspin logo are trademarks of Everspin Technologies, Inc. All
other product or service names are the property of their respective owners.
How to Reach Us:
Home Page:
www.everspin.com
World Wide Information Request
WW Headquarters - Chandler, AZ
5670 W. Chandler Blvd., Suite 100
Chandler, Arizona 85226
Tel: +1-877-480-MRAM (6726)
Local Tel: +1-480-347-1111
Fax: +1-480-347-1175
support@everspin.com
orders@everspin.com
sales@everspin.com
Europe, Middle East and Africa
Everspin Europe Support
support.europe@everspin.com
Japan
Everspin Japan Support
support.japan@everspin.com
Asia Pacific
Everspin Asia Support
support.asia@everspin.com
Copyright © Everspin Technologies, Inc. 2020
30
Copyright © Everspin Technologies 2020
MR20H40 / MR25H40 Revision 12.6 8/2020
相关型号：
MR25H40MDFR
50MHz/20ns tSCK 4Mb SPI Interface MRAM / 40MHz/25ns tSCK 4Mb SPI Interface MRAM
EVERSPIN
MR25H40VDFR
50MHz/20ns tSCK 4Mb SPI Interface MRAM / 40MHz/25ns tSCK 4Mb SPI Interface MRAM
EVERSPIN
MR25MR-11K5-F50-T52
RESISTOR, METAL FILM, 0.25W, 1%, 50ppm, 11500ohm, THROUGH HOLE MOUNT, AXIAL LEADED, ROHS COMPLIANT
RFE
MR25MR-11R5-F50
RESISTOR, METAL FILM, 0.25W, 1%, 50ppm, 11.5ohm, THROUGH HOLE MOUNT, AXIAL LEADED, ROHS COMPLIANT
RFE
MR25MR-147R-F50-T52
RESISTOR, METAL FILM, 0.25W, 1%, 50ppm, 147ohm, THROUGH HOLE MOUNT, AXIAL LEADED, ROHS COMPLIANT
RFE
©2020 ICPDF网 联系我们和版权申明