8203CB [EXAR]
Telecom Circuit, 1-Func, PBGA196, 15 X 15 MM, 1 MM PITCH, BGA-196;
| 型号： | 8203CB |
| 厂家： | 
EXAR CORPORATION |
| 描述： | Telecom Circuit, 1-Func, PBGA196, 15 X 15 MM, 1 MM PITCH, BGA-196 电信 电信集成电路 |
| 文件： | 总286页 (文件大小：2077K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
820x
Acceleration Processor
Data Sheet
Hifn Confidential
®
DS-0157-D, © April 1, 2010, Hi/fn , Inc. All rights reserved. 04/10
No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or
translated into any language in any form by any means without the written permission of Hi/fn, Inc. (“Hifn”)
Licensing and Government Use
Any Hifn software (“Licensed Programs”) described in this document is furnished under a license and may be
used and copied only in accordance with the terms of such license and with the inclusion of this copyright
notice. Distribution of this document or any copies thereof and the ability to transfer title or ownership of this
document’s contents are subject to the terms of such license.
Such Licensed Programs and their documentation have been developed at private expense and no part of such
Licensed Programs is in the public domain. Use, duplication, disclosure, and acquisition by the U.S.
Government of such Licensed Programs is subject to the terms and definitions of their applicable license.
Disclaimer
Hifn reserves the right to make changes to its products, including the contents of this document, or to
discontinue any product or service without notice. Hifn advises its customers to obtain the latest version of
relevant information to verify, before placing orders, that information being relied upon is current. Every
effort has been made to keep the information in this document current and accurate as of the date of this
document’s publication or revision.
Hifn warrants performance of its products to the specifications applicable at the time of sale in accordance
with Hifn's standard warranty or the warranty provisions specified in any applicable license. Testing and other
quality control techniques are utilized to the extent Hifn deems necessary to support such warranty. Specific
testing of all parameters, with the exception of those mandated by government requirements, of each product
is not necessarily performed.
Certain applications using Hifn products may involve potential risks of death, personal injury, or severe
property or environmental damage (“Critical Applications”). Hifn products are not designed, intended,
authorized, or warranted to be suitable for use in life saving, or life support applications, devices or systems
or other critical applications. Inclusion of Hifn products in such critical applications is understood to be fully at
the risk of the customer. Questions concerning potential risk applications should be directed to Hifn through a
local sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards. “Typical”
parameters can and do vary in different applications. All operating parameters, including “Typicals,” should be
validated for each customer application by the customer’s technical experts.
Hifn does not warrant that its products are free from infringement of any patents, copyrights or other
proprietary rights of third parties. In no event shall Hifn be liable for any special, incidental or consequential
damages arising from infringement or alleged infringement of any patents, copyright, or other third party
intellectual property rights.
The use of this product in stateful compression protocols (for example, PPP or multi-history applications) with
certain configurations may require a license from Motorola. In such cases, a license agreement for the right to
use Motorola patents may be obtained through Hifn or directly from Motorola.
Patents
May include one or more of the following United States patents: 4,701,745; 5,003,307; 5,016,009;
5,126,739; 5,146,221; 5,414,425; 5,463,390; 5,506,580; and 5,5532,694. Other patents pending.
Trademarks
®
®
®
®
TM
Hi/fn , MeterFlow , MeterWorks , and LZS , are registered trademarks of Hi/fn, Inc. Hifn
,
TM
FlowThrough , and the Hifn logo are trademarks of Hi/fn, Inc. All other trademarks and trade names are the
property of their respective holders.
IBM, IBM Logo, and IBM PowerPC are trademarks of International Business Machines Corporation in the United
States, or other countries.
Microsoft, Windows, Windows NT and the Windows logo are trademarks of Microsoft Corporation in the United
States, and/or other countries.
Exporting
This product may only be exported from the United States in accordance with applicable Export Administration
Regulations. Diversion contrary to United States laws is prohibited.
Hifn Confidential
If you have signed a Hifn Confidential Disclosure Agreement that includes this document as part of its subject
matter, please use this document in accordance with the terms of the agreement. If not, please destroy the
document.
820x – Data Sheet, DS-0157-D
Hifn Confidential
Page 2
Table of Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1 Product Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
1.1.7
High Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flexible Design for Packet Processing . . . . . . . . . . . . . . . . . . . .
Engine Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command and Data Endian Conversion Modes . . . . . . . . . . . . . .
DMA Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Integrity Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Other features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
21
21
22
22
22
22
1.2
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.1
Data Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.1.1
2.1.2
2.1.3
ECC & Parity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CRC Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real Time Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
27
27
2.1.3.1 Compression Engine Real Time Verification . . . . . . . . . . . . . . 28
2.1.3.2 Encryption Engine Real Time Verification . . . . . . . . . . . . . . . . 29
2.1.3.3 Hash Engine Real Time Verification . . . . . . . . . . . . . . . . . . . . 30
2.1.4
2.1.5
Data Integrity Model for Encode Operations . . . . . . . . . . . . . . . .
Data Integrity Model for Decode Operations. . . . . . . . . . . . . . . .
31
33
2.2
Clock Domains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
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2.3
Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3 Data Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.1
Command Pointer Ring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.1.1
3.1.2
Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . .
39
41
3.1.2.1 Desc_result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.1.2.2 Desc_cmd_base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.1.2.3 Desc_cmd_cmp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.1.2.4 Desc_cmd_enc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.1.2.5 Desc_cmd_hash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.1.2.6 Desc_cmd_pad. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.1.2.7 Desc_srcX and Desc_dstX . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.1.3
Command Structure Conventions . . . . . . . . . . . . . . . . . . . . . . .
67
3.1.3.1 Initial Hash engine Value (IHV) . . . . . . . . . . . . . . . . . . . . . . 67
3.1.3.2 MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.1.3.3 Initialization Vector (IV) and Additional Authenticated Data (AAD)
71
3.1.3.4 Key Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.1.3.5 Data Stream Information Fields . . . . . . . . . . . . . . . . . . . . . . 76
3.1.3.6 Hash Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.1.3.7 IPAD & OPAD for HMAC & SSL3.0-MAC (SHA256 | MD5) . . . . . 79
3.1.3.8 AES-GCM and GMAC Operations . . . . . . . . . . . . . . . . . . . . . . 80
3.1.3.9 MAC Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.1.3.10 IPsec Packet Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.1.4
Free Pool Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
3.2
3.3
Result Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Command Operation Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
4 Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.1
Encode Operations Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
4.1.1
4.1.2
4.1.3
4.1.4
Hash Engine before Compression Engine . . . . . . . . . . . . . . . . . .
Hash Engine after Compression Engine . . . . . . . . . . . . . . . . . . .
Hash Engine after Pad Engine. . . . . . . . . . . . . . . . . . . . . . . . .
Hash Engine after Encryption Engine. . . . . . . . . . . . . . . . . . . .
98
99
100
101
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4.2
Decode Operations Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.2.1
4.2.2
4.2.3
4.2.4
Hash Engine before Encryption Engine. . . . . . . . . . . . . . . . . . .
Hash Engine after Encryption Engine. . . . . . . . . . . . . . . . . . . .
Hash Engine after Pad Engine. . . . . . . . . . . . . . . . . . . . . . . . .
Hash Engine after Compression Engine . . . . . . . . . . . . . . . . . .
102
103
104
105
5 Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.1
DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
PCIe Outbound Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCIe Inbound Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Pointer Ring Prefetch . . . . . . . . . . . . . . . . . . . . . . .
Read Request Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Request Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Completion Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
107
107
107
108
109
109
5.2
5.3
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Channel Manager. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
Channel Manager Inbound Data Controller. . . . . . . . . . . . . . . .
Channel Manager Source Buffer . . . . . . . . . . . . . . . . . . . . . . .
Channel Manager Outbound Data Controller. . . . . . . . . . . . . . .
Channel Manager Result Buffer. . . . . . . . . . . . . . . . . . . . . . . .
Channel Manager Data Process Controller . . . . . . . . . . . . . . . .
110
111
111
112
112
5.4
PKP Manager. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
PKP Inbound Data Controller . . . . . . . . . . . . . . . . . . . . . . . . .
PKP Source Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PKP Outbound Data Controller . . . . . . . . . . . . . . . . . . . . . . . .
PKP Result Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PKP Interface Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PKP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
113
113
113
114
114
114
5.5
5.6
RNG Engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Hash Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.6.1
5.6.2
5.6.3
5.6.4
Hash In_AFIFO & Out_AFIFO . . . . . . . . . . . . . . . . . . . . . . . . .
Hash_AFIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hash Interface Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hash Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
115
115
115
116
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5.6.4.1 Hash Core Operation Modes. . . . . . . . . . . . . . . . . . . . . . . . 116
5.6.4.2 Hash Core Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.7
5.8
5.9
LZS Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.7.1
5.7.2
5.7.3
LZS In_AFIFO & Out_AFIFO . . . . . . . . . . . . . . . . . . . . . . . . . .
LZS Core Interface Controller. . . . . . . . . . . . . . . . . . . . . . . . .
LZS Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
122
122
122
GZIP Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.8.1
5.8.2
5.8.3
GZIP In_AFIFO & Out_AFIFO . . . . . . . . . . . . . . . . . . . . . . . . .
GZIP Core Interface Controller . . . . . . . . . . . . . . . . . . . . . . . .
GZIP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
123
123
124
Pad Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.10 Encryption Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.10.1 Encryption In_AFIFO & Out_AFIFO . . . . . . . . . . . . . . . . . . . . .
5.10.2 Encryption Interface Controller. . . . . . . . . . . . . . . . . . . . . . . .
5.10.3 Encryption AES and 3DES Cores . . . . . . . . . . . . . . . . . . . . . . .
125
125
125
5.11 Clock and Reset Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.12 Temperature Sensor Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
6 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.1
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
820x Error Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
820x Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . .
820x Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . .
Soft Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Minor Revision Register. . . . . . . . . . . . . . . . . . . . . . . .
Card Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
130
131
133
135
137
138
139
6.2
DMA Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
Command Pointer Ring 0 Base Address Register. . . . . . . . . . . .
Command Pointer Ring 0 Write Pointer Register . . . . . . . . . . . .
Command Pointer Ring 0 Read Pointer Register . . . . . . . . . . . .
Command Pointer Ring 1 Base Address Register. . . . . . . . . . . .
Command Pointer Ring 1 Write Pointer Register . . . . . . . . . . . .
Command Pointer Ring 1 Read Pointer Register . . . . . . . . . . . .
140
141
141
142
143
143
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6.2.7
6.2.8
6.2.9
Result Ring 0 Base Address Register . . . . . . . . . . . . . . . . . . . .
Result Ring 0 Write Pointer Register . . . . . . . . . . . . . . . . . . . .
Result Ring 1 Base Address Register . . . . . . . . . . . . . . . . . . . .
144
144
145
145
146
147
147
148
151
155
6.2.10 Result Ring 1 Write Pointer Register . . . . . . . . . . . . . . . . . . . .
6.2.11 Free Pool Ring Base Address Register . . . . . . . . . . . . . . . . . . .
6.2.12 Free Pool Write Pointer Register . . . . . . . . . . . . . . . . . . . . . . .
6.2.13 Free Pool Read Pointer Register . . . . . . . . . . . . . . . . . . . . . . .
6.2.14 DMA Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.15 Channel Manager 0-1 Error Status Register . . . . . . . . . . . . . . .
6.2.16 Channel Manager 0-1 Error Command Index Register . . . . . . . .
6.3
6.4
Engine Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
6.3.1 Hash Engine Mute Table Entry Registers . . . . . . . . . . . . . . . . . 156
Public Key Processor Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .158
6.4.1
6.4.2
Public Key Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . .
Public Key Command Entry Registers . . . . . . . . . . . . . . . . . . .
158
159
6.4.2.1 Public Key Command Register Format . . . . . . . . . . . . . . . . . 161
6.4.2.2 Public Key Instruction Register Format . . . . . . . . . . . . . . . . 163
6.4.2.3 Public Key Data Register Format. . . . . . . . . . . . . . . . . . . . . 165
6.4.2.4 Public Key Result Register . . . . . . . . . . . . . . . . . . . . . . . . . 168
6.4.3
Public Key Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . .
170
6.5
RNG Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
RNG Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RNG Test Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RNG Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . .
RNG Interrupt Control/Status Register . . . . . . . . . . . . . . . . . .
RNG Buffer Control/Status Register. . . . . . . . . . . . . . . . . . . . .
RNG Buffer Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
RNG Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . .
171
171
172
174
176
177
178
6.6
GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
GPIO Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Software Data Register . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . .
GPIO Interrupt Mask Register. . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Interrupt Type Register. . . . . . . . . . . . . . . . . . . . . . . . .
179
180
180
181
182
182
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6.6.7
6.6.8
6.6.9
GPIO Interrupt Polarity Register . . . . . . . . . . . . . . . . . . . . . . .
GPIO Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . .
GPIO Interrupt Raw Status Register . . . . . . . . . . . . . . . . . . . .
183
183
184
184
185
185
186
6.6.10 GPIO De-Bounce Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.11 GPIO Interrupt Clear Register. . . . . . . . . . . . . . . . . . . . . . . . .
6.6.12 GPIO Interrupt Ext Register . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.13 GPIO Interrupt Sync Register. . . . . . . . . . . . . . . . . . . . . . . . .
6.7
Serial/Parallel Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
6.7.6
6.7.7
6.7.8
SPI Register Operation flow . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Command Address Register . . . . . . . . . . . . . . . . . . . . . . .
SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI User Defined Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Command Configuration 0 Register. . . . . . . . . . . . . . . . .
Flash Command Configuration 1 Register. . . . . . . . . . . . . . . . .
187
190
191
193
194
195
196
197
6.8
Temperature Sensor Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . .198
6.8.1
6.8.2
6.8.3
TSC Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSC Command Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
198
198
200
7 PCIe Configuration Register Definition . . . . . . . . . . . . . . . . . . . 201
7.1
Type 0 PCIe Compatible Configuration Space . . . . . . . . . . . . . . . . . . . . . .203
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . .
Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
203
204
205
207
209
209
209
210
210
210
211
212
212
7.1.10 BIST Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.11 Base Address Register 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.12 Base Address Register 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.13 Cardbus CIS Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . .
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7.1.14 Sub-System Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . .
7.1.15 Sub-System ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.16 Expansion ROM Base Address Register . . . . . . . . . . . . . . . . . .
7.1.17 Capabilities Pointer Register. . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.18 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.19 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.20 Min_Gnt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.21 Max_Lat Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
212
213
213
214
214
214
214
214
7.2
Power Management Capabilities Registers. . . . . . . . . . . . . . . . . . . . . . . . .215
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Next Capabilities Pointer Register . . . . . . . . . . . . . . . . . . . . . .
Power Management Capabilities Register. . . . . . . . . . . . . . . . .
Power Management Control/Status Register. . . . . . . . . . . . . . .
PMCSR-BSE Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
215
215
216
217
218
218
7.3
7.4
MSI Capability Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Next Capabilities Pointer Register . . . . . . . . . . . . . . . . . . . . . .
Message Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Message Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
Message Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
219
220
221
222
222
PCI Express Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Next Capabilities Pointer Register . . . . . . . . . . . . . . . . . . . . . .
PCIe Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Capabilities (DEV_CAP) Register. . . . . . . . . . . . . . . . . .
Device Control (DEV_CTL) Register. . . . . . . . . . . . . . . . . . . . .
Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Capabilities Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
223
224
224
225
228
230
232
233
234
7.5
Advanced Error Reporting Capability Registers . . . . . . . . . . . . . . . . . . . . .235
7.5.1
7.5.2
7.5.3
Enhanced Capability Header Register . . . . . . . . . . . . . . . . . . .
Uncorrectable Error Status Register . . . . . . . . . . . . . . . . . . . .
Uncorrectable Error Mask Register . . . . . . . . . . . . . . . . . . . . .
237
238
239
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7.5.4
7.5.5
7.5.6
7.5.7
Uncorrectable Error Severity Register . . . . . . . . . . . . . . . . . . .
Correctable Error Status Register . . . . . . . . . . . . . . . . . . . . . .
Correctable Error Mask Register . . . . . . . . . . . . . . . . . . . . . . .
Advanced Error Capabilities and Control Register . . . . . . . . . . .
240
241
242
243
8 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
8.1
8.2
8.3
8.4
8.5
8.6
PCI Express Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Miscellaneous Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
GPIO/Probe Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
JTAG Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Power and Ground Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
9 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
9.1
9.2
9.3
Error Detection Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Error Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Error Handling Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
10 DC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
10.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
10.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
10.3 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
10.3.1 Digital Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.2 Analog Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
252
252
10.4 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
10.5 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
10.6 I/O Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
11 AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
11.1 Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
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11.2 PLL Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
11.3 Flash Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
11.4 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
11.5 PCIe Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
12 Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
12.1 Heat Sink Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
12.2 Junction Temperature Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
12.3 Thermal Sensor Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
13 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
13.1 General Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
13.2 Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
14 Errata. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Appendix A: IPsec Encapsulating Security Payload (ESP) Format 273
Appendix B: CRC Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Appendix C: AES CBC/XTS FK Generation . . . . . . . . . . . . . . . . . . . 277
Appendix D: MAC and IPAD and OPAD . . . . . . . . . . . . . . . . . . . . . . 281
Addendum I Document Revision History . . . . . . . . . . . . . . . . . . . . 284
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List of Figures
Figure 1-1. Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 2-1. 820x Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 2-2. Compression Engine LZS Real Time Verification . . . . . . . . . . . . . . . . . .28
Figure 2-3. Compression Engine GZIP Real Time Verification. . . . . . . . . . . . . . . . . .29
Figure 2-4. Encryption Engine Real Time Verification . . . . . . . . . . . . . . . . . . . . . . .30
Figure 2-5. Hash Engine Real Time Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 2-6. Encode Operation Real Time Verification . . . . . . . . . . . . . . . . . . . . . . .32
Figure 2-7. Decode Operation Real Time Verification . . . . . . . . . . . . . . . . . . . . . . .34
Figure 2-8. 820x Modules that can be Clock Gated. . . . . . . . . . . . . . . . . . . . . . . . .36
Figure 3-1. Command Pointer Ring Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 3-2. Command Pointer Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 3-3. Dual Command Ring Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 3-4. Normal Mode Command Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 3-5. Small Packet Mode Command Structure. . . . . . . . . . . . . . . . . . . . . . . .41
Figure 3-6. Endian Format Field Swap Options. . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Figure 3-7. Basic Data Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Figure 3-8. Partial IHV Field for a Stateful HMAC Operations . . . . . . . . . . . . . . . . . .68
Figure 3-9. Partial IHV Field for a Stateful XCBC-MAC Operations . . . . . . . . . . . . . .68
Figure 3-10. Partial IHV Field for a Stateful AES-GCM-MAC/GMAC Operations . . . . . .68
Figure 3-11. Partial IHV Field for a Stateful SSL3.0-MAC Operations . . . . . . . . . . . .69
Figure 3-12. MAC Field Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Figure 3-13. AES IV Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Figure 3-14. Key Format 1 (72 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Figure 3-15. Key Format 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Figure 3-16. Key Format 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Figure 3-17. Key Format 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Figure 3-18. Hash Entry Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Figure 3-19. Hash Buffer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Figure 3-20. AES-GCM Implementation Illustration . . . . . . . . . . . . . . . . . . . . . . . .80
Figure 3-21. IPsec Example: Applying IPPCP and ESP in Tunnel Mode . . . . . . . . . . .83
Figure 3-22. Free Pool Ring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Figure 3-23. Free Pool Usage Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Figure 3-24. Result Ring Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Figure 3-25. Command Process Flow Example. . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Figure 4-1. Encode Operation: Hash Engine before Compression Engine. . . . . . . . . .99
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Figure 4-2. Encode Operation: Compression Engine before Hash Engine. . . . . . . . .100
Figure 4-3. Encode Operation: Hash Engine after Pad Engine . . . . . . . . . . . . . . . .101
Figure 4-4. Encode Operation: Hash Engine after Encryption Engine . . . . . . . . . . .102
Figure 4-5. Decode Operation: Hash Engine before Encryption Engine . . . . . . . . . .103
Figure 4-6. Decode Operation: Hash Engine after Encryption Engine . . . . . . . . . . .104
Figure 4-7. Decode Operation: Hash Engine after Pad Engine . . . . . . . . . . . . . . . .105
Figure 4-8. Decode Operation: Hash Engine after Compression Engine. . . . . . . . . .106
Figure 5-1. DMA Command Pointer Prefetch Example. . . . . . . . . . . . . . . . . . . . . .108
Figure 5-2. Channel Manager Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Figure 5-3. PKP Manager Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Figure 5-4. Hash Engine Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Figure 5-5. Application Example of Slice Hash + File Hash . . . . . . . . . . . . . . . . . .117
Figure 5-6. SHA Core Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 5-7. MD5 Core Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 5-8. LZS Engine Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
Figure 5-9. GZIP Engine Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Figure 5-10. Pad Engine Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Figure 5-11. Encryption Engine Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .125
Figure 5-12. Die Temperature Measurement Procedure . . . . . . . . . . . . . . . . . . . .127
Figure 6-1. PCIe Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 6-2. PKP Command Entry Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
Figure 6-3. SPI Example Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 6-4. SPI Operation Flash Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
Figure 7-1. 820x PCI-Express Configuration Space. . . . . . . . . . . . . . . . . . . . . . . .202
Figure 8-1. Example PLL Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Figure 11-1. Flash Write Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 11-2. Flash Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 11-3. JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Figure 13-1. Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Figure 13-2. Ball Map Drawing - Top View - Upper Left Quadrant. . . . . . . . . . . . . .263
Figure 13-3. Ball Map Drawing - Top View - Upper Right Quadrant. . . . . . . . . . . . .264
Figure 13-4. Ball Map Drawing - Top View - Lower Left Quadrant. . . . . . . . . . . . . .265
Figure 13-5. Ball Map Drawing - Top View - Lower Right Quadrant. . . . . . . . . . . . .266
Figure A-1. IPsec ESP Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Figure C-1. GCM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Figure C-2. CBC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Figure D-1. IPAD and OPAD Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
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List of Tables
Table 1-1. 820x Engine Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 1-2. Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 2-1. Description of 820x Major Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 3-1. CRC Enable Behavior for all Commands except AES-XTS. . . . . . . . . . . . .46
Table 3-2. PAD_AG[3:0] Field Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 3-3. MAC Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Table 3-4. Command Structure Values for IPsec Example . . . . . . . . . . . . . . . . . . . .83
Table 3-5. GZIP Decode Error Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Table 5-1. Temperature Sensor Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Table 7-1. Register Type Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 8-1. PCIe Interface Signal Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
Table 8-2. Miscellaneous Interface Signal Definition. . . . . . . . . . . . . . . . . . . . . . .246
Table 8-3. Miscellaneous Interface Signal Definition. . . . . . . . . . . . . . . . . . . . . . .247
Table 8-4. SPI Interface Signal Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
Table 8-5. JTAG Interface Signal Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
Table 8-6. Power and Ground Interface Description . . . . . . . . . . . . . . . . . . . . . . .248
Table 10-1. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
Table 10-2. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . .251
Table 10-3. VDD_25_33 Power Supply Requirements. . . . . . . . . . . . . . . . . . . . . .252
Table 10-4. VDD_10 Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . .252
Table 10-5. VDD_25A Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . .252
Table 10-6. VDD_10A Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . .253
Table 10-7. VDDA_PLL0, VDDA_PLL1 Power Supply Requirements . . . . . . . . . . . .253
Table 10-8. 8204 Current and Power Per Power Domain. . . . . . . . . . . . . . . . . . . .253
Table 10-9. 8203 Current and Power Per Power Domain. . . . . . . . . . . . . . . . . . . .254
Table 10-10. 8202 Current and Power Per Power Domain . . . . . . . . . . . . . . . . . . .254
Table 10-11. 8201 Current and Power Per Power Domain . . . . . . . . . . . . . . . . . . .255
Table 10-12. Normal IO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255
Table 10-13. PCIe PHY Transmitter Characteristics . . . . . . . . . . . . . . . . . . . . . . .256
Table 10-14. PCIe PHY Receiver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .256
Table 11-1. PLL0 and PLL1 Reference Clock Requirements . . . . . . . . . . . . . . . . . .257
Table 11-2. Flash Interface AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .258
Table 11-3. JTAG Interface AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .259
Table 12-1. Thermal Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 13-1. General Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
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Table 13-2. Alphabetical Ball List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Table 13-3. Numeric Ball List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Table 14-1. 820x Major vs, Minor Revision Matrix . . . . . . . . . . . . . . . . . . . . . . . .271
Table A-1. IPsec ESP Packet Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . .273
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Preface
Welcome to the Data Sheet for Hifn’s 820x, a high performance, low power, compression/
encryption/hash acceleration processor. This document describes the 820x operation, data
structures, data flow and specifications.
Audience
This document is intended for:
• Project managers
• System engineers
• Hardware and software development engineers
• Marketing and product managers
Prerequisite
Before proceeding, you should generally understand:
• PCI Express
• GZIP, eLZS and AES algorithms
• Hash, MAC algorithms
• General networking concepts
Document Organization
This document is organized as follows:
Chapter 1, “Product Description" provides an overview of the 820x processor.
Chapter 2, “Operation" describes key features of the 820x operations.
Chapter 3, “Data Structures" defines the format of the data structures used by the 820x.
Chapter 4, “Data Flow" gives examples of the typical data flows within the 820x.
Chapter 5, “Modules" describes the internal 820x modules in more detail.
Chapter 6, “Register Definition" details the syntax and usage of the internal 820x registers.
Chapter 7, “PCIe Configuration Register Definition" details the syntax and usage of the
PCIe registers.
Chapter 8, “Signal Description" defines the external interfaces for the 820x device.
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Chapter 9, “Error Handling" describes the 820x error handling features.
Chapter 10, “DC Specifications" defines the 820x DC specifications (all are TBD at this
time).
Chapter 11, “AC Specifications" defines the 820x AC specifications (all are TBD at this
time).
Chapter 12, “Thermal Specifications" defines the 820x thermal specifications.
Chapter 13, “Package Specifications" defines the 820x package specifications.
Appendix A through Appendix D provide detailed information on how the algorithm are
calculated. This material is included for reference only. Hifn’s SDK automatically implements
these algorithms.
Related Documents
The following documents can be used as a reference to this document.
UG-0211
AN-0197
820x Design Guidelines User Guide
820x Performance Application Note
Customer Support
For technical support about this product, please contact your local Hifn sales office,
representative, or distributor.
For general information about Hifn and Hifn products refer to: www.hifn.com
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Glossary
Term
AAD
AES
CBC
CM
Definition
Additional Authentication Data
Advanced Encryption Standard
Cipher Block Chaining
Channel Manager
Command Pointer Ring
Cyclic Redundancy Check
Counter Mode
CPR
CRC
CTR
DES
DH
Data Encryption Standard
Diffie-Hellman key exchange protocol
Data Integrity Field for AES-XTS
Data Process Channel
DIF
DPC
DSA
DSS
ECB
ECC
ECDH
ECDSA
ECRC
eLZS
ESP
Digital Signature Algorithm
Digital Signature Standard
Electronic Codebook
Error correction code
Elliptic-Curve Diffie-Hellman
Elliptic-Curve Digital Signature Algorithm
End-to-End cyclic Redundancy Check
Enhanced LZS
Encapsulating Security Payload
Galois Message Authentication Code
GNU ZIP
GMAC
GZIP
HMAC
IHV
Hash Message Authentication Code
Initial Hash Value
Inner Padding
IPAD
IPPCP
IPsec
IV
IP Payload Compression Protocol
IP Security Protocol
Initial Vector
Joint Test Action Group
Lempel-Ziv Stac
JTAG
LZS
Message Authentication Code
Outer Padding
MAC
OPAD
PHY
Physical-Layer interface - usually for PCI express
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Term
PKP
PLL
RC
Definition
Public Key Processor
Phase-Locked Loop
PCIe Root Complex
Random Number Generator
RNG
RSA
S0
Ron Rivest, Adi Shamir and Leonard Adleman
Initial Value for Hash Engine GCM-MAC and GMAC calculation
Serial Peripheral Interface
SPI
Security Socket Layer
SSL
TLS
XTS
Transport Layer Security
XES-based Tweaked CodeBook mode with Cipher Text Stealing
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1 Product Description
Hifn’s 820x is a high-performance, low-power, look-aside acceleration device that is ideal
for both storage and networking markets. The 820x provides hardware acceleration of
compression, encryption and hashing algorithms including GZIP, LZS, AES, 3DES, SHA,
MAC and some public key algorithms such as DH, RSA, ECC. The 820x has a PCIe 2.0 Gen1
compliant interface to communicate with the host system.
Figure 1-1 shows a typical 820x application example. The 820x can be employed on a half-
height PCIe card to accelerate encryption, hash and LZS/GZIP compression.
Figure 1-1. Application Example
1.1 Features
1.1.1
High Performance
• Dual channel compression, encryption, pad, and hash engines
• Compression/Decompression engine with LZS and GZIP algorithms
• Encryption/Decryption engine supports:
• AES-GCM, CBC, CTR and ECB with 128, 192 or 256 bit keys
• AES-XTS with 256 or 512 bit keys
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• 3DES
• Hash engine supports:
• SHA1, SHA256
• MD5
• HMAC, GMAC, X-CBC-MAC and SSL3.0 MAC
• Public Key Processor
• Random Number Generator
• Compression, Encryption, Padding, MAC (Hash) in single pass
• Low Power
• Static clock gating of channels
• Dynamic clock gating for unused processing engines
• Dynamic clock gating of unused algorithm core in processing engine
1.1.2
Flexible Design for Packet Processing
• Position of the Hash engine for calculating MAC is programmable
• Truncated data stream head and tail pointers in each processing engine for packet
processing
• Programmable mute table to null the 16 byte packet header
• Programmable length MAC inserted into data stream
1.1.3
Engine Features
Table 1-1. 820x Engine Features
Engine
Features
LZS
Industry-standard LZS algorithm
Enhanced LZS (eLZS) algorithm with anti-expansion compression
Complies with RFC 1951, and RFC 1952
GZIP
Dynamic Huffman Algorithm for high compression ratio
Supports multiple algorithms:
Encryption
AES-GCM, -XTS, -CBC, -CTR and -ECB and 3DES
Supports 128, 192 and 256 bit keys for AES (except XTS mode)
Supports 256 and 512 bit keys for AES-XTS
Supports stateful encryption operation
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Table 1-1. 820x Engine Features
Engine
Features
Hash
Algorithms supported: HMAC-SHA1, HMAC-SHA256, HMAC-MD5, GMAC, X-
CBC-MAC, SSL3.0-MAC
Slice and file hash operation
MAC inserted into the data stream
Stateful hash and MAC operation
Pad
PKP
Supports padding with multiple algorithm in encode operation
Remove padding in decode operation
RSA, DSA, DH, and ECDH and ECDSA (elliptic curve) operations
Support up to 8K-bits modular arithmetic and exponentiation
1.1.4
Command and Data Endian Conversion Modes
• No swap
• Byte swap in word
• Word swap, no byte swap in word
• Word swap, and byte swap in word
1.1.5
DMA Features
• Indirect command addressing
• Unlimited scatter-gather
• Maximum 16K commands in command pointer ring
• Two command pointer rings with round-robin arbitration (the priority of command
pointer rings is handled by host software)
• Free pool ring to avoid result data overflow
• Small packet command structure mode
1.1.6
Data Integrity Features
• Input CRC32 check, output CRC32 generator
• ECRC protection through PCIe bus (requires host RC support)
• ECC or Parity protection for data path RAMs
• Real time verification for all data transformation (Encryption and Compression
engines), and hash or MAC calculation (Hash engine)
1.1.7
Other features
• PCI Express x4, PCI Express x1 or PCI Express x2 interface
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• JTAG support
• ACJTAG support for PCIe interface
• GPIO interface
• SPI interface to access flash chip
• Thermal diode on chip to manage and prevent device overheating
• 196 ball HSBGA package (15 x 15 mm body, 1 mm ball pitch)
1.2 Ordering Information
There are four speed variations and three process variations of the 820x device.
Table 1-2. Part Numbers
Part Number
8201IB
Process
Speed
Industrial
1.2 Gbps Acceleration Processor
1.2 Gbps Acceleration Processor
8201IB-F
Industrial, RoHS 6
compliant
8201CB
Commercial
1.2 Gbps Acceleration Processor
1.2 Gbps Acceleration Processor
8201CB-F
Commercial, RoHS 6
compliant
8202IB
Industrial
2.4 Gbps Acceleration Processor
2.4 Gbps Acceleration Processor
8202IB-F
Industrial, RoHS 6
compliant
8202CB
Commercial
2.4 Gbps Acceleration Processor
2.4 Gbps Acceleration Processor
8202CB-F
Commercial, RoHS 6
compliant
8203IB
Industrial
4.8 Gbps Acceleration Processor
4.8 Gbps Acceleration Processor
8203IB-F
Industrial, RoHS 6
compliant
8203CB
Commercial
4.8 Gbps Acceleration Processor
4.8 Gbps Acceleration Processor
8203CB-F
Commercial, RoHS 6
compliant
8204IB
Industrial
6.0 Gbps Acceleration Processor
6.0 Gbps Acceleration Processor
8204IB-F
Industrial, RoHS 6
compliant
8204CB
Commercial
6.0 Gbps Acceleration Processor
6.0 Gbps Acceleration Processor
8204CB-F
Commercial, RoHS 6
compliant
Note: The performance data is based on preliminary AES algorithm simulations.
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2 Operation
Figure 2-1 shows a block diagram of the 820x. Each block is defined in Table 2-1.
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Figure 2-1. 820x Block Diagram
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Table 2-1. Description of 820x Major Blocks
Block Name
Description
CC
Completion Controller
Receives the completion data from the PCIe Inbound Manager, and then
allocates the data to the proper Channel/PKP Manager according to the
tags.
CFG_REGS
Configuration Registers
Channel Manager
0/1
Channel Manager 0 and Channel Manager 1
Controls all command processing: fetching command structures and data
from host memory into the source buffer, transmitting results from the
result buffer to host memory.
CLK_RST_Gen
CPP
Clock and Reset Generation
Generates the clock and reset signals for all modules.
Command Pointer Ring Prefetch
Prefetches the command pointer from the command ring.
Encryption Engine
Encrypt Engine
Encrypts/Decrypts the data stream using the AES or 3DES algorithm.
General Purpose IO
GPIO
GZIP Engine
GZIP Engine
Compresses/Decompresses the data stream using the GZIP algorithm.
Hash Engine
Hash Engine
LZS Engine
Calculates the hash value or MAC value of the data stream.
LZS Engine
Compresses/Decompresses the data stream using the LZS or enhanced LZS
(eLZS) algorithm.
Pad Engine
Pad Engine
Adds/Removes padding data from the data stream.
PCI express end point controller
PCI express physical layer
PCIe Inbound Manager
PCIe Core
PCIe Serdes
PIM
Receives the PCIe completion from the PCIe Core, and sends/receives
memory read/memory write to/from the PCIe Core.
PKP Engine
Public Key Processor Engine
The PKP engine consists of two pairs of public key processors.
PKP Manager
PKP Manager
Controls instruction and operand data fetching from host memory to the
PKP engine, and transmits the calculated result from the PKP engine to host
memory.
POM
PCIe Outbound Manager
Sends the PCIe write data and read requests to the PCIe Core.
Random Number Generator
RNG
RRC
Read Request Controller
Arbitrates read requests from the CPP, Channel Manager 0, Channel
Manager 1 and PKP Manager, and sends read requests to the PCIe
Outbound Manager.
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Table 2-1. Description of 820x Major Blocks
Block Name
SPI
Description
SPI interface that connects to the external flash chip
Temperature Sensor Controller
TSC
Provides host software access to the temperature sensor parameters.
Write Request Controller
WRC
Arbitrates the write requests from Channel Manager 0, Channel Manager 1
and PKP Manager, and sends the write requests to the PCIe Outbound
Manager.
2.1 Data Integrity
The 820x provides robust data integrity with a combination of Error Code Correction (ECC),
CRC, and Real Time Verification (RTV). These features combine to create strong data
protection for encode and decode operations.
2.1.1
ECC & Parity Protection
All data in RAM is protected with 6-bit Error Code Correction (ECC6), 8-bit Error Code
Correction (ECC8) and parity.
• ECC6 is used to protect 16 bit width RAM
• ECC8 is used to protect 64 bit width RAM
• Parity is used to protect the PCIe Core RAMs
ECC6 and ECC8 provide detection of all single, double, and triple bit errors.
2.1.2
CRC Protection
The host may configure the PCIe configuration register to either enable/disable ECRC
protection. If enabled, the PCIe Core will generate the ECRC on the fly to protect data on
the PCIe bus.
Data CRC can be generated by the host or by the 820x, depending on the configuration
settings in the command structure. Please refer to the “CRC_EN” field of the Command
Structure for more information (Section 3.1.2.2). The CRC will be verified by the 820x, and
may be sent to the host or stripped from the data stream.
2.1.3
Real Time Verification
The Compression, Encryption and Hash engines contain internal real time verification logic
that ensures all transforms are completed successfully and any detected errors are reported
prior to the command completing.
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2.1.3.1
Compression Engine Real Time Verification
The Compression engine contains one compression core and one decompression core for
LZS and GZIP compression operations. Data for compression operations in the encode
direction will be automatically decompressed to verify that the decompressed CRC matches
the original CRC of the raw data. The Compression engine also employs an ECC in its FIFO.
For compression operations in the encode direction, raw data with an embedded CRC is
compressed by the compression core. The compressed data is then decompressed to verify
that the decompressed CRC matches the original input CRC. If the CRCs do not match, the
Compression engine reports a CRC error to the host. To add further real time verification, a
6-bit ECC is added to the compressed data before it is written to the destination FIFO. This
ECC is verified by the LZS Engine when reading data out from the destination FIFO.
For compression operations in the decode direction, the compressed data with an
embedded CRC is decompressed in the decompression core. The decompressed CRC is
verified by the decompression core, and if an error is detected it will be reported to the
host. If CRC32 is not enabled, this CRC check is also disabled.
Figure 2-2 illustrates LZS real time verification in the Compression engine for encode and
decode operations. In the following figures, a CRC in parenthesis, as in RAW (CRC),
signifies that the CRC is embedded into the data. A CRC that is added to a value, as in RAW
+ CRC, signifies that the CRC is in a header, separate from the data.
Figure 2-2. Compression Engine LZS Real Time Verification
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Figure 2-3 illustrates GZIP real time verification in the Compression engine. The GZIP real
time verification is similar to the LZS real-time verification except that the Compression
engine does not generate the ECC.
Figure 2-3. Compression Engine GZIP Real Time Verification
2.1.3.2
Encryption Engine Real Time Verification
The Encryption engine contains two encryption cores and two decryption cores for AES and
3DES operations. The Encryption engine performs real time verification for both encode and
decode operations by having both cores encrypt or decrypt the input data simultaneously.
The results from both cores are compared and if an error is detected it will be reported to
the host.
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Figure 2-4. Encryption Engine Real Time Verification
2.1.3.3
Hash Engine Real Time Verification
The Hash engine contains two hash cores to implement real time verification of the data.
For single File hash and Slice hash operations, both Hash cores calculate the hash/MAC
simultaneously and the two results are compared. If an error is detected it will be reported
to the host. For “File hash + Slice hash” operations, one core calculates the “File hash” and
the other core calculates the “Slice Hash”. Figure 2-5 shows the real time verification for
File hash and Slice hash operations.
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Figure 2-5. Hash Engine Real Time Verification
2.1.4
Data Integrity Model for Encode Operations
This section describes the data integrity model for encode operations using the parity, CRC,
ECC and engine real time verification features described in the previous sections. Figure 2-
6 illustrates the model described below.
Raw data with a PCIe standard CRC (ECRC) from the host enters the 820x over the PCIe
bus through the 820x PCIe core. The PCIe core verifies the ECRC and generates parity
before writing the data into RAM and into the PCIe Inbound Manager (PIM). The PIM
verifies the parity and generates an 8-bit Error Correction Code (ECC8) and enters the data
plus the ECC8 into the source buffer. When a Channel Manager reads the data from the
source buffer, it first verifies the ECC, generates a CRC, and sends the raw data and CRC
to the Compression engine. The Compression engine compresses the data and CRC,
performs real time verification by decompressing the data and verifying the CRC, and sends
the data to the Pad engine. The Pad engine adds padding to the data stream, and sends the
padded data to the encryption engine (the Pad engine does not perform any real time
verification). The Encryption engine encrypts the padded compressed data, performs real
time verification, and sends the result to the Hash engine. The Hash engine calculates the
MAC and performs real time verification on the hash result.
An 8-bit ECC is added to the output data of the Encryption engine and written into the
result buffer. The Channel Manager reads the data from the result buffer, verifies the ECC,
and sends the data to the PCIe Outbound Manager (POM). The POM adds parity before
writing the data into the PCIe Core RAM. When data is read from the PCIe Core RAM by the
PIM, the parity is first verified and an ECRC is generated before the final transformed data
is sent to the host.
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The example shown in Figure 2-6 where the 820x generates the embedded CRC rather
than the host supplying it is the most popular configuration.
Figure 2-6. Encode Operation Real Time Verification
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2.1.5
Data Integrity Model for Decode Operations
This section describes the data integrity model for decode operations using the parity, CRC,
ECC and engine real time verification features described in the previous sections. Figure 2-
7 illustrates the model described below.
Compressed, encrypted data with an embedded hash, and MAC arrive from the host over
the PCIe bus with the standard PCIe CRC (ECRC) and enters the 820x through the 820x
PCIe core. The PCIe core verifies the ECRC and generates parity before writing the data into
RAM and into the PCIe Inbound Manager (PIM). The PIM verifies the parity and generates
an 8-bit Error Correction Code (ECC8) and enters the data plus the ECC8 into the source
buffer. When a Channel Manager reads the data from the source buffer, it first verifies the
ECC, and the sends the encrypted, compression data with padding to the Hash engine and
the Encryption engine. The Hash engine uses the embedded MAC and performs real time
verification on the hash result. The Encryption engine decrypts the encrypted data and
sends the padded compressed data result to the Pad engine. The Pad engine removes the
padding from the data stream, and sends the compressed data to the compression engine
(the Pad engine does not perform any real time verification). The compression engine
decompresses the data and CRC, performs real time verification.
The CRC output from the compression engine is compared to the raw CRC, and, if verified,
stripped from the raw data. An 8-bit ECC is added to the raw data and written into the
result buffer. The Channel Manager reads the data from the result buffer, verifies the ECC,
and sends the data to the PCIe Outbound Manager (POM). The POM adds parity before
writing the data into the PCIe Core RAM. When data is read from the PCIe Core RAM by the
PIM, the parity is first verified and an ECRC is generated before the final raw data is sent to
the host.
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Figure 2-7. Decode Operation Real Time Verification
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2.2 Clock Domains
The 820x logic operates with six main clock domains:
• PCIe Serdes, PCIe Core, DMA, Probe, Pad engine and JTAG (125MHz from PCIe
Serdes PLL)
• Hash Engine (278MHz from CLK_RST_Gen)
• LZS Engine interface logic and Encrypt Engine (208MHz from CLK_RST_Gen)
• LZS Engine Core Logic (417MHz from CLK_RST_Gen)
• GZIP Engine (250MHz from CLK_RST_Gen)
• PK Core (375MHz from CLK_RST_Gen)
2.3 Clock Gating
Hifn’s 820x supports aggressive static and dynamic clock gating.
Static clock gating will disable the clock to the Channel Managers, Data Process Channels,
PKP Manager, PKP Engine, and RNG if the corresponding register enable bits are set to
zero. If the software disables a Channel Manager, the clock to all modules in this channel
will also be disabled.
Dynamic clock gating will disable the clock for all unused engines in Data Process Channels
for each command. For example, if one command only compresses data, the clock of the
Pad Engine, Hash Engine and Encrypt Engine will be gated automatically.
The shaded regions in Figure 2-8 show which 820x blocks employ clock gating.
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Figure 2-8. 820x Modules that can be Clock Gated
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3 Data Structures
This section describes the 820x data structures for the command pointer ring, result ring,
free pool ring, and the command structure format.
3.1 Command Pointer Ring
The command pointer ring is a linear array of command pointers which point to the actual
commands. The 820x uses indirect command addressing to execute commands. By using
indirect command addressing, the commands themselves may be located anywhere in host
memory.
The host software must maintain the command pointer ring and ensure that the command
pointer ring base address is 8-byte aligned.
In 32-bit addressing mode, every command pointer is 4 bytes; in 64-bit addressing mode,
every command pointer is 8 bytes.
Figure 3-1. Command Pointer Ring Format
The maximum number of command pointers in the command pointer ring is configurable by
the host using the DMA control registers, specifically the DMA Configuration Register (see
Section 6.2.14, “DMA Configuration Register"). After the host software determines the
memory location of the command pointer ring and command structure, it should update the
820x related DMA control registers. The 820x will fetch the command pointer, and then
fetch the command structure. The detailed command execution flow is described in
Section 3.3, “Command Operation Sequence".
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Figure 3-2 illustrates a typical command pointer ring structure.
Figure 3-2. Command Pointer Ring
Typically the host would maintain only one command ring, but the Express DX 17xx also
supports a dual command ring mode. In this mode, the host maintains two command
pointer rings and two result rings in host memory. The Express DX 17xx Software
Development Kit will place all higher priority commands in one command ring and the lower
priority commands into the other command ring. However, since the Express DX 17xx
fetches commands from both command rings using a round-robin scheme with equal
priority, there is no assurance that the high priority ring will execute commands faster than
the low priority ring. If the host can assure that there are fewer high priority commands
than low priority commands, a priority scheme can be supported.
The two command pointer rings and result rings have the same structures and
configuration as shown in Figure 3-3.
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Figure 3-3. Dual Command Ring Mode
Command rings are implemented in PCIe host memory. The host writes a complete
command structure as an entry in the command pointer ring. The 820x reads the command
structure and interprets its various fields to perform the appropriate operations. Once the
820x has completed executing a command, it updates the appropriate entries within the
corresponding command structure. The host then reads the entries in the command
structure that have been updated by the 820x to fetch the results.
The 820x does not maintain a “full” bit for the command pointer ring; it is the responsibility
of the host not to overflow the command ring.
3.1.1
Command Structure
The host must ensure that the starting address of all command structures are 512-byte
aligned. This constraint will avoid the PCIe 4K boundary read request limitation because the
820x maximum command read request is 512 bytes.
The 820x supports two command structure modes: normal mode and small packet mode.
The command structure mode is defined in the Desc_cmd_base descriptor. In normal
mode, the data may be any size. In small packet mode, the size is reduced to improve
small packet performance. The performance improvement of small packet mode is achieved
by removing the data read request latency of 2000ns ~ 8000ns.
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A normal mode command structure consists of a linear array of descriptors. The size of one
command structure is only limited by the amount of host contiguous physical memory. Each
command will have a unique command structure.
In normal mode, the command structure includes one result descriptor, one base command
descriptor, one compression command descriptor, one encryption command descriptor, one
hash command descriptor, one pad command descriptor, and several pairs of source and
destination descriptors.
Figure 3-4. Normal Mode Command Structure
A small packet mode command structure includes one result descriptor, one base command
descriptor, one compression command descriptor, one encryption command descriptor, one
hash command descriptor, one pad command descriptor, two destination descriptors and
data. The data field includes information fields and the source data.
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Figure 3-5. Small Packet Mode Command Structure
3.1.2
Command Descriptor Format
Descriptors are the building blocks of the 820x command structure.
Note: For all descriptors, reserved bits must be written as zeroes.
3.1.2.1
Desc_result
The result descriptor holds the command result. After the 820x completes a command, it
will write to this descriptor. The Desc_result format is the same (8 bytes) for either 32-bit
or 64-bit addressing modes.
Reserved
FileSize[47:32] / Dest_byte_count[47:32]
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
FileSize[31:0] / Dest_byte_count[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
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Field Name
Description
Bits
Default
OVFL
Overflow bit.
The 820x will set this bit if the destination data size
exceeded the total destination buffer space. This bit
will not be set if the Free Pool is being used.
63
0
0
1
No destination buffer overflow occurred
Destination buffer overflow occurred
ERR
FP
Error bit.
The 820x will set this bit if any type of error
occurred during command processing.
62
0
0
1
No error occurred
Error occurred
Free Pool bit.
If all destination buffers are consumed and the FP_V
bit in the Desc_cmd_base is set, the 820x will set
this bit to indicate it is using the Free Pool to store
the result data. Once the 820x uses the Free Pool,
the 820x will not longer set the the OVFL bit.
61
60
59
0
0
0
0
1
820x is not using the free pool
820x is using the free pool
Reserved
DONE
Reserved
Done bit.
This bit is written to and read by both the host and
820x. The host software must set this bit to one
after the command structure is written. The 820x
will write a zero to this but when it has completed a
command.
0
1
820x has completed the command
Host has set up the command for the 820x
CMP_EXP
Reserved
Compression Expansion bit.
This bit defines how the compression expansion is
calculated.
58
0
0
0
1
Len(cmp) + Head_size < Len(RAW)
Len(cmp) + Head_Size >= len(raw)
57:48
Reserved
File_Size[47:0] /
Dest_byte_count[47:0]
File Size / Destination Data Byte Count.
This field contains the File Size or Destination Data
Byte Count used to calculate the hash or MAC value
of the last block of source data.
The data in the source buffer includes information
fields and raw data. The File size indicates the size
of the raw data, excluding the information fields.
47:0
0
This field is written to and read by both the host
and the 820x.
The host must write the file size to this field for file
hash, AES-GCM, or MAC length padding operations.
The 820x will overwrite this field with the
Dest_byte_count[47:0] after the command
completes.
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3.1.2.2
Desc_cmd_base
This descriptor defines the command parameters that are common to all types of
commands. The Desc_cmd_base format is 8 bytes for either 32-bit or 64-bit addressing
modes.
Reserved
Packet_Size[8:0]
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Reserved
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Reserved
Bits
Default Description
63:41
0
Reserved
Packet_size[8:0]
Packet Size.
This field is only valid when Command Structure
Mode, CSM, is set to small packet mode.
The packet size will vary with the command
addressing mode (32 or 64-bit addressing) and the
size of the information field (see Section 3.1.3.5).
This field indicates the real source data size, not
including the information and descriptor fields. Note,
for small packet mode, the total command size must
be less than or equal to 512 bytes.
The packet size range in bytes is:
1 - maximum_packet_size
where
40:32
0
Maximum_packet_size = 512 - (info field) -
(descriptor field)
| Total cmd structure size must be <= 512 bytes |
Info field
Desc field
Source data
|
packet_size[8:0]
|
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Field Name
Bits
Default Description
CRC_EN[1:0]
CRC Enable.
The CRC enable bit is only valid if the disable count
flag, DC, is set to one.
The behavior of this bit depends if the command is
for AES-XTS.
For all commands except AES-XTS:
00 The input data does not contain a CRC; the
820x will not append or verify the CRC
01 For an encode command, the input data
contains 4 bytes of CRC; the 820X will verify the
CRC. For a decode command, the 820X will
verify the CRC after decoding and send the data
and the 4 bytes of CRC to the host.
10 For an encode command, the input data does
not contain a CRC; the 820x will append and
verify 4 bytes of CRC. For a decode command,
the 820x will verify the CRC after decoding, strip
the 4 bytes of CRC, and send only the raw data
to the host
31:30
0
11 Reserved.
For AES-XTS commands:
00 The input data does not contain a CRC; the
820x will not append or verify the CRC
01 For both encode or decode operations, the 820x
will verify the source data CRC and update the
CRC field of the DIF.
1x Reserved.
DIF Format:
4 bytes
Ref tag
2 bytes
CRC
2 bytes
Meta tag
For a more detailed description of the CRC_EN bit’s
behavior for all commands except AES-XTS, please
refer to Table 3-1.
EF[1:0]
IRQ_EN
Endian Format.
Sets the data endian format. Refer to Figure 3-6 for
an illustration of the swap options.
00 no swap
29:28
0
0
01 byte swap within word
10 word swap, no byte swap within word
11 word swap and byte swap within word
Interrupt Enable.
If set, the 820x will interrupt the host when this
command completes.
27
0
820x will not interrupt the host when this
command completes
1
820x will interrupt the host when this command
completes
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Field Name
Bits
Default Description
FP_V
Free Pool Valid.
This bit is written to by the host to indicate if the
820x may use the Free Pool
Note, if the Free Pool is not used and the
destination buffers are not large enough to
accommodate the resulting data, the 820x will set
the OVFL bit in Desc_result descriptor.
26
0
0
1
Do not allow the 820x to use the free pool
Permit 820x to use the free pool
DC
Disable Count.
If this bit is set, the 820x will process all raw data
sent to it by the host and disregard the head and
tail count values. If set, the host software does not
need to set values for the source count and head
counters; the 820x will ignore these fields.
25
0
0
All source and head counts in successive
descriptors are valid.
1
Disable all source and head counts in successive
descriptors
DIR
Disable Information Routing.
Refer to Section 3.1.3.5, “Data Stream Information
Fields" for more information.
24
0
0
820x will send the information fields to the host
destination buffer for data integrity verification
1
820x will not send the information fields to the
host destination buffer
Reserved
PAD
23:11
10
0
0
Reserved.
Pad Engine Enable/Disable.
If disabled, data will pass through the Pad engine
unaltered.
0
1
Disable the Pad engine
Enable the Pad engine
HASH
ENC
Hash Engine Enable/Disable.
If disabled, data will pass through the Hash engine
unaltered.
9
8
7
0
0
0
0
1
Disable the Hash engine
Enable the Hash engine
Encryption Engine Enable/Disable.
If disabled, data will pass through the Encryption
engine unaltered.
0
1
Disable the Encryption engine
Enable the Encryption engine
CMP
Compression Engine Enable/Disable.
If disabled, data will pass through the Compression
engine unaltered.
0
1
Disable the Compression engine
Enable the Compression engine
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Field Name
Bits
Default Description
CSM
Command Structure Mode.
This bit sets the command structure mode to either
normal or small packet mode. Refer to Section
3.1.1 for more information.
6
0
0
0
1
Normal mode
Small packet mode
Reserved
CMD
5:1
Reserved
Command Type.
Indicates the command type:
0
Encode
For compression, encryption and hash
operations
1
Decode
0
0
For decompression and decryption operations,
and authentication using the hash engine to
verify the MAC
Note that the 820x supports stateful encryption and
hash/MAC operations, but does not support stateful
compression operations. The host software must not
submit a compression operation when performing a
stateful MAC operation.
Table 3-1. CRC Enable Behavior for all Commands except AES-XTS
CRC_EN Operation
Value
Host input to 820x
820x Output
00
N/A
Data
Data
820x does not verify or append a
CRC
01
Encode
Decode
Data
4 bytes CRC
Compressed (Data + CRC)
820x verifies CRC and compresses
input data
Compressed (Data + CRC)
Data
4 bytes CRC
820x decompresses input data and
verifies CRC
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Table 3-1. CRC Enable Behavior for all Commands except AES-XTS
CRC_EN Operation
Value
Host input to 820x
820x Output
10
Encode
Data
Data
4 bytes CRC
Compressed (Data + CRC)
820x adds CRC and then
compresses the input data and CRC
Decode
Compressed (Data + CRC)
Data
4 bytes CRC
Data
820x decompresses input data,
verifies CRC, and then removes CRC
11
Encode
Decode
Reserved
Reserved
Reserved
Reserved
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Figure 3-6. Endian Format Field Swap Options
3.1.2.3
Desc_cmd_cmp
This descriptor defines the compression engine related parameters. Desc_cmd_cmp is 8
bytes for either 32-bit or 64-bit addressing modes.
CMP_Source_Count[23:0]
CMP_Header_Count[7:0]
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
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Reserved
HEAD_SIZE[7:0]
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Default
CMP_Source_Count
[23:0]
Compression Source Count.
The number of bytes of compression data.
The data stream following the header will be
processed by the compression engine. The
compression engine will stop processing data and
return to passing through the remaining data in
data stream after the Compression Source Counter
reaches zero. The 820x Compression Source
Counter begins to decrement after the Compression
Head Counter has expired.
The behavior of this field depends on the setting of
compression count mode, CMP_CM.
63:40
0
If CMP_CM = 0,
0
All data from Head Counter expired to EOB (end
of block) need to be processed by the
current engine
1 - 2241 to 224 bytes need to be processed by the
current engine
If CMP_CM =1,
0 - 2240 to 224 bytes after the last byte processed
by the previous processing engine need
to be processed by current engine
CMP_Header_Count
[7:0]
Compression Header Count.
This 8-bit field sets the number of double words that
the compression engine will pass through before it
begins processing the incoming data stream.
39:32
0
GZIP_MODE[1:0]
GZIP Operation Mode.
00 Static Huffman mode
01 Dynamic Huffman mode
10 Store mode
31:30
29:16
0
0
11 Reserved
In Store mode, GZIP is added to the header but the
data is unchanged.
Reserved
Reserved.
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Field Name
Description
Bits
Default
HEAD_SIZE[7:0]
Head Size.
The number of bytes required for the compression
expansion calculation.
0 - 255: Head size in bytes
15:8
0
The Compression engine will set the cmp_expansion
bit (defined in the desc_result and result ring) to
one if
len(cmp) + Head_Size >= len(raw).
CMP_CM
Compression Count Mode.
If this bit is set to zero, the compression source
count in the 820x begins to decrement after the last
header byte has been passed through the 820x. If
this bit is set to one, the compression source
counter begins to decrement after the last byte
processed by the previous processing engine. Please
refer to Section 3.1.3.10, “IPsec Packet Processing"
for more information.
7
0
0
820x begins to decrement the compression
source count after the last header byte
1
820x begins to decrement the compression
source count after the last byte processed by
the previous processing engine
Reserved
6:2
1:0
0
0
Reserved.
CMP_AG[1:0]
Compression Algorithm.
Used to set the compression algorithm.
00 LZS algorithm
01 eLZS algorithm
10 GZIP algorithm
11 Reserved
3.1.2.4
Desc_cmd_enc
This descriptor defines the encryption engine related parameters. Desc_cmd_enc is 8 bytes
for either 32-bit or 64-bit addressing modes.
ENC_Source_Count[23:0]
ENC_Header_Count[7:0]
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Sector_Size[23:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
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Field Name
Description
Bits
Default
ENC_Source_Count
[23:0]
Encryption Source Count.
The number of bytes of encryption data.
The data stream following the header will be
processed by the encryption engine. The encryption
engine will stop processing data and return to
passing through the remaining data in data stream
after the Encryption Source Counter reaches zero.
The 820x Encryption Source Counter begins to
decrement after the Encryption Head Counter has
expired.
The behavior of this field depends on the setting of
encryption count mode, ENC_CM.
63:40
0
If ENC_CM = 0,
0
All data from Head Counter expired to EOB (end
of block) need to be processed by the
current engine
1 - 2241 to 224 bytes need to be processed by the
current engine
If ENC_CM =1,
0 - 2240 to 224 bytes after the last byte processed
by the previous processing engine need
to be processed by current engine
ENC_Header_Count
[7:0]
Encryption Header Count.
This 8-bit field sets the number of double words that
the encryption engine will pass through before it
begins processing the incoming data stream.
39:32
31:8
0
0
Sector_Size[23:0]
Sector Size.
Sector size in 4 byte words.
This field represents the sector size when
ENC_AG[3:0] is set to the AES-XTS algorithm.
Note that the sector size does not include the DIF (8
bytes) for XTS.
Because the minimum sector size is 128 bytes, a
sector size of 0x000000 to 0x00001F translates to
0x000020 words.
KS[1:0]
AES Key Size.
00 128 bit key
01 192 bit key
10 256 bit key
7:6
0
11 512 bit key (only valid for AES-XTS)
Note: AES-XTS only supports 256 and 512 bit keys.
Other AES modes support 128, 192 and 256 bits
keys.
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Field Name
Description
Bits
Default
ENC_CM
Encryption Count Mode.
If this bit is set to zero, the encryption source
count in the 820x begins to decrement after the last
header byte has been passed through the 820x. If
this bit is set to one, the encryption source counter
begins to decrement after the last byte processed
by the previous processing engine. Please refer to
Section 3.1.3.10, “IPsec Packet Processing" for
more information.
5
0
0
0
820x begins to decrement the encryption
source count after the last header byte
1
820x begins to decrement the encryption
source count after the last byte processed by
the previous processing engine
Reserved
4
Reserved.
ENC_AG[3:0]
Encryption Algorithm.
0000AES-GCM
Hash engine should be set to AES-GCM-MAC
algorithm
0001AES-CBC
0010AES-CTR
0011AES-ECB
0100AES-XTS
3:0
0
Compression Engine must be disabled and
Hash_OP[1:0] cannot be set any type of
MAC operation
01013DES
All other settings are reserved.
Note: GMAC operations use the AES algorithm. If
sharing logic with other AES modes, the GMAC will
be implemented in the Encryption Engine.
3.1.2.5
Desc_cmd_hash
This descriptor defines the hash engine related parameters. Desc_cmd_hash is 8 bytes for
either 32-bit or 64-bit addressing modes.
During a Slice Hash operation, the Hash engine will calculate the hash value for every slice
of data. A single Slice Hash operation must contain more than one slice. The size of one
slice data is defined by Slice_Size[15:0].
During a File Hash operation, the Hash engine calculates one hash value for the entire file.
File Hash operations may be stateless or stateful. For a stateless file hash operation, one
command operates on data from one file and the “file hash chaining value” of this
command is the “File Hash” of the file (see Section 3.1.3.6). For a stateful file hash
operation, one data file is operated on by several commands, and each command is
assigned a file hash chaining value by the 820x. The file hash chaining value of the prior
final command is used as the “File hash” of the file.
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Note: Host software manages the stateful file hash operation flow. The software must wait
for one data block of the file from the current command to finish before proceeding to the
next block of the file in the next command. This is because the next command's IHV (initial
hash vector) will use the previous command's file chaining hash value.
Please refer to Section 3.1.3.6, “Hash Buffer" for a detailed description of a hash operation.
HASH_Source_Count[23:0]
HASH_Header_Count[7:0]
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Slice_Size[15:0]/AAD_Size[11:0]+MAC_Size[3:0]
MTI[3:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Default
HASH_Source_Count
[23:0]
Hash Source Count.
The number of bytes of hash data.
The data stream following the header will be
processed by the hash engine. The hash engine will
stop processing data and return to passing through
the remaining data in data stream after the Hash
Source Counter reaches zero. The 820x Hash
Source Counter begins to decrement after the Hash
Head Counter has expired.
Note: This field is NOT valid when performing the
last block of a stateful file hash operation.
The behavior of this field depends on the setting of
hash count mode, HASH_CM.
63:40
0
If HASH_CM = 0,
0
All data from Head Counter expired to EOB (end
of block) need to be processed by the
current engine
1 - 2241 to 224 bytes need to be processed by the
current engine
If HASH_CM =1,
0 - 2240 to 224 bytes after the last byte processed
by the previous processing engine need
to be processed by current engine
HASH_Header_Count
[7:0]
Hash Header Count.
This 8-bit field sets the number of double words that
the hash engine will pass through before it begins
processing the incoming data stream.
39:32
0
Note: This field is NOT valid when performing the
last block of a stateful file hash operation.
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Field Name
Description
Bits
Default
Slice_Size[15:0]
- or -
The value of this field depends on the type of hash
operation.
For slice hash operations (HASH_OP = 000 or 010),
this field represents the hash slice size.
bits [31:2] =
AAD_Size[11:0]
The slice size is in bytes and must be a multiple
of 64 bytes.
bits [19:16] =
MAC_Size[3:0]
Note: The total data size of one command can
be an arbitrary number of bytes. The 820x will
split the data into slices according to the
Slice_Size. If the last slice is less than the
Slice_Size, the 820x will pad the data with
zeroes so that it is a multiple of 64 bytes.
Each slice is treated as a complete hash
operation (with length padding). The 820x will
send the host the hash value per slice of data.
For AES-GCM-MAC hash operations (HASH_OP =
111) this field represents the Additional
Authenticated Data size, AAD_Size[11:0].
The AAD size values is in bytes with a range of
0x000 - 0xFFF, which translates into 0 - 4095
bytes
Note: In GMAC mode, the host software does
not need to fill out the AAD Size because the
AAD will be written to the Hash engine as source
data, and so the Hash engine will calculate the
length by itself. Please refer to Section 3.1.3.8,
“AES-GCM and GMAC Operations" for details on
GMAC operations.
31:16
0
For all hash MAC operations (HASH_OP = 011 or
1xx), this field represents MAC_Size[3:0].
For an encode operation, MAC_Size represents
the number of words that will be inserted into
the data stream.
0MAC is not inserted into the data stream
after calculated
1 - 15Insert 2 to 16 words into the data
stream
The number of inserted MAC words for MD5
is 16 bytes, for SHA1 20 bytes, for SHA2 32
bytes. The 820x will truncate the MAC value
according to the configuration before
inserted the MAC into the data stream.
For decode operations, MAC_Size represents the
MAC size on the information bus (see
Section 3.1.3.5, “Data Stream Information
Fields"). The hash engine will compare the
calculated MAC with the MAC on the information
bus of this length. For example, if the calculated
HMAC with SHA256 is 32 bytes and the
MAC_Size is 24 bytes, the hash engine will
compare the first 24 bytes of the calculated
HMAC with the MAC on the information bus.
This feature is useful in SSL. The MAC will be
inserted at the end of the data stream that is
processed by the hash engine.
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Field Name
Description
Bits
Default
MTI[3:0]
Mute Table Index.
This field selects the mute table entries to be used
on the first 16 bytes of the data stream processed
by the Hash engine.
0000Disable mute function
0001Mute table entry 1
0010Mute table entry 2
0011Mute table entry 3
0100Mute table entry 4
0101Mute table entry 5
0110Mute table entry 6
0111Mute table entry 7
All other values are not defined.
15:12
0
Please refer to Section 6.3.1, “Hash Engine Mute
Table Entry Registers" for details.
PS[1:0]
Hash Engine Position
This field’s behavior depends on whether the
operation is encode or decode.
For encode operations, the hash engine is:
00 Before the compression engine
01 After the compression engine
10 After the pad engine
11:10
0
11 After the encryption engine
For decode operations, the hash engine is:
00 Before the encryption engine
01 After the encryption engine
10 After the pad engine
11 After the compression engine
Please refer to Chapter 4, “Data Flow" for more
information.
HASH_CM
Hash Count Mode.
If this bit is set to zero, the hash source count in
the 820x begins to decrement after the last header
byte has been passed through the 820x. If this bit is
set to one, the hash source counter begins to
decrement after the last byte processed by the
previous processing engine. Please refer to
Section 3.1.3.10, “IPsec Packet Processing" for
more information.
9
0
0
820x begins to decrement the hash source
count after the last header byte
1
820x begins to decrement the hash source
count after the last byte processed by the
previous processing engine
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Field Name
Description
Bits
Default
LB
Last Block.
The host should set this bit to indicate the last block
of data. For stateful operations, data from one
command is considered one block.
8
0
0
1
For stateful operations, if not last block
For stateless operations, or for stateful
operations if last block
Please refer to Section 3.1.3.9, “MAC Operations"
for detailed usage of this bit.
FB
First Block.
The host should set this bit to indicate the first block
of data. For stateful operations, data from one
command is considered one block.
7
0
0
1
For stateful operations, if not first block
For stateless operations, or for stateful
operations if first block
Please refer to Section 3.1.3.9, “MAC Operations"
for detailed usage of this bit.
HASH_OP[2:0]
Hash operation.
000Slice hash only, internal integrity checking
001File hash only, internal integrity checking
010Slice hash + file hash, no internal integrity
checking
011HMAC, internal integrity checking
100SSL3.0 MAC, internal integrity checking
101XCBC-MAC, internal integrity checking
110GMAC, internal integrity checking;
Encryption engine must be disabled
111AES-GCM-MAC, internal integrity checking;
Encryption engine must be set to AES-GCM
algorithm
6:4
0
For encode operations, if PS == 00, Hash_OP may
be any one of the eight choices and the Hash engine
will calculate the hash or MAC. If PS != 00, the
Hash Engine will only calculate the MAC.
For decode operations, Hash_OP may only be set to
MAC operations (1xx). The Hash engine will
calculate the MAC and compare the calculated value
to the MAC in the data stream.
Note: If the operation is SSL3.0 MAC, the source
data in host memory should include "Seq. No. ||
Type || Length || Application Data". Please refer to
Appendix D.1 for details.
Note: If the operation is XCBC-MAC, GMAC or AES-
GCM-MAC, Hash0_AG and Hash1_AG are not valid
since these MACs use the AES algorithm core.
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Field Name
Description
Bits
Default
HASH1_AG[1:0]
Hash Core 1 algorithm.
This field is only valid when Hash_OP[3:0] = 0010.
In this case, Hash Core 0 will calculate the file hash
while Hash Core 1 calculates the slice hash.
For all other operations, Hash Core 1 is only used
for real time verification and must be set to the
same value as Hash Core 0.
3:2
0
00 SHA-1
01 SHA-256
10 MD5
11 Reserved
HASH0_AG[1:0]
Hash Core 0 algorithm.
00 SHA-1
1:0
0
01 SHA-256
10 MD5
11 Reserved
3.1.2.6
Desc_cmd_pad
This descriptor defines the pad engine related parameters. Desc_cmd_pad is 8 bytes for
either 32-bit or 64-bit addressing modes.
PAD_Source_Count[23:0]
PAD_Header_Count[7:0]
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Next_Head[7:0]
Reserved
PAD_Len[7:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
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Field Name
Description
Bits
Default
PAD_Source_Count
[23:0]
Pad Source Count.
The number of bytes of pad data.
The data stream following the header will be
processed by the pad engine. The pad engine will
stop processing data and return to passing through
the remaining data in data stream after the pad
Source Counter reaches zero. The 820x pad Source
Counter begins to decrement after the pad Head
Counter has expired.
The behavior of this field depends on the setting of
hash count mode, PAD_CM.
If PAD_CM = 0,
63:40
0
0
All data from Head Counter expired to EOB (end
of block) needs to be processed by the
current engine
1 - 2241 to 224 bytes need to be processed by the
current engine
If PAD_CM =1,
0 - 2240 to 224 bytes after the last byte processed
by the previous processing engine needs
to be processed by current engine
PAD_Header_Count
[7:0]
Pad Header Count.
This 8-bit field sets the number of double words that
the pad engine will pass through before it begins
processing the incoming data stream.
39:32
0
Next_Head[7:0]
Next Header.
This field is only valid when the ESP bit is set to
one.
The Next_Head[7:0] value is an IPv4/IPv6 protocol
number describing the format of the Payload data
field. The host software must this field for IPsec
packet processing.
For an encode operation, the host software must
enter this field into the command structure. The Pad
Engine will append it to the data stream.
31:24
0
For a decode operation, the host software should set
this field to zero when building the command
structure. The 820x will update this field after the
command completes.
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Field Name
Description
Bits
Default
ESP
ESP Header Pad.
For an encode operation,
0
The value of Next_Head[7:0] will not be
inserted by the pad engine.
1
Pad engine will pad Next_Head[7:0] with “pad”
and Pad_Len[7:0] for IPsec packet processing.
The ESP Trailer will also be included in the
Dest_byte_count.
For a decode operation,
0
Pad engine will extract the Pad_Len[7:0] field
from the data stream, and write the pad
length to the host command structure after the
command completes
1
Pad engine will extract Pad_Len[7:0] and
Next_Head[7:0] fields from the data stream,
and write the pad length and next header to
the host command structure after the
command completes
Note: For both encode and decode operations,
Pad_AG[3] must be set to one if ESP = 1.
23
0
Regardless of the ESP value, the Pad Engine will
always apply padding even if the data is already a
multiple of the MOD-X.
Please refer to Appendix A for more information
about ESP IPsec processing.
ESP Header Format for ESP = 0:
1 byte
Pad
Payload data
Pad Length
ESP Header Format for ESP = 1:
|--------------ESP Trailer----------|
1 byte
1 byte
Pad
Payload data
Pad Length
Next Header
Reserved
22:19
18:11
0
0
Reserved.
Pad_Len[7:0]
Pad Length.
This field is only valid for decode operations.
For a decode operation, the pad engine removes the
padding from the data stream. This field is the
number of bytes that the pad engine stripped from
the data.
The pad engine will extract this field from the data
stream.
Note: The host software should set this field to zero
when building the command structure. The 820x will
update this field in the command structure after the
command completes.
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Field Name
Description
Bits
Default
PAD_CM
Pad Count Mode.
If this bit is set to zero, the pad source count in the
820x begins to decrement after the last header byte
has been passed through the 820x. If this bit is set
to one, the pad source counter begins to decrement
after the last byte processed by the previous
processing engine. Please refer to Section 3.1.3.10,
“IPsec Packet Processing" for more information.
10
0
0
820x begins to decrement the pad source count
after the last header byte
1
820x begins to decrement the pad source
count after the last byte processed by the
previous processing engine
PAD_EN
Pad Check Enable.
This bit is only valid for decode operations.
0
Pad engine will remove and not verify the
padding values defined by PAD_AG[3:0]
9
8
0
0
1
Pad engine will remove and verify the padding
values defined by PAD_AG[3:0]
Reserved
Reserved.
PAD_MOD[2:0]
Pad Modulo.
This field is used to set the alignment of the payload
after padding has been added.
000MOD-4: the payload after padding is 4 bytes
aligned
001MOD-8: the payload after padding is 8 bytes
aligned
010MOD-16: the payload after padding is 16 bytes
aligned
7:5
0
011MOD-32: the payload after padding is 32 bytes
aligned
100MOD-64: the payload after padding is 64 bytes
aligned
101MOD-128: the payload after padding is 128
bytes aligned
110MOD-256: the payload after padding is 256
bytes aligned
111Reserved
Reserved
4
0
Reserved.
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Field Name
Description
Bits
Default
PAD_AG[3:0]
Pad Engine algorithm.
The behavior of this field depends if the operation is
encode or decode and the setting of the ESP field
(see Section 3.1.2.6).
Refer to Table 3-2 for the decode values for this
field.
For all algorithms, the pad length is the number of
bytes in the preceding Padding field, except for
setting 1010 when the pad length is the number of
bytes in the preceding Padding field plus the “pad
length” byte.
PAD_AG[3] indicates whether the pad length field is
included in the padding. If PAD_AG[3] = 0, the pad
length field is not included, and if
3:0
0000
PAD_AG[3] = 1, the pad length field is included.
PAD_AG[3] = 0, without Length byte
Pad
Payload data
PAD_AG[3] = 1, with Length byte
Pad
Payload data
Pad Length
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Table 3-2. PAD_AG[3:0] Field Decoding
Encode/ ESP
Decode
PAD_AG Description
[3:0]
Encode
0
0000
0001
0010
0011
0100
1000
1001
1010
Padding value is 0 - 255.
For example, if 5 bytes are required to pad out to modulo 8, 5 bytes
will be inserted, the padding will be 00, 01, 02, 03, 04.
Padding value 1 - 255 - 0.
For example, If padding 256 bytes, the padding will be 1, 2, 3, ...
255, 0.
Padding with same value, the value is the number of bytes inserted.
For example, If 5 bytes are required to pad out to modulo 8, 5
bytes will be inserted, the padding will be 05, 05, 05, 05, 05.
Padding will be all zeroes.
For example, If 5 bytes are required to pad out to modulo 8, 5
bytes will be inserted, the padding will be 00, 00, 00, 00, 00.
Padding with number of bytes minus one inserted.
For example, If 5 bytes are required to pad out to modulo 8, 5
bytes will be inserted, the padding will be 04, 04, 04, 04, 04.
Padding value 0 - 255, with pad length field.
For example, If 5 bytes are required to pad out to modulo 8, 5
bytes will be inserted, the padding will be 00, 01, 02, 03, 04.
Padding value 1 - 255 - 0, with pad length field.
For example, If 5 bytes are required to pad out to modulo 8, 5
bytes will be inserted, the padding will be 01, 02, 03, 04, 04.
Padding with same value, the value is the number of bytes inserted,
with pad length field.
For example, If 5 bytes are required to pad out to modulo 8, 5
bytes will be inserted, the padding will be 05, 05, 05, 05, 05.
1011
1100
Padding with all zero, with pad length field.
For example, If 5 bytes are required to pad out to modulo 8, 5
bytes will be inserted, the padding will be 00, 00, 00, 00, 04.
Padding with number of bytes inserted minus 1, with pad length
field.
For example, If 5 bytes are required to pad out to modulo 8, 5
bytes will be inserted, the padding will be 04, 04, 04, 04, 04.
All
others
Reserved.
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Table 3-2. PAD_AG[3:0] Field Decoding
Encode/ ESP
Decode
PAD_AG Description
[3:0]
Encode
1
0xxx
1000
Not allowed
Padding value 0 - 255, with pad length field and next_header.
For example, if 5 bytes are required to pad out to modulo 8, 5 bytes
will be inserted, the padding will be 00, 01, 02, 03, <next_header>.
1001
1010
Padding value 1 - 255 - 0, with pad length field and next_header.
For example, if 5 bytes are required to pad out to modulo 8, 5 bytes
will be inserted, the padding will be 01, 02, 03, 03, <next_header>.
Note: please refer to RFC 2406 (ESP) for this configuration.
Padding with same value, the value is the number of bytes inserted,
with pad length field and next_header.
For example, if 5 bytes are required to pad out to modulo 8, 5 bytes
will be inserted, the padding will be 04, 04, 04, 04, <next_header>.
1011
1100
Padding with all zeroes, with pad length field and next_header.
For example, if 5 bytes are required to pad out to modulo 8, 5 bytes
will be inserted, the padding will be 00, 00, 00, 03, <next_header>.
Padding with number of bytes inserted minus 1, with pad length
field and next_header.
For example, if 5 bytes are required to pad out to modulo 8, 5 bytes
will be inserted, the padding will be 03, 03, 03, 03, <next_header>.
All
others
Reserved.
Decode
0
0000
0001
0011
0100
1000
1001
No verification and removal (no pad length field)
No verification and removal (no pad length field)
No verification and removal (no pad length field)
No verification and removal (no pad length field)
Verify the removed padding value 0 - 255 and the pad length field
Verify the removed padding value 1 - 255 - 0 and the pad length
field
1010
1011
1100
Verify the removed padding of number of bytes inserted, and the
pad length field
Verify the removed padding value of all zeroes and the pad length
field
Verify the removed padding of number of bytes inserted minus one,
and the pad length field
All
others
Reserved.
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Table 3-2. PAD_AG[3:0] Field Decoding
Encode/ ESP
Decode
PAD_AG Description
[3:0]
Decode
1
0xxx
1000
Not valid.
Verify the removed padding value 0 - 255, pad length field; remove
next_header
1001
1010
1011
1100
Verify the removed padding value 1 - 255 - 0, pad length field;
remove next_header
Verify the removed padding of number of bytes inserted, pad length
field; remove next_header
Verify the removed padding value of all zeroes, pad length field;
remove next_header
Verify the removed padding value of all padding length value less
one, pad length field; remove next_header
All
others
Reserved.
3.1.2.7
Desc_srcX and Desc_dstX
This source descriptor is only used in normal mode. The source data descriptors point to
source data buffers. The source buffer address length may be an arbitrary number of bytes.
The source buffer address is byte aligned except for when the source buffer is used to store
the information fields for the “Key”, “IHV”, “MAC”, or “IV”, in which case its address should
be 8-byte aligned. If a source buffer contains information fields, it should not contain
source data.
The destination data descriptors point to the destination buffers. The destination buffer
address and length must be on an 8 byte boundary. Usually, the destination buffers are
used to store the result data, and must be fully consumed in order. For hash related
operations, the first destination buffer is used to store hash values only.
The source and destination descriptors both contain 8 bytes in the 32-bit addressing mode
and 16 bytes in the 64-bit addressing mode.
32-bit Addressing Mode Format:
BYTE_COUNT[30:0]
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
ADDR[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
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Field Name
Description
Bits
Default
Last
Last.
Used to identify the current descriptor as the last
valid descriptor in the command. The host software
must set this bit in the command structure.
Although the source and destination descriptors
must be in pairs in normal mode, the LAST flag
need NOT be set in the same pair. For example, the
source buffer LAST flag may be set at Dest_src2,
but the destination descriptor buffer LAST flag is set
at Dest_dst6.
63
0
Note: In small packet mode, there are two
destination descriptors but no source descriptors.
Byte_Count[30:0]
Byte Count.
The size of the source or destination buffer in bytes.
It indicates the size of the data block defined by this
descriptor.
62:32
0
For the source descriptor, the byte count is an
arbitrary number of bytes.
For the destination descriptor, the byte count must
be a multiple of 8 bytes.
ADDR[31:0]
Address.
The starting physical address of the source or
destination descriptor.
For source descriptors, including those that only
contain AAD, the address is byte aligned. If the
source buffers include the information fields “Key”,
“IV”, “IHV”,”MAC”, or “GZIP History”, the address
must be on an 8-byte boundary.
31:0
0
For destination descriptors, the address is always
aligned on an 8-byte boundary.
64-bit Addressing Mode Format:
BYTE_COUNT[30:0]
127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100
Reserved
99 98 97 96
95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
ADDR[63:32]
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
ADDR[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
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Field Name
Description
Bits
Default
Last
Last.
Used to identify the current descriptor as the last
valid descriptor in the command. The host software
must set this bit in the command structure.
Although the source and destination descriptors
must be in pairs in normal mode, the LAST flag
need NOT be set in the same pair. For example, the
source buffer LAST flag may be set at Dest_src2,
but the destination descriptor buffer LAST flag is set
at Dest_dst6.
127
0
Note: In small packet mode, there are two
destination descriptors but no source descriptors.
Byte_Count[30:0]
Byte Count.
The size of the source or destination buffer in bytes
and indicates the block size defined by the
descriptor.
126:96
95:63
0
0
For the source descriptor, the byte count is an
arbitrary number of bytes.
For the destination descriptor, the byte count must
be a multiple of 8 bytes.
Reserved
Reserved.
Address.
ADDR[63:0]
The starting physical address of the source or
destination descriptor.
For source descriptors, including those that only
contain AAD, the address is byte aligned. If the
source buffers include the information fields “Key”,
“IV”, “IHV”, ”MAC”, or “GZIP History”, the address
must be on an 8-byte boundary.
63:0
0
For destination descriptors, the address must be
aligned on an 8-byte boundary.
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3.1.3
Command Structure Conventions
This section designates some command structure conventions, clarifies some confusing
topics, and provides a better understanding of how a command structure is built.
All data streams described in this section are assumed to have the basic format shown
below:
Figure 3-7. Basic Data Sequence
3.1.3.1
Initial Hash engine Value (IHV)
For a hash related operations, the host software must write the Initial Hash Value (IHV) for
the hash engine in the proper place in the source buffer. IHV stands for not only the initial
hash operation value, but also the partial MAC operation value in stateful MAC operation.
Because a slice hash operation always uses the same default value, the host software need
not write the IHV for slice hash operations. The descriptions below apply for file hash and
all types of hash/MAC operations.
For a stateless hash operation or the first block of a stateful hash operation, the IHV is the
default value defined by the hash algorithm. For a stateful hash/MAC operation after the
first block, the host software should read the IHV (Partial hash/MAC result) from the hash
buffer (the first destination buffer is used as a hash buffer in a hash related command).
Default Initial Hash Vector for Hash Operations
The default value and size of the IHV depend on the hash algorithm. In the 820x, the host
software must pad the IHV to 256 bits for all algorithms before writing the IHV to the first
source buffer.
The examples below illustrate the default IHV after padding for three common hash
algorithms.
SHA1: IHV[0:255] ={ 67452301
efcdab89
98badcfe
h10325476
c3d2e1f0
96'd0};
SHA256: IHV[0:255] = { 6a09e667
bb67ae85
3c6ef372
a54ff53a
510e527f
9b05688c
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1f83d9ab
5be0cd19};
MD5: IHV[0:255] = { 67452301
efcdab89
98badcfe
10325476
128'd0};
Partial HMAC Value for Stateful Operations
For a stateful HMAC operation, the host software should write the partial HMAC value into
the IHV field for all blocks except the first.
Figure 3-8. Partial IHV Field for a Stateful HMAC Operations
Partial XCBC-MAC Value for Stateful Operations
For a stateful XCBC-MAC operation, the host software should write the partial XMAC-MAC
value into the IHV field for all blocks except the first.
Figure 3-9. Partial IHV Field for a Stateful XCBC-MAC Operations
Partial AES-GCM-MAC/GMAC Value for Stateful Operations
For a stateful AES-GCM-MAC or GMAC operation, the host software should write the partial
AES-GCM-MAC/GMAC value into the IHV field for all blocks except the first. Please refer to
Section 3.1.3.9, “MAC Operations" for a description of how to calculate s0.
Figure 3-10. Partial IHV Field for a Stateful AES-GCM-MAC/GMAC Operations
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Partial SSL3.0-MAC Value for Stateful Operations
For a stateful SSL3.0-MAC operation, the host software should write the partial SSL3.0-MAC
value into the IHV field for all blocks except the first.
Because the IHV is not protected by a CRC, the 820x will transmit the IHV to the host
destination buffer if the DIR bit in the Desc_cmd_base is set to one. The host software can
then determine whether the IHV has been corrupted.
Figure 3-11. Partial IHV Field for a Stateful SSL3.0-MAC Operations
3.1.3.2
MAC
For encode operations, the host software configures the Hash Engine's position in the data
processing channel and builds the command structure according to the application’s
requirement. The Hash Engine calculates the MAC value of the input data stream. The 820x
writes the resulting MAC value to the first entry of the hash buffer.
For decode operations, the host software writes the MAC value into the proper location of
the source buffer. The 820x Channel Manager will separate the MAC value from the source
data stream and put it on the hash information bus (Please refer to Section 3.1.3.5, “Data
Stream Information Fields" for details). The Hash Engine calculates the MAC value of the
input data stream, compares it with the value in the information bus, and then reports the
verified value or failure flag to the host. For a stateful MAC operation, the host software
should also write the partial MAC value into the IHV field. The MAC value field in the first
source buffer is fixed to 256 bits (32 bytes) as shown in Figure 3-12 below.
Because the MAC is not protected by a CRC, the 820x will transmit the MAC to the host
destination buffer. The host software can then determine whether the MAC has been
corrupted.
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Figure 3-12. MAC Field Format
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3.1.3.3
Initialization Vector (IV) and Additional Authenticated Data
(AAD)
All AES related operations except AES-ECB require a 16 byte initialization vector (IV) for
AES-CTR, AES-CBC, AES-XTS and GMAC, or a 32 byte initialization vector for AES-GCM, in
the source buffer. The 16 byte IV for AES-XTS is actually the logic address of the disk
sector. The Normal IV is the initial vector for the Encryption Engine AES algorithm and the
S0_IV is the initialization vector for the Hash Engine MAC operation AES algorithm.
As shown in Figure 3-13 below, the 16 byte IV for GMAC operations is the S0_IV (J0) for
the S0 calculation. AES-GCM requires 16 bytes of Normal_IV (J0) for the Encryption Engine
and another 16 bytes of S0_IV for the Hash engine. The Normal_IV and S0_IV are the
same value for stateless operation or for the first block of a stateful operation. The
Normal_IV and S0_IV will be different for the middle blocks and last block of a stateful
operation because the Normal_IV is not the first block initial value for the Encryption
engine, but S0_IV is the first block initial value for the Hash engine.
Figure 3-13. AES IV Lengths
Some AES-GCM related operations require Additional Authenticated Data (AAD) which is
authenticated but not encrypted.
In normal mode, the AAD can be written into a single source buffer, or several source
buffers. The length and address of a source buffer that only contains the AAD may be of
arbitrary length.
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In small packet mode, the host software must write the AAD into the command structure.
The AAD length must be padded so that it is aligned on an 8-byte boundary. For example,
if AAD_Size is equal to 57, the AAD field in the command structure would be 64 bytes
(padded with 7 bytes of zeroes).
Because the IV and AAD are not protected by a CRC, the 820x will transmit the IV and AAD
to the host destination buffer. The host software can then determine whether the IV or AAD
have been corrupted.
3.1.3.4
Key Format
For Encryption and Hash related operations, the host software must write the encryption
key to the 820x. The key must be located in the first source buffer and may have one of
the five formats described in this section.
For all key formats described in this section, reserved fields and the CRC verified “Key +
reserved fields” should be filled with zeroes when written by the host software.
The 820x will automatically verify the key CRC when reading the key, and report a “key
CRC error” to the host if the CRC verification failed. Although the key is CRC protected, the
820x will still write the key to the host destination buffer if the DIR bit in the
Desc_cmd_base descriptor is set to one.
Key Format 1: AES, 3DES
If the Encryption Engine and Hash Engine are both enabled and Hash_OP[3:0] is set to a
Slice Hash, File Hash or Slice + File Hash operation, the Hash Engine will calculate the hash
values without a key and the Encryption Engine will encrypt the data with a key. If the
Encryption Engine is disabled, AES commands will not require a key. This format for these
operations only includes the encryption key and requires 72 bytes.
If the Encryption engine and Hash engine are both enabled, and Hash_OP[3:0] is set to
GMAC or AES-GCM-MAC, the Encryption engine and Hash engine will use the same AES key
to separately calculate the cipher text and authentication value. This format for these
operations only includes the AES key and requires 72 bytes.
The key format shown in Figure 3-14 is used for AES and 3DES operations.
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Figure 3-14. Key Format 1 (72 bytes)
Key Format 2: HMAC, SSL3.0-MAC
If the Encryption and Hash engines are enabled and Hash_OP[3:0] is set to “HMAC” or
“SSL3.0-MAC (SHA256 or MD5)”, the Hash engine will calculate the MAC, and the IPAD and
OPAD fields must be generated by the host software according to the MAC key (please refer
to Section 3.1.3.7, “IPAD & OPAD for HMAC & SSL3.0-MAC (SHA256 | MD5)" for details).
If the Encryption and Hash engines are disabled, commands will not require keys. If only
the Encryption engine is disabled, the AES Key Field will be reserved. If only the Hash
engine is disabled, the IPAD and OPAD fields will be reserved.
Note: If ENC_AG[3:0] is set to XTS, Hash_OP[3:0] cannot be set to any MAC operation.
The 512 bit AES-XTS key is not permitted in this key format.
The key format shown in Figure 3-15 is used for HMAC and SSL3.0-MAC (SHA256 or MD5)
operations. This format includes the AES key, IPAD and OPAD and requires 104 bytes.
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Figure 3-15. Key Format 2
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Key Format 3: SSL3.0 MAC (SHA1)
If both the Encryption and Hash engines are enabled and Hash_OP[3:0] is set to “SSL3.0
MAC (SHA1)”, the Hash engine will calculate the SSL 3.0 MAC and requires the MAC Key.
Please refer to Section 3.1.3.9, “MAC Operations" for detail.
If both the Encryption and Hash engines are disabled, commands will not require keys. If
only the Encryption engine is disabled, the AES key field will be reserved. If only the Hash
Engine is disabled, the MAC key field will be reserved.
The key format shown in Figure 3-16 is used for SSL3.0 MAC (SHA1) operations. This
format includes the AES key and the MAC key and requires 72 bytes.
Figure 3-16. Key Format 3
Key Format 4: XCBC-MAC
If both the Encryption and Hash engines are enabled and Hash_OP[3:0] is set to “XCBC-
MAC”, the Hash engine will calculate the XCBC-MAC and requires a 128 bit XCBC-MAC Key.
If both the Encryption and Hash engines are disabled, commands will not require keys. If
only the Encryption engine is disabled, the AES key field will be reserved. If only the Hash
Engine is disabled, the XCBC-MAC key field will be reserved.
The key format shown in Figure 3-17 is used for XCBC-MAC operations. This format
includes the AES key and the XCBC-MAC key and requires 72 bytes.
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Figure 3-17. Key Format 4
3.1.3.5
Data Stream Information Fields
For some operations, the data stream will contain a mixture of the IHV, MAC, Key, IV and
AAD information fields. The sequence for these information fields in the source buffer is:
Key, IHV, IV, MAC, and AAD.
Source Buffer 0, Source Buffer 1, Source Buffer 2
Other Source Buffers
Source Data
Key
IHV
IV
MAC
AAD
If a command does not require all fields, those fields may be removed from the data
stream sequence. For example, a “Compression + encryption” command only requires the
Key, IV and AAD information fields.
Source Buffer 0, Source Buffer 1
IV AAD
Other Source Buffers
Source Data
Key
The 820x DMA will extract the information fields from the data stream and send them to
the appropriate engines on the information bus. Please note the actual data stream sent
into the 820x’s data processing channels does NOT include these information fields. When
calculating the “Head Count” and “Source Count” for the command structure, the host
software should exclude the information fields.
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All information bus fields except the AAD are aligned on an 8-byte boundary. Therefore, the
length of the source buffer with information fields are 8-byte aligned, except for a source
buffer that only contains the AAD. To simplify the software design, the input AAD is byte
aligned, but the output AAD is 8-byte aligned.
The 820x will write all information fields to the host destination buffer if the DIR bit in the
Desc_cmd_base descriptor is set to one. The host software can then determine if any of the
information fields have been corrupted. All information fields are located in the header of
the first destination buffer as shown in the example result data stream below.
Dest_byte_count includes all resultant output from the 820x.
Dest_byte_count = Destination Buffer 0, Destination Buffer 1
Key
IHV
IV
MAC
AAD
Result Data
Source buffers that contain information fields also can be handled in a scatter-gather
scheme to facilitate software packet processing. For example, the key field is a session
related parameter, while the other information fields are packet related parameters. The
host software can write the key into source buffer 0, setting the value for the whole
session. The other information fields, whose values change according to the packet, can be
saved into the remaining source buffers. In this way, the host software will not need to
copy the key repeatedly to host memory for the hundreds of packets for that session.
3.1.3.6
Hash Buffer
The Hash buffer is a dedicated buffer for storing hash values. The 820x will write to the
hash buffer before writing the command result entry into the destination buffer and the
result ring. The host software can be assured that when a command result is available, the
hash value for that command is also available.
The Hash buffer is actually the first destination buffer. If a command is hash related, the
first destination buffer will be used to store only the hash values; all destination data will be
written to host memory using the second destination buffer even if there is space remaining
in the hash buffer.
The hash buffer starting address and length must be aligned to 32-bytes, and for kernel
mode applications must be physically contiguous.
Every entry in the hash buffer is 256 bits to accommodate hash values of SHA-256, SHA-1,
MD5 and all MACs, therefore the hash buffer size must be a multiple of 256 bits. The hash
entry format is shown in Figure 3-18.
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Figure 3-18. Hash Entry Format
The first entry is always used to store the file hash chaining value or the MAC value; the
other entries are used to sequentially store the slice hash values.
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Figure 3-19. Hash Buffer Format
3.1.3.7
IPAD & OPAD for HMAC & SSL3.0-MAC (SHA256 | MD5)
SSL 3.0 MAC is a variation of the HMAC algorithm:
HMAC
MAC = H(K xor Pad2 || H(K xor Pad1 || M))
SSL 3.0 MAC
MAC = H(K || Pad2 || H(K || Pad1 || Seq. No. || Type || Length || Application Data))
The 820x uses an improved method to calculate the HMAC for better performance using the
IPAD and OPAD:
820x HMAC
MAC(K,M) = H(OPAD, H(IPAD,M))
The host software computes the IPAD and OPAD and writes the values to the 820x as the
key. The IPAD, derived from H(K xor Pad2) and the OPAD, derived from H(K xor Pad1) are
easily generated in software using a single 512 bit block hash.
This improved method may also be applied to SSL3.0 MAC so that the IPAD is derived from
H(K || Pad1) and the OPAD is derived from H(K || Pad2), the difference being the XOR and
||. If the host software works in SSL3.0 MAC mode, the input data should be “Seq. No. ||
Type || Length || Application Data”.
However, there is a special case for SSL 3.0 MAC using the SHA-1 algorithm. The designer
could easily make a mistake if the SHA-1 length of (K || Pad) is not 512 bits, and thus not
reuse the HMAC flow.
The recommended approach for computing the HMAC and SSL 3.0 MAC is:
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• For HMAC operations, the host software should pre-compute the IPAD and OPAD
using H(K xor Pad1) and H(K xor Pad2) and then write the data to the 820x.
• For SSL3.0-MAC (MD5 or SHA-256) operations, the host software should pre-
compute the IPAD and OPAD using H(K || Pad1) and H(K || Pad2) and then write
“Seq. No. || Type || Length || Data” to the 820x.
• For SSL3.0-MAC (SHA-1) operations, the host software should not pre-compute the
IPAD and OPAD and write K directly to the 820x using “Seq. No. || Type || Length ||
Data”.
3.1.3.8
AES-GCM and GMAC Operations
AES-GCM operation is different from other AES operations. The output of an AES-GCM
operation has two parts: a cipher text whose length is identical to the plain text, and an
authentication tag.
The cipher text is an output of the encryption engine, and the authentication tag is an
output of the hash engine. When performing AES-GCM operations, the host software must
enable both the encryption and hash engines.
Figure 3-20. AES-GCM Implementation Illustration
GMAC is a special case of AES-GCM mode in which the cipher text size equals zero. When
the 820x performs AES-GCM authenticated encryption, the Encryption engine performs the
encryption operation and then the hash engine performs the authentication operation. For
GMAC mode, the encryption and authentication occurs in the hash engine, using the AAD as
the input data.
3.1.3.9
MAC Operations
The 820x Hash engine supports stateless and stateful MAC operations. The MAC operation
is complex due to the number of parameters and operations, and the cooperation required
between the 820x and the software. Table 3-3 identifies the parameters that must be set
for different types of MAC operations.
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Table 3-3. MAC Operation Table (Sheet 1 of 2)
AES_ SSL3 XCB
GCM .0- C-
Key MAC MAC
Key Key
MAC Type FB
LB
IPAD OPA SO_I IHV
File Data
Size
State
D
V
HMAC
Arbitrary
Stateless
1
1
√
√
√
length
512-bit
aligned
First
Block
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
512-bit
aligned
Middle
Block
√
√
Arbitrary
length
Last
Block
√
√
√
√
√
XCBC-
MAC
Arbitrary
length
Stateless
√
128-bit
aligned
First
Block
√
128-bit
aligned
Middle
Block
√
√
√
Arbitrary
length
Last
Block
√
GCM-
MAC
Arbitrary
length
Stateless
√
√
√
√
√
128-bit
aligned
First
Block
128-bit
aligned
Middle
Block
√
√
Arbitrary
length
Last
Block
√
√
GMAC
Arbitrary
length
Stateless
128-bit
aligned
First
Block
128-bit
aligned
Middle
Block
√
√
Arbitrary
length
Last
Block
√
SSL3.0-
MAC
(SHA256
MD5)
Arbitrary
length
Stateless
√
√
√
√
512-bit
aligned
First
Block
512-bit
aligned
Middle
Block
√
√
Arbitrary
length
Last
Block
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Table 3-3. MAC Operation Table (Sheet 2 of 2)
AES_ SSL3 XCB
GCM .0- C-
Key MAC MAC
Key Key
MAC Type FB
LB
IPAD OPA SO_I IHV
File Data
Size
State
D
V
SSL3.0-
Arbitrary
Stateless
1
1
√
√
√
√
√
√
X
X
X
√
MAC
length
(SHA1)
512-bit
aligned
First
Block
1
0
0
0
0
1
512-bit
aligned
Middle
Block
Arbitrary
length
Last
Block
√
3.1.3.10
IPsec Packet Processing
The 820x has been optimized to maximize IPsec packet processing performance.
The 820x has four processing engines: compression, encryption, pad, and hash. The
processing order depends on whether the operation is encode or decode and the position of
the hash engine using the PS bits in the hash descriptor. Please refer to Chapter 4, “Data
Flow" for a detailed description of the operation sequence.
Each processing engine may be enabled or disabled. A disabled processing engine simply
passes data forward to the next processing unit without altering the data or modifying the
context.
Each processing engine has two counters: a Header Counter and a Source Counter. The
Header Counter is used to determine how many bytes the processing engine will pass
through before processing the data. This counter is useful to skip header fields in many
network communication protocols. The Source Counter determines how many bytes will be
processed by that processing engine. The Source Counter may be programmed to start
from the first byte to be processed, or after the last byte processed by the previous
processing engine. This flexibility takes into account the variable output sizes produced by
the compression and pad engines. Once the source count of a processing engine reaches
zero, any remaining bytes in the input data stream will be passed through the processing
engine without altering the data or modifying the context.
Figure 3-21 shows an example of how the 820x would processes an IPsec packet in
conjunction with the host software. This IPsec example illustrates how to apply IPPCP and
ESP in tunnel mode.
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Figure 3-21. IPsec Example: Applying IPPCP and ESP in Tunnel Mode
The 820x command structure controls each processing engine by specifying which part of
the block each engine is working on. Through careful selection of the Header Counter and
Source Count values in each processing engine, relatively complex patterns of compression,
encryption, padding and authentication can be performed. Table 3-4 below shows the
values that the host software would set for processing this example packet.
Table 3-4. Command Structure Values for IPsec Example
Command Structure Field
Length /
Value
Desc_cmd_cmp Descriptor
CMP_Header_Count
CMP_CM
B
0
CMP_Source_Count
Desc_cmd_pad Descriptor
Pad_Header_Count
Pad_CM
C-B
A
1
0
Pad_Source_Count
Desc_cmd_enc Descriptor
ENC_Header_Count
ENC_CM
A
1
0
ENC_Source_Count
Desc_cmd_hash Descriptor
Hash_Header_Count
PS
0
3
1
0
Hash_CM
Hash_Source_Count
For this example, the host software would construct the source data as:
ESP Header + IPPCP Header + Original IP Header + Original TCP Header + Original
Data Payload
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The 820x DMA would fetch the data and distribute it to the appropriate processing engines.
Because the header of this data block is not to be compressed, the compression engine
should skip over the ESP and IPPCP headers. Setting CMP_Header_Count to “B” represents
the number of bytes of data the compression engine would pass through. The compression
engine would begin compressing the Source Count bytes, “C-B”.
The Pad, Encryption and Hash engines work in a similar fashion, except for the fact that in
this example they have been set with CountMode of 1 and a SourceCount of 0. Each of
these processing engines passes through the number of bytes in the Header Counter, and
then process the same amount of data as processed by the previous engine.
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3.1.4
Free Pool Ring
The host software may use the 820x Free Pool to store result data if all the command’s
destination buffers are consumed in order to avoid an overflow error. Figure 3-22 illustrates
the Free Pool Ring.
Figure 3-22. Free Pool Ring
The 820x does not maintain a “full” bit for the Free Pool Ring; it is the responsibility of the
host not to overflow the free pool ring.
The Free Pool has same the format for both 32-bit or 64-bit addressing:
Free_Pool_Len[13;0]
CMD_Index[13:0]
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Free_Pool_Adr[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
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Field Name
Description
Bits
Default
Free_Pool_Len[13:0]
Free Pool Length.
This field indicates the size of the block defined by
the free pool descriptor. The size of the free pool
descriptor buffer is 8-bytes.
63:50
0
CMD_Index[13:0]
CPR
Command Index.
49:36
35
0
0
The index number of the command that used the
Free Pool entry.
Command Pointer Ring.
This bit identifies which command pointer ring used
the free pool entry.
0
Free pool entry is from a command in Command
Pointer Ring 0
1
Free pool entry is from a command in Command
Pointer Ring 1
Reserved
END
34
33
0
0
Reserved
End.
The command that used this entry is finished.
VALID
Entry Valid.
This bit indicates that the free pool entry is valid.
The host software will set this bit when writing a
new free pool entry. The 820x will clear this bit after
reading the free pool entry.
32
0
0
0
1
Free pool entry not valid
Free pool entry valid
Free_Pool_Adr[31:0]
Free Pool Buffer Starting Address.
The starting physical address of the descriptor free
pool. The Free Pool Entry format is the same for
both 32-bit and 64-bit addressing. Even if operating
in a 64-bit physical addressing environment, the
820x free pool physical addresses must be located
in the first 4GB (0 - 0xffffffff).
31:0
This field must be aligned on an 8 byte boundary.
Both the host and the 820x may read from and write to the Free Pool Ring; the host writes
to the ring at initialization, and the 820x reads from the ring when needed. After the 820x
has used a free pool entry, it will clear the Valid bit for that entry to inform the host that
the entry was used by a Channel Manager. After the host has finished processing a
command and finds that the command used the free pool by reading the FP bit in the result
descriptor, it should read the Free Pool Ring to determine how many entries were used by
that command. The host can then read the result data for that command from the Free Pool
buffers using the free pool address and length. Figure 3-24 illustrates a free pool ring
example.
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Figure 3-23. Free Pool Usage Example
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3.2 Result Ring
The result ring contains a completed command’s resultant data pointers and execution
status (successful completion or errors occurred). The 820x writes to the result ring and the
host reads from the result ring. The 820x will write to the result ring when a command
completes and then update its result ring write pointer appropriately.
The size of the result ring is always identical to the size of command pointer ring. The result
ring must be aligned to an 8-byte boundary and reside entirely in a physically contiguous
range of memory.
In general in the case of an error, bits [31:17] of a result ring entry summarize the source
of the error, while bits [63:32] provide a more detailed identification of the error. The error
bits remain set until cleared by the host software.
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
CMD_IDX[14:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Default
CM_DCRC
Channel Manager Data CRC error.
63
0
0
1
Channel Manager did not detect data CRC error
Channel Manager detected data CRC error
CM_KCRC
CM_ECC
Channel Manager Key CRC error.
62
0
0
1
Channel Manager did not detect key CRC error
Channel Manager detected key CRC error
Channel Manager ECC/Parity error.
0
Channel Manager did not detect ECC/Parity error
on this channel
61
0
0
1
Channel Manager detected ECC/Parity error on
this channel
Reserved
60:59
Reserved.
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Field Name
Description
Bits
Default
PAD_CFG_ERR
Pad Engine Software Configuration Error.
0
Pad Engine did not detect software configuration
error
58
0
1
Pad Engine detected software configuration
error
PAD_MALFORM_ERR
ENC_RV_ERR
Pad Engine Malformed Packet Error.
0
Pad Engine did not detect malformed packet
error
57
0
1
Pad Engine detected malformed packet error
Encryption Engine Real Time Verification Error.
0
Encryption Engine did not detect real time
verification error
56
55
0
0
1
Encryption Engine detected real time
verification error
ENC_PAR_ERR
Encryption Engine Parity Error.
0
1
No parity error in 3DES key
Encryption engine detected parity error in 3DES
key
ENC_DIF_CRC_ERR
Encryption Engine DIF CRC Error in AES-XTS
operation.
0
Encryption Engine did not detect DIF CRC error
in AES-XTS operation
54
53
0
0
1
Encryption Engine detected DIF CRC error in
AES-XTS operation
ENC_MALFORM_ERR
HASH_RV_ERR
Encryption Engine Malformed Packet Error.
0
Encryption Engine did not detect malformed
packet error
1
Encryption Engine detected malformed packet
error
Hash Engine Real Time Verification Error or HMAC
Error.
0
Hash engine did not detect real time verification
or HMAC error
52
0
1
Hash engine detected real time verification or
HMAC error
HASH_MAC_ERR
HASH_CFG_ERR
Hash Engine MAC Check Error.
0
1
Hash engine did not detect MAC check error
Hash engine detected MAC check error
51
50
0
0
Hash Engine Software Configuration Error.
0
Hash Engine did not detect software
configuration error
1
Hash Engine detected software configuration
error
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Field Name
Description
Bits
Default
HASH_MALFORM_ERR
Hash Engine Malformed Packet Error.
0
Hash Engine did not detect malformed packet
error
49
0
1
Hash Engine detected malformed packet error
Reserved
48
0
0
Reserved.
GZIP_DECODE_ERR
[5:0]
GZIP Error.
47:42
Please refer to Table 3-5 for the decoding of this
field.
GZIP_RV_ERR
GZIP Engine Real Time Verification Error.
0
GZIP engine did not detect real time verification
error
GZIP engine detected real time verification
error
41
40
0
0
1
GZIP_CFG_ERR
GZIP_MALFORM_ERR
GZIP Engine Software Configuration Error.
0
GZIP Engine did not detect software
configuration error
1
GZIP Engine detected software configuration
error
GZIP Engine Malformed Packet Error.
0
GZIP Engine did not detect malformed packet
error
39
38:37
36
0
0
0
1
GZIP Engine detected malformed packet error
Reserved
Reserved.
LZS_CRT_ERR
LZS Engine Corruption Error.
0
LZS engine did not detect EOR/multiple record
error
1
LZS engine detected EOR/multiple record error
LZS_ECC_ERR
LZS Engine ECC Error.
0
LZS engine did not detect ECC error in decode
operation
35
34
0
0
1
LZS engine detected ECC error in decode
operation
LZS_TOKEN_ERR
LZS Engine Token Error.
This bit will be set if the LZS engine identifies an
undefined token in the LZS engine data stream. A
token at the end of a compressed block normally
indicates the end of the compression data stream.
0
1
LZS engine did not detect token error
LZS engine detected token error
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Field Name
Description
Bits
Default
LZS_RV_ERR
LZS Engine Real Time Verification/CRC Error.
real time verification error when encode, identifies
CRC error when decode
0
LZS Engine did not detect real time verification
error for a encode operation, or a CRC error for
a decode operation
33
0
1
LZS Engine detected real time verification
error for a encode operation, or a CRC error for
a decode operation
LZS_MALFORM_ERR
CMD_ERR
LZS Engine Malformed Packet Error.
0
LZS Engine did not detect malformed packet
error
32
31
0
0
1
LZS Engine detected malformed packet error
Command Error.
This bit summarizes the command error status. It
will be set if any of the error bits, excluding the
overflow error bit, in this entry are set.
0
1
No error occurred for this command
Error occurred for this command
OFLOW
Overflow.
This bit indicates if an overflow error occurred in the
destination data buffer.
30
0
0
1
No overflow error occurred for this command
Overflow error occurred for this command
CMP_EXP
Compression Expansion bit.
This bit defines how the compression expansion is
calculated.
29
28
27
0
0
0
0
1
Len(cmp) + head_size < len(raw)
Len(cmp) + Head_Size >= len(raw)
RSVD
Reserved.
CM_ERR
Channel Manager Error.
This bit indicates if any error occurred in either
channel manager.
0
1
No error occurred in either channel manager
Error occurred in one or both channel managers
ENC_ERR
Encryption Engine Error.
This bit indicates if an error occurred in the
Encryption engine.
26
0
0
No Encryption engine error occurred for this
command
1
Encryption engine error occurred for this
command
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Field Name
Description
Bits
Default
HASH_ERR
Hash Engine Error.
This bit indicates if an error occurred in the hash
engine.
25
0
0
1
No hash engine error occurred for this command
Hash engine error occurred for this command
LZS_ERR
GZIP_ERR
PAD_ERR
LZS Engine Error.
This bit indicates if an error occurred in the LZS
engine.
24
23
0
0
0
1
No LZS engine error occurred for this command
LZS engine error occurred for this command
GZIP Engine Error.
This bit indicates if an error occurred in the GZIP
engine.
0
1
No GZIP engine error occurred for this command
GZIP engine error occurred for this command
Pad Engine Error.
This bit indicates if an error occurred in the Pad
engine.
22
0
0
0
0
0
1
No Pad engine error occurred for this command
Pad engine error occurred for this command
Reserved
CM_ID
21:18
17
Reserved.
Channel Manager Identifier.
This bit identifies which Channel Manager reported
the error.
0
1
Channel Manager 0 reported the error
Channel Manager 1 reported the error
Reserved
16:15
Reserved.
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Field Name
Description
Bits
Default
CMD_IDX
Command Index.
The command index field contains a Valid bit
and the index number of the completed
command in the result ring. The bit position of
the Valid bit depends on the command ring
size, as described below. The Valid bit toggles
each time the write pointer wraps the result
ring.
For a command ring size of 16K:
bit 14 Valid bit if command ring size is 16K
bit 13:0 Command index of completed command
For a command ring size of 8K:
14:0
0
bit 13 Valid bit if command ring size is 8K
bit 12:0 Command index of completed command
For a command ring size of 4K:
bit 12 Valid bit if command ring size is 4K
bit 11:0 Command index of completed command
A similar pattern can be applied for command ring
sizes < 4K.
Table 3-5 decodes the GZIP errors for the field GZIP_DECODE_ERR[5:0]. These errors indicate
that the data sent to the 820x has been corrupted.
Table 3-5. GZIP Decode Error Table
Error Code
Bits
Code Definition
6-bit
signed
Value
Comment
0X_XXXX
11_1111
11_1110
11_1101
11_1100
11_1011
11_1010
11_1001
11_1000
11_0111
11_0110
No error
0 -31
-1
SYS_GENERAL_ERROR
Not used.
SYS_BAD_MAGIC_NUMBER
SYS_BAD_GZIP_HEADER
SYS_BAD_FILE_NAME
SYS_BAD_FCOMMENT
SYS_BAD_EXTRA
-2
Incorrect magic number
-3
Bad compression mode or flags
Extra length greater than file length
Extra length greater than file length
Extra length greater than file length
Bad length or distance
-4
-5
-6
SYS_BAD_LENDIS
-7
SYS_STC_INVALID_SYMBOL
SYS_STC_INVALID_DISTANCE
SYS_STO_LEN_MISMATCH
-8
Static, invalid OP field
-9
Static, invalid OP field
STORED LEN (bypass mode) does not
match NLEN
-10
-11
SYS_BAD_BLOCK_TYPE
SYS_BAD_NO_DYN_SUPP
11_0101
11_0100
Block type 3 detected
Attempt dynamic frame with no support.
Only valid for cores built without dynamic
support.
-12
-13
SYS_DYN_NO_LAST_LENGTH
11_0011
No last length in dynamic mode
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Table 3-5. GZIP Decode Error Table
Error Code
Bits
Code Definition
6-bit
signed
Value
Comment
SYS_DYN_NLEN_OR_NDIST
11_0010
NLEN > MAXLCODES or
NDIST > MAXDCODES
Invalid code lengths
-14
SYS_DYN_INVALID_CODE_LEN
STS_DYN_TOO_MANY_LENGTH
STS_DYN_INVALID_CODE_LEN
STS_DYN_TOO_MANY_LENS
STS_DYN_OVER_SUBSCRIBED
STS_DYN_INCOMPLETE_SET
STS_DYN_ENOUGH_NOT_ENOUGH
11_0001
11_0000
10_1111
10_1110
10_1101
10_1100
10_1011
10_1010
-15
-16
-17
-18
-19
-20
-21
Invalid code lengths
Not used
Not used
Oversubscribed set of lengths
Incomplete set of lengths
Not enough space for dynamic table
No more data present in stream
STS_DYN_UNEXPECTED_END_OF_ST
REAM
-22
10_1001 to
10_0000
Not defined
Not used
-23 to -
32
The Valid bit in the CMD_IDX[14:0] field informs the host software that the corresponding
command has finished and indicates that there are valid entries in the result ring. The value
of the Valid bit toggles every time the result ring is completely used, i.e., the 820x write
pointer has wrapped the ring. For example, for the first pass through the result ring the
value of the Valid bit indicating valid entries is one. After the 820x’s write pointer wraps
around the result ring, the Valid bit will be zero, and so on for every complete pass through
the result ring. During initialization, the host software should write a zero to the Valid bit.
This simple mechanism is sufficient to allow the host to differentiate unambiguously
whether an entry in the result ring has been updated.
Figure 3-24 shows an example of how the result ring and command pointer ring are used
to process a command and its results. To simplify the illustration, this example shows a
command pointer ring only with 4 entries, but the actual minimum command pointer ring
size is 16 entries.
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Figure 3-24. Result Ring Example
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3.3 Command Operation Sequence
The 820x has a high performance DMA engine that supports two command pointer rings
using a round-robin arbitration scheme. Figure 3-25 shows how the 820x and the host
software work together to process a command. The flow is described in the figure below.
Figure 3-25. Command Process Flow Example
1. Host configures the 820x control registers (Refer to Chapter 6 for details).
2. Host sets up Command Pointer Ring 0 and Command Pointer Ring 1 and writes
the command structures into host memory.
3. Host writes the source data into the source buffers.
4. Host writes the index number of the commands into the Command Pointer Ring
using the 820x Command Pointer Ring Write Pointer (Wcp) register and updates
its own Command Pointer Ring Write Pointer (Wch). The 820x maintains a
Command Pointer Ring Read Pointer (Rcp) register which may be read by the
host at any time. It is the responsibility of the host not to overflow the Command
Pointer Ring by ensuring that the write pointer never advances to meet the read
pointer. If several commands are ready for submission at the same time, the host
may build the command structures for all these commands and then issue a
single write to the write pointer register to improve efficiency.
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5. If dual command pointer ring mode is enabled, the host should update the
appropriate command write pointer of Command Pointer Ring 0 or Command
Pointer Ring 1.
6. As long as the read and the write pointer registers for Command Pointer Ring 0
or Command Pointer Ring 1 are not equal, the 820x recognizes that commands
are available to fetch from host memory. A command read request will be sent by
the 820x Read Request Controller which will alternate sending the command to
either Command Pointer Ring 0 or Command Pointer Ring 1. In this example, the
command is sent to Command Pointer Ring 0.
7. The 820x reads the source descriptor to determine the location of the source data
and the operation. The Compression, Decompression, Hash, and Pad engines
process the data according to the control fields in the command structure.
8. The 820x writes the slice hash values and file chaining hash value to the first
destination buffer if the command has Hash related operation.
9. After the Compression, Decompression, Hash, and Pad engines complete
processing the data, the 820x writes the result data to the host destination
buffers whose location is defined in the destination descriptor.
10. After the 820x writes the result data to host memory, it updates the appropriate
command structure Result Ring. Because the 820x has two channels (each
channel includes one group of Compression, Decompression, Hash, and Pad
engines) which process commands in parallel, and the commands may have
different sizes, it is very probable for commands to complete out of order. The
Result Ring is used to keep track of the finished commands.
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4 Data Flow
The 820x has four processing engines: Compression, Encryption, Pad, and Hash. Each
processing engine may be enabled or disabled in the command descriptor base register
(Section 3.1.2.2, “Desc_cmd_base"). A disabled processing engine simply passes data
forward to the next processing engine without altering the data or modifying the context.
The Pad engine is typically used for packet processing applications to pad or remove data;
storage applications may disable the Pad engine to conserve power.
The order of processing depends on whether the operation is in the encode or decode
direction. The positions of Compression, Encryption and Pad engines are fixed, but the
position of the Hash engine is configurable using Hash Engine Position PS configuration bits
in the hash descriptor command structure (Section 3.1.2.5, “Desc_cmd_hash").
In addition, in the data stream sent to a processing engine, the amount of header and
trailer data skipped by the engine may be adjusted according to the Source_Count and
Header_Count fields in the command descriptor structures for each engine. This feature is
can used to accelerate packet processing.
4.1 Encode Operations Data Flow
4.1.1
Hash Engine before Compression Engine
Figure 4-1 shows the data flow when the position of the Hash Engine is before the
Compression engine and all four engines are enabled.
1. The DMA fetches “RAW” data from the host according to the command structures,
and sends the data to processing channel 0 or processing channel 1.
2. In parallel, processing channels 0 and 1 begin to process the “RAW” data for
separate commands.
3. The Hash engine simultaneously calculates the hash values for the “RAW” data,
and passes the “RAW” data to the Compression engine.
4. The Compression engine compresses the “RAW” data, and then sends the
compressed RAW data “CMP” to the Pad engine.
5. The Pad engine passes through the “CMP” data and adds “Pad” to the data stream
for the Encryption Engine.
6. The Encryption engine encrypts the “CMP + Pad” data, and then sends the result,
ENC (CMP + Pad), to the DMA.
7. Finally, the DMA sends the result data, ENC (CMP +Pad), from the Encryption
engine and the hash values from the Hash engine to host memory according to
the command structures.
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Figure 4-1. Encode Operation: Hash Engine before Compression Engine
In this figure, the Hash engine only calculates the hash values on the RAW data. The 820x
can also calculate MAC values on the RAW data by setting the configuration fields
appropriately in the command structure. The 820x can only calculate hash or MAC values
when the Hash engine's position is before the Compression engine. In any other position,
the Hash engine can only calculate MAC values.
4.1.2
Hash Engine after Compression Engine
Figure 4-2 shows the data flow when the Hash engine position is after the Compression
engine and all four engines are enabled. In this configuration, the Hash engine calculates
the MAC value on the CMP data instead of the RAW data. The data flow for the remaining
engines is the same as described in Section 4.1.1, “Hash Engine before Compression
Engine".
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Figure 4-2. Encode Operation: Compression Engine before Hash Engine
4.1.3
Hash Engine after Pad Engine
Figure 4-3 shows the data flow when the Hash engine position is after the Pad engine and
all four engines are enabled. In this configuration, the Hash engine calculates the MAC
value of the compressed and padded data, CMP + Pad. The data flow for the remaining
engines is the same as described in Section 4.1.1, “Hash Engine before Compression
Engine".
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Figure 4-3. Encode Operation: Hash Engine after Pad Engine
4.1.4
Hash Engine after Encryption Engine
Figure 4-4 shows the data flow when the position of the Hash engine is after the Encryption
engine and all four engines are enabled. In this configuration, the Hash engine calculates
the MAC value on the encrypted, compressed data with padding, ENC(CMP + Pad). The
data flow for the remaining engines is the same as described in Section 4.1.1, “Hash
Engine before Compression Engine".
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Figure 4-4. Encode Operation: Hash Engine after Encryption Engine
4.2 Decode Operations Data Flow
4.2.1
Hash Engine before Encryption Engine
Figure 4-5 shows the data flow when the position of the Hash Engine is before the
Encryption engine and all four engines are enabled. The data flow is the reverse of the
“Hash Engine after Encryption Engine” encode operation.
1. First, the DMA fetches the encrypted, compressed data with padding, ENC (CMP
+ Pad) & MAC, from the host according to the command structures, and sends
the data to processing channel 0 or processing channel 1.
2. In parallel, processing channels 0 and 1 begin to process the “ENC (CMP + Pad)
& MAC” data for separate commands.
3. The MAC value is sent to the Hash engine through the information bus, and the
“ENC (CMP + Pad)” data is sent to the Hash engine through the data bus. Please
refer to Section 3.1.3.5, “Data Stream Information Fields" for details.
4. The Hash engine calculates the MAC value of the “ENC (CMP + Pad)” data and
compares the result to the MAC value on information bus to determine whether
the input stream is valid, and also passes through the “ENC (CMP + Pad)” data to
the Encryption engine.
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5. The Encryption engine decrypts the “ENC (CMP + Pad)” data, and then sends the
“CMP + Pad” data to the Pad engine.
6. The Pad engine passes through the “CMP” data to the Compression Engine, and
removes the “Pad” data in the data stream.
7. The Compression engine decompresses the “CMP” data, and then sends the
resulting “RAW” data to the DMA.
8. Finally, the DMA sends the result data to host memory according to command
structures.
Figure 4-5. Decode Operation: Hash Engine before Encryption Engine
4.2.2
Hash Engine after Encryption Engine
Figure 4-6 shows the data flow when the position of the Hash engine is after the Encryption
engine and all four engines are enabled. In this configuration, the Hash Engine calculates
MAC value for the compressed data with padding, “CMP + Pad”, and compares the
calculated MAC value against the MAC value in the information bus. The data flow for the
remaining engines is the same as described in Section 4.2.1, “Hash Engine before
Encryption Engine". This data flow is the reverse of the encode operation “Hash Engine
after Pad engine”.
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Figure 4-6. Decode Operation: Hash Engine after Encryption Engine
4.2.3
Hash Engine after Pad Engine
Figure 4-7 shows the data flow when the position of the Hash engine is after the Pad
engine and all four engines are enabled. In this configuration, the Hash engine calculates
the MAC value on the compressed “CMP” data and compares the calculated MAC value
against the MAC value on the information bus. The data flow for the remaining engines is
the same as described in Section 4.2.1, “Hash Engine before Encryption Engine". This flow
is the reverse of the encode operation “Hash Engine after Compress Engine”.
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Figure 4-7. Decode Operation: Hash Engine after Pad Engine
4.2.4
Hash Engine after Compression Engine
Figure 4-8 shows the data flow when the position of the Hash engine is after the
Compression engine and all four engines are enabled. In this configuration, the Hash engine
calculates the MAC value of the RAW data and compares it against the MAC value on the
information bus. The data flow for the remaining engines is the same as described in
Section 4.2.1, “Hash Engine before Encryption Engine". The data flow is the reverse of the
“Hash Engine before Compression Engine” encode operation.
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Figure 4-8. Decode Operation: Hash Engine after Compression Engine
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5 Modules
This chapter gives a more detailed description of some of the key 820x internal modules:
DMA, Configuration registers, Channel Managers, PKP Manager, PKP Core, RNG engine,
Hash engine, LZS engine, GZIP engine, Pad engine, Encryption engine, and the clock
generator.
5.1 DMA
5.1.1
PCIe Outbound Manager
The PCIe Outbound Manager (POM) provides a transmit interface between the PCIe Core
and DMA modules. The main functions of the PIM are:
• Send write requests to the PCIe Core transmit interface
• Send read requests to the PCIe Core transmit interface
• Convert output data to the correct endian format
5.1.2
PCIe Inbound Manager
The PCIe Inbound Manager (PIM) provides a receive interface between the PCIe Core and
DMA modules. The main functions of the PIM are:
• Decode the completion PCIe TLP (Transaction Layer Packet) from the PCIe Core
completion receive interface, and send the completion data to Completion Controller
• Decode memory writes and memory reads from the PCIe Core ELBI interface (a local
bus of the PCIe Core for reading or writing application-owned register space), and
send write and read requests to the Configuration Register module
• Send interrupts to the host through the PCIe Core interface
• Convert input data to the correct endian format
5.1.3
Command Pointer Ring Prefetch
The Command Pointer ring Prefetch (CPP) module is used to prefetch command pointers
from the host command pointer ring. The CPP implements a 128 byte Command Pointer
Ring (CPR) buffer which can accommodate 16 command pointers in 64-bit addressing mode
(8 bytes per pointer) and 32 command pointers in 32-bits addressing mode (4 bytes per
pointer).
When the Command Pointer Ring buffer is half empty and the CPR Read Pointer is not equal
to the CPR write pointer, the CPP module sends a read request to the Read Request
controller (RRC, discussed in Section 5.1.4 below) to prefetch the maximum command
pointer ring entries from host memory (8 entries for 64-bit addressing mode or 16 entries
for 32-bit addressing mode). This CPP request has the highest priority in the RRC.
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Figure 5-1 illustrates how the CPP pre-fetches 8 command pointers using 64-bit addressing.
Initially, the host software writes 9 command pointers into the command pointer ring and
updates the CPR write pointer for the 820x. At this point, the 820x CPR read pointer is zero
because it has not read any of the commands. Once the CPP discovers that the CPR buffer
is empty and CPR Read Pointer is not equal to the CPR write pointer, the 820x will fetch the
8 CPR entries and store them into the CPR buffer.
Figure 5-1. DMA Command Pointer Prefetch Example
Note: If dual command ring mode is enabled, the CPP will maintain two CPR buffers. The
arbitration of the two CPR buffer read requests uses a round-robin scheme.
5.1.4
Read Request Controller
The Read Request controller (RRC) arbitrates the read requests from multiple sources,
builds the TLP, and sends a read request to the POM. The main functions of the RRC are:
• Store the source descriptor starting address and byte count
• Arbitrate read requests from both channel managers, the PKP manager and the CPP
• Split the source descriptor into TLP read requests and send requests to the POM
• Arbitrate command process requests from the dual command ring using a round-
robin scheme.
• Send out the command read request and then update the command pointer ring
read pointer
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• Push the source descriptor head and tail pointers into the pointer FIFO in the
Channel Manager Inbound Data Controller (IDC) when sending source data read
requests (The head and tail pointers indicate the valid bytes in a single quad-word
as the source buffer starting address and length is arbitrary)
5.1.5
Write Request Controller
The Write Request controller (WRC) arbitrates the write requests from multiple sources,
builds the TLP, and sends write requests to the POM. The main functions of the WRC are:
• Store the destination descriptor starting address and byte count
• Arbitrate destination write requests from both channel managers and the PKP
manager
• Split the destination descriptor into TLP write requests and send those requests to
the POM
• Generate a Free Pool write request if a Free Pool entry is used by the channel
manager
• Generate the command structure result field and result ring write requests when a
command completes
• Update the result ring write pointer after a command completes
5.1.6
Completion Controller
The Completion Controller (CC) distributes completion data to the proper destination
according to the PCIe tags, which tag a completion. The main functions of the Completion
Controller are:
• Decode the command structure and send the command to a channel manager
• Write the source descriptors to the RRC source descriptor buffer and destination
descriptors to the WRC destination descriptor buffer
• Write the completion data to the corresponding channel manager's source buffer
• Maintain the read request record table
5.2 Configuration Registers
The Configuration Registers (CFG_REGS) module implements all 820x registers accessed by
the host through the PCIe bus. The main functions of the Configuration Registers are:
• Implement all registers
• Respond to PCIe memory write and read request from the PIM
• Provide global configuration signals to all other modules
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5.3 Channel Manager
There are two channel managers in the 820x. Each channel manager controls one Data
Processing Channel. The DMA controller issues the read and write requests needed to
execute a command and the control the data flow for the Data Processing Channels encode
and decode operations.
Figure 5-2. Channel Manager Block Diagram
5.3.1
Channel Manager Inbound Data Controller
The Inbound Data Controller (IDC) controls the command structure and fetching the source
data. The main functions of the Inbound Data Controller are:
• Issue command structure read requests and put the command into the command
buffer after the command completes
• Issue source descriptor read requests
• Issue source data read requests while maintaining the source data read request tags
and ensuring the source buffer is available before issuing the source data read
request (The IDC can generate a maximum 8 outstanding data read requests)
• Issue free pool descriptor read requests if the destination descriptors are all
consumed
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• Maintain two entries into the command buffers to improve performance by
prefetching the next command's command structure and source data if all the
current command’s source data is consumed
• Maintain the source descriptor head and tail pointer FIFO, which is used to indicate
the valid bytes in a single quad word because the source buffer starting address and
length is arbitrary
5.3.2
Channel Manager Source Buffer
The source buffer is implemented as a two-port 72-bit memory (64 bits of data and 8 bits
of ECC). The source buffer memory is segmented into multiple blocks; each block
comprises multiple cells. The cell size is fixed at 128-bytes, the minimum
max_read_request_size.
When a Channel Manager requests a block of source data, the length will be the cell size,
except the first and the last requests of a source descriptor because the starting address of
a source descriptor is arbitrary aligned. The number of cells in a block are a power of 2 and
depend on the parameter max_read_request_size which may be 128, 256, 512, 1K, or 2K
bytes. Each Channel Manager has a 4K byte deep source buffer, and supports
max_read_request_size equal 128, 256 or 512 bytes, therefore each block may consist of
1, 2, or 4 cells.
For data integrity, every 64 bits of data are protected by 8 bits of ECC.
Note: The default maximum read request size, max_read_request_size for the PCIe
specification is 512 bytes. If the host configures the max read request size to 1KB or 2KB,
the 820x will still send 512B read requests over the PCIe interface.
5.3.3
Channel Manager Outbound Data Controller
The Outbound Data Controller (ODC) controls the result data and command process status
writes to host. The main functions of the Outbound Data Controller are:
• Issue data write requests to the POM when data in the result buffer exceeds the
maximum read request size
• Issue destination descriptor read requests and free pool entry read requests
• Issue hash/MAC values write requests to the POM if used
• Issue free pool entry write requests if the free pool is used
• Issue command structure result field write requests and result ring write requests
when a command completes
• Organize the errors reported by the processing engines
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5.3.4
Channel Manager Result Buffer
The Result Buffer is used to temporarily store the destination data generated by the
processing engines. Unlike source data, destination data is stored into the result buffer in
the order that the commands complete and is fetched using the same sequence, therefore
it mimics a FIFO.
The size of the write request payload must not exceed the parameter max_payload_size.
The host software sets this parameter during initialization and is typically set to 128 bytes.
If the result buffer is 1KB deep, it can accommodate 8 TLPs.
The result buffer is implemented as a dual-port 1K-byte memory. The data bus width is 72-
bits (64 bits of data and 8 bits of ECC).
Note: The 820x supports a maximum payload size, max_payload_size, of 128, 256 or 512
bytes. If the host configures the max read request size to 1KB or 2KB, the 820x will still
send 512B read requests over the PCIe interface.
5.3.5
Channel Manager Data Process Controller
The Data Process Controller (DPC) controls the data process flow and interface with all
processing engines. The main functions of the Data Process Controller are:
• Separate the information bus from the source buffer, and feed the information bus
field to the processing engines
• Read and align the data from the source buffer, and feed the source data to
processing engines
• Verify the Key CRC if the command uses an the key
• For encode operations, append a CRC to the source data or verify the CRC of input
data
• For decode operations, verify the data CRC
• Read the result data from the processing engines; align and write the data into the
result buffer
• Control the encode and decode data flow
5.4 PKP Manager
The PKP Manager controls the flow of fetching instructions and operand data from host
memory to the PKP engine, and the flow of transmitting the calculated results from the PKP
engine to host memory.
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Figure 5-3. PKP Manager Block Diagram
5.4.1
PKP Inbound Data Controller
The PKP Inbound Data Controller (IDC) controls the PKP instruction and source data
fetching. The IDC can generate a maximum of 8 outstanding data read requests. The main
functions of the IDC are:
• Issue instruction and data read requests, maintain source data read request tags
and ensure source buffer is available when issuing source data read requests
• Prefetch the next command's source data to improve performance
5.4.2
PKP Source Buffer
The PKP Source buffer is used to buffer the instruction and data of a PK operation, and is
implemented as a two-port 72-bit memory. The memory is segmented into multiple blocks.
Each block is comprised of multiple cells as described in Section 5.3.2, “Channel Manager
Source Buffer". For data integrity, every 64 bits of data are protected by 8 bits of ECC.
5.4.3
PKP Outbound Data Controller
The PKP Outbound Data Controller (ODC) controls writing the result data to the host. The
main function of the ODC is:
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• Issue data write request to the POM when the data is available (the PKP result data
is ready when the calculation is finished; the PIC will write the data into the result
buffer continuously).
5.4.4
PKP Result Buffer
The PKP Result Buffer is used to temporarily store the calculated result generated by the
PKP Engine. Unlike the source data, the destination data is stored in-sequence into the
result buffer and is fetched using the same sequence, similar to a FIFO.
The PIC writes data to the Result Buffer after each PKP calculation completes. Whenever
result data is available in the PKP Data Register, the PIC will continuously transfer the data
to the result buffer until the Result Buffer is full.
Result buffer is implemented as a 72-bit RAM, with 64 bits of data and 8 bits of ECC.
5.4.5
PKP Interface Controller
The PKP Interface Controller (PIC) is the communication channel between the PKP Manager
and the PKP Engine. The main functions of the PIC are:
• Read instructions from the source buffer, and transfer them to the PKP Engine Linear
Instruction Registers (LIRs)
• Read data from the source buffer, and transfer them to the PKP Engine Data
Registers
• Control the command execution flow
5.4.6
PKP Core
The PKP Core is IP from Athena. Please refer to Athena’s EXP-E5200 Public Key
Cryptography Microprocessor for more information.
5.5 RNG Engine
The RNG Engine is Hifn IP. Please contact Hifn if detailed information is required.
5.6 Hash Engine
The Hash Engine calculates the hash or MAC values. The Hash Engine comprises an input
AFIFO, output AFIFO, Hash AFIFO, Hash interface controller and two Hash cores.
This engine can skip leading bytes and consume varying amounts of payload data to
support current and future network security protocols. These options are provided on a per
command basis.
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Figure 5-4. Hash Engine Block Diagram
Note, the Information Bus includes Hash_Head_Count, Hash_Source_Count from the
Channel Manager.
5.6.1
Hash In_AFIFO & Out_AFIFO
The Hash In_AFIFO and Out_AFIFO are used to transfer data and control signals between
the DMA clock domain (125M) and the Hash Engine clock domain (200M).
5.6.2
Hash_AFIFO
The Hash AFIFO is used to store the hash values calculated by the Hash cores, and
synchronize the data transfer between the DMA clock domain (125M) and the Hash Engine
clock domain (200M).
The Hash_AFIFO is implemented as a 34 x 32 bit flip-flop. A MD5 hash result is 128 bits (16
bytes) and occupies four entries (4 DWs) in the Hash_AFIFO; a SHA1 hash result is 160 bits
(20 bytes) and occupies three entries (5 DWs) of the Hash_AFIFO; a SHA2 hash result is
256 bits (32 bytes) and occupies four entries (8 DWs) of the Hash_AFIFO. Therefore, the
Hash_AFIFO can accommodate at least 4 hash result values.
5.6.3
Hash Interface Controller
The Hash Interface Controller (HIC) is the communication bridge between the In_AFIFO,
Hash_AFIFO and Hash cores. The main functions of the HIC are:
• Read the source data from the In_AIFIO, truncate the header and tail from the data
stream, and then send the truncated data to the Hash core according to
Hash_Head_Count and Hash_Source_Count
• Control the real time verification flow
• Control the two Hash core’s execution of the required operation
• Read the hash values from the Hash Cores and send them to the Hash_AFIFO
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• Combine the source data with the MAC value, and then send it to the Out_AFIFO
• Report the Hash core status to the Channel Manager after each command completes
5.6.4
Hash Core
The Hash engine contains two Hash cores. Each core supports six operation modes:
• slice hash only
• file hash only
• slice hash + file hash
• MAC
• SSL3.0 MAC
• XCBC-MAC (with SHA1, SHA256, and MD5 algorithms).
5.6.4.1
Hash Core Operation Modes
Slice Hash only
In this mode, one core calculates the hash value, while the other is used for real time
verification. Each slice is treated as a complete hash operation (with length padding).
File Hash only
In this mode, one core calculates the hash value, while the other is used for real time
verification. Hash engine will load the initial hash value into the hash cores during
initialization, and performs length padding on the last block of data (one command, one
block data).
A File Hash operation performs the hash operation on the entire data block of one
command. A File Hash command can be either stateless or stateful. If the hash of one file
can be done in one command, it is considered stateless; otherwise if the hash of one file
requires two or more commands, it is considered stateful.
Example of a stateless File Hash (one file per command):
The Hash core uses the default initial hash value, and adds length padding at the end
of the data block. The output hash is considered complete.
Example of a stateful file hash (one file uses three commands):
a. The Hash core uses the default initial hash value for the data block of the first com-
mand, and does not add padding. The output hash is considered incomplete but is
used as the IHV for the second command.
b. For the second command, the Hash core uses the IHV calculated from the first com-
mand, and does not add padding. The output hash is considered incomplete but is
used as the IHV for the third command.
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c. For the third command, the Hash core uses the IHV calculated from the second
command, and pads the last data block. The output is considered complete and is the
hash value of the entire file.
Slice Hash + File Hash
In this mode, one Hash core calculates the slice hash, while the other calculates the file
hash. No internal data integrity checking is performed in this mode.
Figure 5-5 shows an application example of a Slice Hash + File Hash operation.
Figure 5-5. Application Example of Slice Hash + File Hash
MAC
The MAC is actually keyed hash functions within a keyed hash function. The general
notation for a MAC message M using key K is:
MAC(K,M) = H(K xor opad, H(K xor ipad, M))
MAC(K,M) = H(OPAD, H(IPAD,M))
Where H is one of the hashing algorithms (SHA-1, SHA-256, or MD5), IPAD and OPAD are
the pre-computed partial results of the 64-element array (of values 0x36 and 0x5c
respectively) computed from the secured key (K) and IV (Initial Value). Either hashing
algorithm provides automatic pad insertion and MAC defined length insertion on an
arbitrary sized data block.
SSL3.0 MAC
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In this mode, one Hash core calculates the SSL3.0 MAC, while the other performs real time
verification.
The MAC in SSL3.0 is calculated as follows:
Hash(Write Secret || Pad2 || Hash(Write Secret || Pad1 || Seq. No. || Type || Length
|| Application Data))
Where:
Hash = SHA-1 or MD5
Write Secret = 20 bytes if SHA-1, 16 bytes if MD5; from Crypto Header
Pad1 = 48/40 bytes of 0x36 (MD5/SHA-1)
Pad2 = 48/40 bytes of 0x5C (MD5/SHA-1)
SeqNum = 8 byte Sequence Number from Crypto Header
Type = Type byte from SSL Header
Length = 16 bit Length of payload (no padding!)
The host software must combine “Seq. No. || Type || Length || Application Data” as source
data, and the Hash Engine will calculate the SSL3.0 MAC.
XCBC-MAC
The AES-XCBC-MAC-96 algorithm is a variant of the basic CBC-MAC with obligatory 10*
padding; however, AES-XCBC-MAC-96 is secure for messages of arbitrary length. The AES-
XCBC-MAC-96 calculations require numerous encryption operations; this encryption MUST
be accomplished using AES with a 128-bit key. Given a 128-bit secret key K, AES-XCBC-
MAC-96 is calculated as follows for a message M that consists of n blocks, M[1]... M[n], in
which the blocksize of blocks M[1]... M[n-1] is 128 bits and the blocksize of block M[n] is
between 1 and 128 bits:
(1) Derive 3 128-bit keys (K1, K2 and K3) from the 128-bit secret
key K, as follows:
K1 = 0x01010101010101010101010101010101 encrypted with Key K
K2 = 0x02020202020202020202020202020202 encrypted with Key K
K3 = 0x03030303030303030303030303030303 encrypted with Key K
(2) Define E[0] = 0x00000000000000000000000000000000
(3) For each block M[i], where i = 1... n-1:
XOR M[i] with E[i-1], then encrypt the result with Key K1, yielding E[i].
(4) For block M[n]:
(a) If the blocksize of M[n] is 128 bits:
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XOR M[n] with E[n-1] and Key K2, then encrypt the
result with Key K1, yielding E[n].
(b) If the blocksize of M[n] is less than 128 bits:
(i) Pad M[n] with a single “1” bit, followed by the num-
ber of “0” bits (possibly none) required to increase
M[n]'s blocksize to 128 bits.
(ii) XOR M[n] with E[n-1] and Key K3, then encrypt the
result with Key K1, yielding E[n].
(5) The authenticator value is the leftmost 96 bits of the 128-bit E[n].
NOTE1: If M is the empty string, pad and encrypt as in (4b) to create M[1] and E[1]. This
will never be the case for ESP or AH, but is included for completeness sake.
NOTE2: [CBC-MAC-2] defines K1 as follows:
K1 = Constant1A encrypted with Key K | Constant1B encrypted with Key K.
However, the second encryption operation is only needed for AES-XCBC-MAC with keys
greater than 128 bits; thus, it is not included in the definition of AES-XCBC-MAC-96.
AES-XCBC-MAC-96 verification is performed as follows:
Upon receipt of the AES-XCBC-MAC-96 authenticator, the entire 128-bit value is computed
and the first 96 bits are compared to the value stored in the authenticator field. Keying
Material AES-XCBC-MAC-96 is a secret key algorithm. For use with either ESP or AH a fixed
key length of 128-bits MUST be supported. Key lengths other than 128-bits MUST NOT be
supported (i.e. only 128-bit keys are to be used by AES-XCBC-MAC-96).
5.6.4.2
Hash Core Algorithms
SHA1/SHA256 Core
The SHA-1/SHA-256 calculation core performs the secure hash algorithm on N x 512-bit
blocks (N < 2k) and produces a single 160-bit/256-bit hash result, CVN+1, using the 512-
bit input blocks and CVN, the previous hash result.
To calculate the hash value of an input message MCALC = Min + PadSHA-1 (PadSHA-1
includes lengthSHA-1), which by definition must be an integral number of 512-bit blocks
{B0, B1, B2, …, BL}, the following sequence is performed:
1. To indicate the start of a new hash calculation, set the CV value to the SHA-1/
SHA-256 initial value from a previously calculated partial result.
2. Write the first block to the calculation core. (16 x 32-bit words)
3. Wait for the hash value calculation to complete.
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4. If the last block was written to the core, latch the hash value, otherwise, write
the next block to the calculation core and go to step 3.
Figure 5-6 shows a block diagram of the SHA Core.
Figure 5-6. SHA Core Block Diagram
MD5 Core
The MD5 calculation core performs the MD5 message digest algorithm on a N x 512-bit
blocks (N < 4k) and produces a single 128-bit message digest, CVN+1, using the 512-bit
input blocks and CVN, the previous message digest.
To calculate the hash value of an input message MCALC= MIN + PadMD5 (PadMD5 includes
lengthMD5), which by definition must be an integral number of 512-bit blocks {B0, B1, B2,
…, BL}, the following sequence is performed:
1. To indicate the start of a new hash calculation, set the CV value to the MD5 initial
value from a previously calculated partial result.
2. Write the first block to the calculation core. (16 x 32-bit words)
3. Wait for the hash value calculation to complete.
4. If the last block was written to the core, latch the hash value, otherwise, write
the next block to the calculation core and go to step 3.
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Figure 5-7 shows a block diagram of the MD5 Core.
Figure 5-7. MD5 Core Block Diagram
5.7 LZS Engine
The LZS Engine compresses/decompresses source data using Hifn’s LZS and enhanced LZS
(eLZS) algorithms. The LZS engine comprises an input AFIFO, output AFIFO, LZS interface
controller and LZS core. This engine can skip leading bytes and consume varying amounts
of payload data to support current and future network security protocols. These options are
provided on a per command basis.
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Figure 5-8. LZS Engine Block Diagram
Note: The Information Bus includes CMP_Head_Count and CMP_Source_Count from the
Channel Manager.
5.7.1
LZS In_AFIFO & Out_AFIFO
The LZS In_AFIFO and Out_AFIFO are used to transfer data and control signals between
the DMA clock domain (125M) and the LZS Engine interface controller clock domain (150M).
Both the In_AFIFO and Out_AFIFO are implemented as 39 x 16 bit flip-flops.
5.7.2
LZS Core Interface Controller
The LZS core Interface Controller (LIC) is the communication bridge between the In_AFIFO,
Out_AFIFO, and LZS core. The main functions of the LIC are:
• Read the source data from the In_AIFIO, pass through the header and tail of the
data stream to next engine (Out_AFIFO), and send the remaining data to the LZS
core according to the CMP_Head_Count and CMP_Source_Count.
• Write to the LZS core command register at the beginning of each command.
• Read the result data from the LZS Core, merge the tail of the source data stream
and the result data into a double word, and send it to the Out_AFIFO.
• Report the LZS core status to the Channel Manager after each command completes.
5.7.3
LZS Core
The LZS Core is Hifn IP. The LZS core is a high performance lossless data compression
processor that uses the industry-standard Lempel-Ziv-Stac (LZS®) compression algorithm,
as well as the “Enhanced LZS” (eLZS) algorithm. The output of the compression engine is
tied to the input of the decompression engine for compression operation verification.
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The LZS Core uses an anti-expansion algorithm that prevents the output from expanding
during compression. If the output expands during compression the original uncompressed
input along with certain header bytes is passed through as the output.
5.8 GZIP Engine
GZIP Engine compresses/decompresses source data with the GZIP algorithm, it includes the
input AFIFO, output AFIFO, GZIP interface controller and GZIP core.
Figure 5-9. GZIP Engine Block Diagram
5.8.1
GZIP In_AFIFO & Out_AFIFO
The GZIP In_AFIFO and Out_AFIFO are used to transfer data and control signals between
the DMA clock domain (125M) and the GZIP Engine interface controller clock domain
(200M).
Both the In_AFIFO and Out_AFIFO are implemented as 39 x 16 bit flip-flops.
5.8.2
GZIP Core Interface Controller
The GZIP Core Interface Controller (GIC) is the communication bridge between the
In_AFIFO, Out_AFIFO and GZIP core. The main functions of the GIC are:
• Read the source data from the In_AIFIO, pass through the header and tail of the
data stream to next engine (Out_AFIFO), and send the remaining data to the GZIP
core according to the CMP_Head_Count and CMP_Source_Count.
• Control the operation flow of GZIP core.
• Read the result data from the GZIP Core, merge the tail of the source data stream
and the result data into a double word, and send it to the Out_AFIFO.
• Report the GZIP core status to Channel Manager after each command completes.
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5.8.3
GZIP Core
The GZIP core complies with RFC 1951, and RFC 1952 and supports the Dynamic Huffman
algorithm for a high compression ratio.
5.9 Pad Engine
The Pad Engine is used to add padding to the data stream for encode operations and
remove padding for decode operations. This engine can skip leading bytes and consume
varying amounts of payload data to support current and future network security protocols.
These options are provided on a per command basis.
Figure 5-10. Pad Engine Block Diagram
The main functions of the Pad Engine are:
• For encode operations, receive the data stream from the Channel Manager, adding
padding to the data stream according to the required algorithm.
• For encode operations, receive the data stream from Channel Manager, truncating
the padding from the data stream.
• Extract the “Next Header” and “Pad Length” fields from data stream for decode
operations.
• Detect Pad errors according to the pad algorithm.
5.10 Encryption Engine
The Encryption Engine encrypts/decrypts source data with either the AES or 3DES
algorithm. The Encryption Engine is comprised of the input AFIFO, output AFIFO, Encryption
interface controller, AES Core and 3DES Core. This engine can skip leading bytes and
consume varying amounts of payload data to support current and future network security
protocols. These options are provided on a per command basis.
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Figure 5-11. Encryption Engine Block Diagram
5.10.1
Encryption In_AFIFO & Out_AFIFO
The Encryption In_AFIFO and Out_AFIFO are used to transfer data and control signals
between the DMA clock domain (125M) and the Encryption Engine interface controller clock
domain (200M).
Both the In_AFIFO and Out_AFIFO are implemented as 39 x 16 bit flip-flops.
5.10.2
Encryption Interface Controller
The Encryption Interface Controller (EIC) is the communication bridge between the
In_AFIFO, Out_AFIFO, AES core, and 3DES core. The main functions of the EIC are:
• Read the source data from the In_AIFIO, pass through the header and tail of data
stream to the next engine (Out_AFIFO), and send the remaining data to the AES
core/3DES core according to the ENC_Head_Count and ENC_Source_Count.
• Control the operation flow of the AES and 3DES cores.
• Read the result data from the AES Core/3DES cores, merge the tail of the source
data stream and the result data into a double word, and send it to the Out_AFIFO.
• Report the AES and 3DES core status to the Channel Manager after each command
completes.
5.10.3
Encryption AES and 3DES Cores
The AES and 3DES cores are Hifn IP. The Encryption/Decryption engine supports AES-GCM,
CBC, CTR and ECB with 128, 192 or 256 bit keys, AES-XTS with 256 or 512 bit keys, and
3DES.
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5.11 Clock and Reset Generator
The CLK_RST_Gen module resides in the core of the 820x, and is responsible for the
generation and management of all clocks and resets throughout the device. The major
components of the CLK_RST_Gen module are:
• Main PLL x 1
• PCIE PHY PLL x 1
• Clock dividers, distribution and gating logic
• Reset generation logic
The Main PLL is used to multiply the input clock to a frequency of 600MHz, which is then
divided down to 200MHz, 150MHz, and 300MHz for the processing engines. The PCIe PHY
PLL is used to generate a 125MHz clock for most of the DMA related modules.
To conserve power, the CLK_RST_Gen modules uses a clock gating cell statically or
dynamically to disable the clock to each data processing channel engine.
CLK_RST_Gen also generates the power on reset and software reset signals for all modules.
5.12 Temperature Sensor Controller
The 820x contains an internal temperature sensor that measures the die temperature using
measured voltages from internal analog circuitry. These voltages are converted to a signal
value through an ADC, allowing the values to be read by the host.
The 820x also contains a controller for the temperature sensor. The host may read/write
directly to the 820x temperature sensor controller (TSC) registers. In contrast, the
temperature sensor registers may only be accessed indirectly by the host via the
temperature sensor controller registers. Refer to Section 6.8, “Temperature Sensor
Controller Registers" for a complete description of the TSC registers.
The flow diagram in Figure 5-12 illustrates the procedure for measuring and calculating the
820x die temperature using the temperature sensor controller registers to read and write to
the temperature sensor registers. Table 5-1 defines the TSC addresses that should be used
to access the temperature sensor registers.
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Figure 5-12. Die Temperature Measurement Procedure
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Table 5-1. Temperature Sensor Register Map
Temperature Sensor Register Name
TSC_Addr
0x17
0x9
Bit Field
[12:2]
[1:0]
iv
mode
dac_mode
sel
0x8
[14:12]
[4]
0x9
adc_out
0xA
[9:0]
Note: The interval between two consecutive reads must be greater than 100 μs.
As shown in Figure 5-12, two equations are used to determine the die temperature:
a = (m2 - m1)/m1
Temperature = 105.6 + 189.6 x (a - 1.1) - 96.6 x (a - 1.1)^2
The host software can read the “m1” and “m2” values from the TSC Data register (Section
6.8.2), calculate the average over the last 80 values, and then calculate the temperature
using the equations listed above. Note: This formula may be modified by Hifn for the
production version of the device.
For example, to read from a temperature sensor register:
1. Write the temperature sensor register address to TSC Address (0x8F0).
2. Write 0x4 to the TSC Command Register (0x8F8).
3. Poll the TSC_OP_Done bit in the TSC Command Register (0x8F8) until set.
4. Read the TSC Data Register (0x8F4) to get the temperature sensor value.
To write to a temperature sensor register
1. Write the value to be written to the temperature sensor register to the TSC Data
Register (0x8F4).
2. Write the temperature sensor register address to the TSC Address Register
(0x8F0).
3. Write 0x2 to the TSC Command Register (0x8F8).
4. Poll the TSC_OP_Done bit in the TSC Command Register (0x8F8) until set.
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6 Register Definition
This section describes the 820x registers for configuration, DMA control, PKP control, and
engine configuration registers.
The registers are mapped into 4K bytes of PCIe memory space that can be accessed
through the PCIe bus. The absolute register address can be calculated using:
PCIe Address = PCIe base address + offset
PCIe Memory Space (4K bytes)
0x0000
Configuration
0x01FF
0x0200
DMA Control
0x03FF
0x0400
Engine Configuration
0x057F
0x0580
PKP Control
RNG Control
GPIO
SPI
Probe Control
0x0A00
Reserved
0x0FFF
Figure 6-1. PCIe Memory Map
The host should not read/write to/from reserved registers. If the host writes to a reserved
register, the write will be ignored by the 820x. Likewise, if the host reads a reserved
register, the return value will be all zeros.
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6.1 Configuration Registers
6.1.1
Status Register
The Status register provides the 820x internal status to host. These signals may be
connected to LEDs as status indicators.
Type:
Offset
Read only
x‘0000’
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Reserved
PCIe_Link
Description
Bits
Reset
31:4
0
Reserved.
PCIe Link Status
3
2
0
0
0
1
PCIe link is down and not operational
PCIe link is up and operational
820x_Err
PKP_Busy
820x Status
0
1
No 820x errors detected
820x error detected
Public Key Processor Status
0
1
PKP Manager and PKP Engine not busy
PKP Manager and PKP Engine busy
1
0
0
0
Note: the host software may only disable the PKP
when the PKP is not busy.
CM_Busy
Channel Manager Status
0
1
Channel Manager not busy
Channel Manager busy
Note: the host software may only disable the
Channel Manager when the Channel Manager is not
busy.
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6.1.2
820x Error Register
The 820x Error register provides additional information to the host if an 820x error occurs.
Type:
Offset
Read/Write one to clear
x‘0004’
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Reserved
OFLOW
Description
Bits
Reset
31:11
0
Reserved.
Destination buffer overflow
10
9
0
0
0
1
No destination buffer overflow detected
Destination buffer overflow detected
CLP_TO
Completion Timeout
This bit will be set if outstanding read requests for
completion packets do not return to the 820x within
the timeout window valued defined in the PCIe
specification.
0
1
No completion timeout error detected
Completion timeout error detected
CLP_CA
Host Completion Abort
This will be set if the host could not respond to a
read request issued by the 820x.
8
0
0
1
No completion abort error detected
Completion abort error detected
PCIE_ECRC_ERR
PCIE_PARITY_ERR
CM_ERR
PCIe Core ECRC Error
7
6
0
0
0
1
No ECRC error detected by PCIe Core
ECRC error detected by PCIe Core
PCIe Core Parity Error
0
1
No PCIe Core Parity error detected
PCIe Core Parity error detected
Command Error
This bit will be set if any error is detected by the
Channel Manager (see Section 6.2.15, “Channel
Manager 0-1 Error Status Register")
5
0
0
1
No command error detected
Command error detected
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Field Name
Description
Bits
Reset
AES_ERR
Encryption Engine Error
4
0
0
1
No Encryption Engine error detected
Encryption Engine error detected
HASH_ERR
GZIP_ERR
LZS_ERR
PAD_ERR
Hash Engine Error
3
2
1
0
0
0
0
0
0
1
No Hash Engine error detected
Hash Engine error detected
GZIP Engine Error
0
1
No GZIP Engine error detected
GZIP Engine error detected
LZS Engine Error
0
1
No LZS Engine error detected
LZS Engine error detected
PAD Engine Error
0
1
No PAD Engine error detected
PAD Engine error detected
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6.1.3
820x Interrupt Status Register
The 820x Interrupt Status register provides the 820x interrupt status to the host. Once an
interrupt is set, it may be cleared by the host by either writing a one to that bit, by a
hardware reset or a Miscellaneous Soft Reset (MISC_RST fromSection 6.1.5). However, the
PKP_INT bit can only be reset by a hardware or PKP soft reset.
Type:
Offset
Read/Write one to clear
x‘0008’
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Reserved
GPIO_INT
Description
Reserved.
Bits
Reset
31:10
0
GPIO Interrupt
9
8
0
0
0
1
No GPIO interrupt occurred
GPIO interrupt occurred
RNG_INT
SPI_INT
Random Number Generator Interrupt
0
1
No RNG interrupt occurred
RNG interrupt occurred
Serial to Parallel Interface Interrupt
7
0
0
0
1
No SPI interrupt occurred
SPI interrupt occurred
Reserved
FP_INT
6:5
Reserved.
Free Pool Interrupt
This interrupt will be set when a free pool descriptor
is used by the 820x.
4
3
0
0
0
1
No Free Pool interrupt occurred
Free Pool interrupt occurred
PCIE_ERR_INT
PCIe Error Interrupt
The 820x was not able to recover from a PCIe error.
0
1
No PCIe Error interrupt occurred
PCIe Error interrupt occurred
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Field Name
Description
Bits
2
Reset
CM_ERR_INT
Command Error Interrupt
The 820x detected a command error but that error
was corrected internally.
0
0
0
1
No Command Error interrupt occurred
Command Error interrupt occurred
Reserved
CMD_INT
1
Reserved
Command Done Interrupt
Channel manager has completed a command.
When this bit is set to one and the IRQ_EN bit in the
command structure is set to one, the 820x will send
this interrupt to the host after the command
completes.
0
0
0
1
No Command Done interrupt occurred
Command Done interrupt occurred
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6.1.4
820x Interrupt Enable Register
The 820x interrupt Enable register provides the capability for the host to enable/disable
820x interrupts. All interrupt enable bits in this register may be reset by a hardware reset
or a Miscellaneous Soft Reset (MISC_RST fromSection 6.1.5) except the PKP_INT_EN bit
which can only be reset by a hardware or PKP soft reset. Refer to Section 6.1.3 for a
detailed description of each interrupt.
Type:
Offset
Read/Write
x‘000C’
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Reserved
Description
Bits
Reset
31:10
0
Reserved.
GPIO_INT_EN
GPIO Interrupt Enable
9
8
0
0
0
1
GPIO interrupt disabled
GPIO interrupt enabled
RNG_INT_EN
SPI_INT_EN
Random Number Generator Interrupt Enable
0
1
RNG interrupt disabled
RNG interrupt enabled
Serial to Parallel Interface Interrupt Enable
7
6:5
4
0
0
0
0
1
SPI interrupt disabled
SPI interrupt enabled
Reserved
Reserved
FP_INT_EN
Free Pool Interrupt Enable
0
1
Free Pool interrupt disabled
Free Pool interrupt enabled
PCIE_ERR_INT_EN
CM_ERR_INT_EN
Reserved
PCIe Error Interrupt Enable
3
0
0
1
PCIe Error interrupt disabled
PCIe Error interrupt enabled
Command Error Interrupt Enable
2
1
0
0
0
1
Command Error interrupt disabled
Command Error interrupt enabled
Reserved
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Field Name
Description
Bits
Reset
CMD_INT_EN
Command Done Interrupt Enable
Channel manager has completed a command.
0
0
0
1
Command Done interrupt disabled
Command Done interrupt enabled
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6.1.5
Soft Reset Register
The Soft Reset register provides the host the capability to reset the 820x during error
recovery. The Soft Reset register will be cleared by the 820x after the reset is complete.
After a soft reset, the 820x will wait 64 clock cycles to ensure that all modules are reset.
Type:
Offset
Read/Write
x‘0018’
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Reserved
RNG_RST
Description
Bits
Reset
31:5
0
Reserved.
Random Number Generator Soft Reset
4
3
0
0
0
1
Do not reset the RNG
Reset the RNG
GPIO_RST
MISC_RST
General Purpose I/O Soft Reset
0
1
Do not reset the GPIO
Reset the GPIO
Miscellaneous Soft Reset
0
1
Do not reset the misc modules
2
0
Reset all other modules except the GPIO, RNG,
PKP Manager, PKP cores, PCIe core and PHY
PKP_RST
Public key Processor Soft Reset
1
0
0
0
0
1
Do not reset the PKP
Reset the PKP manager and the two PKP pairs
PCIE_RST
PCIe Soft Reset
0
1
Do not reset the PCIe
Reset the PCIe core and PHY
820x – Data Sheet, DS-0157-D
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Hifn Confidential
6.1.6
Device Minor Revision Register
The Device Minor Revision register reflects the device’s minor revision number.
Type:
Offset
Read only
x‘0020
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
Reserved
31:4
0
Reserved.
DEV_MIN_REV[3:0]
Device Minor Revision Number.
Please refer to Chapter 14, “Errata" for the
difference between the 820x revisions.
3:0
0
0000 Preliminary release
0001 First production release
820x – Data Sheet, DS-0157-D
Page138
Hifn Confidential
6.1.7
Card Version Register
The Card Version register allows the host to read the version number of the card. The card
version is read from pads that can be pulled high or low on the card.
Type:
Offset
Read only
x‘0100’
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Reserved.
Bits
31:3
2:0
Reset
Reserved
0
0
CARD_VER[2:0]
Card Version
820x – Data Sheet, DS-0157-D
Page139
Hifn Confidential
6.2 DMA Control Registers
6.2.1
Command Pointer Ring 0 Base Address Register
This register is the base address of the command pointer ring (CPR) 0 in host memory. The
820x uses this base address plus an offset to fetch a command pointer, and then uses the
command pointer to fetch the corresponding command structure. The CPR base address
must be 8-byte aligned, and the command pointer in CPR must be 512-byte aligned.
Type:
Offset
Read/Write
x‘0200’
CPR0_BASEADR_H[31:0]
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
CPR0_BASEADR_L[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
CPR0_BASEADR_H
[31:0]
Command pointer ring 0 base address high double
word
63:32
0
CPR0_BASEADR_L
[31:0]
Command pointer ring 0 base address low double
word
31:0
0
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Page140
Hifn Confidential
6.2.2
Command Pointer Ring 0 Write Pointer Register
This register is a copy of the command pointer ring 0 write pointer in host memory. The
host must update this register whenever new commands are added into the command
pointer ring 0.
The 820x Command Ring 0 Write Pointer register stores the index number (i.e., 1, 2, 3…)
of the corresponding command ring write pointer in host memory. The host updates this
register whenever a new command is submitted to Command Ring 0. The 820x uses the
stored index number (i.e., 1, 2, 3) to refer to the Command Pointer Ring 0 Base Address
register (Section 6.2.1), and calculate the actual address of the newly submitted command
structure in Command Ring 0.
Please refer to Section 3.3, “Command Operation Sequence" for more information about
this register.
Type:
Offset
Read/Write
x‘0208’
CPR0_WP[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Command pointer ring 0 write pointer
Bits
Reset
CPR0_WP[31:0]
31:0
0
6.2.3
Command Pointer Ring 0 Read Pointer Register
This register is the 820x command pointer ring 0 read pointer. The host may read this
register to determine how many entries in the command pointer ring 0 have been read by
the 820x.
Type:
Offset
Read/Write
x‘020C’
CPR0_RP[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Command pointer ring 0 read pointer
Bits
Reset
CPR0_RP[31:0]
31:0
0
820x – Data Sheet, DS-0157-D
Page141
Hifn Confidential
6.2.4
Command Pointer Ring 1 Base Address Register
This register is the base address of the command pointer ring (CPR) 1 in host memory. The
820x uses this base address plus an offset to fetch a command pointer, and then uses the
command pointer to fetch the corresponding command structure. The CPR base address
must be 8-byte aligned, and the command pointer in CPR must be 512-byte aligned.
Type:
Offset
Read/Write
x‘0210’
CPR1_BASEADR_H[31:0]
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
CPR1_BASEADR_L[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
CPR1_BASEADR_H
[31:0]
Command pointer ring 1 base address high double
word
63:32
0
CPR1_BASEADR_L
[31:0]
Command pointer ring 1 base address low double
word
31:0
0
820x – Data Sheet, DS-0157-D
Page142
Hifn Confidential
6.2.5
Command Pointer Ring 1 Write Pointer Register
This register is a copy of the command pointer ring 1 write pointer in host memory. The
host must update this register whenever new commands are added into the command
pointer ring 1.
The 820x Command Ring 1 Write Pointer register stores the index number (i.e., 1, 2, 3…)
of the corresponding command ring write pointer in host memory. The host updates this
register whenever a new command is submitted to Command Ring 1. The 820x uses the
stored index number (i.e., 1, 2, 3) to refer to the Command Pointer Ring 1 Base Address
register (Section 6.2.4), and calculate the actual address of the newly submitted command
structure in Command Ring 0.
Please refer to Section 3.3, “Command Operation Sequence" for more information about
this register.
Type:
Offset
Read/Write
x‘0218’
CPR1_WP[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Command pointer ring 1 write pointer
Bits
Reset
CPR1_WP[31:0]
31:0
0
6.2.6
Command Pointer Ring 1 Read Pointer Register
This register is the 820x command pointer ring 1 read pointer. The host may read this
register to determine how many entries in the command pointer ring 1 have been read by
the 820x.
Type:
Offset
Read/Write
x‘021C’
CPR1_RP[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Command pointer ring 1 read pointer
Bits
Reset
CPR1_RP[31:0]
31:0
0
820x – Data Sheet, DS-0157-D
Page143
Hifn Confidential
6.2.7
Result Ring 0 Base Address Register
This register is the result ring 0 base address in host memory. After the 820x finishes a
command, it will write the result to the result ring. The Result Ring (RR) base address must
be 8-byte aligned.
Type:
Offset
Read/Write
x‘0220’
RR0_BASEADR_H[31:0]
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RR0_BASEADR_L[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
RR0_BASEADR_H
[31:0]
Result ring 0 base address high double word
Result ring 0 base address low double word
63:32
0
RR0_BASEADR_L
[31:0]
31:0
0
6.2.8
Result Ring 0 Write Pointer Register
This register is the 820x result ring 0 write pointer. The host can read this register to
determine the how many entries the 820x has written to the result ring 0.
Type:
Offset
Read/Write
x‘0228’
RR0_WP[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Result ring 0 write pointer
Bits
Reset
RR0_WP[31:0]
31:0
0
820x – Data Sheet, DS-0157-D
Page144
Hifn Confidential
6.2.9
Result Ring 1 Base Address Register
This register is the result ring 1 base address in host memory. After the 820x finishes a
command, it will write the result to the result ring. The Result Ring (RR) base address is 8-
byte aligned.
Type:
Offset
Read/Write
x‘0230’
RR1_BASEADR_H[31:0]
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RR1_BASEADR_L[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
RR1_BASEADR_H
[31:0]
Result ring 1 base address high double word
Result ring 1 base address low double word
63:32
0
RR1_BASEADR_L
[31:0]
31:0
0
6.2.10
Result Ring 1 Write Pointer Register
This register is the 820x result ring 1 write pointer. The host can read this register to
determine the how many entries the 820x has written to the result ring 1.
Type:
Offset
Read/Write
x‘0238’
RR1_WP[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Result ring 1 write pointer
Bits
Reset
RR1_WP[31:0]
31:0
0
820x – Data Sheet, DS-0157-D
Page145
Hifn Confidential
6.2.11
Free Pool Ring Base Address Register
This register is the base address of the Free Pool Ring (FPR). The 820x uses this base
address plus an offset to fetch a free pool entry.
Type:
Offset
Read/Write
x‘0240’
FPR_BASEADR_H[31:0]
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
FPR_BASEADR_L[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
FPR_BASEADR_H
[31:0]
Free pool ring base address high double word
Free pool ring base address low double word
63:32
0
FPR_BASEADR_L
[31:0]
31:0
0
820x – Data Sheet, DS-0157-D
Page146
Hifn Confidential
6.2.12
Free Pool Write Pointer Register
This register is a copy of the Free Pool Ring write pointer in host memory. The host must
update this register when a new entry is added to the free pool ring.
Type:
Offset
Read/Write
x‘0248’
FPR_WP[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
FPR_WP[31:0]
31:0
0
Free pool write pointer
6.2.13
Free Pool Read Pointer Register
This register is the 820x Free Pool Ring read pointer. The host may read this register to
determine how many free pool ring entries have been read by the 820x.
Type:
Offset
Read only
x‘024C’
FPR_RP[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
FPR_RP[31:0]
31:0
0
Free pool read pointer
820x – Data Sheet, DS-0157-D
Page147
Hifn Confidential
6.2.14
DMA Configuration Register
This register is used to set the DMA configuration parameters. The host must configure this
register during system initialization.
Type:
Offset
Read/Write
x‘0250’
Reserved
CPR_SIZE[3:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Reserved
Description
Bits
Reset
31:30
0
Reserved.
DIS_GZIP_RV
Disable GZIP engine real time verification
When the GZIP real time verification core is
disabled, the GZIP clock is also gated to save
power.
29
28
27
0
0
0
0
1
Enable GZIP engine real time verification
Disable GZIP engine real time verification
DIS_LZS_RV
DIS_ENC_RV
DIS_HASH_RV
Reserved
Disable LZS engine real time verification
When the LZS real time verification core is
disabled, the LZS clock is also gated to save
power.
0
1
Enable LZS engine real time verification
Disable LZS engine real time verification
Disable Encryption engine real time verification
When the ENC real time verification core is
disabled, the ENC clock is also gated to save
power.
0
1
Enable ENC engine real time verification
Disable ENC engine real time verification
Disable Hash engine real time verification
When the HASH real time verification core is
disabled, the HASH clock is also gated to save
power.
0
1
26
0
0
Enable HASH engine real time verification
Disable HASH engine real time verification
25:17
Reserved
820x – Data Sheet, DS-0157-D
Page148
Hifn Confidential
Field Name
Description
Bits
Reset
CM_EN[1:0]
Channel Manager Enable
If set, the Channel Manager is enabled to process
commands, otherwise, the Channel Manager will not
process commands and its clock is disabled.
00 Disable Channel Manager 0 and Channel
Manager 1
16:15
14:13
0
0
01 Enable Channel Manager 0
10 Enable Channel Manager 1
11 Enable Channel Manager 0 and Channel
Manager 1
Reserved
Reserved
CPR_SIZE[3:0]
Command Pointer Ring Size
Sets the maximum number of commands in the
command pointer ring.
Note: the command pointer ring size value is the
same for command pointer ring 0 and command
pointer ring 1.
000032
000164
0010128
0011256
0100512
01011K
12:9
0
01102K
01114K
10008K
100116K
1010 - 1111Reserved
Reserved
8:7
6:4
0
0
Reserved
FPR_SIZE[2:0]
Free Pool Ring Size
Sets the maximum number of entries in the free
pool ring.
Note: the free pool is shared by commands in the
CPR0 or CPR1.
0004
0018
01016
01132
10064
101128
110256
111512
820x – Data Sheet, DS-0157-D
Page149
Hifn Confidential
Field Name
Description
Bits
Reset
HOST_EF[1:0]
Host Endian Format
Sets the endian format of the host command pointer
ring, command structure, result ring and free pool
ring.
3:2
0
00 No swap
01 Byte swap in word
10 Word swap, no byte swap in word
11 Word swap and byte swap in word
TWO_CPR_EN
Two Command Ring Pointer Enable
1
0
0
0
0
1
Only Command Ring Pointer 0 enabled
Both Command Ring Pointer 0 and 1 enabled
ADDR64_MODE
DMA Addressing Mode
0
1
32-bit addressing mode
64-bit addressing mode
820x – Data Sheet, DS-0157-D
Page150
Hifn Confidential
6.2.15
Channel Manager 0-1 Error Status Register
If a 820x Channel Manager detects an error, the 820x will set the appropriate bit in this
register. The Host may read the Channel Manager Error Status register to determine the
source of the error. This information may also be read from the entry in the result ring.
Because the Channel Managers continue to process commands after an error, the error bits
in this register may be overwritten. It is recommended that the host validates the error bit
with the result ring error from the command.
Type:
Offset
Read/Write to clear
x‘0260’
Channel Manager 0 error status
Channel Manager 1 error status
x‘0264’
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Channel Manager Data CRC error
Bits
Reset
CM_DCRC
31
0
0
1
Channel Manager did not detect data CRC error
Channel Manager detected data CRC error
CM_KCRC
CM_ECC
Channel Manager Key CRC error
30
29
0
0
0
1
Channel Manager did not detect key CRC error
Channel Manager detected key CRC error
Channel Manager ECC/Parity error
0
Channel Manager did not detect ECC/Parity
error on this channel
1
Channel Manager detected ECC/Parity error
on this channel
Reserved
PAD_ERR
28
27
0
0
Reserved
Pad Engine Padding Error
0
1
Pad Engine did not detect padding error
Pad Engine detected padding error
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Page151
Hifn Confidential
Field Name
Description
Bits
Reset
PAD_CFG_ERR
Pad Engine Software Configuration Error
0
Pad Engine did not detect software configuration
error
26
0
1
Pad Engine detected software configuration
error
PAD_MALFORM_ERR
AES_RV_ERR
Pad Engine Malformed Packet Error.
0
Pad Engine did not detect malformed packet
error
25
24
0
0
1
Pad Engine detected malformed packet error
Encryption Engine Real Time Verification Error.
0
Encryption engine did not detect real time
verification error
1
Encryption engine detected real time
verification error
AES_AU_ERR
Authentication Error in AES-GCM Mode.
0
Authentication error in AES-GCM mode not
detected
23
22
21
0
0
0
1
Authentication error in AES-GCM mode
detected
AES_CFG_ERR
AES_MALFORM_ERR
HASH_RV_ERR
Encryption Engine Software Configuration Error.
0
Encryption Engine did not detect software
configuration error
1
Encryption Engine detected software
configuration error
Encryption Engine Malformed Packet Error.
0
Encryption Engine did not detect malformed
packet error
1
Encryption Engine detected malformed packet
error
Hash Engine Real Time Verification Error or HMAC
Error.
0
Hash engine did not detect real time verification
or HMAC error
20
0
1
Hash engine detected real time verification or
HMAC error
HASH_MAC_ERR
HASH_CFG_ERR
Hash Engine MAC Check Error.
0
1
Hash engine did not detect MAC check error
Hash engine detected MAC check error
19
18
0
0
Hash Engine Software Configuration Error.
0
Hash Engine did not detect software
configuration error
1
Hash Engine detected software configuration
error
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Page152
Hifn Confidential
Field Name
Description
Bits
Reset
HASH_MALFORM_ERR
Hash Engine Malformed Packet Error.
0
Hash Engine did not detect malformed packet
error
17
0
1
Hash Engine detected malformed packet error
GZIP_DECODE_ERR
[5:0]
GZIP Decode Error.
16:11
10
0
0
For a description of this field, please refer to
Table 3-5 on page 93.
GZIP_RCRC_ERR
GZIP Engine RCRC Error
0
GZIP engine did not detect RCRC error in
decode operation
1
GZIP engine detected RCRC error in decode
operation
GZIP_RV_ERR
GZIP Engine Real Time Verification Error
0
GZIP engine did not detect real time verification
error
9
0
1
GZIP engine detected real time verification
error
GZIP_CFG_ERR
GZIP_MALFORM_ERR
GZIP Engine Software Configuration Error
0
GZIP Engine did not detect software
configuration error
8
7
0
0
1
GZIP Engine detected software configuration
error
GZIP Engine Malformed Packet Error
0
GZIP Engine did not detect malformed packet
error
1
GZIP Engine detected malformed packet error
LZS_ECC_ERR
LZS_TERR
LZS Engine ECC Error
0
1
LZS engine did not detect ECC error
LZS engine detected ECC error
6
5
4
0
0
0
LZS Engine Token Error
0
1
LZS engine did not detect token error
LZS engine detected token error
LZS_DERR
LZS Engine Data Error
0
1
LZS engine did not detect data error
LZS engine detected data error
LZS_RCRC_ERR
LZS Engine RCRC Error
0
LZS engine did not detect RCRC error in
decode operation
3
1
LZS engine detected RCRC error in decode
operation
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Page153
Hifn Confidential
Field Name
Description
Bits
Reset
LZS_RV_ERR
LZS Engine Real Time Verification Error
0
LZS engine did not detect real time verification
error
2
1
LZS engine detected real time verification error
LZS_CFG_ERR
LZS Engine Software Configuration Error
0
LZS Engine did not detect software configuration
error
1
0
0
0
1
LZS Engine detected software configuration
error
LZS_MALFORM_ERR
LZS Engine Malformed Packet Error
0
LZS Engine did not detect malformed packet
error
1
LZS Engine detected malformed packet error
820x – Data Sheet, DS-0157-D
Page154
Hifn Confidential
6.2.16
Channel Manager 0-1 Error Command Index Register
The Channel Manager 0-1 Error Command Index register records the last processing
command index when the PCIe related error occurred. This record can be used to facilitate
software error recovery.
Type:
Offset
Read only
x‘0268’
Channel Manager 0 error command index
Channel Manager 1 error command index
x‘026C’
CPR1_CMD_INX[14:0]
CPR0_CMD_INX[14:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
31
Reset
Reserved
0
0
0
Reserved
CPR1_CMD_INX[14:0]
Reserved
30:16
15
Command Pointer Ring 1 Command Index [14:0]
Reserved
CPR0_CMD_INX[14:0]
Command Pointer Ring 0 Command Index [14:0]
If command ring size is 16K, bit 14 is the valid bit;
if command ring size is 8K, bit 13 is the valid bit;
if command ring size is 4K, bit 12 is the valid bit.
14:0
0
A similar pattern may be applied for command ring
sizes < 4K.
820x – Data Sheet, DS-0157-D
Page155
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6.3 Engine Configuration Registers
6.3.1
Hash Engine Mute Table Entry Registers
The Hash Engine Mute Table Entry register provides a mask that controls the input to the
Hash engine. The mask nulls specific segments of the data stream prior to being submitted
to the Hash core. The masks are programmable by the host and are selected by the “MTI”
field in command structure.
Each mute table entry is 32 bits wide to mute up to 16 bytes of the data stream. There are
seven entries in the mute table. Each bit of the mute table entry masks one nibble (4-bit)
of data, therefore a 32-bit register word supports a 16-byte header. The table below
provides the map between the mute table entry bit and the 16-byte header nibble (4-bit).
Type:
Offset
Read/Write
x‘0400’
x‘0404’
x‘0408’
x‘040C’
x‘0410’
x‘0414’
x‘0418’
Mute table entry 1
Mute table entry 2
Mute table entry 3
Mute table entry 4
Mute table entry 5
Mute table entry 6
Mute table entry 7
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Mute Data Stream Byte 15, bits [7:4]
Bits
Reset
Byte15_HN
31
0
0
1
Do not mute data stream byte 15, bits [7:4]
Mute data stream byte 15, bits [7:4]
Byte15_LN
Mute Data Stream Byte 15, bits [3:0]
30
0
0
1
Do not mute data stream byte 15, bits [3:0]
Mute data stream byte 15, bits [3:0]
.
.
.
.
.
.
.
.
.
.
.
.
Byte0_HN
Mute Data Stream Byte 0, bits [7:4]
1
0
0
1
Do not mute data stream byte 0, bits [7:4]
Mute data stream byte 0, bits [7:4]
820x – Data Sheet, DS-0157-D
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Field Name
Description
Bits
Reset
Byte0_LN
Mute Data Stream Byte 0, bits [3:0]
0
0
0
1
Do not mute data stream byte 0, bits [3:0]
Mute data stream byte 0, bits [3:0]
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6.4 Public Key Processor Control Registers
The Public Key Processor (PKP) implements a group of registers, through which the host
may control the PKP engine and execute complex computations. The PKP Manager fetches
source data and instructions from host memory, and then sends the computation result to
host memory according to the PKP command registers.
To increase performance, the 820x implements two pairs of PK cores; a pair consists of one
master PK core and one slave PK core.
6.4.1
Public Key Enable Register
The Public Key Engine register is used to enable/disable either of the Public Key Engine
pairs and the Public Key Engine.
Type:
Offset
Read/Write
x‘0580’
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Reserved
Description
Bits
Reset
31:3
0
Reserved.
DIS_PK_PAIR1
Disable Public Key Pair 1
If the PK core 1 is disabled, the PK core 1 clock is
also disabled to save power.
2
1
0
0
0
1
Enable Public Key Pair 1
Disable Public Key Pair 1
DIS_PK_PAIR0
Disable Public Key Pair 0
If the PK core 0 is disabled, the PK core 0 clock is
disabled to save power.
0
1
Enable Public Key Pair 0
Disable Public Key Pair 0
PK_EN
Public Key Enable
Note: the host software should first enable the PKP,
and then write commands to the PKP command
entry.
0
0
0
Disable the PKP Manager and PKP Engine and
clock
1
Enable the PKP Manager and PKP Engine
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6.4.2
Public Key Command Entry Registers
The Public Key Command Entry registers control the eight PKP command entries in the
820x. Each entry includes one command register, one instruction register, one data
register, and one result register as shown below.
PKP Command (4 bytes)
PKP Instruction (16 bytes)
PKP Data (16 bytes)
PKP Result (16 bytes)
Figure 6-2. PKP Command Entry Format
820x – Data Sheet, DS-0157-D
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Type:
Offset
Read/Write
x‘0600’
x‘0610’
x‘0620’
x‘0630’
x‘0640’
x‘0650’
x‘0660’
x‘0670’
x‘0680’
x‘0690’
x‘06A0’
x‘06B0’
x‘06C0’
x‘06D0’
x‘06E0’
x‘06F0’
x‘0700’
x‘0710’
x‘0720’
x‘0730’
x‘0740’
x‘0750’
x‘0760’
x‘0770’
x‘0780’
x‘0790’
x‘07A0’
x‘07B0’
x‘07C0’
x‘07D0’
x‘07E0’
x‘07F0’
Public Key entry 0 command register
Public Key entry 0 instruction register
Public Key entry 0 data register
Public Key entry 0 result register
Public Key entry 1 command register
Public Key entry 1 instruction register
Public Key entry 1 data register
Public Key entry 1 result register
Public Key entry 2 command register
Public Key entry 2 instruction register
Public Key entry 2 data register
Public Key entry 2 result register
Public Key entry 3 command register
Public Key entry 3 instruction register
Public Key entry 3 data register
Public Key entry 3 result register
Public Key entry 4 command register
Public Key entry 4 instruction register
Public Key entry 4 data register
Public Key entry 4 result register
Public Key entry 5 command register
Public Key entry 5 instruction register
Public Key entry 5 data register
Public Key entry 5 result register
Public Key entry 6 command register
Public Key entry 6 instruction register
Public Key entry 6 data register
Public Key entry 6 result register
Public Key entry 7 command register
Public Key entry 7 instruction register
Public Key entry 7 data register
Public Key entry 7 result register
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6.4.2.1
Public Key Command Register Format
The Command register indicates the PKP command flag and status.
EF[1:0]
LIRA_M[10:0]
LIRA_S[10:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
CMD_V
Command Valid
After this bit is set, the 820x will begin to process
the command for this entry.
Note: The host must set this bit to one after setting
the Instruction Register, Data Register and Result
Register.
31
0
The 820x will clear this bit after the process is
complete. The host must poll this register to
determine whether a command has completed.
0
1
Command in this entry is not valid
Command in this entry is valid
PAIR
PK Pair Notification
After the 820x finishes a command, it will set this
bit to inform the host which PK pair completed the
current command. The host software need not
configure this bit.
30
29
0
0
0
1
PK Pair 0 completed this command
PK Pair 1 completed this command
ECC_ERR
ECC error
0
No ECC error in source buffer or destination
buffer
1
ECC error in source buffer or destination buffer
ADDR_ERR
Reserved
Host Access PKP Address out of range
This error is due to an error in software
configuration. The 820x reports the error but takes
no action.
28
27
0
0
Reserved
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Field Name
Description
Bits
Reset
IS_V
Instruction Register Valid
This bit is used to simplify the command operation
process. Usually, the host loads the instruction
programs in the first command, and then sets the
LIRA in the following commands because the
instruction programs have already been loaded in
the PKP Linear Instruction Register by the first
command.
If this bit is set to one, the PKP Manager will wait
until all PK pairs are idle, and then write the
instruction to all PK pairs. This mechanism can
simplify the instruction loading to all PK pairs, and
maintain the same instruction field for all PK pairs.
In other words, the 820x can balance the PK pair
load, and the load balancing is transparent to the
host software.
26
0
0
1
Instruction Register is not valid in this entry
820x requires load instruction in host memory
into the PKP engine instruction register
DATA_V
Data Register Valid
The 820x will load data to one of the PK pairs when
this bit is set to one.
Typically, the host would set this bit to zero when
writing to the PK pair instruction register for the first
command that does not require any computation.
25
0
0
1
Data Register is not valid for this entry
Data Register is valid for this entry
Reserved
EF[1:0]
24
0
0
Reserved
Instruction and Data Endian Format
00 No swap
23:22
01 Byte swap in word
10 Word swap, no byte swap in word
11 Word swap and byte swap in word
LIRA_M[10:0]
LIRA_S[10:0]
PKP Master Linear Instruction Register (LIR) start
address
21:11
10:0
0
0
The PKP Master will execute instruction code from
this address.
PKP Slave Linear Instruction Register (LIR) start
address
The PKP Slave will execute instruction code from
this address.
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6.4.2.2
Public Key Instruction Register Format
The Instruction register indicates the host source instruction buffer address, the PKP
destination instruction register address, and the instruction size.
PKP_Istr_Addr_S[14:0]
Istr_Len_S[10:0]
127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100
99 98 97 96
PKP_Istr_Addr_M[14:0]
Istr_Len_M[10:0]
95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
Host_Istr_Addr[63:32]
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Host_Istr_Addr[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
Reserved
127:125
0
Reserved
PKP_Istr_Addr_S[14:0]
PKP Slave Linear Instruction Register (LIR) Start
Address
124:110
109:107
0
0
This address must be 4-byte aligned because all PKP
registers are double word aligned.
Reserved
Reserved
Istr_Len_S[10:0]
PKP Slave Instruction Size
Istr_Len_M and Istr_len_S cannot both be equal to
zero for any command when IS_V = 1 in the PK
command register.
106:96
0
The host instruction buffer size = Istr_len_M +
Istr_Len_S.
0
No instruction for PKP Slave
1 - 2047 Number of double word instructions
Reserved
95:93
92:78
77:75
0
0
0
Reserved
PKP_Istr_Addr_MS[14:0]
PKP Master Linear Instruction Register (LIR) Start
Address
This address must be 4-byte aligned because all PKP
registers are double word aligned.
Reserved
Reserved
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Field Name
Description
Bits
Reset
Istr_Len_M[10:0]
PKP Master Instruction Size
Istr_Len_M and Istr_len_S cannot both equal to
zero for any command when IS_V = 1.
74:64
0
The host instruction buffer size = Istr_len_M +
Istr_Len_S.
0
No instruction for PKP Slave
1 - 2047 Number of double word instructions
Host_Istr_Addr[63:0]
Host Instruction Buffer Address
63:0
0
This address must be 8-byte aligned.
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6.4.2.3
Public Key Data Register Format
The Public Key Data register indicates the source data size for PK Slave, the source data
size for the PK Master, and the host source data buffer address. The host source buffer size
is equal to the total source data size for PK Slave plus the total source data size for the PK
Master. TSR, BER, FPR and MMR are PK core internal registers. Detailed information will be
provided in a PK document that will be released in the future.
Data_Len_S[31:0]
127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100
Data_Len_M[31:0]
99 98 97 96
95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
Host_Data_Addr[63:32]
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Host_Data_Addr[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
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Field Name
Description
Bits
Reset
Data_Len_S[31:0]
PKP Slave Source Data Length.
This field is a conglomeration of 4 subfields:
TSR_CNT[1:0], FPR_LEN[9:0], MMR_LEN[9:0] and
BER_LEN[9:0]. The total source data length is the
sum of these 4 subfields. If TSR_CNT + FPR_LEN +
MMR_LEN + BER_LEN = 0, there is no source data
for the slave PKP.
Bits [127:126] = TSR_CNT[1:0]
PKP TSR data count
00 Zero
01 Same as BER_LEN
10 Same as MMR_LEN
11 Same as FPR_LEN
Bits [125:116] = FPR_LEN[9:0]
PKP FPR data count
127:96
0
0
Zero, no data for FPR register
1 - 10231 ~ 1023 double words (32 bits)
Bits [115:106] = MMR_LEN[9:0]
PKP MMR data count
0
Zero, no data for MMR register
1 - 10231 ~ 1023 double words (32 bits)
Bits [105:96] = BER_LEN[9:0]
PKP BER data count
0
Zero, no data for BER register
1 - 10231 ~ 1023 double words (32 bits)
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Field Name
Description
Bits
Reset
Data_Len_M[31:0]
PKP Master Source Data Length.
This field is a conglomeration of 4 subfields:
TSR_CNT[1:0], FPR_LEN[9:0], MMR_LEN[9:0] and
BER_LEN[9:0]. The total source data length is the
sum of these 4 subfields. If TSR_CNT + FPR_LEN +
MMR_LEN + BER_LEN = 0, there is no source data
for the master PKP.
Bits [95:94] = TSR_CNT[1:0]
PKP TSR data count
00 Zero
01 Same as BER_LEN
10 Same as MMR_LEN
11 Same as FPR_LEN
Bits [93:84] = FPR_LEN[9:0]
PKP FPR data count
95:64
0
0
Zero, no data for FPR register
1 - 10231 ~ 1023 double words (32 bits)
Bits [83:74] = MMR_LEN[9:0]
PKP MMR data count
0
Zero, no data for MMR register
1 - 10231 ~ 1023 double words (32 bits)
Bits [73:64] = BER_LEN[9:0]
PKP BER data count
0
Zero, no data for BER register
1 - 10231 ~ 1023 double words (32 bits)
Host_Data_Addr[63:0]
Host Data Buffer Address
63:0
0
This address must be 8-byte aligned.
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6.4.2.4
Public Key Result Register
The Result register indicates the host destination result buffer address, the PKP source
result register address, and the result size. The host result data buffer size is equal to
Data_Len_M plus Data_Len_S.
PKP_Data_Addr_S[14:0]
Data_Len_S[10:0]
127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100
99 98 97 96
PKP_Data_Addr_M[14:0]
Data_Len_M[10:0]
95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
Host_Result_Addr[63:32]
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Host_Result_Addr[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
Reserved
127:125
0
Reserved.
PKP_Data_Addr_S[14:0]
PKP Slave Result Data Register Start Address.
This address must be 4-byte aligned.
124:110
109:107
0
0
Reserved
Reserved
Data_Len_S[10:0]
PKP Slave Result Data Size.
This field must be 2 double word aligned.
Data_Len_M and Data_Len_S cannot both equal to
zero for any command when IS_V = 1.
106:96
0
The host result data buffer size = Data_Len_M +
Data_Len_S.
0
No Result Data for PKP Master
1 - 2047 Number of double word data
Reserved
95:93
92:78
77:75
0
0
0
Reserved.
PKP_Data_Addr_M[14:0]
PKP Master Result Data Register Start Address.
This address must be 4-byte aligned.
Reserved
Reserved.
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Field Name
Description
Bits
Reset
Data_Len_M[10:0]
PKP Master Result Data Size.
This field must be 2 double word aligned.
Data_Len_M and Data_Len_S cannot both equal to
zero for any command when IS_V = 1.
74:64
0
The host result data buffer size = Data_len_M +
Data_Len_S.
0
No data for PKP Slave
1 - 2047 Number of double word data
Host_Result_Addr[63:0]
Host Result Data Buffer Address.
63:0
0
This address must be 8-byte aligned.
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6.4.3
Public Key Internal Registers
To access the PKP internal registers, please refer to the EXP-E5200 Public Key
Cryptography Microprocessor Datasheet from Athena.
Type:
Offset
Read/Write
x‘0TBD’
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6.5 RNG Control Registers
6.5.1
RNG Enable Register
The RNG Enable register is used by the host to enable the 820x Random Number
Generator.
Type:
Offset
Read/Write
x‘0800’
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Reserved
RNG_EN
Description
Bits
Reset
31:1
0
Reserved
Random Number Generator Enable/Disable
0
0
0
1
RNG and RNG clock disabled
RNG enabled
6.5.2
RNG Test Register
The RNG Test register allows the host software to perform read/write tests to the RNG
address space. It serves no other function and causes no side effects. This register may be
accessed at any time.
Type:
Offset
Read/Write
x‘0804’
Test[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
Test[31:0]
Test data read/written from host into RNG memory
space.
31:0
0
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6.5.3
RNG Interrupt Enable Register
The RNG Interrupt Enable register allows the host software to enable/disable the 820x RNG
interrupts. If a RNG Enable bit is set to one, the interrupt is enabled for that event. If the
enable bit is cleared to zero, the interrupt will be disabled and will not interrupt the host,
but the interrupt will appear in the RNG Interrupt Control / Status register as expected.
The LEG2_XOR_ERR, LEG1_XOR_ERR and TREE_XOR_ERR pertain to internal RNG logic. If
any of these errors occur, please contact Hifn customer support.
Type:
Offset
Read/Write one to clear
x‘0808’
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Reserved
Description
Bits
Reset
31:6
0
Reserved.
RING_FAIL_EN
Ring Failure Interrupt Enable
Asserts an interrupt if any of the ring oscillators are
not oscillating.
5
4
3
2
0
0
0
0
0
1
Disable ring failure interrupt
Enable ring failure interrupt
LEG2_XOR_ERR_EN
LEG1_XOR_ERR_EN
TREE_XOR_ERR_EN
Leg 2 XOR Error Interrupt Enable
Asserts an interrupt if there was an error in the Leg
2 XOR RNG logic.
0
1
Disable Leg 2 XOR error interrupt
Enable Leg 2 XOR error interrupt
Leg 1 XOR Error Interrupt Enable
Asserts an interrupt if there was an error in the Leg
1 XOR RNG logic.
0
1
Disable Leg 1 XOR error interrupt
Enable Leg 1 XOR error interrupt
Tree XOR Error Interrupt Enable
Asserts an interrupt if there was an error in the Tree
XOR RNG logic.
0
1
Disable Tree XOR error interrupt
Enable Tree XOR error interrupt
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Field Name
Description
Bits
Reset
BUF_DONE_EN
Buffer Done Flag Interrupt Enable
Asserts an interrupt if the Buffer_Done_Flag in the
Interrupt Control / Status Register is set.
1
0
0
1
Disable Buffer Done Flag interrupt
Enable Buffer Done Flag interrupt
ILL_ACC_EN
Illegal Access Interrupt Enable
Asserts an interrupt if an illegal access to reserved
memory space by one of the N8TBus interfaces was
detected.
0
0
0
1
Disable Illegal Access interrupt
Enable Illegal Access interrupt
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6.5.4
RNG Interrupt Control/Status Register
The RNG Interrupt Control/Status register allows the host software to read the 820x RNG
interrupt status. The error bits in this registers will be set if that error event has occurred.
If the error's corresponding enable bit is set in the RNG Interrupt Enable Register, an
interrupt will be generated to the host.
The LEG2_XOR_ERR, LEG1_XOR_ERR and TREE_XOR_ERR pertain to internal RNG logic. If
any of these errors occur, please contact Hifn customer support.
Type:
Offset
Read/Write one to clear
x‘080C’
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
Reserved
31:6
0
Reserved.
RING_FAIL_FLAG
Ring Failure Flag.
One or more ring oscillators failed to oscillate.
5
4
3
2
0
0
0
0
0
1
Ring failure not detected
Ring failure detected
LEG2_XOR_ERR_FLAG
LEG1_XOR_ERR_FLAG
TREE_XOR_ERR_FLAG
Leg 2 XOR Error Flag.
An error was detected in the RNG Leg 2 XOR logic.
0
1
Leg 2 XOR error not detected
Leg 2 XOR error detected
Leg 1 XOR Error Flag.
An error was detected in the RNG LEG 1 XOR logic.
0
1
Leg 1 XOR error not detected
Leg 1 XOR error detected
Tree XOR Error Interrupt Flag.
An error was detected in the RNG Tree XOR logic.
0
1
Tree XOR error not detected
Tree XOR error detected
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Field Name
Description
Bits
Reset
BUF_DONE_FLAG
Buffer Done Flag
Buffer has been filled with random seeds, i.e., a 1-
to-0 transition of the Buffer_Go/Busy bit was
detected.
1
0
0
1
Buffer Done Flag condition not detected
Buffer Done Flag condition detected
ILL_ACC_FLAG
Illegal Access Flag
An access to reserved memory space by one of the
N8TBus interfaces was detected.
0
0
0
1
Illegal Access not detected
Illegal Access detected
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6.5.5
RNG Buffer Control/Status Register
The RNG Buffer Control/Status register provides buffer control and status information. This
register may be read at any time. However, writing to this register is only allowed when
Buffer_Go/Busy is zero, otherwise the access will be treated as an access to reserved
memory space.
The Sample Interval should generally be set such that at the currently specified bit rate
(see RNG configuration register Bit Rate field in Section 6.5.7) at least 32 bits have been
sampled between sample intervals. Setting the Sample Interval larger helps with increasing
entropy of the random numbers, at the cost of generating random numbers at a smaller
rate. For example,
Sample Interval >= 32 * (bit rate + 1)
should always be true for normal operation. While
Sample Interval ~= 128 * (bit rate + 1)
is recommended for a reasonable entropy versus performance compromise.
Type:
Offset
Read/Write
x‘0810’
Buffer_Words field is Read only
BUF_WORDS[4:0]
SMPL_INVL[25:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
BUF_GO_BSY
Buffer Go/Busy
Writing a one to this bit causes the RNG buffer to be
filled with 16 new random seeds, regardless of the
number of unread seeds still in the Buffer (if any).
This bit will remain set until the operation is
complete, at which time it will return to zero.
31
0
0
1
RNG Buffer ready to be filled
Initiates filling RNG Buffer with new random
seed
BUF_WORDS[4:0]
SMPL_INVL[25:0]
Buffer Words
The number of random seeds available in the buffer.
This field will be decremented on each valid access
of the Buffer Data Register (Section 6.5.6).
30:26
25:0
0
0
Sample Interval
Number of clocks to skip between capturing the 32
bit output of the Seed Generator into the RNG
buffer.
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6.5.6
RNG Buffer Data Register
The contents of the RNG Buffer may be read, one word at a time, through this register. This
register must never be written; any writes will be treated as an access to Reserved memory
space. This register may be read only when RNG Buffer Control Status register (Section
6.5.5) bits BUF_GO/BSY is zero and BUF_WORDS is nonzero; otherwise the read will be
treated as an access to Reserved memory space.
Type:
Offset
Read only
x‘0814’
When BUF_GO/BSY is zero AND
BUF_WORDS is nonzero
BUF_DATA[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Data from RNG seed buffer.
Bits
Reset
BUF_DATA[31:0]
31:0
0
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6.5.7
RNG Configuration Register
The RNG Configuration register is used to set the RNG bit rate. The bit rate is used to
determine the RNG sample rate, as described in Section 6.5.4, “RNG Interrupt Control/
Status Register".
Type:
Offset
Read/write
x‘0824’
Reserved
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
RSVD
Description
Reserved.
Bit Rate.
Bits
Reset
31:11
0
BIT_RATE[2:0]
The number of 125MHz clock cycles between bit
samples in the serial-to-parallel conversion /
whitening LFSR.
0
1
2
3
4
5
6
7
125 Mbps (continuous)
62.5 Mbps
10:8
000
41.7 Mbps
31.25 Mbps
25 Mbps
20.8 Mbps
17.9 Mbps
15.63 Mbps
RSVD
7:0
0
Reserved.
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6.6 GPIO Registers
The GPIO registers provide flexibility to configure the 820x GPIO pins. The operation
sequence for configuring the GPIO registers is:
1. Set the GPIO port direction to either input or output.
2. Configure the interrupt mode if needed.
3. Read data from the GPIO EXT register if the GPIO are configured as input; write
data to the GPIO SW DATA register if the GPIO are configured as output.
6.6.1
GPIO Enable Register
The GPIO Enable register is used by the host to enable the 820x General Purpose I/O
registers.
Type:
Offset
Read/Write
x‘0850’
GPIO Enable Register
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Reserved
GPIO_EN
Description
Bits
Reset
31:1
0
Reserved
General Purpose I/O Enable/Disable.
0
0
0
1
GPIO and GPIO clock disabled
GPIO enabled
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6.6.2
GPIO Software Data Register
If the data direction bits in the GPIO Data Direction register are set to “output” mode and
the control field is set to “Software” mode, then data written to the GPIO Software Data
register are output to the 820x general purpose I/O pins. The value read back is equal to
the last value written to this register.
Type:
Offset
Read/Write
x‘0854’
Reserved
GPIO_SW_DATA[15:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
Reserved
31:16
0
Reserved.
GPIO_SW_DATA
[15:0]
GPIO_SW GPIO Software Data.
_RESET
15:0
6.6.3
GPIO Data Direction Register
The GPIO Data Direction register is used to control the direction of the data bits in the GPIO
Software register. Each bit may be independently set as either input or output. The default
direction is input.
Type:
Offset
Read/Write
x‘0858’
Reserved
GPIO_DDR[15:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
Reserved
31:16
0
Reserved.
GPIO_DDR
[15:0]
GPIO Data Direction.
The direction for each bit can be set as:
15:0
0
0
1
Input
Output
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6.6.4
GPIO Interrupt Enable Register
The GPIO Interrupt Enable register allows each GPIO bit to be independently configured as
an interrupt. By default, using the GPIO ports as interrupts is disabled. If a one is written
to a bit of this register, that GPIO bit will become an interrupt. Otherwise, it operates as a
normal GPIO port. Interrupts will be disabled if the corresponding Data Direction register bit
is set to Output or if its Mode is set to Hardware.
Type:
Offset
Read/Write
x‘0860’
Reserved
GPIO_INT_EN[15:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
Reserved
31:16
0
Reserved.
GPIO_INT_EN
[15:0]
GPIO Interrupt Enable.
Each GPIO bit can be configured as:
15:0
0
0
1
Normal GPIO port (default)
Interrupt
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6.6.5
GPIO Interrupt Mask Register
The GPIO Interrupt Mask register is used to mask the GPIO interrupts. By default, all
interrupts bits are unmasked.
If a one is written to a bit in this register, that bit will be masked from generating an
interrupt. The host may be read this register to determine the masked/unmasked status of
each bit.
Type:
Offset
Read/Write
x‘0864’
Reserved
GPIO_INT_MASK[15:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
Reserved
31:16
0
Reserved.
GPIO_INT_MASK
[15:0]
GPIO Interrupt Mask.
Each GPIO bit can be masked as:
15:0
0
0
1
Unmasked (default)
Masked
6.6.6
GPIO Interrupt Type Register
The GPIO Interrupt Type register controls whether the interrupt is level-sensitive or
otherwise edge-sensitive. Each bit may be independently set.
Type:
Offset
Read/Write
x‘0868’
Reserved
GPIO_INT_TYPE[15:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
Reserved
31:16
0
Reserved.
GPIO_INT_TYPE
[15:0]
GPIO Interrupt Type.
Each GPIO bit can be set as:
15:0
0
0
1
Level-sensitive (default)
Edge-sensitive
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6.6.7
GPIO Interrupt Polarity Register
The GPIO Interrupt Polarity register controls the polarity of the edge or level sensitivity for
each GPIO bit. If a zero is written to a bit of this register, the polarity for that GPIO
interrupt bit will be configured as falling-edge or active-low; otherwise, if a one is written,
the bit will be configured as rising-edge or active-high. Each bit may be independently set.
Type:
Offset
Read/Write
x‘086C’
Reserved
GPIO_INT_POL[15:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
Reserved
31:16
0
Reserved.
GPIO_INT_POL
[15:0]
GPIO Interrupt Polarity.
Each GPIO bit can be set as:
15:0
0
0
1
Active-low (default)
Active-high
6.6.8
GPIO Interrupt Status Register
The GPIO Interrupt Status register may be read by the host to determine the GPIO
interrupt status. This register will reflect any masking that has been set using the GPIO
Interrupt Mask register.
Type:
Offset
Read/Write
x‘0870’
Reserved
GPIO_INT_STAT[15:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
Reserved
31:16
0
Reserved.
GPIO_INT_STAT
[15:0]
GPIO Interrupt Status
15:0
0
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6.6.9
GPIO Interrupt Raw Status Register
The GPIO Interrupt Raw Status register may be read by the host to determine the GPIO
interrupt status. This register does not reflect any masking that has been set using the
GPIO Interrupt Mask register.
Type:
Offset
Read/Write
x‘0874’
Reserved
GPIO_INT_RAW_STAT[15:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
Reserved
31:16
0
Reserved.
GPIO_INT_RAW
STAT
[15:0]
GPIO Interrupt Raw Status.
15:0
0
6.6.10
GPIO De-Bounce Register
The GPIO De-Bounce register controls whether an external signal that is the source of an
interrupt needs to be debounced to remove any spurious glitches. Writing a one to a bit in
this register enables the debouncing circuitry. Once enabled, a signal must be valid for two
periods of an external clock before it is internally processed.
Type:
Offset
Read/Write
x‘0878’
Reserved
GPIO_DEBOUNCE[15:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
Reserved
31:16
0
Reserved.
GPIO_DEBOUNCE
[15:0]
GPIO De-bounce enable/disable.
15:0
0
0
1
Disable debounce (default)
Enable debounce
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6.6.11
GPIO Interrupt Clear Register
The GPIO Interrupt Clear register controls the clearing of edge type interrupts. If a one is
written into a bit of this register, the interrupt corresponding to that bit will be cleared.
Type:
Offset
Read/Write
x‘087C’
Reserved
GPIO_INT_CLR[15:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
Reserved
31:16
0
Reserved.
GPIO_INT_CLR
[15:0]
GPIO Interrupt Clear.
15:0
0
0
1
Do not clear interrupt (default)
Clear interrupt
6.6.12
GPIO Interrupt Ext Register
If the data direction of the GPIO port is configured as “input,” this register can be used to
read the values on the GPIO port. When the data direction of GPIO Port is set as “output,”
reading this location reads the data register for that port.
Type:
Offset
Read/Write
x‘0880’
Reserved
GPIO_INT_EXT[15:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
Reserved
31:16
0
Reserved.
GPIO_INT_EXT
[15:0]
External GPIO Interrupt.
Data dir=input
15:0
0
Read GPIO port
Data dir=output
Read data register for that GPIO port
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6.6.13
GPIO Interrupt Sync Register
The GPIO Interrupt Sync register controls whether level sensitive interrupts are
synchronized to pclk_intr.
Type:
Offset
Read/Write
x‘0884’
Reserved
GPIO_INT_SYNC[15:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Reserved.
GPIO Sync.
Bits
Reset
Reserved
31:16
0
GPIO_INT_SYNC
[15:0]
15:0
0
0: Do not synchronize to pclk_intr
1: Synchronize to pclk_intr
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6.7 Serial/Parallel Interface Registers
The 820x serial to parallel interface (SPI) can be used to connect the 820x to an external
flash. The host can read/write the flash data through PCIe memory write/read SPI
registers. Figure 6-3 illustrates how the 820x may be connected to a flash device.
Figure 6-3. SPI Example Usage
The following flash devices are recommended:
Silicon Storage Technology: SST25VF032B 32 Mbit SPI Serial Flash
Spansion S25FL128P
6.7.1
SPI Register Operation flow
Prior to configuring any other SPI registers, it is necessary to set the SPI Enable Register.
The registers Flash Command Configuration Register 0 and Flash Command Configuration
Register 1 are set once during initialization by the host software. Setting the SPI Command
Address Register will trigger the 820x SPI module to process the current SPI command.
The following diagram illustrates the process flow for a flash operation.
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Figure 6-4. SPI Operation Flash Example
The sequence to write 4 bytes of data to the flash device would be:
1. Configure SPI Enable Register for a write operation.
2. Set WREN, Byte-Program, and RD-status fields in the Flash Command
Configuration register 0. (Note: This step is only required if not using a
recommended flash, or if this field has been set previously).
3. Write the 4 bytes of data to be programmed into the Flash into the SPI Data
Register.
4. Set the CS, SPI_CMD, SPI_CLK_DIV, SPI_ADDR fields in the SPI Command
Address Register. The 820x SPI module will then perform the write command.
5. When the write command is done, the 820x SPI module will issue a SPI_IRQ
interrupt to the host, and simultaneously set the SPI_OP_DONE field and
SPI_Status field in the SPI Status Register.
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The sequence to read 4 bytes of data from the flash device would be:
1. Configure the SPI Enable Register for a read operation.
2. Set the RD_Data field in the Flash Command Configuration Register 1, and set
the RD-status field in Flash Command Configuration Register 0. (Note: This step
is only required if not using a recommended flash, or if these fields have been set
previously).
3. Set the CS, SPI_CMD, SPI_CLK_DIV, and SPI_ADDR fields in the SPI Command
Address Register. The 820x SPI module will then perform the read command.
4. When the read command is done, the 820x SPI module will issue a SPI_IRQ
interrupt to the host, and simultaneously set the SPI_OP_DONE field and the
SPI_Status field in the SPI Status Register. The host software can the read the
data from the SPI data register.
The sequence to erase data from the flash device would be:
1. Configure the SPI Enable Register for a write operation.
2. Set the WREN, Sector_Erase/Chip_Erase, and RD-status fields in the Flash
Command Configuration Register 0. (Note: This step is only required if not using
a recommended flash, or if these fields have been set previously).
3. Set the CS, SPI_CMD, SPI_CLK_DIV, and SPI_ADDR fields in SPI Command
Address Register. The 820x SPI module will then perform the erase flash
command.
4. When the erase flash command is done, the 820x SPI module will issue a
SPI_IRQ interrupt to the host, and simultaneously set the SPI_OP_DONE and
SPI_Status fields in the SPI Status Register.
The sequence to write a user defined command to the flash device would be:
1. Configure the SPI Enable Register for a write operation.
2. Set the SPI_User_CMD field in the SPI User Defined Command Register. (Note:
This step is only required if not using a recommended flash, or if these fields
have been set previously)
3. Set the CS, SPI_CMD, SPI_CLK_DIV, and SPI_ADDR fields in the SPI Command
Address Register. The 820x SPI module will then perform the write command.
4. When the write command is done, the 820x SPI module will issue a SPI_IRQ
interrupt to the host, and simultaneously set the SPI_OP_DONE and SPI_Status
fields in the SPI Status Register.
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6.7.2
SPI Enable Register
The SPI Enable register is used by the host to enable the 820x serial to parallel interface.
Type:
Offset
Read/Write
x‘08C0’
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Reserved
SPI_EN
Description
Bits
Reset
31:1
0
Reserved
Serial to Parallel Interface Enable/Disable
0
0
0
1
SPI interface disabled
SPI interface enabled
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6.7.3
SPI Command Address Register
The SPI Enable register is used by the host to enable the 820x serial to parallel interface.
Once the host writes to this register, the 820x will issue a SPI write/read operation to the
external chip. For a write operation, the host should first write the data to the SPI Data
Register before writing to this register. For a read operation, the read data will be stored in
SPI Data Register after the SPI_OP_Done bit in the SPI Status Register is set.
Type:
Offset
Read/Write
x‘08C4’
SPI_ADR[23:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
CS
Chip Select
31
0
0
1
Reserved
Current operation is for the flash chip
SPI_CMD[2:0]
Serial to Parallel Command.
If CS = 1 (flash operations)
000Write 4 bytes of data to flash
001Read 4 bytes of data from flash
010Read Identification (one byte manufacture ID
and one byte Device ID)
30:28
0
011Sector Erase (sector size depends on flash type)
100User defined command (the User Defined
Command Register defines the detail
command, the 820x will just write the
command to flash)
Others Reserved
SPI_CLK_DIV[2:0]
SPI Clock Divisor.
The SPI clock is equal to 125MHZ/SPI_CLK_DIV.
000No division
001Divide by 2
010Divide by 4
27:25
0
011Divide by 8
100Divide by 16
101Divide by 32
110Divide by 64
111Divide by 128
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Field Name
Reserved
Description
Bits
Reset
24
0
Reserved.
SPI_ADR[23:0]
Flash Physical Address.
Valid only when CS = 0.
23:0
0
This is the sector address if the operation is “erase
sector”.
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6.7.4
SPI Data Register
The SPI Data register can be used by the host to read and write data through the 820x
Serial to Parallel interface.
Type:
Offset
Read/Write
x‘08C8’
SPI_DATA[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Serial to Parallel Interface Data.
Bits
Reset
SPI_DATA[31:0]
For SPI write operations, the host should write the
data to this register before writing to the SPI
Command Address register (Section 6.7.3).
31:0
0
When SPI read operations, the 820x will write the
data to this register when the operation is done.
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6.7.5
SPI Status Register
The SPI Status register can be read by the host to determine when a SPI read or write
operation on the serial to parallel interface has completed. This register may also be used
to read the Flash device’s status.
Type:
Offset
Read only
x‘08CC’
Reserved
FLASH_WR_STATUS[7:0]
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
Reserved
31:16
0
Reserved
FLASH_WR_STATUS[
7:0]
Flash Write Status.
This field is only valid for 4 byte flash write
operations.
15:8
7:1
0
0
The 820x will read this field to determine if the flash
write operation has completed.
Reserved
Reserved
SPI_OP_DONE
SPI Operation Done.
This bit is read only from the host. When a SPI
read/write operation is done, the 820x will assert
this signal.
0
1
When the host writes to the SPI Command Address
Register (Section 6.7.3), the 820x will automatically
clear this bit.
0
1
SPI read/write operation not done
SPI read/write operation done
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6.7.6
SPI User Defined Register
The SPI User Defined register can be used by the host to write custom commands to the
device(s) attached to the serial to parallel interface. Please refer to the specifications for
the attached devices for a list of predefined commands.
Type:
Offset
Read only
x‘08D0’
Reserved
SPI_USER_CMD[7:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
Reserved
31:8
0
Reserved
SPI_USER_CMD
[7:0]
SPI User Defined Command.
This field can be used by the host to write any valid
command defined by the device attached to the SPI
interface.
For example, if a Spansion S25FL128P device is
attached to the SPI interface, the user may issue a
deep power down mode command (B9h). The host
would write ‘B9h’ to this field, and then set
SPI_CMD to ‘100’ in the SPI Command Address
Register. The 820x will then write the power down
mode command to the flash device.
7:0
0
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6.7.7
Flash Command Configuration 0 Register
The SPI Flash Command Configuration Register 0 can be used by the host to store the flash
command value that the 820x uses to access the external flash chip.
The host must set the commands in this register before writing to the Command Address
register. After writing a command to this register, the host must verify that the command
has completed by polling the SPI_OP_DONE bit in the SPI Status register until it is set.
Once the command has been written to the flash, the host should write to the Command
Address register to complete the requested action.
The default values for this register are suitable for either Spansion S25FL128P or Silicon
Storage Technology SST25VF032B flash devices. If using any other flash devices, the user
should confirm the operation sequence is compatible with above two devices, and initialize
the Flash Command Configuration Register 0 accordingly.
Type:
Offset
Read/Write
x‘08D4’
RDID[7:0]
RD_STATUS[7:0]
BYTE_PROG[7:0]
WREN[7:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
RDID[7:0]
Read Identification.
A command OpCode of 90H will read the flash
vendor’s ID and device ID.
31:24
0x90
The default value is the manufacturer’s ID for the
SST25VF032B device.
RD_STATUS[7:0]
BYTE_PROG[7:0]
Read Status Command.
23:16
15:8
0x05
0x02
A command OpCode of 05H will read the flash
status register.
Byte/Page Program command.
A command OpCode of 02H will initiate a write data
to the flash device.
After this command is sent to the flash, the SPI
Data and Command Address register should be
written.
WREN[7:0]
Write Enable.
This field should be used to send a write enable
command to a flash device other than the
recommended flash device.
7:0
0x06
If using the recommended flash devices, the 820x
will automatically send this command to the flash
device before a write data or erase command.
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6.7.8
Flash Command Configuration 1 Register
The Flash Command Configuration 1 register can used to erase either the entire flash or a
particular sector of the flash. Please refer to the manufacturer’s documentation for the
unique values to execute these commands.
Type:
Offset
Read/Write
x‘08D8’
Reserved
FLASH_ERASE[7:0]
SECTOR_ERASE[7:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Reserved.
Bits
Reset
Reserved
31:16
0
FLASH_ERASE[7:0]
Flash Erase.
A command OpCode of C7H will erase the entire
flash. The WREN command must be sent to the
flash before this command.
15:8
7:0
0xC7
0x20
SECTOR_ERASE
[7:0]
Sector Erase.
A command OpCode of 20H will erase a 4K byte
sector of the flash. The WREN command must be
sent to the flash before this command.
Please refer to the vendor’s documentation for other
valid values.
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6.8 Temperature Sensor Controller Registers
The temperature sensor controller registers are used to access the internal temperature
sensor registers.
Refer to Section 5.12, “Temperature Sensor Controller" for a definition of the parameters
“m1”, “m2”, and “a”, and how they are used to calculate the 820x die temperature.
6.8.1
TSC Address Register
The TSC Address register is used to set the temperature sensor register address. The host
should set the TSC address before a reading or writing to the 820x temperature sensor.
Type:
Offset
Read/Write
x‘08F0’
Reserved
TSC_ADDR[15:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
31:16
15:0
Reset
Reserved
0
0
Reserved.
TSC_ADDR[15:0]
Temperature Sensor Address
6.8.2
TSC Data Register
The TSC Data register is used to store the data read from the temperature sensor or store
the data to be written to the temperature sensor. Note that the host should set the TSC
address using the TSC Address register before issuing a read or write register command.
Refer to Section 5.12, “Temperature Sensor Controller" for a definition of the parameters
“m1”, “m2”, and “a”, and how they are used to calculate the 820x die temperature.
Type:
Offset
Read/Write
x‘08F4’
TSC_DATA[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
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Field Name
Description
Bits
Reset
TSC_DATA[31:0]
Temperature Sensor Data.
Read/Write TSC data
For a TSC write operations, the host should write
the data to this register before setting the TSC
command register.
X'FFFF_
FFFF
31:0
When a TSC read operation is done (TSC_OP_DONE
= 0), the 820x will write the temperature parameter
“m1” to bits [9:0] and parameter “m2” to bits
[25:16].
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6.8.3
TSC Command Register
The TSC Command register can be used by the host to read or write data from/to the
internal 820x PHY register pointed to by the TSC Address register.
Type:
Offset
Read/Write
x‘08F8’
TSC_OP_DONE is read only
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Reserved
Description
Bits
Reset
31:3
0
Reserved.
TSC_CMD[1:0]
Temperature Sensor Controller Command.
The host software should write to this field to trigger
a temperature sensor register operation.
00 Reserved
01 Register Write
10 Register Read
11 Reserved
For a “Register Write” command, the 820x will write
TSC_Data[15:0] to the temperature sensor register
with address TSC_ADDR. Note, the host must first
write to the TSC_Addr and TSC_Data registers
before issuing this command.
2:1
00
For a “Register Read” command, the 820x will read
from the temperature sensor register with address
TSC_Addr, and write the value to TSC_Data[15:0].
Note, the host must write to TSC_Addr before
issuing the command, and then read TSC_Data after
the TSC_OP_Done bit is set by the 820x.
TSC_OP_DONE
Temperature Sensor Controller Operation Done.
This bit is read only from the host.
0
820x will automatically clear this bit after the
host writes to this register.
0
1
1
820x will assert this bit when a TSC read/write
operation is done
820x – Data Sheet, DS-0157-D
Page200
Hifn Confidential
7 PCIe Configuration Register Definition
This section describes the 820x PCIe configuration registers. The registers are mapped into
4K bytes of PCIe configuration space that can be accessed through the PCIe bus. The offset
values in this section are given in hex.
The host should not read/write to/from reserved registers. If the host writes to a reserved
register, the write will be ignored by the 820x. Likewise, if the host reads a reserved
register, the return value will be all zeros.
Table 7-1 lists the register types definitions used to describe the PCIe configuration
registers in this chapter. Fields marked as 'Read Only' usually indicate the 820x capability
and may not be altered by host; fields marked as 'Read/Write' may be altered by the host
(usually BIOS or OS) for special purposes.
Table 7-1. Register Type Definitions
Register Type
Description
RO
Read only.
Register bits are read-only and cannot be altered by software.
Sticky - Read only.
ROS
Registers are read-only and cannot be altered by software. Registers are
not initialized or modified by hot reset.
RW
Read/Write.
Register bits are read-write and may be either set or cleared by software to
the desired state.
RW1C
RWS
Read-only status, Write-1-to-clear status.
Register bits indicate status when read, a set bit indicating a status event
may be cleared by writing a 1. Writing a 0 to RW1C bits has no effect.
Sticky - Read-Write.
Registers are read-write and may be either set or cleared by software to the
desired state. Bits are not initialized or modified by hot reset.
HWINIT
Hardware Initialized.
Register bits are initialized by firmware or hardware mechanisms such as
pin strapping or serial EEPROM. Bits are read-only after initialization and
can only be reset with a power on reset.
Figure 7-1 illustrates the 820x PCIe Configuration registers.
820x – Data Sheet, DS-0157-D
Page201
Hifn Confidential
Figure 7-1. 820x PCI-Express Configuration Space
820x – Data Sheet, DS-0157-D
Hifn Confidential
Page202
7.1 Type 0 PCIe Compatible Configuration Space
7.1.1
Vendor ID Register
The Vendor ID register identifies Hifn as the manufacturer of the 820x device.
Offset
x‘0000’
VENDOR_ID[15:0]
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
820x
Bits
Type
Value
Vendor_ID[15:0]
This 16-bit register identifies Hifn as the
manufacturer of the 820x. The value
hardwired in this read-only register is
assigned by a central authority (the PCI
SIG) that controls issuance of the
numbers.
15:0
RO
0x13A3
820x – Data Sheet, DS-0157-D
Page203
Hifn Confidential
7.1.2
Device ID Register
The Device ID register identifies the 820x.
Type:
Offset
Read only
x‘0002’
DEVICE_ID[15:0]
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
820x
Bits
Type
Value
Device_ID[15:0]
This 16-bit value is assigned by Hifn
and identifies the 820x. In conjunction
with the Vendor ID and Revision ID
PCIe registers, and the Minor Revision
820x register, the Device ID can be
used to locate a 820x-specific driver
for the 820x.
0x0033 = 8201 device
0x0034 = 8202 device
0x0035 = 8203 device
0x0037 = 8204 device
preset
value will
match the
chip
15:0
RO
version
820x – Data Sheet, DS-0157-D
Page204
Hifn Confidential
7.1.3
Command Register
The Command register is used to enable or disable The I/O space, Memory space, Bus
Master, Parity Error Response, System Errors, and Interrupts.
Offset
x‘0004’
Reserved
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
820x
Bits
Type
Value
Reserved
INT_DIS
15:11
RO
0
Reserved
Interrupt Disable.
Controls whether the 820x can
generate INTx interrupt messages.
0
1
820x enabled to generate INTx
interrupt messages.
820x's disabled to generate INTx
interrupt messages is disabled.
If the 820x had already transmitted an
Assert_INTx emulation interrupt
10
RW
0
messages and this bit is then set, the
820x must transmit a corresponding
Deassert_INTx message for each
previously transmitted assert message
Note that INTx emulation interrupt
messages forwarded by Root and
Switch Ports from devices downstream
of the Root or Switch Port are not
affected by this bit.
Reserved
9
8
7
RO
RW
RO
0
0
0
Reserved
SERR#_EN
System Error Enable.
This active low bit enables or disables
the reporting of errors detected by the
820x to the Root Complex.
0
820x may send detected errors to
the Root Complex
1
820x may not send detected errors
to the Root Complex
Reserved
Reserved
820x – Data Sheet, DS-0157-D
Page205
Hifn Confidential
Field Name
Description
820x
Bits
6
Type
RW
Value
PERR_RESP
Parity Error Response.
This bit is used to enable or disable the
Master Data Parity Error bit in the
Status register.
0
0
0
1
Disable MSTR_DPERR
Enable MSTR_DPERR
Reserved
5:3
RO
Reserved
BUS_MASTER_EN
Bus Master Enable.
0
1
Disables the 820x from issuing
memory or IO requests, and from
generating MSI messages.
2
RW
0
Enables the 820x to issue memory
or IO requests, including MSI
messages.
Requests other than memory or IO
requests are not controlled by this bit.
MEM_EN
Memory Address Space Decoder
Enable.
0
Memory decoder is disabled and
Memory transactions targeting the
820x are not recognized.
1
0
RW
RO
0
0
1
Memory decoder is enabled and
Memory transactions targeting the
820x are accepted.
IO_EN
IO Address Space Decoder Enable.
0
IO decoder is disabled and IO
transactions targeting the 820x are
not recognized.
1
IO decoder is enabled and IO
transactions targeting the 820x are
accepted.
820x – Data Sheet, DS-0157-D
Page206
Hifn Confidential
7.1.4
Status Register
The Status register is used to report errors and interrupts from the 820x to the host. The
read only fields of this register are automatically updated by the 820x to reflect their
internal status.
Offset
x‘0006’
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
820x
Bits
Type
Value
PERR_DET
Parity Error Detected.
Regardless of the state the Parity Error
Enable bit in the 820x's Command
register, this bit is set if the 820x
receives a Poisoned TLP.
15
RO
0
0
0
820x has not received a Poisoned
TLP.
1
820x received a Poisoned TLP.
SIG_SYS_ERR
Signaled System Error.
0
820x has not sent a fatal or non-
fatal message.
14
RO
1
The 820x sent an ERR_FATAL or
ERR_NONFATAL message, and the
SERR Enable bit in the Command
register is set to one.
RCVD_MSTR_ABORT
RCVD_TAR_ABORT
Received Master Abort.
0
820x has not sent a master abort
message.
13
12
RO
RO
0
0
1
820x received a Completion with
Unsupported Request Completion
Status.
Received Target Abort.
0
820x has not sent a received
target abort message.
1
820x received a Completion with
Completer Abort Completion Status.
820x – Data Sheet, DS-0157-D
Page207
Hifn Confidential
Field Name
Description
820x
Bits
11
Type
RO
Value
SIG_TAR_ABORT
Signaled Target Abort.
0
820x has not sent a signal target
abort message.
0
1
The 820x, acting as a Completer,
terminated a request by issuing
Completer Abort Completion Status
to the Requester.
Reserved
10:9
RO
Reserved
MSTR_DPERR
Master Data Parity Error.
The Master Data Parity Error bit is set
by a 820x if the Parity Error Enable bit
is set in the Command register and
either of the following two conditions
occurs:
-the 820x receives a poisoned
Completion.
8
RO
0
-the 820x poisons a write request.
If the Parity Error Enable bit is cleared,
the Master Data Parity Error status bit
is never set.
0
No Master Data Parity Error
occurred.
1
Master Data Parity Error occurred.
Reserved
CAP_LIST
7:5
4
RO
RO
0
1
Reserved
Capabilities List.
Indicates the presence of one or more
extended capability register sets in the
lower 48 dwords of the 820x's PCI-
compatible configuration space.
0
1
Capabilities List not present.
Capabilities List present.
INT_STAT
Interrupt Status.
Indicates that the 820x has an interrupt
request outstanding (that is, the 820x
transmitted an interrupt message that
is waiting to be serviced).
Note that INTx emulation interrupts
forwarded by Root and Switch Ports
from devices downstream of the Root
or Switch Port are not reflected in this
bit.
3
RO
0
Note: this bit is only associated with
INTx messages, and has no meaning if
the device is using Message Signaled
Interrupts.
0
820x has no interrupt request
outstanding.
1
820x has an interrupt request
outstanding.
Reserved
2:0
RO
N/A
Reserved
820x – Data Sheet, DS-0157-D
Page208
Hifn Confidential
7.1.5
Revision ID Register
The Revision ID register identifies the major revision number assigned to each 820x device.
Please refer to Section 6.1.6 for the minor revision number of the 820x device.
Offset
x‘0008’
REVISION_ID[7:0]
7
6
5
4
3
2
1
0
Field Name
Description
820x
Bits
Type
Value
REVISION_ID[7:0]
This 8-bit value is assigned by Hifn to
identify the revision number of the
820x.
7:0
RO
0x00
0 = First major revision of the 820x
7.1.6
Class Code Register
The Class Code register defines the 820x encryption/decryption controller.
Offset
x‘0009’
CLS_CODE[23:0]
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
0x108000 Encryption/Decryption controller.
Bits
Type
Default
CLS_CODE[23:0]
23:0
RO
7.1.7
Cache Line Size Register
Offset
x‘00C’
The Cache Line Size register is implemented as a read-write field for legacy compatibility
purposes but has no impact on the 820x's functionality. The typical read value is 108000h.
820x – Data Sheet, DS-0157-D
Page209
Hifn Confidential
7.1.8
Master Latency Timer Register
Offset
x‘00D’
The Master Latency Timer register is implemented for legacy compatibility purposes but has
no impact on the 820x's functionality. This register is hard-wired to 0x00.
7.1.9
Header Type Register
Offset
x‘00E’
The Header Type register is a read-only optional register whose value is hard-wired to
0x00.
7.1.10
BIST Register
Offset
x‘00F’
The BIST register is used for control and status of the BIST function. This register is hard-
wired to 0x00.
820x – Data Sheet, DS-0157-D
Page210
Hifn Confidential
7.1.11
Base Address Register 0, 1
The Base Address 0 register provides the 820x base address on a 4KB boundary and some
memory configuration parameters. This address in memory space is where the standard
820x register set will reside and be accessed. For 32-bit systems, the base address is set
using only BAR 0. For 64-bit systems, the base address is set using both BAR 0 and BAR 1.
Offset
x‘0010’
BASE_ADR[56:25]
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
BASE_ADR[24:0]
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
820x
Bits
Type
Value
BASE_ADR[56:0]
Base Address.
[63:32] Only used for 64-bit 4KB
memory base address
63:7
RW
0
[31:7] Indicates 32-bit 4KB memory
base address
Reserved
6:4
3
RO
RO
0
0
Reserved
PRE_FTCH
Prefetchable memory.
0
1
Non-Prefetchable memory
Prefetchable memory
DEC_TYP
Decoder Type.
00 32 bit decoder; locate memory
00 for a
32-bit
system;
10 for a
64-bit
anywhere in lower 4GB; use only
BAR0
2:1
RW
RO
01 Reserved
10 64-bit decoder; locate memory
anywhere in 264 memory space;
uses BAR0 and BAR1
system
11 Reserved
MEM_IND
Memory Space Indicator.
x0 Base Address Register0 is a
memory address decoder
0
0
x1 Base Address Register0 is an IO
address decoder
820x – Data Sheet, DS-0157-D
Page211
Hifn Confidential
7.1.12
Base Address Register 2-5
The Base Address Registers 2-5 are not used by the 820x, are read only, and will be read
as all zeroes.
7.1.13
Cardbus CIS Pointer Register
Offset
x‘0028’
This optional read-only register is used by devices that contain a CardBus and PCIe
interface. The 820x does not support Cardbus so this register is hard-wired to 0x00000000.
7.1.14
Sub-System Vendor ID Register
The Sub-System Vendor ID register identifies Hifn as the manufacturer of the 820x device.
This value is hard coded in the 820x device.
Offset
x‘002C’
SUBSYS_VENDOR_ID[15:0]
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
820x
Bits
Type
Value
SUBSYS_VENDOR_
ID[15:0]
This 16-bit register identifies the
manufacturer of the subsystem. The
value hardwired in this read-only
register is assigned by a central
authority (the PCI SIG) that controls
issuance of the numbers.
15:0
RO
0x13A3
820x – Data Sheet, DS-0157-D
Page212
Hifn Confidential
7.1.15
Sub-System ID Register
The Sub-System ID register identifies the 820x. This value is hard coded in the 820x
device.
Offset
x‘002E’
SUBSYS_ID[15:0]
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
820x
Bits
Type
Value
SUBSYS_ID[15:0]
This 16-bit value is assigned by the
subsystem manufacturer and identifies
the type of subsystem.
15:0
RO
0x036
7.1.16
Expansion ROM Base Address Register
The ROM Base address register (ROM BAR) provides the 820x expansion ROM Base address
and address decode enable. This register sets the address space in memory for the
attached Flash device.
Offset
x‘0030’
If the Expansion ROM is enabled, bits
[23:11] are RO to reserve 16M space.
EXP_ROM_BAR[20:0]
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
820x
Bits
Type
Value
EXP_ROM_BAR
[20:0]
Expansion ROM Base Address.
[31:24] The base address of the
expansion ROM
31:11
RW
If the Expansion ROM is enabled, bits
[23:11] are RO to reserve 16M space.
Reserved
10:1
0
RO
0
0
Reserved.
ADR_DEC_EN
Address Decode Enable.
RW
0
1
Disable expansion ROM
Enable expansion ROM
820x – Data Sheet, DS-0157-D
Page213
Hifn Confidential
7.1.17
Capabilities Pointer Register
Offset
x‘0034’
The Capabilities Pointer register is used to point to a linked list of capabilities implemented
by the 820x. This read-only register value is hard-wired to 0x40, the Power Management
Capabilities structure.
7.1.18
Interrupt Line Register
Offset
x‘003C’
The Interrupt Line register communicates interrupt line routing information to device
drivers and operating systems. Values in this register are programmed by system software
and are system architecture specific. The typical read value is 0x0B.
7.1.19
Interrupt Pin Register
Offset
x‘003D’
The Interrupt Pin register identifies the legacy interrupt Message(s) used by the 820x. This
register is a read-only register whose value will be read as 0x01, indicating the 820x uses
INTA.
7.1.20
Min_Gnt Register
Offset
x‘003E’
This legacy register is a read-only register whose value is hard-wired to 0x00.
7.1.21
Max_Lat Register
Offset
x‘003F’
This legacy register is a read-only register whose value is hard-wired to 0x00.
820x – Data Sheet, DS-0157-D
Page214
Hifn Confidential
7.2 Power Management Capabilities Registers
The Power Management registers indicate the 820x power management capabilities.
PMC[15:0]
NXT_CAP_PTR[7:0]
CAP_ID[7:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA_REG[7:0] PMSCR_BSE[7:0]
9
8
7
6
5
5
4
3
2
1
1
0
0
PMCSR[15:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
4
3
2
7.2.1
Capability ID Register
The Capability Identifier register, when read by system software as 01h, indicates that the
data structure currently being pointed to is the PCI Power Management data structure.
Offset
x‘0040’
Field Name
Description
820x
Bits
Type
Value
CAP_ID
Power Management Capability ID.
01h = identifies the linked list item as
being the PCI Power Management
registers
7:0
RO
0x01
7.2.2
Next Capabilities Pointer Register
The Next Capabilities register describes the location of the next item in the 820x’s
capability list. The value given is an offset into the 820x’s PCI Configuration Space.
Offset
x‘0041’
Field Name
Description
820x
Bits
Type
Value
NXT_CAP_PTR
Power Management Next Capabilities
Pointer.
7:0
RO
0x50
50h = PCIe MSI capabilities structure
820x – Data Sheet, DS-0157-D
Page215
Hifn Confidential
7.2.3
Power Management Capabilities Register
The Power Management Capabilities register is a 16-bit read-only register which provides
information on the capabilities of the function related to power management. The
information in this register is generally static and known at design time.
Offset
x‘0042’
Field Name
Description
820x
Bits
Type
Value
PME Support
PME Support.
Indicates the PM states supported by the
820x. A one in a bit indicates the 820x is
capable of sending a Power Management
Event (PME) message. A zero in a bit
indicates PME notification is not
supported in the respective PM state.
15:11
RO
0x0B
Bit
11
12
13
14
15
PM State
D0 (supported by 820x)
D1 (supported by 820x)
D2 (not supported by 820x)
D3hot (supported by 820x)
D3cold (not supported by 820x)
D2 Support
D1 Support
Aux Current
D2 Support.
10
9
RO
RO
0
1
0 = D2 PM state not supported
D1 Support.
1 = D1 PM state supported
Aux Current.
The Aux_Current field reports the
3.3Vaux current requirements for the
820x. The 820x reports 375mA max.
8:6
RO
111
Device-Specific
Initialization
Device-Specific Initialization.
A one in this bit indicates that
immediately after entry into the D0
Uninitialized state, the 820x requires
additional configuration above and
beyond setup of its PCI configuration
Header registers before the Class driver
can use the 820x. Microsoft OSs do not
use this bit. Rather, the determination
and initialization is made by the Class
driver.
5
RO
0
Reserved
4
3
RO
RO
0
0
Reserved.
PME Clock
Version Field
The 820x does not use PME Clock.
Version Field.
This field indicates the version of the PCI
Bus PM Interface spec that the 820x
complies with.
2:0
RO
0x3
820x – Data Sheet, DS-0157-D
Page216
Hifn Confidential
7.2.4
Power Management Control/Status Register
The Power Management Control/Status (PMCSR) register is used to manage the PCI
function’s power management state as well as to enable/monitor Power Management
Events (PMEs).
Offset
x‘0044’
Field Name
Description
820x
Bits
Type
Value
PME_STAT
PME Status.
This bit is set to “0” because the 820x
does not support PME# generation from
D3cold.
15
RW1C
0
0
DAT_SCALE
DAT_SEL
PME_EN
Data Scale.
This field is set to “00b” in the 820x
because the PM Data register is not
implemented.
14:13
12:9
RO
Data Select.
This field is set to “0000b” in the 820x
because the PM Data register is not
implemented.
RW
0000
PME Enable.
This bit is set to “0” because the 9720
does not support PME# generation from
D3cold.
8
RW
RO
0
0
Reserved
7:4
Reserved.
NO_SFT_RST
No Soft Reset.
The 820x sets this bit to 0 to indicate it
will perform an internal reset upon
transitioning from D3hot to D0 via
software control of the PowerState bits.
Configuration Context is lost when
performing the soft reset. Upon transition
from the D3hot to the D0 state, full
reinitialization sequence is needed to
return the device to D0 Initialized.
3
2
RO
RO
0
0
Reserved
Reserved.
820x – Data Sheet, DS-0157-D
Page217
Hifn Confidential
Field Name
Description
820x
Bits
Type
Value
PWR_STATE
Power State.
This 2-bit field is used both to determine
the current power state of the 820x and
to set the 820x into a new power state.
The definition of the field values is given
below.
00b - D0
1:0
RW
00
01b - D1
10b - D2
11b - D3hot (not supported)
If software attempts to write an
unsupported state to this field, the write
operation must complete normally on the
bus; however, the data is discarded and
no state change will occur.
7.2.5
PMCSR-BSE Register
Offset
x‘0046’
The PMCSR PCI-to-PCI Bridge Support Extensions register does not apply to the 820x.
When read, the register will return zeroes.
7.2.6
Data Register
Offset
x‘0047’
The Data register is not used by the 820x but may be written to by system software. When
read, the register will typically return all zeroes.
820x – Data Sheet, DS-0157-D
Page218
Hifn Confidential
7.3 MSI Capability Registers
The MSI Capability registers indicate the 820x Message Signaled Interrupt capabilities. The
820x uses a 64-bit Message Address.
MSG_CTL[15:0]
NXT_PTR[7:0]
CAP_ID[7:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
MSG_ADR[31:0]
9
9
8
8
7
7
6
6
5
4
3
2
1
1
0
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
5
4
3
2
MSG_ADR[63:32]
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
MSG_DATA[15:0]
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
7.3.1
Capability ID Register
The Capability Identifier register, when read by system software as 05h, indicates that the
820x is MSI capable.
Offset
x‘0050’
Field Name
Description
820x
Bits
Type
Value
CAP_ID
MSI Capability.
7:0
RO
0x05
05h = MSI capable
820x – Data Sheet, DS-0157-D
Page219
Hifn Confidential
7.3.2
Next Capabilities Pointer Register
The Next Capabilities register describes the location of the next item in the 820x’s
capability list. The value given is an offset into the 820x’s PCI Configuration Space.
Offset
x‘0051’
Field Name
Description
820x
Bits
Type
Value
NXT_PTR
MSI Next Pointer.
7:0
RO
0x70
70h = PCIe capabilities structure
820x – Data Sheet, DS-0157-D
Page220
Hifn Confidential
7.3.3
Offset
Message Control Register
x‘0053’
Field Name
Description
820x
Bits
Type
Value
Reserved
15:9
RO
0
Reserved.
PER_VEC_MSK
Per-vector masking.
The 820x does not support MSI per-
vector masking.
8
7
RO
RO
0
1
0 = Per-vector masking not supported
64_ADR_CAP
64-bit Address.
The 820x is capable of generating a 64-
bit message address.
1 = 64-bit address capable
MULT_MESS_EN
Multiple Message Enable.
System software writes to this field to
indicate the number of allocated vectors
(equal to or less than the number of
requested vectors).
6:4
3:1
RW
RO
000
000
000 = 1 vector allowed
MULT_MESS_CAP
MSI Enable
Multiple Message Capable.
System software reads this field to
determine the number of requested
vectors.
000 = 1 vector requested
MSI Enable.
System configuration software sets this
bit to enable MSI.
0 = 820x is prohibited from using MSI to
request service
0
RW
0
1 = If the MSI-X Enable bit in the MSI-X
Message Control register is 0, the
820x is permitted to use MSI to
request service.
820x – Data Sheet, DS-0157-D
Page221
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7.3.4
Message Address Register
Offset
x‘0054 - x0058’
Field Name
Description
820x
Bits
Type
Value
MSG_ADR
MSI Message Address.
If the Message Enable bit (bit 0 of the
Message Control register) is set, the
contents of this register specifies the
DWORD aligned address (AD[63:02]) for
the MSI memory write transaction.
AD[1:0] are driven to zero during the
address phase.
63:2
RW
Reserved
Reserved.
1:0
RO
00
Always returns 0 on read. Write
operations have no effect.
7.3.5
Message Data Register
Offset
x‘005C’
Field Name
Description
820x
Value
Bits
Type
MSG_DATA
MSI Message Data.
If the Message Enable bit (bit 0 of the
Message Control register) is set, the
message data is driven onto the lower
word (MSG_ADR[15:0]) of the memory
write transaction’s data phase.
15:0
RW
MSG_ADR[31:16] are driven to zero
during the memory write transaction’s
data phase. C/BE[3:0]# are asserted
during the data phase of the memory
write transaction.
820x – Data Sheet, DS-0157-D
Page222
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7.4 PCI Express Capability Registers
The PCI Express Capability registers are required for PCI Express devices. The capability
structure is a mechanism for enabling PCI software transparent features requiring support
on legacy operating systems. In addition to identifying a PCI Express device, the PCI
Express Capability structure is used to provide access to PCI Express specific Control/Status
registers and related Power Management enhancements.
PCIE_CAP[15:0]
NXT_CAP_PTR[7:0]
CAP_ID[7:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DEV_CAP[31:0]
9
9
8
8
7
7
6
6
5
5
5
5
5
4
4
4
4
4
3
3
3
3
3
2
2
2
2
2
1
1
1
1
1
0
0
0
0
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DEV_STAT[15:0]
DEV_CTL[15:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LINK_CAP[31:0]
9
8
7
6
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LINK_STAT[15:0]
9
8
7
6
LINK_CTL[15:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
7.4.1
Capability ID Register
The Capability Identifier register, when read by system software as 10h, indicates that the
820x is PCIe capable.
Offset
x‘0070’
Field Name
Description
820x
Bits
Type
Value
CAP_ID[7:0]
PCIe Capable.
7:0
RO
0x10
10h = 820x is PCIe capable
820x – Data Sheet, DS-0157-D
Page223
Hifn Confidential
7.4.2
Next Capabilities Pointer Register
The Next Capabilities register describes the location of the next item in the 820x’s
capability list. The value given is an offset into the 820x’s PCI Configuration Space.
Offset
x‘0071’
Field Name
Description
820x
Bits
Type
Value
NXT_PTR[7:0]
Next Capability Pointer.
7:0
RO
0x00
00h = Advanced Error structure
7.4.3
PCIe Capabilities Register
The PCI Express Capabilities (PCIE_CAP) register identifies the PCI Express device type and
its associated capabilities.
Offset
x‘0072’
Field Name
Description
820x
Bits
Type
Value
RSVD
15:14
RO
00
Reserved.
INT_MSG_NUM[4:0]
Interrupt Message Number.
13:9
8
RO
0x0
This field is not used by the 820x.
SLOT_IMPL
Slot Implemented.
HWINIT
0
This bit is not used by the 820x.
DEV_PORT_TYP[3:0]
Device/Port Type.
Indicates the type of PCI Express
logical device.
7:4
3:0
RO
RO
0000
0000 = 820x is PCI Express Endpoint
device
CAP_VER[3:0]
Capability Version.
01
Indicates the PCI Express capability
structure version number.
820x – Data Sheet, DS-0157-D
Page224
Hifn Confidential
7.4.4
Device Capabilities (DEV_CAP) Register
The Device Capabilities register identifies the PCI Express device specific capabilities.
Offset
x‘0074’
Field Name
Description
820x
Bits
Type
Value
Reserved
31:28
RO
0
Reserved
Captured Slot Power
Limit Scale[1:0]
Captured Slot Power Limit Scale.
This field specifies the scale used for
the Slot Power Limit Value, which is set
by the Set_Slot_Power_Limit Message
for the 820x. Most systems will read
0x0, which means 1.0x.
27:26
RO
Captured Slot Power
Limit Value[7:0]
Captured Slot Power Limit Value.
This field is used in combination with
the Slot Power Limit Scale value to
specify the upper limit on the power
supplied by the slot. The power limit (in
Watts) is calculated by multiplying the
value in this field by the value in the
Slot Power Limit Scale field. This value
is set by Set_Slot_Power_Limit
25:18
17:15
14
RO
RO
RO
Message for the 820x. Most systems
will read 0x19, which represents 25W.
Reserved
0x0
Reserved
Power Indicator
Present
Power Indicator Present.
When set to one, indicates a Power
Indicator is implemented on the card or
module. Valid for the following PCI
Express device types:
0
Express Endpoint device
Legacy Express Endpoint device
Switch upstream port
Express-to-PCI/PCI-X bridge
Attention Indicator
Present
Attention Indicator Present.
When set to one, indicates an Attention
Indicator is implemented on the card or
module. Valid for the following PCI
Express device Types:
13
RO
0
Express Endpoint device
Legacy Express Endpoint device
Switch upstream port
Express-to-PCI/PCI-X bridge
820x – Data Sheet, DS-0157-D
Page225
Hifn Confidential
Field Name
Description
820x
Bits
Type
Value
Attention Button
Present
Attention Button Present.
When set to one, indicates an Attention
Button is implemented on the card or
module. Valid for the following PCI
Express device types:
12
RO
0
Express Endpoint device
Legacy Express Endpoint device
Switch upstream port
Express-to-PCI/PCI-X bridge
Endpoint L1s
Acceptable
Latency[2:0]
Endpoint L1s Acceptable Latency.
Acceptable latency that an Endpoint can
withstand due to the transition from L1
state to the L0 state. This value is an
indirect indication of the amount of the
Endpoint's internal buffering. Power
management software uses this value
to compare against the L1 Exit
11:9
RO
0x3
Latencies reported by all components in
the path between this Endpoint and its
parent Root Port to determine whether
ASPM L1 entry can be used with no loss
of performance.
The 820x requires an endpoint L1
acceptable latency of 8ꢀs maximum.
Endpoint L0s
Acceptable
Latency[2:0]
Endpoint L0s Acceptable Latency.
Acceptable total latency that an
Endpoint can withstand due to the
transition from the L0s state to the L0
state. This value is an indirect
indication of the amount of the
Endpoint's internal buffering. Power
management software uses this value
to compare against the L0s exit
latencies reported by all components in
the path between this Endpoint and its
parent Root Port to determine whether
ASPM L0s entry can be used with no
loss of performance.
8:6
RO
0x3
The 820x requires an endpoint L0
acceptable latency of 4ꢀs maximum.
Extended Tag Field
Supported
Extended Tag Field Supported.
Max supported size of the Tag field
when this function acts as a Requester.
0 = 5-bit Tag field supported (max of
32 outstanding request per Requester).
5
RO
0x0
1 = 8-bit Tag field supported (max of
256 outstanding request per
Requester).
If 8-bit Tags are supported and will be
used, this feature is enabled by setting
the Extended Tag Field Enable bit in the
Device Control register to one.
820x – Data Sheet, DS-0157-D
Page226
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Field Name
Description
820x
Bits
Type
Value
Phantom Functions
Supported[1:0]
Phantom Functions Supported.
When the device within which a
function resides does not implement all
eight functions, a non-zero value in this
field indicates that this is so. Assuming
all functions are not implemented and
that the programmer has set the
Phantom Function Enable bit in the
Device Control register, a function may
issue request packets using its own
function number as well as one or more
additional function numbers.
This field indicates the number of msbs
of the function number portion of
Requester ID that are logically
combined with the Tag identifier.
00 = The Phantom Function feature is
not available within this device.
01 = The msb of the function number
in the Requestor ID is used for
Phantom Functions. The device
designer may implement functions 0-3.
When issuing request packets,
Functions 0, 1, 2, and 3 may also use
function numbers 4, 5, 6, and 7,
respectively, in the packet's Requester
ID.
4:3
RO
0x0
10 = The two msbs of the function
number in the Requestor ID are used
for Phantom Functions. The device
designer may implement functions 0
and 1. When issuing request packets,
Function 0 may also use function
numbers 2, 4, and 6 in the packet's
Requester ID. Function 1 may also use
function numbers 3, 5, and 7 in the
packet's Requester ID.
11 =All three bits of the function
number in the Requestor ID are used
for Phantom Functions. The device
designer must only implement Function
0 (and it may use any function number
in the packet's Requester ID).
Max Payload Size
Supported[2:0]
Max Payload Size Supported.
Defines the Max data payload size that
the 820x supports for TLPs.
2:0
RO
0x2
The 820x supports 512 bytes max
payload size.
820x – Data Sheet, DS-0157-D
Page227
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7.4.5
Device Control (DEV_CTL) Register
The Device Control register controls PCI Express device specific parameters. The system
software may read and write the fields of this register to control the operation of the 820x.
Offset
x‘0078’
Field Name
Description
820x
Bits
Type
Value
RSVD
15
RO
00
Reserved.
MAX_RD_REQ_SZ
[2:0]
Maximum Read Request Size.
This field sets the maximum Read
Request size for the Device as a
Requester. The Device must not
generate read requests with size
exceeding the set value.
14:12
RW
010
Supported 820x read request sizes:
000 = 128 bytes
001 = 256 bytes
010 = 512 bytes
EN_NO_SNOOP
Enable No Snoop.
This bit is set to 1 in the 820x,
indicating the 820x is permitted to set
the No Snoop bit in the Requester
Attributes of transactions it initiates
that do not require hardware enforced
cache coherency.
11
RW
1
AUX_PWR_EN
PHANT_EN
Auxiliary (AUX) Power PM Enable.
This bit is set to 0 by the 820x,
disabling the 820x to draw AUX power
independent of PME AUX power.
10
9
RWS
RW
0
0
0
Phantom Functions Enable.
This bit is hardwired to 0 as the 820x
device does not implement this
capability.
EXT_TAG_EN
Extended Tag Field Enable.
This bit is set to 0 in the 820x to
disable the 820x from using an 8-bit
Tag field as a requester.
8
RW
820x – Data Sheet, DS-0157-D
Page228
Hifn Confidential
Field Name
Description
820x
Bits
Type
Value
MAX_PAY_SZ[2:0]
Maximum Payload Size.
This field sets maximum TLP payload
size for the device/function. As a
Receiver, the device must handle TLPs
as large as the set value; as
Transmitter, the device must not
generate TLPs exceeding the set value.
7:5
RW
000
Supported 820x payload sizes:
000 = 128 bytes max payload size
001 = 256 bytes max payload size
010 = 512 bytes max payload size
EN_RLX_ORD
Enable Relaxed Ordering.
This bit is hardwired to 0 as the 820x
device never sets the Relaxed Ordering
attribute in transactions it initiates as a
requester.
4
RW
0
NON_SPT_REQ_REP
_EN
Unsupported Request Reporting Enable.
This bit, in conjunction with other bits,
controls the signaling of Unsupported
Requests by sending Error Messages.
3
2
1
0
RW
RW
RW
RW
0
0
0
0
FTL_ERR_REP_EN
Fatal Error Reporting Enable.
This bit, in conjunction with other bits,
controls sending ERR_FATAL Messages.
NON_FTL_ERR_REP_
EN
Non-Fatal Error Reporting Enable.
This bit, in conjunction with other bits,
controls sending ERR_NONFATAL
Messages.
COR_ERR_REP_EN
Correctable Error Reporting Enable.
This bit, in conjunction with other bits,
controls sending ERR_COR Messages.
820x – Data Sheet, DS-0157-D
Page229
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7.4.6
Device Status Register
The Device Status register provides information about PCI Express device specific
parameters.
Offset
x‘007A’
Field Name
Description
820x
Bits
Type
Value
RSVD
15:6
RO
00
Reserved.
TRNS_PEND
Transactions Pending.
This bit when set indicates that the
820x has issued Non- Posted Requests
which have not been completed. The
820x reports this bit cleared only when
all outstanding Non-Posted Requests
have completed or have been
5
RO
0
terminated by the Completion Timeout
mechanism.
AUX_PWR_DET
AUX Power Detected.
This bit is set to 0 in the 820x,
indicating the 820x does not use AUX
power.
4
3
RO
0
0
UNSUP_REQ_DET
Unsupported Request Detected.
This bit indicates that the 820x received
an Unsupported Request. Errors are
logged in this register regardless of
whether error reporting is enabled or
disabled in the Device Control register.
RW1C
FTL_ERR_DET
Fatal Error Detected.
This bit indicates the status of the fatal
errors detected. Errors are logged in
this register regardless of whether error
reporting is enabled or disabled in the
Device Control register.
2
RW1C
0
Errors are logged in this register
regardless of the settings of the
correctable error mask register in the
Advanced Error Handling registers.
NON_FTL_ERR_DET
Non-Fatal Error Detected.
This bit indicates the status of the non-
fatal errors detected. Errors are logged
in this register regardless of whether
error reporting is enabled or disabled in
the Device Control register.
1
RW1C
0
Errors are logged in this register
regardless of the settings of the
correctable error mask register in the
Advanced Error Handling registers.
820x – Data Sheet, DS-0157-D
Page230
Hifn Confidential
Field Name
Description
820x
Bits
Type
Value
COR_ERR_DET
Correctable Error Detected.
This bit indicates the status of the
correctable errors detected. Errors are
logged in this register regardless of
whether error reporting is enabled or
disabled in the Device Control register.
0
RW1C
0
Errors are logged in this register
regardless of the settings of the
correctable error mask register in the
Advanced Error Handling registers.
820x – Data Sheet, DS-0157-D
Page231
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7.4.7
Link Capabilities Register
The Link Capabilities register identifies PCI Express Link specific capabilities.
Offset
x‘007C’
Field Name
Description
820x
Bits
Type
RO
Value
Port Number[7:0]
Port Number.
31:24
23:18
0
0
The 820x has a single PCIe port; the
port number is zero.
Reserved
RO
Reserved.
L1 Exit Latency[2:0]
L1 Exit Latency.
Indicates the L1 exit latency for the
Link (i.e., the length of time this Port
requires to complete a transition from
L1 to L0).
17:15
RO
0x4
The 820x L1 Exit latency required is
8ꢀs to 16ꢀs.
L0 Exit Latency[2:0]
L0 Exit Latency.
Indicates the L0s exit latency for the
Link (i.e., the length of time this Port
requires to complete a transition from
L0s to L0).
14:12
11:10
RO
RO
0x3
0x3
The 820x L0 Exit latency required is
256ns to less than 512ns.
Active State Link PM
Support[1:0]
Active State Power Management
(ASPM) Support.
Indicates the level of ASPM supported
on this Link.
The 820x supports L0 and L1.
Max Link Width[5:0]
Max Link Speed[3:0]
Max Link Width.
9:4
3:0
RO
RO
0x4
0x1
The 820x max link width is x4.
Max Link Speed.
0001 = 2.5 Gb/s
820x – Data Sheet, DS-0157-D
Page232
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7.4.8
Link Control Register
The Link Control register controls PCI Express Link specific parameters.
Offset
x‘0080’
Field Name
Description
820x
Bits
Type
Value
Reserved
15:9
RO
0
0
Reserved.
EN_CLK_PWR_MAN
Enable Clock Power Management.
This bit is hardwired to 0 as the 820x
device does not support Clock Power
Management.
8
7
RW
RW
EXT_SYNC
CLK_CFG
Extended Synch.
This bit when set forces the
transmission of additional ordered sets
when exiting the L0s state and when in
the Recovery state.
0
1
This bit is not used by the 820x.
Common Clock Configuration.
This bit when set indicates that the
820x and the component at the
opposite end of this Link are operating
with a distributed common reference
clock.
6
RW
RTN_LINK
LINK_DIS
RCB
Retrain Link.
5
4
RW
RW
0
0
This field is not applicable and is
reserved for the 820x device.
Link Disable.
This field is not applicable and is
reserved for the 820x device.
Read Completion Boundary.
3
2
RW
RO
0
0
This bit is hardwired to 0 as the 820x
device does not support RCB.
Reserved
Reserved.
ASPM_CTL[1:0]
Active State Power Management
(ASPM) Control.
This field controls the level of ASPM
supported on the given PCI Express
Link.
1:0
RW
00
820x supported values are:
00 = Disabled
820x – Data Sheet, DS-0157-D
Page233
Hifn Confidential
7.4.9
Link Status Register
The Link Status register provides information about PCI Express Link specific parameters.
Offset
x‘0082’
Field Name
Description
820x
Bits
Type
Value
Reserved
15:14
RO
0
Reserved.
DAT_LINK_ACT
Data Link Layer Link Active.
This bit indicates the status of the Data
Link Control and Management State
Machine. It returns a 1b to indicate the
DL_Active state, 0b otherwise.
13
RO
0
This bit must be implemented if the
corresponding Data Link Layer Active
Capability bit is implemented.
Otherwise, this bit must be hardwired
to 0b.
SLT_CLK_CFG
Slot Clock Configuration.
This bit indicates that the 820x uses
the same physical reference clock that
the platform provides on the connector.
12
HWINIT
1
LINK_TRN
UNDEF
Link Training.
11
10
RO
RO
0
0
This field is not applicable to the 820x
device and is hardwared to zero.
Undefined.
This legacy bit is no longer used.
NEG_LINK_WDTH
[5:0]
Negotiated Link Width.
This field indicates the negotiated width
of the given PCI Express Link.
Defined encodings are:
000001 = x1
000010 = x2
000100 = x4 (typical value)
001000 = x8
9:4
RO
001100 = x12
010000 = x16
100000 = x32
All other encodings are reserved. The
value in this field is undefined when the
Link is not up.
LINK_SP[3:0]
Link Speed.
This field indicates the negotiated Link
speed of the given PCI Express Link.
3:0
RO
0001
Defined encodings are:
0001b 2.5 Gb/s PCI Express Link
820x – Data Sheet, DS-0157-D
Page234
Hifn Confidential
7.5 Advanced Error Reporting Capability Registers
The Advanced Error Reporting Capability registers is an optional extended capability that
may be implemented by PCI Express devices supporting advanced error control and
reporting.
ENH_CAP_ HEAD[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
UNC_ERR_STAT[31:0]
9
9
9
9
9
9
9
8
8
8
8
8
8
8
7
7
7
7
7
7
7
6
6
6
6
6
6
6
5
5
5
5
5
5
5
4
4
4
4
4
4
4
3
3
3
3
3
3
3
2
2
2
2
2
2
2
1
1
1
1
1
1
1
0
0
0
0
0
0
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
UNC_ERR_MASK[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
UNC_ERR_SEV[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
COR_ERR_STAT[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
COR_ERR_MASK[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ERR_CAP_CTL[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
HEAD_LOG[127:96]
127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100
HEAD_LOG[95:64]
99 98 97 96
95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
HEAD_LOG[63:32]
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
820x – Data Sheet, DS-0157-D
Page235
Hifn Confidential
HEAD_LOG[31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
820x – Data Sheet, DS-0157-D
Page236
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7.5.1
Enhanced Capability Header Register
Offset
x‘0100’
Field Name
Description
820x
Bits
Type
Value
NXT_CAP_OFF[10:0]
Next Capability Offset.
This field contains the offset to the next
PCI Express capability structure or 000h
if no other items exist in the linked list of
capabilities.
31:20
RO
000h
000h = Terminating list of capabilities
CAP_VER[3:0]
Capability Version.
19:16
15:0
RO
RO
1h
This field is the version number of the
capability structure present.
EXT_CAP_ID[15:0]
PCI Express Extended Capability ID.
The Extended Capability ID for the
Advanced Error Reporting Capability is
0001h.
0001h
820x – Data Sheet, DS-0157-D
Page237
Hifn Confidential
7.5.2
Uncorrectable Error Status Register
The Uncorrectable Error Status register indicates error detection status of individual errors
on a 820x device. An individual error status bit that is set indicates that a particular error
was detected; software may clear an error status by writing a one to the respective bit.
Offset
x‘0104’
Field Name
Description
820x
Bits
31:21
20
Type
RO
Value
Reserved
0
0
0
0
0
0
0
0
Reserved.
REQ_ERR_STAT
ECRC_ERR_STAT
TLP_STAT
RW1CS
RW1CS
RW1CS
RW1CS
RW1CS
RW1CS
RW1CS
Unsupported Request Error Status.
ECRC Error Status (Optional).
Malformed TLP Status.
19
18
RV_OVF_STAT
CMPL_STAT
17
Receiver Overflow Status (Optional).
Unexpected Completion Status.
Completer Abort Status (Optional).
Completion Timeout Status.
16
CMPL_ABORT_STAT
CMPL_TMOUT_STAT
FC_ERR_STAT
15
14
Flow Control Protocol Error Status
(Optional).
13
RW1CS
0
POIS_TLP_STAT
Reserved
12
11:6
5
RW1CS
RO
0
0
0
0
0
0
Poisoned TLP Status.
Reserved.
DWN_ERR_STAT
DLNK_PROT_STAT
Reserved
RW1CS
RW1CS
RO
Surprise Down Error Status (Optional).
Data Link Protocol Error Status.
Reserved.
4
3:1
0
UNDEF
RO
Undefined.
820x – Data Sheet, DS-0157-D
Page238
Hifn Confidential
7.5.3
Uncorrectable Error Mask Register
The Uncorrectable Error Mask register controls reporting of individual errors by the device
to the PCI Express Root Complex via a PCI Express error Message. A masked error
(respective bit set to 1b in the mask register) is not logged in the Header Log register, does
not update the First Error Pointer, and is not reported to the PCI Express Root Complex by
an individual device.
Offset
x‘0108’
Field Name
Description
820x
Bits
31:21
20
Type
RO
Value
Reserved
0
0
0
1
1
0
0
0
Reserved.
REQ_ERR_MSK
ECRC_ERR_MSK
TLP_MSK
RWS
RWS
RWS
RWS
RWS
RWS
RWS
Unsupported Request Error Mask.
ECRC Error Mask (Optional).
Malformed TLP Mask.
19
18
RV_OVF_MSK
CMPL_MSK
17
Receiver Overflow Mask (Optional).
Unexpected Completion Mask.
Completer Abort Mask (Optional).
Completion Timeout Mask.
16
CMPL_ABORTMSK
CMPL_TMOUT_MSK
FC_ERR_MSK
15
14
Flow Control Protocol Error Mask
(Optional).
13
RWS
1
POIS_TLP_MSK
Reserved
12
11:6
5
RWS
RO
0
0
1
0
0
0
Poisoned TLP Mask.
Reserved.
DWN_ERR_MSK
DLNK_PROT_MSK
Reserved
RWS
RWS
RO
Surprise Down Error Mask (Optional).
Data Link Protocol Error Mask.
Reserved.
4
3:1
0
UNDEF
RO
Undefined.
820x – Data Sheet, DS-0157-D
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7.5.4
Uncorrectable Error Severity Register
The Uncorrectable Error Severity register controls whether an individual error is reported as
a Nonfatal or Fatal error. An error is reported as fatal when the corresponding error bit in
the severity register is set. If the bit is cleared, the corresponding error is considered non-
fatal.
Offset
x‘010C’
Field Name
Description
820x
Bits
31:21
20
Type
RO
Value
Reserved
0
0
0
1
1
0
0
0
Reserved.
REQ_ERR_SEV
ECRC_ERR_SEV
TLP_SEV
RWS
RWS
RWS
RWS
RWS
RWS
RWS
Unsupported Request Error Severity.
ECRC Error Severity (Optional).
Malformed TLP Severity.
19
18
RV_OVF_SEV
CMPL_SEV
17
Receiver Overflow Severity (Optional).
Unexpected Completion Severity.
Completer Abort Severity (Optional).
Completion Timeout Severity.
16
CMPL_ABORT_SEV
CMPL_TMOUT_SEV
FC_ERR_SEV
15
14
Flow Control Protocol Error Severity
(Optional).
13
RWS
1
POIS_TLP_SEV
Reserved
12
11:6
5
RWS
RO
0
0
1
1
0
0
Poisoned TLP Severity.
Reserved.
DWN_ERR_SEV
DLNK_PROT_SEV
Reserved
RWS
RWS
RO
Surprise Down Error Severity (Optional).
Data Link Protocol Error Severity.
Reserved.
4
3:1
0
UNDEF
RO
Undefined.
820x – Data Sheet, DS-0157-D
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7.5.5
Correctable Error Status Register
The Correctable Error Status register reports error status of individual correctable error
sources on a 820x device. When an individual error status bit is set, it indicates that a
particular error occurred; software may clear an error status by writing a 1 to the
respective bit.
Offset
x‘0110’
Field Name
Description
820x
Bits
31:14
13
Type
RO
Value
Reserved
0
0
0
0
0
0
0
0
0
Reserved.
ADV_ERR_STAT
REPLY_TMOUT_STAT
Reserved
RW1CS
RW1CS
RO
Advisory Non-Fatal Error Status.
Replay Timer Timeout Status.
Reserved.
12
11:9
8
REPLAY_NUM_STAT
BAD_DLLP_STAT
BAD_TLP_STAT
Reserved
RW1CS
RW1CS
RW1CS
RO
REPLAY_NUM Rollover Status.
Bad DLLP Status.
7
6
Bad TLP Status.
5:1
0
Reserved.
RX_ERR_STAT
RW1CS
Receiver Error Status.
820x – Data Sheet, DS-0157-D
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7.5.6
Correctable Error Mask Register
The Correctable Error Mask register controls reporting of individual correctable errors by the
820x to the PCI Express Root Complex via a PCI Express error Message. A masked error
(respective bit set in mask register) is not reported to the PCI Express Root Complex by an
individual device.
Offset
x‘0114’
Field Name
Description
820x
Bits
31:14
13
Type
RO
Value
Reserved
0
1
0
0
0
0
0
0
0
Reserved.
ADV_ERR_MSK
REPLY_TMOUT_MSK
Reserved
RWS
RWS
RO
Advisory Non-Fatal Error Mask.
Replay Timer Timeout Mask.
Reserved.
12
11:9
8
REPLAY_NUM_MSK
BAD_DLLP_MSK
BAD_TLP_MSK
Reserved
RWS
RWS
RWS
RO
REPLAY_NUM Rollover Mask.
Bad DLLP Mask.
7
6
Bad TLP Mask.
5:1
0
Reserved.
RX_ERR_MSK
RWS
Receiver Error Mask.
820x – Data Sheet, DS-0157-D
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7.5.7
Offset
Advanced Error Capabilities and Control Register
x‘0118’
Field Name
Description
820x
Bits
Type
Value
Reserved
31:9
RO
0
Reserved.
ECRC_CHK_CAP
ECRC Check Enable.
8
7
RWS
RO
0
This bit when set enables ECRC checking.
ECRC_CHK_CAP
ECRC_EN
ECRC Check Capable.
1
0
1
This bit indicates that the 820x is capable
of checking ECRC.
ECRC Generation Enable.
6
5
RWS
RO
This bit when set enables ECRC
generation.
ECRC_CAP
ECRC Generation Capable.
This bit indicates that the 820x is capable
of generating ECRC
FRST_ERR_PTR[4:0]
First Error Pointer.
The First Error Pointer is a read-only
register that identifies the bit position of
the first error reported in the
4:0
ROS
0
Uncorrectable Error Status register.
820x – Data Sheet, DS-0157-D
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8 Signal Description
8.1 PCI Express Interface
The 820x provides a PCIe x4 interface for communicating with the host.
Table 8-1. PCIe Interface Signal Definition
Signal Name
I/O Type Signal Type
Description
PCIE_TXP[3:0]
Output
Output
Input
LVDS
LVDS
LVDS
LVDS
Differential positive transmit outputs for
lanes 0/1/2/3
PCIE_TXN[3:0]
PCIE_RXP[3:0]
PCIE_RXN[3:0]
Differential negative transmit outputs for
lanes 0/1/2/3
Differential positive receive inputs for lanes
0/1/2/3
Input
Differential negative receive inputs for lanes
0/1/2/3
PCIE_REFCLK_P
PCIE_REFCLK_N
PCIE_REFRES
Input
Input
Input
LVDS
LVDS
Analog
Differential positive reference clock
Differential negative reference clock
PCIE reference resistor to calibrate the RX
and TX termination.
To calibrate the Rx and Tx termination
resistors to 50Ω, connect a 191Ω 1%
precision external resistor, ResRef, to the
ResRef pin. The resistor should be 1%
tolerant and can be in any form factor. The
board trace connecting the ResRef pin to the
external resistor constitutes parasitic
resistance and should be minimized. Power
dissipation in the component is < 20 mW
peak during a calibration that lasts < 20 ꢀs.
At all other times, power dissipation is zero.
Do not connect a capacitor to the ResRef
pin.
PCIE_RXEQCTL[2:0]
PCIE_LOS_LVL[4:0]
Input
Input
LVCMOS25_33
LVCMOS25_33
Receiver equalization control
Loss of signal detection control for PCIE PHY
820x – Data Sheet, DS-0157-D
Page244
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Table 8-1. PCIe Interface Signal Definition
Signal Name
I/O Type Signal Type
Description
PCIE_TX_BOOST
[3:0]
Input
LVCMOS25_33
Transmit boost control for PCIE PHY.
The transmitter can be programmed to
provide a pre-emphasis or de-emphasis
boost. The boost is achieved by reducing the
drive level of a non-transitioning bit with
respect to a transitioning bit. These pins can
be transitioned asynchronously.
The amount of boost the transmitter
supplies is programmable up to 5.75 dB in
increments of ~0.37 dB.
Boost = -20log(1 - (PCIE_TX_BOOST[3:0] +
0.5)/32) dB
To produce 3.5 dB of boost as specified in
the PCIe base specification, set
tx_boost[3:0] to 4'b1011. This is one step
higher than the calculated value because the
calculated value is at the IP pads and does
not take into account any package loss.
A value of 4'b0000 produces 0 db of boost.
Transmit level control for PCIE PHY.
PCIE_TX_LVL[4:0]
Input
Input
LVCMOS25_33
LVCMOS25_33
Fine resolution setting of transmit signal
level, common to all lanes connected to a
single clock module. Setting the maximum
Tx amplitude to greater than 1 V peak-to-
peak differential results in overdrive
(applying 1.2 V) to the thin-gate output
transistors.
PERST_N
PCIe reset.
Assertion of this active low signal will reset
the whole chip except the PCIE core sticky
registers. This pad should be connected to
PCIe slot reset.
0: Reset full chip except PCIe Core sticky
registers
1: No PCIe reset
PCIE_PHY_CFG
Input
LVCMOS25_33
PCIe PHY default configuration
0: PCIE PHY configuration is determined by
values from PCIE_RXEQCTL[2:0],
PCIE_REFCLK_CFG, PCIE_LOS_LVL[4:0],
PCIE_TX_BOOST[3:0] and
PCIE_TX_LVL[4:0] input signals.
1: PCIE PHY configuration is determined by
a set of pre-defined values either hard-
wired inside the device or configured
from the optional external flash device.
820x – Data Sheet, DS-0157-D
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8.2 Miscellaneous Interface
Table 8-2. Miscellaneous Interface Signal Definition
Signal Name
I/O Type Signal Type
Description
POR_N
Input
LVCMOS25_33
Power on reset.
Active low power on reset. When asserted,
this bit will reset the entire device including
the PCIE core sticky registers.
0: Reset entire chip
1: No reset
PCIE_LINKUP
PLL_LOCK
Output
Output
LVCMOS25_33
LVCMOS25_33
PCIe Link Status
This pad may be connected to a LED.
0: PCIe link down
1: PCIe link up
PLL Lock Status.
Device internal PLL clock output frequency
lock status.
0: One or both of the internal clock
generation PLLs and/or the PCIe PHY PLL
failed to successfully lock.
1: Both of the internal clock generation PLLs
and the PCIe PHY PLL successfully locked.
BOARD_VERSION
[2:0]
Input
LVCMOS25_33
Board Version
Users may drive this signal to annotate the
version of the board containing the 820x
device.
PLL0_REF_CLK
PLL1_REF_CLK
VRET_PLL0
Input
Input
Input
LVCMOS25_33
LVCMOS25_33
Analog
66.6667 MHz PLL0 reference clock
66.6667 MHz PLL1 reference clock
VRET for PLL0
An external bypass capacitor should be
connected between VDDA_PLL0 and this
signal. See Figure 8-1 for an example of an
external PLL connection circuit.
VRET_PLL1
Input
Input
Analog
VRET for PLL1
An external bypass capacitor should be
connected between VDDA_PLL0 and this
signal. See Figure 8-1 for an example of an
external PLL connection circuit.
EXT_FLASH_EN
LVCMOS25_33
External Flash Enable.
0: External Flash interface disabled
1: External Flash interface enabled and Flash
device attached
Figure 8-1 provides an example circuit for the PLL.
820x – Data Sheet, DS-0157-D
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Figure 8-1. Example PLL Circuit
8.3 GPIO/Probe Interface
Table 8-3. Miscellaneous Interface Signal Definition
Signal Name
I/O Type
Signal Type
Description
GPIO[15:0]
Input/Output
LVCMOS25_33
General purpose IOs
8.4 Flash Interface
Table 8-4. SPI Interface Signal Definition
Signal Name
I/O Type
Signal Type
Description
FLASH_SO
Output
LVCMOS25_33
Serial output.
Output data from the 820x to the Flash
device.
FLASH_SI
Input
LVCMOS25_33
Serial input.
Flash input data driven from the output of
the Flash device.
FLASH_SCK
FLASH_CS
Output
Output
LVCMOS25_33
LVCMOS25_33
Clock output to the Flash device.
Chip select output signal from the 820x to
the Flash device.
820x – Data Sheet, DS-0157-D
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8.5 JTAG Interface
Table 8-5. JTAG Interface Signal Definition
Signal Name
JTAG_TCK
I/O Type
Input
Signal Type
Description
LVCMOS25_33
LVCMOS25_33
LVCMOS25_33
LVCMOS25_33
LVCMOS25_33
JTAG test clock
JTAG_TDI
Input
JTAG test data in, internally pulled up
JTAG test data out
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
Output
Input
JTAG test mode select, internally pulled up
Input
JTAG reset, internally pulled up
Connect to an external pull-down resistor for
normal operation.
There is an errata for this pin that causes other
circuitry in the chip to be reset by this input.
(see Chapter 14, “Errata).
8.6 Power and Ground Interface
Table 8-6. Power and Ground Interface Description
Pin Name
VDD10
Description
Voltage Level
1.0V
Core digital power supply
VDD25_33
This power domain can be connected with 2.5V
or 3.3V. If 2.5V power domain is used, all IO
signals in that domain will not be 3.3V tolerant
2.5V or 3.3V
VDD10A
VDD25A
VDDA_PLL0
VDDA_PLL1
VSS
Analog power supply for PCIE PHY
Analog power supply for PCIE PHY
Analog power supply for on chip PLL0
Analog power supply for on chip PLL1
Digital ground
1.0V
2.5V
2.5V
2.5V
GND
820x – Data Sheet, DS-0157-D
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9 Error Handling
9.1 Error Detection Methods
There are three methods the host software can use to detect if errors have occurred in the
820x:
1. Read the “ERR” bit of the Desc_result descriptor in the command structure. This
bit will be set if any error has occurred.
2. Read the result status in the result ring.
3. Poll the 820x error status register.
If the host is only interested in whether an error has occurred, the best method would be
to read the “ERR” bit. If the host is interested in detailed error information for the current
command, the best method would be to read the result status in the result ring. If the host
is interested in the type of error that occurred without regard to the command that created
the error, the best method would be to read the 820x error status and Channel Manager
error status registers, where any errors are recorded until it is cleared by host.
9.2 Error Categories
There are two error categories for the 820x:
Category 1 errors: Channel Manager Detected Error
All errors in this category will not block the 820x’s operation even if the errors occur
while processing a command. These errors will corrupt the command result. Refer to
“Channel Manager 0-1 Error Status” register for details.
Category 2 errors: PCIe Core Reported Error
Error in this category would include completion timeout, completion abort, parity error
and ECRC error. All errors in this category will block the 820x's operation because the
820x cannot access the completion data.
9.3 Error Handling Mechanism
The 820x error handing mechanism adapts well to network and storage applications with
minimum system overhead.
Self recovery from Category 1 errors:
The 820x will recover from these errors because these errors will not block the 820x’s
operation. The 820x will continue processing commands and set the error status bits
in the command structure and result ring for the command that errored. The host soft-
ware can then reschedule the failed command according to the result information.
820x – Data Sheet, DS-0157-D
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Host reset 820x for Category 2 errors:
The 820x cannot recover from these errors because the errors will not allow the com-
mand to complete.
1. If this category of error is detected by the 820x, the 820x will terminate all
commands in both 820x's channels, and then wait for the host's soft reset.
2. The host software may use one of the three methods described above to detect
the 820x error. Once the error has been detected, the host should poll the
CM_BUSY bit of the Status register before resetting the 820x.
3. When the CM_BUSY bit is cleared to zero by the 820x, the host software writes to
the Soft Reset register to reset the entire 820x chip except the PCIe core.
4. THe host software then reschedules all terminated commands.
The 820x command pointer ring read pointer and result ring write pointer will be writ-
able during the error handling phase to facilitate the software error recovery flow.
820x – Data Sheet, DS-0157-D
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10 DC Specifications
10.1 Absolute Maximum Ratings
Table 10-1. Absolute maximum ratings
Symbol
Description
Min
Max
Units
VDD_25_33
This power domain may be connected to
either a 2.5V or 3.3V supply. If a 2.5V
power domain is used, all IO signals in
that domain are not 3.3V tolerant.
VSS-0.5
4.0
V
VDD_10
DC supply 1.0V Core Voltage
VSS-0.2
VSS-0.4
VSS-0.2
1.2
3.0
1.2
V
V
V
VDD_25A
VDD_10A
VDDA_PLL0
2.5V analog power supply for PCIE PHY
1.0V analog power supply for PCIE PHY
2.5V analog power supply for on chip
PLL0
VSS-0.4
3.0
V
VDDA_PLL1
TSTG
2.5V analog power supply for on chip
PLL1
VSS-0.4
-40
3.0
V
Storage Temperature
130
°C
Caution
!
Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
10.2 Recommended Operating Conditions
Table 10-2. Recommended operating conditions
Symbol
Tj
Description
Min
Max
Units
Junction Temperature, 0 CFS airflow
-40
125
°C
Notes:
1. For normal device operation, adhere to the limits in this table. Sustained operations of a
device at conditions exceeding these values, even if they are within the absolute maximum
rating limits, may result in permanent device damage or impaired device reliability. Device
functionality to stated DC and AC limits is not guaranteed if conditions exceed recommended
operating conditions.
2. Recommended operation conditions require accuracy of the power supplies as described in
Section 10.3.
820x – Data Sheet, DS-0157-D
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10.3 Power Supplies
The following subsections provide details concerning the digital and analog power supply
connections on the 820x device. Generally speaking, analog supplies can be derived from
the same power source as the digital supplies, but are more noise-sensitive and require
additional filtering and careful layout/routing.
10.3.1
Digital Power Supplies
Table 10-3. VDD_25_33 Power Supply Requirements
Parameter
Description
Min
Max
Units
Operating range
Voltage range for nominal
2.25
2.75
3.63
V
V
operating conditions for 2.5V
Voltage range for nominal
operating conditions for 3.3V
2.97
0.1
Rise time
Overshoot
Ripple
Time from 10% to 90% mark
Maximum overshoot allowed
Maximum voltage ripple
10
80
60
ms
mV
mV
Table 10-4. VDD_10 Power Supply Requirements
Parameter
Description
Min
Max
Units
Operating range
Voltage range for nominal
operating conditions
0.95
0.1
1.05
V
Rise time
Overshoot
Ripple
Time from 10% to 90% mark
Maximum overshoot allowed
Maximum voltage ripple
10
50
30
ms
mV
mV
10.3.2
Analog Power Supplies
Table 10-5. VDD_25A Power Supply Requirements
Parameter
Description
Min
Max
Units
Operating range
Voltage range for nominal
operating conditions
2.38
0.1
2.63
V
Rise time
Overshoot
Ripple
Time from 10% to 90% mark
Maximum overshoot allowed
Maximum voltage ripple
10
80
60
ms
mV
mV
820x – Data Sheet, DS-0157-D
Page252
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Table 10-6. VDD_10A Power Supply Requirements
Parameter
Description
Min
Max
Units
Operating range
Voltage range for nominal
operating conditions
0.95
0.1
1.05
V
Rise time
Overshoot
Ripple
Time from 10% to 90% mark
Maximum overshoot allowed
Maximum voltage ripple
10
50
30
ms
mV
mV
Table 10-7. VDDA_PLL0, VDDA_PLL1 Power Supply Requirements
Parameter
Description
Min
Max
Units
Operating range
Voltage range for nominal
operating conditions
2.38
0.1
2.63
V
Rise time
Overshoot
Ripple
Time from 10% to 90% mark
Maximum overshoot allowed
Maximum voltage ripple
10
80
60
ms
mV
mV
10.4 Power Sequencing
The 820X power supplies do not have any sequencing requirements. However, all 1.0 V
supplies should be powered on simultaneously.
10.5 Power Consumption
Note: All power data for VDD_10 in this section has been obtained with PTPX estimation
and will be updated after post silicon test.
Table 10-8. 8204 Current and Power Per Power Domain
2
Power Supply
Nominal
Voltage(V)
TYP Current
(mA)
Max Current
(mA)
TYP Power
(mW)
Max Power
(mW)
VDD_25_331
2.5
3.3
1.0
2.5
1.0
2.5
2.5
40
43
100
113
40
1,700
70
60
8
43
3,320
70
80
8
132
1,700
175
60
149
3,486
184
84
VDD_10
VDD_25A
VDD_10A
VDDA_PLL0
VDDA_PLL1
20
21
8
8
20
21
820x – Data Sheet, DS-0157-D
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Table 10-8. 8204 Current and Power Per Power Domain
2
Power Supply
Nominal
Voltage(V)
TYP Current
(mA)
Max Current
(mA)
TYP Power
(mW)
Max Power
(mW)
Total using
2.5v nominal of
VDD_25_33
1,886
3,529
2,075
3,909
Total using
3.3v nominal of
VDD_25_33
1,886
3,529
2,107
3,945
Note:
1. VDD_25_33 current listed does not include any current delivered to external loads driven by
the 820x.
2. Max power is calculated as 105% of nominal, at 125°C junction temperature.
Table 10-9. 8203 Current and Power Per Power Domain
2
Power Supply
Nominal
Voltage(V)
TYP Current
(mA)
Max Current
(mA)
TYP Power
(mW)
Max Power
(mW)
VDD_25_331
2.5
3.3
1.0
2.5
1.0
2.5
2.5
30
43
75
113
149
30
43
99
VDD_10
1,160
70
2,530
70
1,160
175
60
2,657
184
84
VDD_25A
VDD_10A
VDDA_PLL0
VDDA_PLL1
60
80
8
8
20
21
8
8
20
21
Total using
2.5v nominal of
VDD_25_33
1,336
2,739
1,510
3,079
Total using
3.3v nominal of
VDD_25_33
1,336
2,739
1,534
3,115
Note:
1. VDD_25_33 current listed does not include any current delivered to external loads driven by
the 820x.
2. Max power is calculated as 105% of nominal, at 125°C junction temperature.
Table 10-10. 8202 Current and Power Per Power Domain
2
Power Supply
Nominal
Voltage(V)
TYP Current
(mA)
Max Current
(mA)
TYP Power
(mW)
Max Power
(mW)
VDD_25_331
2.5
3.3
1.0
2.5
1.0
2.5
2.5
30
43
75
113
30
765
70
60
8
43
2,170
70
80
8
99
149
2,279
184
84
VDD_10
765
175
60
VDD_25A
VDD_10A
VDDA_PLL0
VDDA_PLL1
20
21
8
8
20
21
820x – Data Sheet, DS-0157-D
Page254
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Table 10-10. 8202 Current and Power Per Power Domain
2
Power Supply
Nominal
Voltage(V)
TYP Current
(mA)
Max Current
(mA)
TYP Power
(mW)
Max Power
(mW)
Total using
2.5v nominal of
VDD_25_33
941
2,379
1.115
2,701
Total using
3.3v nominal of
VDD_25_33
941
2,379
1.139
2,737
Note:
1. VDD_25_33 current listed does not include any current delivered to external loads driven by
the 820x.
2. Max power is calculated as 105% of nominal, at 125°C junction temperature.
Table 10-11. 8201 Current and Power Per Power Domain
2
Power Supply
Nominal
Voltage(V)
TYP Current
(mA)
Max Current
(mA)
TYP Power
(mW)
Max Power
(mW)
VDD_25_331
2.5
3.3
1.0
2.5
1.0
2.5
2.5
30
43
75
113
30
580
70
60
8
43
99
149
2,069
184
84
VDD_10
1,970
70
580
175
60
VDD_25A
VDD_10A
VDDA_PLL0
VDDA_PLL1
80
8
20
21
8
8
20
21
Total using
2.5v nominal of
VDD_25_33
756
2,179
930
2,491
Total using
3.3v nominal of
VDD_25_33
756
2,179
954
2,527
Note:
1. VDD_25_33 current listed does not include any current delivered to external loads driven by
the 820x.
2. Max power is calculated as 105% of nominal, at 125°C junction temperature.
10.6 I/O Characteristics
Table 10-12. Normal IO Characteristics
Symbol
Description
Min
TYP
Max
Units
NOR_VIHT
DC Input High
Threshold
0.7 *
VDD_25_33
V
NOR_VILT
DC Input Low
Threshold
0.3 *
VDD_25_33
V
820x – Data Sheet, DS-0157-D
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Hifn Confidential
Table 10-12. Normal IO Characteristics
Symbol
Description
Min
TYP
Max
Units
VDD_25_33
I/O supply voltage at
2.5V
2.25
2.5
2.75
V
I/O supply voltage at
3.3V
2.97
1K
3.3
3.63
10K
V
Rpull
External resistor
value for pull down
or pull up pins
ꢁ
Table 10-13. PCIe PHY Transmitter Characteristics
Symbol
VCTM
ZD
Description
Min
TYP
Max
600
115
Units
mV
ꢁ
Transmit common mode voltage
Differential output impedance
400
85
Table 10-14. PCIe PHY Receiver Characteristics
Symbol
Description
Min
TYP
Max
Units
VMIN_RX_EYE_HEIGHT
Minimum Rx eye height (differential
peak-to-peak)
175
mV
ZIN
Differential input impedance
Tolerance
85
115
350
ꢁ
PPM
-350
ppm
820x – Data Sheet, DS-0157-D
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11 AC Specifications
11.1 Reset Timing
The 820x has three reset pins, two of which contain an internal Schmitt circuit.
PERST_N
POR_N
This reset pin with hysteresis should be connected to PCIe reset.
This is an asynchronous power on reset with hysteresis.
JTAG_TRST_N This is an asynchronous reset for JTAG and other logic.
There is an errata for the JTAG_TRST_N pin that requires a low to high transition on this
signal during power on reset. To reset the entire chip, POR_N, PERST_N and JTAG_TRST_N
must all be reset.
11.2 PLL Clock Input
Table 11-1. PLL0 and PLL1 Reference Clock Requirements
Symbol
FRefClk
Description
Min
10
Typ
Max
Units
MHz
%
Input clock frequency
Duty Cycle
66.66
D.C.RefClk
JCLK-REF
45
55
Input Jitter (peak-to-peak)
Input clock frequency deviation
0.4
ns
Frequency
tolerance
150
ppm
Aging
Input clock long time deviation
+/- 5
ppm/
year
Trdy
Lock time
0.25
ꢀs
Note: Spread spectrum clocks are not supported.
820x – Data Sheet, DS-0157-D
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11.3 Flash Interface Timing
Figure 11-1. Flash Write Timing
Figure 11-2. Flash Read Timing
Table 11-2. Flash Interface AC Characteristics
Symbol
tWH
Description
Min
Typ
Max
Units
ns
FLASH_SCK high time
FLASH_SCK low time
FLASH_CS setup time
FLASH_CS hold time
FLASH_SI valid time
FLASH_SI hold time
9
9
5
5
0
0
tWL
ns
tCSS
tCSH
tV
ns
ns
10
ns
tHO
ns
820x – Data Sheet, DS-0157-D
Page258
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Table 11-2. Flash Interface AC Characteristics
Symbol
tHD:DAT
tSU:DAT
Description
Min
Typ
Max
Units
ns
FLASH_SO hold time
FLASH_SO setup time
5
5
ns
Note: The parameters in this table were measured with a 30pf load.
11.4 JTAG Interface Timing
The 820x is designed to support the IEEE 1149.1 JTAG standard.
Figure 11-3. JTAG Timing
Table 11-3. JTAG Interface AC Characteristics
Symbol
Tjclk
Description
Min
Max
Units
ns
JTAG clock frequency
20
15
Tth
JTAG_TMS and JTAG_TDI hold time
JTAG_TMS and JTAG_TDI setup time
JTAG_TDO propagation delay
ns
10
10
Tjsu
ns
Tjpr
ns
11.5 PCIe Interface Timing
The 820x PCIe interface is fully compliant to the PCI Express Electromechanical
Specification Revision 2.0 standard.
820x – Data Sheet, DS-0157-D
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12 Thermal Specifications
Table 12-1. Thermal Specifications
Parameter
Max
Junction Temperature (Tj)
125 °C
6.5 °C/W
20.4 °C/W
18 °C/W
17 °C/W
4.2 °C/W
Internal thermal resistance, (
)
jc
Thermal resistance, ( ja) at 0 m/s airflow
Thermal resistance, ( ja) at 1 m/s airflow
Thermal resistance, ( ja) at 2 m/s airflow
Temperature correlation ( jt)
12.1 Heat Sink Requirements
Each application is different, and will require thermal analysis based on the application
environment.
12.2 Junction Temperature Specifications
The maximum operating junction temperature is 125°C. Above this temperature, proper
operation is not guaranteed. For maximum operating life, however, the average junction
temperature in the device should be no more than TBD°C. Worst-case device dissipation
should be used when making these calculations.
12.3 Thermal Sensor Controller
The 820x contains a thermal sensor controller that can be used to read or monitor the 820x
die temperature. Please refer to Section 5.12, “Temperature Sensor Controller” and
Section 6.8, “Temperature Sensor Controller Registers” for detailed information.
820x – Data Sheet, DS-0157-D
Page260
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13 Package Specifications
This chapter provides general and mechanical package information, as well as ball
assignment drawings.
13.1 General Information
Table 13-1. General Package Information
Package Information
Package Type
Ball Count
Description
HSBGA
196
Package Size
Pitch
15mm x 15mm
1.0 mm
13.2 Mechanical Information
The 820x is packaged as a 196 ball HSBGA (15 x 15 mm body, 1 mm ball pitch). Figure
13-1 shows the detailed package specifications for the device.
820x – Data Sheet, DS-0157-D
Page261
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Figure 13-1. Package Dimensions
820x – Data Sheet, DS-0157-D
Page262
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Figure 13-2. Ball Map Drawing - Top View - Upper Left Quadrant
820x – Data Sheet, DS-0157-D
Hifn Confidential
Page263
Figure 13-3. Ball Map Drawing - Top View - Upper Right Quadrant
820x – Data Sheet, DS-0157-D
Hifn Confidential
Page264
Figure 13-4. Ball Map Drawing - Top View - Lower Left Quadrant
820x – Data Sheet, DS-0157-D
Hifn Confidential
Page265
Figure 13-5. Ball Map Drawing - Top View - Lower Right Quadrant
820x – Data Sheet, DS-0157-D
Hifn Confidential
Page266
Table 13-2. Alphabetical Ball List
Signal
Ball
B2
Signal
Ball
P10
P13
P2
Signal
Ball
PCIE_LINKUP
PCIE_TXN[2]
PCIE_TXN[3]
PCIE_TXP[0]
PCIE_TXP[1]
PCIE_TXP[2]
PCIE_TXP[3]
PERST_N
BOARD_VERSION[
0]
C1
PCIE_LOS_LVL[0]
PCIE_LOS_LVL[1]
PCIE_LOS_LVL[2]
PCIE_LOS_LVL[3]
PCIE_LOS_LVL[4]
PCIE_PHY_CFG
PCIE_REFCLK_N
PCIE_REFCLK_P
PCIE_REFRES
PCIE_RXEQCTL[0]
PCIE_RXEQCTL[1]
PCIE_RXEQCTL[2]
PCIE_RXN[0]
L3
BOARD_VERSION[
1]
C2
B1
N1
L2
P5
BOARD_VERSION[
2]
M1
K3
P9
P12
C3
EXT_FLASH_EN
FLASH_CS
FLASH_SCK
FLASH_SI
FLASH_SO
GPIO[0]
GPIO[1]
GPIO[10]
GPIO[11]
GPIO[12]
GPIO[13]
GPIO[14]
GPIO[15]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[7]
GPIO[8]
GPIO[9]
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
NC
E14
B3
D3
N8
N7
L7
PLL_LOCK
D14
K12
K14
A2
C4
PLL0_REF_CLK
PLL1_REF_CLK
POR_N
B4
A4
J2
C5
K1
JTAG_TRST_N
PULLDN25_33
PULLDN25_33
PULLDN25_33
PULLDN25_33
PULLDN25_33
PULLDN25_33
PULLDN25_33
PULLDN25_33
PULLDN25_33
PULLDN25_33
PULLDN25_33
PULLDN25_33
PULLDN25_33
PULLDN25_33
PULLDN25_33
PULLDN25_33
PULLDN25_33
PULLDN25_33
PULLDN25_33
PULLDN25_33
PULLUP25_33
PULLUP25_33
B14
A7
B5
J1
B10
C10
A11
B11
A12
C11
A5
M4
M6
M10
M12
M3
M5
M9
M11
H14
D1
PCIE_RXN[1]
D2
PCIE_RXN[2]
E1
PCIE_RXN[3]
E2
PCIE_RXP[0]
E3
PCIE_RXP[1]
E12
E13
F3
PCIE_RXP[2]
C6
PCIE_RXP[3]
B6
PCIE_TX_BOOST[0
]
F12
F13
F14
G1
A6
A9
PCIE_TX_BOOST[1
]
J14
J13
J12
B9
C9
PCIE_TX_BOOST[2
]
G2
A10
C13
B13
C12
A13
A3
PCIE_TX_BOOST[3
]
H1
H2
PCIE_TX_LVL[0]
PCIE_TX_LVL[1]
PCIE_TX_LVL[2]
PCIE_TX_LVL[3]
PCIE_TX_LVL[4]
PCIE_TXN[0]
G12
G13
G14
H13
H12
P3
J3
K2
K13
L12
B12
L1
NC
C14
D12
D13
NC
NC
PCIE_TXN[1]
P6
820x – Data Sheet, DS-0157-D
Hifn Confidential
Page267
Signal
Ball
D4
D6
D9
D11
F1
Signal
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Ball
E5
Signal
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Ball
J10
K5
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10A
VDD10A
VDD25_33
VDD25_33
VDD25_33
VDD25_33
VDD25_33
VDD25_33
VDD25A
VDD25A
VDDA_PLL1
VDDA_PLL0
VRET_PLL0
VRET_PLL1
VSS
E6
E7
K6
E8
K7
E9
K8
F4
E10
F2
K9
F11
G3
J4
K10
L8
F5
F6
M2
M7
M8
M13
N2
J11
L4
F7
F8
L11
L5
F9
F10
G4
G5
G6
G7
G8
G9
G10
G11
H3
H4
H5
H6
H7
H8
H9
H10
H11
J5
L10
D5
D10
E4
N3
N4
N5
N6
E11
K4
N9
N10
N11
N12
N13
P1
K11
L6
L9
L13
N14
M14
L14
A1
P4
P7
P8
P11
P14
VSS
A8
VSS
A14
B7
VSS
VSS
B8
VSS
C7
J6
VSS
C8
J7
VSS
D7
D8
J8
VSS
J9
820x – Data Sheet, DS-0157-D
Hifn Confidential
Page268
Table 13-3. Numeric Ball List
Signal
Ball
C5
Signal
Ball
E11
E12
E13
E14
F1
Signal
Ball
A1
GPIO[0]
GPIO[3]
VSS
VDD25_33
PULLDN25_33
PULLDN25_33
EXT_FLASH_EN
VDD10
VSS
C6
POR_N
A2
C7
NC
A3
VSS
C8
FLASH_SO
GPIO[2]
GPIO[5]
PULLDN25_33
VSS
A4
GPIO[8]
GPIO[11]
GPIO[15]
JTAG_TDO
JTAG_TCK
NC
C9
A5
C10
C11
C12
C13
C14
D1
VSS
F2
A6
PULLDN25_33
VDD10
F3
A7
F4
A8
VSS
F5
GPIO[6]
GPIO[9]
GPIO[12]
GPIO[14]
JTAG_TMS
VSS
A9
VSS
F6
A10
A11
A12
A13
A14
B1
PULLDN25_33
PULLDN25_33
PCIE_PHY_CFG
VDD10
VSS
F7
D2
VSS
F8
D3
VSS
F9
D4
VSS
F10
F11
F12
F13
F14
G1
VDD25_33
VDD10
D5
VDD10
BOARD_VERSION[
2]
D6
PULLDN25_33
PULLDN25_33
PULLDN25_33
PULLDN25_33
PULLDN25_33
VDD10
PCIE_LINKUP
FLASH_CS
FLASH_SI
GPIO[1]
B2
VSS
D7
B3
VSS
D8
B4
VDD10
D9
B5
VDD25_33
VDD10
D10
D11
D12
D13
D14
E1
G2
GPIO[4]
B6
G3
VSS
B7
NC
VSS
G4
VSS
B8
NC
VSS
G5
GPIO[7]
B9
PLL_LOCK
PULLDN25_33
PULLDN25_33
PULLDN25_33
VDD25_33
VSS
VSS
G6
GPIO[10]
GPIO[13]
PULLUP25_33
JTAG_TDI
JTAG_TRST_N
B10
B11
B12
B13
B14
C1
VSS
G7
E2
VSS
G8
E3
VSS
G9
E4
VSS
G10
G11
G12
G13
G14
H1
E5
VSS
BOARD_VERSION[
0]
VSS
E6
PCIE_TX_LVL[0]
PCIE_TX_LVL[1]
PCIE_TX_LVL[2]
PULLDN25_33
PULLDN25_33
VSS
E7
BOARD_VERSION[
1]
C2
VSS
E8
VSS
E9
PERST_N
C3
C4
VSS
E10
H2
FLASH_SCK
820x – Data Sheet, DS-0157-D
Hifn Confidential
Page269
Signal
Ball
H3
Signal
Ball
K8
Signal
Ball
N1
VSS
VSS
PCIE_LOS_LVL[1]
VSS
VSS
H4
VSS
K9
N2
VSS
H5
VSS
K10
K11
K12
K13
K14
L1
VSS
N3
VSS
H6
VDD25_33
PLL0_REF_CLK
PULLDN25_33
PLL1_REF_CLK
PULLUP25_33
PCIE_LOS_LVL[2]
PCIE_LOS_LVL[0]
VDD10
VSS
N4
VSS
H7
VSS
N5
VSS
H8
VSS
N6
VSS
H9
PCIE_REFCLK_P
PCIE_REFCLK_N
VSS
N7
VSS
H10
H11
H12
H13
H14
N8
VSS
L2
N9
PCIE_TX_LVL[4]
PCIE_TX_LVL[3]
L3
VSS
N10
N11
N12
N13
N14
P1
L4
VSS
PCIE_TX_BOOST[0
]
VDD10A
L5
VSS
VDD25A
L6
VSS
PCIE_RXEQCTL[2]
J1
PCIE_REFRES
VSS
L7
VDDA_PLL0
VSS
PCIE_RXEQCTL[0]
J2
L8
PULLDN25_33
VDD10
VSS
J3
VDD25A
L9
PCIE_TXP[0]
PCIE_TXN[0]
VSS
P2
J4
VDD10A
L10
L11
L12
L13
L14
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
P3
J5
VDD10
P4
VSS
J6
PULLDN25_33
VDDA_PLL1
VRET_PLL1
PCIE_LOS_LVL[3]
VSS
PCIE_TXP[1]
PCIE_TXN[1]
VSS
P5
VSS
J7
P6
VSS
J8
P7
VSS
J9
VSS
P8
VSS
J10
J11
J12
PCIE_TXP[2]
PCIE_TXN[2]
VSS
P9
VDD10
PCIE_RXP[0]
PCIE_RXN[0]
PCIE_RXP[1]
PCIE_RXN[1]
VSS
P10
P11
P12
P13
P14
PCIE_TX_BOOST[3
]
PCIE_TXP[3]
PCIE_TXN[3]
VSS
PCIE_TX_BOOST[2
]
J13
J14
PCIE_TX_BOOST[1
]
VSS
PCIE_RXEQCTL[1]
PULLDN25_33
PCIE_LOS_LVL[4]
VDD25_33
VSS
K1
K2
K3
K4
K5
K6
K7
PCIE_RXP[2]
PCIE_RXN[2]
PCIE_RXP[3]
PCIE_RXN[3]
VSS
VSS
VRET_PLL0
VSS
820x – Data Sheet, DS-0157-D
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Page270
14 Errata
Errata are design defects or errors. Hardware Errata may cause the 820x behavior to
deviate from published specifications.
The 820x device revision history may be tracked using a combination of the PCIe Revision
ID register (Section 7.1.5) and the 820x Minor Revision register (Section 6.1.6). Table 14-
1 lists the current 820x revisions. Each errata described in this section is identified with its
applicable major and minor revision numbers.
Table 14-1. 820x Major vs, Minor Revision Matrix
PCIe Rev ID
Minor Rev
820x Revision
Pre-production
Production
0
0
0
1
Errata 1. JTAG_TRST_N
820x major revision(s): 0
820x minor revision(s): 0, 1
Description:
The signal JTAG_TRST_N requires a low to high transition during power on reset in
order for the chip to operate normally.
Solution:
The JTAG_TRST_N signal may be tied to POR_N.
Errata 2. Small packet condition locks 820x
820x major revision(s): 0
820x minor revision(s): 0, 1
Description:
The 820x will stop retrieving commands from the command ring when all the condi-
tions listed below are met:
a. SDK entered a command in small packet mode
b. PCIe link Maximum Read Request Size is 128B or 256B
c. Last entry in destination buffer ended on 128 or 256B alignment
d. Destination buffer overflow
Solution:
The 820x SDK prevents small packet command submittal if conditions (a) - (c) above
are met. Customers who develop their own drivers must include a similar workaround.
Errata 3. Combination of conditions causes command processing latency
820x major revision(s): 0
820x minor revision(s): 0, 1
820x – Data Sheet, DS-0157-D
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Description:
Command processing latency or hang may occur when all the conditions listed below
are met:
a. Packet Processor (compression, encryption, hash commands) and Public Key
processor commands are simultaneously active
b. Packet Processor asserts interrupt when a command completes
c. Write Request Controller module acknowledges a write request from the
Public Key processor, deasserting the Packet Processor interrupt
d. Software has not entered the interrupt service routine
Solution:
The 820x SDK implements a timer to monitor the completed commands in the result
ring. If the timer expires due to a hardware error, the command in the result ring is
sent to the host. Customers who develop their own drivers must include a similar
workaround.
Errata 4. Die revision 0 of the 820x fails the PCISIG compliance test that brings the link
down and then up before starting the test sequence.
820x major revision(s): 0
820x minor revision(s): 0
Description:
A PCIe link or Root Complex event occurs which prevents the endpoint core of the
820x device from getting into the “DETECT” state from the “L0”, “L0s”or “L1” LTSSM
states defined in the PCIe v2.0 base specification. Usually this type of event is a devi-
ation from normal operation, typically for compliance testing.
Solution:
A hard or soft reset is required if this condition occurs. The production revision of the
820x (major rev 0, minor rev 1) corrects this errata.
820x – Data Sheet, DS-0157-D
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A Appendix A: IPsec Encapsulating
Security Payload (ESP) Format
This section describes the format of the IPsec ESP fields as well as the encryption and
authentication coverage of these fields.
Table A-1. IPsec ESP Packet Field Description
Authentication
Coverage
Section
Field Name
Size
(bytes)
Description
Encryption
Coverage
ESP Header
SPI
Security Parameter Index
(SPI): A 32-bit value that is
combined with the
destination address and
security protocol type to
identify the security
4
4
√
association to be used for
this datagram. See the topic
on security associations for
more details.
Sequence
Number
Sequence Number: A
counter field initialized to
zero when a security
association is formed
between two devices, and
then incremented for each
datagram sent using that
SA. This is used to provide
protection against replay
attacks.
√
√
Payload
Payload Data
Payload Data: The encrypted
payload data, consisting of a
higher layer message or
encapsulated IP datagram.
variable May also include support
information such as an
initialization vector, required
by certain encryption
√
methods.
ESP Trailer
Padding
Additional padding bytes
variable
included as needed for
√
√
√
√
(0 to 255)
encryption or for alignment.
Pad Length
The number of bytes in the
preceding Padding field.
1
Next Header
Contains the protocol
number of the next header
1
√
√
in the datagram. Used to
chain together headers.
ESP Authentication Data
This field contains the
Integrity Check Value (ICV)
resulting from the
variable
application of the optional
ESP authentication
algorithm.
820x – Data Sheet, DS-0157-D
Page273
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Figure A-1. IPsec ESP Packet Format
820x – Data Sheet, DS-0157-D
Page274
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B Appendix B: CRC Algorithms
B.1 Key CRC and XTS DIF
AES-XTS mode DIF CRC and other key CRCs use the CRC16 algorithm below:
F(x) = x16 + x15 + x11 + x9 + x8 + x7 + x5 + x4 + x2 + x + 1
The initial value for the function is “0xFFFF” (refer to t10-dif-03, http://www.t10.org).
Note that the generated CRC for the key need to be swapped.
uint dif_crc16(uint bCnt,const void *data,uint crcVal) {
uint i,j;
const u08b *p = (const u08b *)data;
assert((crcVal & ~0xFFFF) == 0);
for (i=0;i<bCnt;i++) {
crcVal ^= (p[i] << 8);
for (j=0;j<8;j++)
crcVal = (crcVal << 1) ^ ((crcVal & 0x8000) ? 0x18BB7 : 0);
}
assert((crcVal & ~0xFFFF) == 0);
return crcVal;
}
B.2 Data CRC
Data CRCs use the CRC32 algorithm below:
F(x) = x32+x26+x23+x22+x16+x12+x11+x10+x8+ x7+x5+x4+x2+x+1
The initial value of the function is “0xFFFF_FFFF”.
string CalcLCRC(const string Data)
{
string result = "11111111111111111111111111111111";
int byte_num = Data.length() / 8;
string _crc, crc32;
int poly[13] = { 6,9,10,16,20,21,22,24,25,27,28,30,31 };
int src = 0 , dst = 0;
while( dst < Data.length() )
{
if( Data.at(dst + 7 - 2*(dst%8)) != result.at(src) ){
result.push_back('1');
// xor poly 0x04c11db7
for( int i=0; i<13; i++ )
result.at( src + poly[i] ) = result.at( src + poly[i] ) == '0'?'1':'0';
}else
result.push_back('0');
src++ , dst++;
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}
// TODO:: rewire result
crc32 = result.substr (src , 32 ) ;
for ( int i = 0; i < 4 ; i ++ )
for ( int j = 0; j < 8; j ++ )
_crc = _crc + crc32.at( 8 * i + 7 - j );
for ( int i = 0; i < 32; i ++ )
_crc.at( i ) = ( _crc.at(i) == '0' ? '1' : '0' );
return _crc;
}
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C Appendix C: AES CBC/XTS FK
Generation
For more information on the AES algorithm, please refer to the FIPS-197 Specification for
the Advanced Encryption Standard (AES).
C.1 Key Expansion
The key expansion algorithm shown below operates on 32 bit word segments of the keys,
where Nr is the number of rounds (iterations) of the AES algorithm, Nk is the number of 32
bit words in the key (4 for 128 bit keys), Nb is the number of words in a block (4 for this
implementation).
KeyExpansion[Rounds+1][128](Key[128|256])
{
reg[32] temp;
if (sizeof(Key)==256)
{ KeyExpansion[0], KeyExpansion[1]} = Key;
else
// 128 bit key
KeyExpansion[0] = Key;
for(k = sizeof(Key)==256 ? 2 : 1; k<=Rounds; k=k+1) {
temp = ByteSub(RotByte(KeyExpansion[k-1][31:0]));
if (sizeof(Key)==256) begin
lastkey = ExpandedKey[k-2];
if (k%2==0)
temp = temp^{Rcon(k/2 - 1),24'h000000};
end else begin // 128 bit key
lastkey = KeyExpansion[k-1];
temp = temp^{Rcon(k-1),24'h000000};
end
temp = temp ^ lastkey[127:96];
KeyExpansion[k][127:96] = temp;
temp = temp ^ lastkey[95:64];
KeyExpansion[k][95:64] = temp;
temp = temp ^ lastkey[63:32];
KeyExpansion[k][63:32] = temp;
temp = temp ^ lastkey[31:0];
KeyExpansion[k][31:0] = temp;
}
}
For 256-bit keys, each 128 bit key expansion array member is used as the key by each
round of the encryption/decryption algorithm. In this case, (Nr+1)/2 256-bit expanded keys
are required.
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C.2 Encryption Algorithm
An AES encryption algorithm involves an initial key expansion followed by a user specified
number of encryption rounds represented here by Nr. Nr is one of the parameters specified
in the input control word and is typically 10 for 128 bit keys, 14 for 256 bit keys, and a
maximum of 32.
AES_encrypt(State[128], CipherKey[128/256], Rounds)
{
array[128] ExpandedKey[Rounds+1];
ExpandedKey = KeyExpansion(CipherKey) ;
State = Text ^ ExpandedKey[0];
For( i=1 ; i<Rounds ; i++ ) {
State = MixColumn(ShiftRow(ByteSub(State))) ^ ExpandedKey[i];
}
Output = ShiftRow(ByteSub(State)) ^ ExpandedKey[Rounds];
}
Note that since the expanded keys are used in increasing order, the key expansion
algorithm can run concurrently with the encryption algorithm.
C.3 Decryption Algorithm
The AES decryption algorithm is similar to the encryption algorithm, in that it has the same
basic form and uses the same expanded key register array. What is different is that
transformation functions in the decryption round are inverses of those used in the
encryption case. The inverse functions are very similar in form to their forward
counterparts. The decryption algorithm also uses keys in the reverse order from the
expanded key array. This causes the decryption algorithm to run slightly slower than
because all of the expansion keys must be calculated before decryption begins.
AES_decrypt(State[128], CipherKey[128/256], Rounds)
{
array[128] ExpandedKey[Rounds+1];
ExpandedKey = KeyExpansion(CipherKey) ;
State = Text ^ ExpandedKey[Rounds];
For( i=Rounds-1 ; i>0 ; i-- ) {
State = InvMixColumn(InvShiftRow(InvByteSub(State)) ^ ExpandedKey[i]);
}
Output = InvShiftRow(InvByteSub(State)) ^ ExpandedKey[0];
}
The AES Encryption key is different from the Decrypt key because the pre-calculated
decryption key can improve AES performance. Refer to AES Spec §5.2 Key Expansion.
The C code for generating the FK in YD simulation environment can be reused.
LAN security standard IEEE 802.1ae (MACSec) and NIST SP 800-38D use AES cipher in the
GCM mode, while the disk/tape encryption standard IEEE P1619 D16 uses the XTS mode.
Legacy storage designs used the CBC mode, NIST SP 800-38A.
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Figure C-1. GCM Mode
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Figure C-2. CBC Mode
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D Appendix D: MAC and IPAD and
OPAD
D.1 MAC in SSL3.0
The MAC in SSL3.0 is calculated as follows:
Hash(Write Secret || Pad2 || Hash(Write Secret || Pad1 || Seq. No. || Type || Length
|| Application Data))
Where:
Hash = SHA-1 or MD5
Write Secret = 20 bytes if SHA-1, 16 bytes if MD5; from Crypto Header
Pad1 = 48/40 bytes of 0x36 (MD5/SHA-1)
Pad2 = 48/40 bytes of 0x5C (MD5/SHA-1)
SeqNum = 8 byte Sequence Number from Crypto Header
Type = Type byte from SSL Header
Length = 16 bit Length of payload (no padding)
D.2 MAC in TLS1.0
The MAC in TLS 1.0 is calculated as follows:
HMACHash(MACWrite Secret, Seq. No. || Type || Version || Length || Application
Data)
Where:
HMACHash = HMAC-SHA-1 or HMAC-MD5
Write Secret = 20 bytes if SHA-1, 16 bytes if MD5. Note that the Mustang HMAC operation
uses a precomputed IPAD/OPAD formulation of the Write Secret; that is, the
Ipad=hash([WriteSecret]XOR[0x36...]) and opad=hash([WriteSecret]XOR[0x5C...])
SeqNum = 8 byte Sequence Number from Crypto Header
Type = Type byte from SSL Header
Version = 16 bit Version from SSL Header (SSL3.0 = 3,0; TLS1.0 = 3,1)
Length = 16 bit Length of payload (no padding!)
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Note: the Length available in the final output packet SSL/TLS header is the length including
padding. The Length used in the MAC calculation, however, is the SSL.compressedfragment
length, and does NOT include padding.
D.3 MAC in DTLS 1.0
The MAC in DTLS 1.0 is calculated as follows:
HMACHash(MACWrite Secret, Epoch # || Seq. # || Type || Version || Length || Appli-
cation Data)
Where:
HMACHash = HMAC-SHA-1 or HMAC-MD5
Write Secret = 20 bytes if SHA-1, 16 bytes if MD5. Note that the Mustang HMAC operation
uses a precomputed IPAD/OPAD formulation of the Write Secret; that is, the
Ipad=hash([WriteSecret]XOR[0x36...]) and opad=hash([WriteSecret]XOR[0x5C...])
Epoch # = 2 byte explicit Epoch Number from DTLS Header (provided by PP)
Seq# = 6 byte explicit Sequence Number from DTLS Header (provided by PP)
Type = Type byte from DTLS Header
Version = 16 bit Version from DTLS Header (DTLS1.0 = 254,255)
Length = 16 bit Length of payload (before encryption, so no padding)
Note: the Length available in the final output packet SSL/TLS header is the length including
padding. The Length used in the MAC calculation, however, is the
DTLS.compressedfragment length, and DOES not include padding.
D.4 IPAD & OPAD Generation
The pre-computed function is the compressed digest produced by hashing the secure key
(K) padded with zeroes to form a 512-bit block exclusive-or'd with the given IPAD value
(0x36363636) or OPAD value (0x5c5c5c5c). The hashing function is loaded with the IV
(Initial Vector = 0x01234567, 89abcdef, fedcba98, 76543210 for MD5 or = 0x67452301,
efcdab89, 98badcfe, 10325476, c3d2e1f0 for SHA-1 or 0x6a09e667, bb67ae85, 3c6ef372,
a54ff53a, 510e527f, 9b05688c, 1f83d9ab, 5be0cd19 for SHA-256). The figure below shows
the flow of the pre-computed IPAD and OPAD values.
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Figure D-1. IPAD and OPAD Generation
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I Document Revision History
This section lists the additions, deletions, and modifications made to this document for each
release of this document.
I.1 Document Revision A
Update 1.
Initial release.
I.2 Document Revision B
Update 1.
Update 2.
Section 1.2 Part Numbers: added this new section.
Chapter 2 Operation: added internal temperature sensor controller to Figure
2-1 and Table 2-1.
Update 3.
Update 4.
Update 5.
Update 6.
Section 3.1.3.3 IV and AAD, Figure 3-13 AES IV Lengths: added 3DES-CBC.
Section 3.2 Result Ring: updated bits in result ring.
Section 5.12 Temperature Sensor Controller: added this new section.
Section 6.7 Serial/Parallel Interface regs: removed all references to the
external thermal device on the SPI bus. Removed thermal registers.
Update 7.
Update 8.
Section 6.8 Temperature Sensor Controller Regs: added this new section.
Section 7.1 PCIE Interface: renamed pcie_tx and pcie_rx signals. Added
pcie_refclk_p, pcie_refclk_n, pcie_resref.
Update 9.
Section 7.2 Misc Interface: removed CM_busy, PKP_busy, 820x_err,
clk_gating_disable, phy_refclk_sel, thermal_int_n, and added pll0_ref_clk,
pll1_ref_clk.
Update 10. Section 7.6 Test Interface: scan_enable is one bit wide, removed pll_out0
and pll_out1.
Update 11. Section 9.1 Clock Domains: added CPIe_PHY.
Update 12. Section 10.2 Digital Power Supplies: added this new section.
Update 13. Section 10.3 Analog Power Supplies: added this new section.
Update 14. Section 10.4 Power Sequencing: new content for this section.
Update 15. Chapter 11 Thermal Specifications: added thermal resistance and temp
correlation parameter.
Update 16. Section 12 Package Specifications: added package drawing, ball map
drawing, and alphabetical and numerical ball lists.
Update 17. Moved Sections 10.1 Clock Specification and Section 10.2 Clock Gating to
Chapter 2 Operations to be expanded upon later. Added AC and DC
Specifications. Replaced mechanical drawing with latest update. Removed
comments for TX_LVL and PLL0_REF_CLK signals. Changed VDDA_PLL_0 to
VDDA_PLL0 in Table 13-1 alphabetical Ball List. Corrected padding example
in Table 3.2. Checked for old pin names in doc.
Update 18. Section 2.2 remove PCIe_PHY and update speed numbers for clock
domains. Fixed figure in section 3.2. Section 6.1.1 add bit for Over_heated
status and add to diagram. Section 6.7 changed pin labels in figure 6-3.
Section 6.7.7 changed flash_status to byte_prog in diagram. Added
Spansion device to list of recommended devices in Section 6.7. Section 6.8
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changed parameter “1” to “a”. Changed power consumption numbers for
VDD_10 in tables 9.8, 9.9, 9.10, 9.11. Removed duplicate thermal
resistance table in Chap 12.
I.3 Document Revision C
Update 1.
Section 1.2 Ordering Information: added “IB” to all part numbers.
Update 2.
Update 3.
Update 4.
Section 1.1.3 Engine Features: removed CCM encryption.
Section 3.2 Result Ring: changed bit 28 from OVER_HEAT to Reserved.
Section 5.12 Temperature Sensor Controller: updated this section to include
flow diagram, examples and to remove automatic temperature detection.
Update 5.
Update 6.
Update 7.
Section 6.1.1 Status Register: removed over_heated bit and made reserved.
Section 6.1.2 820x Error Register: corrected bit postitions.
Section 6.1.3 820x Interrupt Status Register: changed THERM_INT_N to
Reserved; changed PKP_INT to Reserved.
Update 8.
Update 9.
Section 6.1.4 820x Interrupt Enable Register: changed THERM_INT_N_EN
to Reserved; changed PKP_INT_EN to Reserved.
Section 6.1.5 Command Completion Interrupt Interval Register: removed
this register.
Update 10. Section 6.1.6 Command Completion Interrupt Number Register: removed
this register.
Update 11. Section 6.4.2.1 Public Key Command Register Format: added "host must
poll this register to know whether the command is finished"; changed IRQ
to Reserved.
Update 12. Section 6.5.7 RNG Config Register: added this new register.
Update 13. Section 6.6 GPIO Registers: corrected all GPIO registers to reflect 16-bit
GPIO instead of 32-bit.
Update 14. Section 6.8 Temperature Sensor Controller registers: modified this section
to remove automatic temp detection.
Update 15. Chapter 11 Thermal Specs: removed ambient operating temperature data
from Table 11-1.
Update 16. Section 13 Errata: added errata #2, 3.
I.4 Document Revision D
Update 1.
Section 3.1.3.6 Hash Buffer: added alignment restriction.
Update 2.
Update 3.
Update 4.
Section 6.1.6 Die Revision Reg: added this new register.
Section 8.1 Miscellaneous Interface: updated Figure 8-1.
Section 10.5 Power Consumption: updated power values or all 820x
devices.
Update 5.
Errata: added errata 4.
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