MP8775 [EXAR]

CMOS 20 MSPS, 8-Bit, High Speed Analog-to-Digital Converter; CMOS 20 MSPS ， 8位高速模拟数字转换器


型号：	MP8775
厂家：	EXAR CORPORATION
描述：	CMOS 20 MSPS, 8-Bit, High Speed Analog-to-Digital Converter CMOS 20 MSPS ， 8位高速模拟数字转换器转换器
文件：	总8页 (文件大小：460K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MP8775

CMOS

20 MSPS, 8-Bit, High Speed

Analog-to-Digital Converter

March 1999-4

FEATURES

• 8-Bit Resolution

• Power Down Available: MP8776

• 3 V Version: MP87L75

• Small 20 Pin SOIC Package

• 20 MHz Sampling Rate

• DNL = +1/2 LSB, INL = +1 LSB (typ)

• Internal S/H Function

• Single Supply: 5 V

APPLICATIONS

• V DC Range: 0 V to V

• Digital Color Copiers

• Cellular Telephones

• CCD’s Based Systems

• Hardware Scanners

• Video Capture Boards

• V

DC Range: 1 V to V

REF

• Low Power: 85 mW typ. (excluding reference)

• Latch-Up Free

• ESD Protection: 2000 V Minimum

The designer can choose the internally generated

GENERAL DESCRIPTION

reference voltages by connecting V to V

and V to

RBS

, or provide external reference voltages to the V

RTS

The MP8775 is an 8-bit Analog-to-Digital Converter in a

small 20 pin SOIC package. Designed using an

advanced 5 V CMOS process, this part offers excellent

performance, low power consumption and latch-up free

operation.

and V pins. The internal reference generates 0.6 V at

and 2.6 V at V

Providing external reference

voltages allows easy interface to any input signal range

between GND and V . This also allows the system to

adjust these voltages to cancel zero scale and full scale

errors, or to change the input range as needed.

This device uses a two-step flash architecture to maintain

low power consumption at high conversion rates. The

input circuitry of the MP8775 includes an on-chip S/H

function and allows the user to digitize analog input

The device operates from a single +5 V supply. Power

consumption is 85 mW at F = 20 MHz.

signals between GND and V . Careful design and chip

Specified for operation over the commercial / industrial

(--40 to +85°C) temperature range, the MP8775 is

available in Surface Mount (SOIC), Shrunk Small Outline

(SSOP) and Plastic dual-in-line (PDIP) packages.

layout have achieved a low analog input capacitance.

This reduces “kickback” and eases the requirements of

the buffer/amplifier used to drive the MP8775.

SIMPLIFIED BLOCK AND TIMING DIAGRAM

RTS

MSB

Comp.

DB7 (MSB)

DB0 (LSB)

Latch

Encoder

F/F

Error

LSB

Comp.

Correction

RBS

Sample

CLK

DB7-

DB0

GND

S/H

Clock Logic

CLK

N-3

N-2

N-1

AGND

DGND

Rev. 3.01

E1999

EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z (510) 668-7017

MP8775

ORDERING INFORMATION

Package

Type

Temperature

Range

DNL

(LSB)

INL

(LSB)

Part No.

--40 to +85°C

SOIC

PDIP

MP8775AS

MP8775AN

MP8775AQ

¦3/4

¦1 1/2

SSOP

PIN CONFIGURATIONS

See Packaging Section for

Package Dimensions

DGND

DB0 (LSB)

DGND

DB0 (LSB)

DGND

DB1

DB2

DB3

DB4

DB5

DB6

DB1

DB2

DB3

DB4

DB5

RBS

AGND

RTS

DB6

DB7 (MSB)

CLK

20 Pin PDIP (0.300”)

20 Pin SOIC (Jedec, 0.300”)

20 Pin SSOP

PIN OUT DEFINITIONS

PIN NO.

NAME

DESCRIPTION

Digital Ground

PIN NO.

NAME

CLK

DESCRIPTION

DGND

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

Sample Clock

Data Output Bit 0 (LSB)

Data Output Bit 1

Digital Power Supply

Generates 2.6 V if tied to V

Top Reference

RTS

Data Output Bit 2

Data Output Bit 3

Analog Power Supply

Analog Input

Data Output Bit 4

Data Output Bit 5

AGND

Analog Ground

Data Output Bit 6

RBS

Generates 0.6 V if tied to V

Bottom Reference

Digital Ground

Data Output Bit 7 (MSB)

Digital Power Supply

DGND

Rev. 3.01

03ꢀꢁꢁꢂ

MP8775

ELECTRICAL CHARACTERISTICS TABLE (CONT’D)

25°C

Typ

Description

Symbol

Min

Max

Units

Conditions

AC PARAMETERS

Differential Gain Error

Differential Phase Error

FS = 4 x NTSC

POWER SUPPLIES

Operating Voltage (AV , DV

)

Current (AV + DV

)

Does not include ref. current

Notes:

Tester measures code transitions by dithering the voltage of the analog input (V ). The difference between the measured and the

ideal code width (V

/256) is the DNL error (Figure 2.). The INL error is the maximum distance (in LSBs) from the best fit line to

REF

any transition voltage (Figure 3.). Accuracy is a function of the sampling rate (FS).

Guaranteed. Not tested.

Specified values guarantee functionality. Refer to other parameters for accuracy.

--1 dB bandwidth is a measure of performance of the A/D input stage (S/H + amplifier). Refer to other parameters for accuracy within

the specified bandwidth.

See V input equivalent circuit (Figure 4.). Switched capacitor analog input requires driver with low output resistance.

All inputs have diodes to DV and DGND. Input DC currents will not exceed specified limits for any input voltage between

DGND and DV

t , t should be limited to >5 ns for best results.

Depends on the RC load connected to the output pin.

AGND and DGND pins are connected through the silicon substrate. Connect together at the package and to the analog ground plane.

Specifications are subject to change without notice

ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)^{1, 2, 3}

V_DDto GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

V_RT& V_RB. . . . . . . . . . . . . . . . . . . . V_DD+0.5 to GND --0.5 V

V_IN. . . . . . . . . . . . . . . . . . . . . . . . . . V_DD+0.5 to GND --0.5 V

All Inputs . . . . . . . . . . . . . . . . . . . . . V_DD+0.5 to GND --0.5 V

All Outputs . . . . . . . . . . . . . . . . . . . V_DD+0.5 to GND --0.5 V

Storage Temperature . . . . . . . . . . . . . . . . . . . --65 to +150°C

Lead Temperature (Soldering 10 seconds) . . . . . . . +300°C

Package Power Dissipation Rating @ 75°C

SOIC, SSOP, PDIP . . . . . . . . . . . . . . . . . . . . . . . 700 mW

Derates above 75°C . . . . . . . . . . . . . . . . . . . . . . 9 mW/°C

Notes:

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps

(HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short

transients outside the supplies of less than 100mA for less than 100µs.

V_DDrefers to AV_DDand DV_DD. GND refers to AGND and DGND.

1/FS

PWH

PWL

N + 1

PIPELINE DELAY

N + 2

CLK

Sample “N”

N -- 3

N -- 2

N -- 1

DATA N

DATA

t _HL

t _DL

Figure 1. MP8775 Timing Diagram

Rev. 3.01

MP8775

Output

Codes

Best Fit Line

DNL

LSB

(N+1)

(N)

Real Transfer Line

Analog

Input

EFS

INL

N + 1

Output

Codes

Ideal Transfer Line

N--1

Code Width (N) = V₍_N+1)-- V₍_N)

LSB = [ V -- V ] / 256

LSB

DNL_(N)= [ V_(N+1)-- V_(N)] -- LSB

Figure 2. DNL Measurement

CLK

Analog Input (Volt)

EZS

Figure 3. INL Error Calculation

+5 V

CLK

10µF

0.1µF

5pF

50Ω

Analog

Input

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

1.5pF

+ V

RTS

Digital

Outputs

0.1µF

CLK

MP8775

CLK

6 pF

0.1µF

RBS

CLK

5pF

CLK

Clock

AGND

GND

1.5pF

[N--2]

CLK

Figure 4. Equivalent Input Circuit

Figure 5. Typical Circuit Connections

APPLICATION NOTES

Signals should not exceed AV_DD+0.5V or go below AGND

--0.5V or DV_DD+0.5 V or DGND --0.5 V. All pins have internal

protection diodes that will protect them from short transients

(<100µs) outside the supply range.

capacitive coupling and reflections will contribute noise to the

conversion.

It is possible for the data valid delay (t_DL) to be equal to or

greater than the high pulse width of the sampling clock (t_PWH),

See Figure 1. This can cause timing related errors. For sample

rates above 14 MSPS use only the rising edge of the sample

clock (CLK) to latch data from the MP8775 to other parts of the

system.

AGND and DGND pins are connected internally through the

P-- substrate. DC voltage differences between these pins will

cause undesirable internal substrate currents.

The reference can be biased internally by shorting V_RTto

V_RTSand V_RBto V_RBS. This will generate 0.6 V at V_RBand 2.6 V

at V_RT(see Figure 5.).

The power supply (AV_DD) and reference voltage (V_RT& V_RB

pins should be decoupled with 0.1µF and 10µF capacitors to

AGND, placed as close to the chip as possible.

)

If the internal reference pins V_RTSand/or V_RBSare not used

they should be left unconnected.

The digital outputs should not drive long wires or buses. The

Rev. 3.01

MP8775

PERFORMANCE CHARACTERISTICS

Graph 1. DNL vs. Sampling Frequency

Graph 2. INL vs. Sampling Frequency

Graph 3. Supply Current vs.

Sampling Frequency

Graph 4. Supply Current vs.

Temperature

Graph 5. Reference Resistance vs.

Temperature

Graph 6. SNR vs. Input Frequency

Rev. 3.01

MP8775

Graph 7. SINAD vs. Input Frequency

Graph 8. ENOB vs. Input Frequency

Graph 9. THD vs. Input Frequency

Rev. 3.01

MP8775

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-

prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-

scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are

free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary

depending upon a user’s specific application. While the information in this publication has been carefully checked;

no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or

malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly

affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation

receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the

user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-

stances.

Datasheet March 1999

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

Rev. 3.01

MP8775 [EXAR]

相关型号：

MP8775AN

MP8775AQ

MP8775AS

MP8775E

MP8775E-LF

MP8775EL

MP8775EL-LF

MP8775EL-LF-Z

MP8775EL-Z

MP8775EN-LF

MP8776

MP8776AN