SP3243EUEP [EXAR]
Line Driver/Receiver,;
| 型号： | SP3243EUEP |
| 厂家： | 
EXAR CORPORATION |
| 描述： | Line Driver/Receiver, |
| 文件： | 总24页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
SP3243
3 Driver/5 Receiver Intelligent +3.0V to +5.5V
RS-232 Transceivers
FEATURES
1
2
3
4
5
6
7
28
27
26
C2+
C2-
C1+
V+
■ Meets true EIA/TIA-232-F Standards
from a +3.0V to +5.5V power supply
■ Interoperable with EIA/TIA-232 and
adheres to EIA/TIA-562 down to a +2.7V
power source
V
CC
V-
25 GND
R1IN
R2IN
R3IN
24
C1-
®
SP3243
■ AUTO ON-LINE circuitry automatically
23
ONLINE
wakes up from a 1μA shutdown
■ Regulated Charge Pump Yields Stable
RS-232 Outputs Regardless of VCC
Variations
22
21
20
19
R4IN
SHUTDOWN
STATUS
R2OUT
8
9
R5IN
T1OUT
T2OUT
T3OUT
10
11
R1OUT
■ Enhanced ESD Specifications:
+15kV Human Body Model
18 R2OUT
T3IN 12
17
16
15
R3OUT
R4OUT
R5OUT
+15kV IEC1000-4-2 Air Discharge
+8kV IEC1000-4-2 Contact Discharge
■ 250 Kbps min. transmission rate (EB)
■ 1000 Kbps min. transmission rate (EU)
■ Ideal for High Speed RS-232 Applications
13
14
T2IN
T1IN
Now Available in Lead Free Packaging
DESCRIPTION
TheSP3243productsare3driver/5receiverRS-232transceiversolutionsintendedforportableorhand-
held applications such as notebook and palmtop computers. The SP3243 includes one complementary
receiver that remains alert to monitor an external device's Ring Indicate signal while the device is
shutdown. The SP3243E and EB devices feature slew-rate limited outputs for reduced crosstalk and
EMI. The "U" and "H" series are optimized for high speed with data rates up to 1Mbps, easily meeting
the demands of high speed RS-232 applications. The SP3243 series uses an internal high-efficiency,
charge-pumppowersupplythatrequiresonly0.1μFcapacitorsin3.3Voperation. Thischargepumpand
Sipex's driver architectureallowtheSP3243seriestodelivercompliantRS-232performancefrom a single
power supply ranging from +3.0V to +5.5V. The AUTO ON-LINE® feature allows the device to
automatically "wake-up" during a shutdown state when an RS-232 cable is connected and a connected
peripheral is turned on. Otherwise, the device automatically shuts itself down drawing less than 1μA.
SELECTION TABLE
Device
Power
RS-232
RS-232
External
TTL 3-
State
# of Gauranteed ESD
AUTO ON-LINE®
Circuitry
Supplies
Drivers Receivers Components
Pins
Data Rate Rating
SP3243
SP3243E
SP3243B
+3.0V to +5.5V
+3.0V to +5.5V
+3.0V to +5.5V
3
3
3
3
3
3
5
5
5
5
5
5
4 capacitors
4 capacitors
4 capacitors
4 capacitors
4 capacitors
4 capacitors
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
28
28
28
28
28
28
120
120
2kV
15kV
2kV
250
SP3243EB +3.0V to +5.5V
SP3243U +3.0V to +5.5V
SP3243EU +3.0V to +5.5V
250
15kV
2kV
1000
1000
15kV
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
1
Power Dissipation per package
ABSOLUTE MAXIMUM RATINGS
28-pin SOIC (derate 12.7mW/oC above +70oC)....1000mW
28-pin SSOP (derate 11.2mW/oC above +70oC).....900mW
28-pin TSSOP (derate 13.2mW/oC above +70oC)......1059mW
32-pin MLPQ (derate 29.4mW/oC above +70oC)........2352mW
These are stress ratings only and functional operation
of the device at these ratings or any other above those
indicated in the operation sections of the specifications
below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may
affect reliability and cause permanent damage to the
device.
NOTE 1: V+ and V- can have maximum magnitudes of
7V, but their absolute difference cannot exceed 13V.
VCC.......................................................-0.3V to +6.0V
V+ (NOTE 1).......................................-0.3V to +7.0V
V- (NOTE 1)........................................+0.3V to -7.0V
V+ + |V-| (NOTE 1)...........................................+13V
ICC (DC VCC or GND current).........................+100mA
Input Voltages
TxIN,ONLINE,SHUTDOWN, ...........-0.3VtoVcc +6.0V
RxIN...................................................................+15V
Output Voltages
TxOUT.............................................................+13.2V
RxOUT, STATUS.......................-0.3V to (VCC +0.3V)
Short-Circuit Duration
TxOUT....................................................Continuous
Storage Temperature......................-65°C to +150°C
ELECTRICAL CHARACTERISTICS
Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX
,
C1 - C4 = 0.1μF. Typical values apply at VCC = +3.3V or +5.0V and TAMB = 25°C.
PARAMETER
MIN.
TYP.
MAX. UNITS CONDITIONS
DC CHARACTERISTICS
Supply Current,AUTO ON-LINE
®
1.0
10
μA
All RxIN open, ONLINE = GND,
SHUTDOWN = VCC, VCC = +3.3V,
TAMB = +25°C, TxIN = GND or VCC
Supply Current, Shutdown
Supply Current,
1.0
0.3
10
μA
SHUTDOWN = GND, VCC = +3.3V,
TAMB = +25°C, TxIN = VCC or GND
1.0
mA
ONLINE = SHUTDOWN = VCC, no load,
®
AUTO ON-LINE Disabled
VCC = +3.3V, TAMB = +25°C, TxIN = GND or VCC
LOGIC INPUTS AND RECEIVER OUTPUTS
Input Logic Threshold
VCC = +3.3V or +5.0V, TxIN,
ONLINE, SHUTDOWN
LOW
0.8
V
V
HIGH
2.4
Input Leakage Current
±0.01
±0.05
±1.0
μA
TxIN, ONLINE, SHUTDOWN,
TAMB = +25°C, VIN = 0V to VCC
Output Leakage Current
Output Voltage LOW
Output Voltage HIGH
DRIVER OUTPUTS
Output Voltage Swing
±10
0.4
μA
V
V
Receivers disabled, VOUT = 0V to VCC
IOUT = 1.6mA
IOUT = -1.0mA
VCC - 0.6 VCC - 0.1
±5.0
±5.4
±35
V
All driver outputs loaded with 3KΩ to GND,
TAMB = +25°C
VCC = V+ = V- = 0V, VOUT = ±2V
Output Resistance
Output Short-Circuit Current
Output Leakage Current
300
Ω
±60
±25
mA
μA
VOUT = 0V
VCC = 0V or 3.0V to 5.5V, VOUT = ±12V,
Drivers disabled
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
2
ELECTRICAL CHARACTERISTICS
Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX
,
C1 - C4 = 0.1μF. Typical values apply at VCC = +3.3V or +5.0V and TAMB = 25°C.
PARAMETER
MIN.
TYP.
MAX. UNITS CONDITIONS
RECEIVER INPUTS
Input Voltage Range
Input Threshold LOW
Input Threshold LOW
Input Threshold HIGH
Input Threshold HIGH
Input Hysteresis
-15
0.6
0.8
15
V
V
V
V
V
1.2
1.5
1.5
1.8
0.3
5
VCC = 3.3V
VCC = 5.0V
VCC = 3.3V
VCC = 5.0V
2.4
2.4
V
kΩ
Input Resistance
3
7
®
AUTO ON-LINE CIRCUITRY CHARACTERISTICS (ONLINE = GND, SHUTDOWN = VCC) 25°C
STATUS Output Voltage LOW
STATUS Output Voltage HIGH
Receiver Threshold to Drivers
0.4
V
V
μS
IOUT = 1.6mA
IOUT = -1.0mA
Figure 20
VCC - 0.6
350
0.2
Enabled (tONLINE
)
Receiver Positive or Negative
μS
μS
Figure 20
Figure 20
Threshold to STATUS HIGH
(tSTSH
)
Receiver Positive or Negative
30
Threshold to STATUS LOW
(tSTSL
)
TIMING CHARACTERISTICS
Maximum Data Rate (U)
1000
460
250
120
Kbps RL = 3KΩ, CL = 250pF, one driver active
RL = 3KΩ, CL = 1000pF, one driver active
RL = 3KΩ, CL = 1000pF, one driver active.
RL = 3KΩ, CL = 1000pF, one driver active
(H)
(B)
( - )
Receiver Propagation Delay
tPHL
tPLH
0.15
0.15
μs
Receiver input to Receiver output, CL = 150pF
Receiver Output Enable Time
Receiver Output Disable Time
200
200
ns
ns
ns
Normal operation
Normal operation
Driver Skew (E, EB)
100
500
100
| tPHL - tPLH
|
(EU)
50
Receiver Skew
Transition-Region Slew Rate (U)
50
90
ns
| tPHL - tPLH
|
V/μs VCC = 3.3V, RL = 3KΩ, TAMB = 25°C,
measurements taken from -3.0V to +3.0V or
+3.0V to -3.0V
(EB)
6
30
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
3
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 1000kbps data rate, all drivers
loaded with 3kΩ, 0.1μF charge pump capacitors, and TAMB = +25°C.
6
4
200
150
100
50
2
1Driver at 1Mbps
Other Drivers at 62.5Kbps
All Drivers Loaded with 3K // 250pF
0
-2
-4
-6
T1 at 500Kbps
T2 at 31.2Kbps
All TX loaded 3K // CLoad
0
2.7
3
3.5
4
4.5
5
0
250
500
1000
1500
2000
Supply Voltage (V)
Load Capacitance (pF)
Figure 1. Transmitter Skew VS. Load Capacitance
Figure 2. Transmitter Output Voltage VS. Supply
Voltage for the SP3243EU
40
35
30
6
TxOUT +
4
120Kbps
250Kbps
25
20
15
10
5
2
0
20Kbps
1 Transmitter at full Data Rate
2 Transmitters at 15.5 Kbps
All Transmitters loades 3K + Load Cap
-2
-4
-6
TxOUT -
0
0
1000
2000
3000
4000
5000
2.7
3
3.5
4
4.5
5
Load Capacitance (pF)
Supply Voltage (V
)
DC
Figure 3. Transmitter Output Voltage VS. Load
Capacitance for the SP3243EU
Figure 4. Supply Current VS. Load Capacitance for the
SP3243EU
25
20
15
6
TxOUT +
4
2
0
10
1 Transmitter at 250Kbps
2 Transmitters at 15.6Kbps
-2
5
All drivers loaded with 3K // 1000pF
-4
-6
TxOUT -
0
2.7
3
3.5
4
4.5
5
2.7
3
3.5
4
4.5
5
Supply Voltage (V
)
DC
Supply Voltage (V
)
DC
Figure 5. Supply Current VS. Supply Voltage for the
SP3243EU
Figure 6. Transmitter Output Voltage VS. Supply
Voltage for the SP3243EU
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
4
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 1000kbps data rate, all drivers
loaded with 3kΩ, 0.1μF charge pump capacitors, and TAMB = +25°C.
6
4
25
20
15
10
5
- Slew
+ Slew
TxOUT +
2
0
-2
-4
-6
1 Transmitter at 250Kbps
2 Transmitter at 15.6Kbps
All drivers loaded 3K + Load Cap
TxOUT -
0
0
500 1000
2000 3000 4000 5000
0
1000
2000
3000
4000
5000
Load Capacitance (pF)
Load Capacitance (pF)
Figure 7. Transmitter Output Voltage VS. Load
Capacitance
Figure 8. Slew Rate VS. Load Capacitance
40
35
30
25
20
15
10
5
25
20
15
120Kbps
250Kbps
20Kbps
10
1 Transmitter at 250Kbps
2 Transmitters at 15.6Kbps
All drivers loaded with 3K // 1000pF
1 Transmitter at full Data Rate
2 Transmitters at 15.5 Kbps
5
All Transmitters loades 3K + Load Cap
0
0
0
1000
2000
3000
4000
5000
2.7
3
3.5
4
4.5
5
Load Capacitance (pF)
Supply Voltage (V
)
DC
Figure 9. Supply Current VS. Load Capacitance
Figure 10. Supply Current VS. Supply Voltage
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
5
PIN NUMBER
SP3243EUCR
NAME
EN
FUNCTION
SP3243EU
MLPQ
Receiver Enable. Apply logic LOW for normal operation.
Apply logic HIGH to disable the receiver outputs (high-Z state).
-
-
C1+
V+
Positive terminal of the voltage doubler charge-pump capacitor.
Regulated +5.5V output generated by the charge pump.
Negative terminal of the voltage doubler charge-pump capacitor.
Positive terminal of the inverting charge-pump capacitor.
Negative terminal of the inverting charge-pump capacitor.
Regulated -5.5V output generated by the charge pump.
RS-232 receiver input.
28
27
24
1
28
26
22
29
31
32
2
C1-
C2+
C2-
2
V-
3
R1IN
4
R2IN
RS-232 receiver input.
5
3
R3IN
RS-232 receiver input.
6
4
R4IN
RS-232 receiver input.
7
5
R5IN
RS-232 receiver input.
8
6
R1OUT
R2OUT
R2OUT
R3OUT
R4OUT
R5OUT
STATUS
T1IN
TTL/CMOS receiver output.
19
18
20
17
16
15
21
14
13
12
23
17
16
18
15
14
13
19
12
11
10
21
TTL/CMOS receiver output.
Non-inverting receiver-2 output, active in shutdown.
TTL/CMOS receiver output.
TTL/CMOS receiver output.
TTL/CMOS receiver output.
TTL/CMOS Output indicating online and shutdown status.
TTL/CMOS driver input.
T2IN
TTL/CMOS driver input.
T3IN
TTL/CMOS driver input.
ONLINE
Apply logic HIGH to override Auto-Online circuitry keeping
drivers active (SHUTDOWN must also be logic HIGH,
refer to Table 2).
T1OUT
T2OUT
T3OUT
GND
RS-232 driver output.
RS-232 driver output.
RS-232 driver output.
Ground.
9
7
8
10
11
25
26
22
9
23
25
20
VCC
+3.0V to +5.5V supply voltage.
SHUTDOWN Apply logic LOW to shut down drivers and charge pump.
This overrides all AUTO ON-LINE® circuitry and ONLINE
(refer to Table 2).
NC
No Connection
-
1,24,27,30
Table 1. Device Pin Description
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
6
V
CC
+
+
26
0.1
μ
F
C5
C1
V
CC
28
27
3
C1+
V+
V-
+
+
0.1μ
F
C3
C4
0.1μF
24
1
C1-
C2+
SP3243
+
0.1μF
C2
0.1
μ
F
2
14
13
C2-
T1IN
T1OUT
T2OUT
T3OUT
9
T IN
2
10
11
RS-232
TTL/CMOS
INPUTS
OUTPUTS
T3IN
12
R2OUT
20
19
R1IN
R2IN
R3IN
R4IN
R5IN
R OUT
1
4
5
6
7
8
5KΩ
R2OUT
R3OUT
R4OUT
R5OUT
18
17
16
15
TTL/CMOS
OUTPUTS
5KΩ
RS-232
INPUTS
5KΩ
5KΩ
5KΩ
V
CC
22
23
SHUTDOWN
ONLINE
To μP Supervisor
Circuit
21
STATUS
GND
25
Figure 15. SP3243 Typical Operating Circuit
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
NC
R1IN
NC
GND
®
®
R2IN
C1-
R3IN
ONLINE
SHUTDOWN
STATUS
R2OUT
R1OUT
R4IN
R5IN
SP3243
T1OUT
T2OUT
Figure 13. SP3243 QFN Pinout Configuration
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
7
DESCRIPTION
AUTO ON-LINE® circuitry which reduces the
power supply drain to a 1μA supply current. In
many portable or hand-held applications, an RS-
232 cable can be disconnected or a connected
peripheral can be turned off. Under these condi-
tions, the internal charge pump and the drivers
will be shut down. Otherwise, the system auto-
matically comes online. This feature allows de-
sign engineers to address power saving concerns
without major design changes.
The SP3243transceivers meettheEIA/TIA-232
and ITU-T V.28/V.24 communication protocols
and can be implemented in battery-powered,
portable, or hand-held applications such as note-
book or palmtop computers. The SP3243 de-
vices feature Sipex's proprietary and patented
(U.S.-- 5,306,954) on-board charge pump cir-
cuitry that generates ±5.5V RS-232 voltage lev-
els from a single +3.0V to +5.5V power supply.
TheSP3243EUdevicescanoperateatadatarate
of 1000kbps fully loaded.
THEORY OF OPERATION
The SP3243 series is made up of four basic
circuit blocks:
1. Drivers
2. Receivers
3. the Sipex proprietary charge pump, and
4. AUTO ON-LINE® circuitry.
The SP3243 is a 3-driver/5-receiver device, ideal
for portable or hand-held applications. The
SP3243 includes one complementary
always-active receiver that can monitor an
external device (such as a modem) in shutdown.
This aids in protecting the UART or serial
controller IC by preventing forward biasing
of the protection diodes where VCC may be
disconnected.
Drivers
The drivers are inverting level transmitters that
convert TTL or CMOS logic levels to 5.0V EIA/
TIA-232 levels with an inverted sense relative to
the input logic levels. Typically, the RS-232
output voltage swing is +5.4V with no load and
+5V minimum fully loaded. The driver outputs
are protected against infinite short-circuits to
ground without degradation in reliability. These
drivers comply with the EIA-TIA-232-F and all
previous RS-232 versions. Unused drivers in-
puts should be connected to GND or VCC.
The SP3243 series is an ideal choice for power
sensitive designs. The SP3243 devices feature
V
CC
+
+
26
0.1μF
0.1μF
C5
C1
V
CC
28
27
3
C1+
V+
V-
+
+
C3
C4
0.1μF
0.1μF
24
1
C1-
C2+
SP3243
+
C2
0.1μF
2
14
13
C2-
T1IN
T1OUT
T2OUT
T3OUT
9
TxD
RTS
DTR
T
2IN
10
11
RS-232
OUTPUTS
Thedrivershaveaminimumdatarateof250kbps
(EB) or 1000kbps (EU) fully loaded.
T3IN
12
R2OUT
20
19
UART
or
R1IN
R
1OUT
4
5
RxD
CTS
5KΩ
Serial μC
R
2IN
R
2OUT
18
17
16
15
Figure 17 shows a loopback test circuit used to
test the RS-232 Drivers. Figure18 shows the test
resultswhereonedriverwasactiveat1Mbpsand
all three drivers loaded with an RS-232 receiver
in parallel with a 250pF capacitor. Figure 19
5KΩ
R3IN
R3OUT
R4OUT
DSR
DCD
6
7
8
RS-232
INPUTS
5KΩ
5KΩ
5KΩ
R
4IN
5IN
R
5OUT
R
RI
V
CC
22
23
SHUTDOWN
ONLINE
21
STATUS
GND
25
μP
Supervisor
IC
V
RESET
IN
Figure 16. Interface Circuitry Controlled by Micropro-
cessor Supervisory Circuit
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
8
+3V to +5V
DEVICE: SP3243EU
+
+
0.1μF
0.1μF
C5
C1
V
CC
C1+
SHUTDOWN
TXOUT
RXOUT
High Z
Active
R2OUT
Active
Active
V+
V-
+
+
C3
C4
0.1μF
0.1μF
C1-
C2+
SP3243
0
1
High Z
Active
+
C2
0.1μF
C2-
T1OUT
TXOUT
T1IN
TTL/CMOS
INPUTS
T
XIN
Table 2. SHUTDOWN Truth Tables
R1OUT
R1IN
Note: In AUTO ON-LINE® Mode where ONLINE =
GND and SHUTDOWN = VCC, the device will shut down
if there is no activity present at the Receiver inputs.
TTL/CMOS
OUTPUTS
5kΩ
R
XOUT
RXIN
5kΩ
1000pF
1000pF
V
CC
SHUTDOWN
ONLINE
STATUS
To μP Supervisor
Circuit
GND
Figure 17. Loopback Test Circuit for RS-232 Driver
Data Transmission Rates
showsthetestresultsoftheloopbackcircuitwith
all drivers active at 250kbps with typical
RS-232 loads in parallel with 1000pF capacitors. A
superiorRS-232datatransmissionrateof1Mbps
makes the SP3243EU an ideal match for high
speed LAN and personal computer peripheral
applications.
The receivers convert +5.0V EIA/TIA-232
levels to TTL or CMOS logic output levels.
ReceiversareactivewhentheAUTOON-LINE®
circuitry is enabled or when in shutdown.
Duringtheshutdown, thereceiverswillcontinue
to be active. If there is no activity present at the
receivers for a period longer than 100μs or when
SHUTDOWN is enabled, the device goes into a
standbymodewherethecircuitdraws1μA. The
Receivers
Figure 18. Loopback Test results at 1Mbps
Figure 19. Loopback Test results at 250Kbps
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
9
— VSS charge storage — During this phase of
the clock cycle, the positive side of capacitors
C1 and C2 are initially charged to VCC. Cl+ is
then switched to GND and the charge in C1– is
truth table logic of the SP3243 driver andreceiver
outputs can be found in Table 2.
The SP3243 includes an additional non-invert-
ingreceiverwithanoutputR2OUT. R2OUTisan
extra output that remains active and
monitors activity while the other receiver
outputs are forced into high impedance.
This allows Ring Indicator (RI) from a
peripheral to be monitored without forward
biasing the TTL/CMOS inputs of the other
devices connected to the receiver outputs.
–
+
transferred to C2 . Since C2 is connected to
CC, the voltage potential across capacitor C2 is
V
now 2 times VCC
.
Phase 2
— VSS transfer — Phase two of the clock
connects the negative terminal of C2 to the VSS
storage capacitor and the positive terminal of C2
to GND. This transfers a negative generated
voltage to C . This generated voltage is
4
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the voltage to
C4, the positive side of capacitor C1 is switched
to VCC and the negative side is connected to
GND.
Since receiver input is usually from a transmis-
sion line where long cable lengths and system
interference can degrade the signal, the inputs
haveatypicalhysteresismarginof300mV. This
ensures that the receiver is virtually immune to
noisy transmission lines. Should an input be left
unconnected, aninternal 5KΩpulldownresistor
to ground will commit the output of the receiver
to a HIGH state.
Phase 3
— VDD charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C1 produces –VCC in the negative
terminal of C1, which is applied to the negative
side of capacitor C2. Since C2 is at VCC, the
voltage potential across C2 is 2 times VCC
+
Charge Pump
.
The charge pump is a Sipex–patented design
(U.S. 5,306,954) and uses a unique approach
compared to older less–efficient designs. The
charge pump still requires four external
capacitors, but uses a four–phase voltage
shifting technique to attain symmetrical 5.5V
power supplies. The internal power supply con-
sists of a regulated dual charge pump that pro-
vides output voltages 5.5V regardless of the
input voltage (VCC) over the +3.0V to +5.5V
range. This is important to maintain compliant
RS-232 levels regardless of power supply
fluctuations.
Phase 4
— VDD transfer — The fourth phase of the clock
connects the negative terminal of C2 to GND,
and transfers this positive generated voltage
across C2 to C3, the VDD storage capacitor. This
voltage is regulated to +5.5V. At this voltage,
the internal oscillator is disabled. Simultaneous
with the transfer of the voltage to C3, the
positive side of capacitor C1 is switched to VCC
and the negative side is connected to GND,
allowing the charge pump cycle to begin again.
The charge pump cycle will continue as long as
the operational conditions for the internal
oscillator are present.
The charge pump operates in a discontinuous
mode using an internal oscillator. If the output
voltages are less than a magnitude of 5.5V, the
charge pump is enabled. If the output voltages
exceed a magnitude of 5.5V, the charge pump is
disabled. Thisoscillatorcontrolsthefourphases
of the voltage shifting. A description of each
phase follows.
Since both V+ and V– are separately generated
from VCC, in a no–load condition V+ and V– will
besymmetrical. Olderchargepumpapproaches
that generate V– from V+ will show a decrease in
the magnitude of V– compared to V+ due to the
inherent inefficiencies in the design. The clock
rate for the charge pump typically operates at
greater than 250kHz. The external capacitors
can be as low as 0.1μF with a 16V breakdown
voltage rating.
Phase 1
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
10
Minimum recommended charge pump capacitor value
Input Voltage VCC
Charge pump capacitor value for SP32XX
C1 – C4 = 0.1uF
3.0V to 3.6V
4.5V to 5.5V
3.0V to 5.5V
C1 = 0.047uF, C2-C4 = 0.33uF
C1 – C4 = 0.22uF
The Sipex-patented charge pumps are designed
to operate reliably with a range of low cost
capacitors. Either polarized or non polarized
capacitors may be used. If polarized capacitors
are used they should be oriented as shown in the
Typical Operating Circuit. The V+ capacitor
may be connected to either ground or Vcc.
reduces ripple on the transmitter outputs and
may slightly reduce power consumption. C2,
C3, and C4 can be increased without changing
C1’s value.
Forbestchargepumpefficiencylocatethecharge
pump and bypass capacitors as close as possible
to the IC. Surface mount capacitors are best for
this purpose. Using capacitors with lower
equivalent series resistance (ESR) and self-
inductance,alongwithminimizingparasiticPCB
trace inductance will optimize charge pump
operation. Designersarealsoadvisedtoconsider
that capacitor values may shift over time and
operating temperature.
Thechargepumpoperateswith0.1μFcapacitors
for 3.3V operation. For other supply voltages,
see the table for required capacitor values. Do
notusevaluessmallerthanthoselisted.Increasing
the capacitor values (e.g., by doubling in value)
AUTO ONLINE CIRCUITRY
TheSP3243deviceshaveapatentpendingAUTO
ON-LINE® circuitry on board that saves power
inapplicationssuchaslaptopcomputers, palmtop
(PDA) computers and other portable systems.
input typically sees at least +3V, which are
generated from the transmitters at the other end
of the cable with a +5V minimum. When the
external transmitters are disabled or the cable is
disconnected, the receiver inputs will be pulled
down by their internal 5kΩ resistors to ground.
When this occurs over a period of time, the
internal transmitters will be disabled and the
device goes into a shutdown or standy mode.
WhenONLINEisHIGH, theAUTOON-LINE®
mode is disabled.
The SP3243 devices incorporate an AUTO ON-
LINE® circuit that automatically enables itself
when the external transmitters are enabled and
the cable is connected. Conversely, the AUTO
ON-LINE® circuit also disables most of the
internal circuitry when the device is not being
used and goes into a standby mode where the
device typically draws 1mA. This function can
also be externally controlled by the ONLINE
pin. When this pin is tied to a logic LOW, the
AUTO ON-LINE® function is active. Once ac-
tive, the device is enabled until there is no
activity on the receiver inputs. The receiver
The AUTO ON-LINE® circuit has two stages:
1) Inactive Detection
2) Accumulated Delay
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
11
S
H
U
T
+2.7V
0V
RECEIVER
RS-232 INPUT
VOLTAGES
D
O
W
N
-2.7V
VCC
STATUS
0V
t
STSL
t
STSH
t
ONLINE
+5V
DRIVER
RS-232 OUTPUT
VOLTAGES
0V
-5V
Figure 20. AUTO ON-LINE® Timing Waveforms
The AUTO ON-LINE® mode can be disabled by
theSHUTDOWNpin. IfthispinisalogicLOW,
the AUTO ON-LINE® function will not operate
regardless of the logic state of the ONLINE pin.
Table 3 summarizes the logic of the AUTO ON-
LINE® operating modes. The truth table logic of
the SP3243 driver and receiver outputs can be
found in Table 2.
The first stage, shown in Figure 28, detects an
inactive input. A logic HIGH is asserted on
RXINACT if the cable is disconnected or the
external transmitters are disabled. Otherwise,
RXINACT will be at a logic LOW. This circuit is
duplicated for each of the other receivers.
The second stage of the AUTO ON-LINE® cir-
cuitry, shown in Figure 29, processes all the
receiver's RXINACT signals with an accumu-
lated delay that disables the device to a 1μA
supply current.
The STATUS pin outputs a logic LOW signal
if the device is shutdown. This pin goes to a
logic HIGH when the external transmitters are
enabled and the cable is connected.
The STATUS pin goes to a logic LOW when the
cable is disconnected, the external transmitters
are disabled, or the SHUTDOWN pin is
invoked.Thetypicalaccumulateddelayisaround
20μs.
When the SP3243 devices are shut down, the
charge pumps are turned off. V+ charge pump
output decays to VCC, the V- output decays to
GND. The decay time will depend on the size of
capacitors used for the charge pump. Once in
shutdown, the time required to exit the shut
down state and have valid V+ and V- levels is
typically 200μs.
When the SP3243 drivers or internal charge
pump are disabled, the supply current is reduced
to 1μA. This can commonly occur in hand-held
or portable applications where the RS-232 cable
is disconnected or the RS-232 drivers of the
connected peripheral are turned off.
For easy programming, the STATUS can be
used to indicate DSR or a Ring Indicator signal.
Tying ONLINE and SHUTDOWN together
will bypass the AUTO ON-LINE® circuitry so
this connection acts like a shutdown input pin.
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
12
V
= +5V
CC
C
+5V
3
+
–
+
V
V
Storage Capacitor
Storage Capacitor
DD
+
–
+
–
C
C
2
1
–
SS
C
–5V
–5V
4
Figure 21. Charge Pump — Phase 1
V
= +5V
CC
C
3
+
–
V
Storage Capacitor
Storage Capacitor
DD
SS
+
+
C
C
2
1
–
–
+
–
V
C
–5.5V
4
Figure 22. Charge Pump — Phase 2
[
T
]
+6V
a) C2+
1
T
T
0V
0V
2
2
b) C -
2
-6V
Ch1 2.00V Ch2 2.00V M 1.00μs Ch1 1.96V
Figure 23. Charge Pump Waveforms
V
= +5V
CC
C
+5V
3
+
–
+
V
V
Storage Capacitor
Storage Capacitor
DD
+
–
+
–
C
C
2
1
–
SS
C
–5V
–5V
4
Figure 24. Charge Pump — Phase 3
V
= +5V
CC
C
+5.5V
3
+
–
+
V
Storage Capacitor
Storage Capacitor
DD
SS
+
–
+
–
C
C
2
1
–
V
C
4
Figure 25. Charge Pump — Phase 4
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
13
The SP3243 driver outputs are able to maintain
voltage under loading of up to 2.5mA per driver,
ensuring sufficient output for mouse-driving ap-
plications.
6
4
Vout+
Vout-
2
0
+
-
V
OUT
0
0
-2
-4
-6
Load Current Per Transmitter [mA]
1
V
OUT
Figure 26. SP3243 Driver Output Voltages vs. Load
Current per Transmitter
V
CC
+
26
0.1μF
0.1μF
C5
C1
V
CC
28
27
3
C1+
V+
+
+
+
+
C3
C4
0.1μF
0.1μF
24
1
C1-
SP3243
C2+
V-
C2
0.1μF
2
14
13
C2-
T1IN
T1OUT
T2OUT
T3OUT
9
T IN
2
10
11
T3IN
12
R2OUT
20
19
R1IN
R2IN
R3IN
R4IN
R5IN
R OUT
1
4
5
5KΩ
5KΩ
R2OUT
R3OUT
R4OUT
R5OUT
18
17
16
15
6
7
8
5KΩ
5KΩ
5KΩ
DB-9
Connector
V
CC
22
23
SHUTDOWN
ONLINE
1
2
3
4
5
6
To μP Supervisor
21
STATUS
Circuit
GND
25
7
8
9
DB-9 Connector Pins:
1. Received Line Signal Detector
2. Received Data
6. DCE Ready
7. Request to Send
8. Clear to Send
9. Ring Indicator
3. Transmitted Data
4. Data Terminal Ready
5. Signal Ground (Common)
Figure 27. Circuit for the connectivity of the SP3243 with a DB-9 connector
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
14
RS-232 SIGNAL
AT RECEIVER
INPUT
SHUTDOWN
INPUT
TRANSCEIVER
STATUS
ONLINE INPUT
STATUS OUTPUT
Normal Operation
LOW
YES
NO
HIGH
HIGH
HIGH
LOW
(Auto-Online)
Normal Operation
HIGH
LOW
Shutdown
NO
HIGH
LOW
(Auto-Online)
HIGH / LOW
Shutdown
Shutdown
YES
NO
LOW
LOW
HIGH
LOW
HIGH / LOW
Table 3. AUTO ON-LINE® Logic
R INACT
X
Inactive Detection Block
RS-232
Receiver Block
R OUT
X
R IN
X
Figure 28. Stage I of AUTO ON-LINE® Circuitry
Delay
Stage
Delay
Stage
Delay
Stage
Delay
Stage
Delay
Stage
STATUS
R1INACT
R4INACT
R5INACT
R2INACT
R3INACT
SHUTDOWN
Figure 29. Stage II of AUTO ON-LINE® Circuitry
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
15
normal usage. The transceiver IC receives most
of the ESD current when the ESD source is
applied to the connector pins. The test circuit for
IEC1000-4-2 is shown on Figure 31. There are
two methods within IEC1000-4-2, the Air
Discharge method and the Contact Discharge
method.
ESD TOLERANCE
TheSP3243seriesincorporatesruggedizedESD
cells on all driver output and receiver input pins.
The ESD structure is improved over our previ-
ous family for more rugged applications and
environments sensitive to electro-static dis-
chargesandassociatedtransients.Theimproved
ESDtoleranceisatleast+15kVwithoutdamage
nor latch-up.
With the Air Discharge Method, an ESD voltage
is applied to the equipment under test (EUT)
throughair. Thissimulatesanelectricallycharged
person ready to connect a cable onto the rear of
the system only to find an unpleasant zap just
before the person touches the back panel. The
high energy potential on the person discharges
through an arcing path to the rear panel of the
system before he or she even touches the system.
This energy, whether discharged directly or
through air, is predominantly a function of the
discharge current rather than the discharge
voltage. Variables with an air discharge such as
approach speed of the object carrying the ESD
potential to the system and humidity will tend to
change the discharge current. For example, the
rise time of the discharge current varies with the
approach speed.
There are different methods of ESD testing
applied:
a) MIL-STD-883, Method 3015.7
b) IEC1000-4-2 Air-Discharge
c) IEC1000-4-2 Direct Contact
The Human Body Model has been the generally
accepted ESD testing method for semi-
conductors. This method is also specified in
MIL-STD-883, Method 3015.7 for ESD testing.
The premise of this ESD test is to simulate the
human body’s potential to store electro-static
energy and discharge it to an integrated circuit.
The simulation is performed by using a test
model as shown in Figure 30. This method will
test the IC’s capability to withstand an ESD
transient during normal handling such as in
manufacturing areas where the ICs tend to be
handled frequently.
The Contact Discharge Method applies the ESD
current directly to the EUT. This method was
devised to reduce the unpredictability of the
ESD arc. The discharge current rise time is
constant since the energy is directly transferred
without the air-gap arc. In situations such as
handheldsystems,theESDchargecanbedirectly
dischargedtotheequipmentfromapersonalready
holdingtheequipment. Thecurrentistransferred
ontothekeypadortheserialportoftheequipment
directly andthentravelsthroughthePCBandfinally
to the IC.
The IEC-1000-4-2, formerly IEC801-2, is
generallyusedfortestingESDonequipmentand
systems. For system manufacturers, they must
guarantee a certain amount of ESD protection
since the system itself is exposed to the outside
environment and human presence. The premise
with IEC1000-4-2 is that the system is required
to withstand an amount of static electricity when
ESD is applied to points and surfaces of the
equipmentthatareaccessibletopersonnelduring
R
R
S
S
R
R
C
C
SW2
SW2
SW1
SW1
Device
Under
Test
DC Power
Source
C
C
S
S
Figure 30. ESD Test Circuit for Human Body Model
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
16
CCoonnttaacctt--DDiisscchhaarrggee MMoodduullee
R
R
S
S
R
R
V
V
R
R
C
C
SW2
SW2
SW1
SW1
Device
Under
Test
DC Power
Source
C
C
S
S
R
R
and R add up to 330Ω for IEC1000-4-2.
and R add up to 330Ω for IEC1000-4-2.
S
S
V
V
Figure 31. ESD Test Circuit for IEC1000-4-2
ThecircuitmodelsinFigures30and31represent
the typical ESD testing circuit used for all three
methods. TheCS isinitiallychargedwiththeDC
power supply when the first switch (SW1) is on.
Now that the capacitor is charged, the second
switch(SW2)isonwhileSW1switchesoff. The
voltage stored in the capacitor is then applied
throughRS, thecurrentlimitingresistor, ontothe
device under test (DUT). In ESD tests, the SW2
switch is pulsed so that the device under test
receives a duration of voltage.
30A
15A
0A
FortheHumanBodyModel, thecurrentlimiting
resistor (R ) and the source capacitor (C ) are
1.5kΩ an 1S00pF, respectively. For IEC-10S00-4-
2,thecurrentlimitingresistor(RS)andthesource
capacitor (CS) are 330Ω an 150pF, respectively.
t=0ns
t=30ns
t ➙
Figure 32. ESD Test Waveform for IEC1000-4-2
The higher C value and lower RS value in the
IEC1000-4-2Smodel are more stringent than the
HumanBodyModel. Thelargerstoragecapacitor
injects a higher voltage to the test point when
SW2 is switched on. The lower current limiting
resistor increases the current charge onto the test
point.
DEVICE PIN
TESTED
HUMAN BODY
MODEL
IEC1000-4-2
Air Discharge Direct Contact
Level
Driver Outputs
Receiver Inputs
+15kV
+15kV
+15kV
+15kV
+8kV
+8kV
4
4
Table 4. Transceiver ESD Tolerance Levels
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
17
PACKAGE: PLASTIC
SMALL OUTLINE (SOIC)
(WIDE)
E
H
D
A
Ø
A1
L
e
B
DIMENSIONS (Inches)
Minimum/Maximum
(mm)
28–PIN
A
A1
B
D
E
0.090/0.104
(2.29/2.649)
0.004/0.012
(0.102/0.300)
0.013/0.020
(0.330/0.508)
0.697/0.713
(17.70/18.09)
0.291/0.299
(7.402/7.600)
e
0.050 BSC
(1.270 BSC)
H
L
0.394/0.419
(10.00/10.64)
0.016/0.050
(0.406/1.270)
Ø
0°/8°
(0°/8°)
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
18
PACKAGE: 32 PIN QFN
D
E
4X
Ø
º
A2
A3
A
SEATING PLANE
A1
D2
NX K
NX L
32 PIN QFN
JEDECMO220
(VHHD-4)
Dimensions in
(mm)
MIN NOM MAX
0.80 0.90 1.00
A
A1
A2
0
0.02 0.05
0.65 1.00
0.20 REF
5.00 BSC
0
E2
A3
D
E
e
5.00 BSC
0.50 BSC
NX K
b
0.18
0º
0.25 0.30
Ø
-
14º
e
NX b
3.50
3.65 3.80
D2
E2
L
3.50 3.65 3.80
0.35 0.40 0.45
K
N
ND
NE
0.20
-
32
8
-
8
32 PIN QFN
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
19
PACKAGE: 28 PIN SSOP
D
N
SEE DETAIL “A”
E
E1
1
2
INDEX AREA
D
2
E1
e
x
2
2 NX R R1
A
Gauge Plane
Seaing Plane
A
L
Ø
L1
DETAIL A
28 Pin SSOP JEDEC MO-150 (AH) Variation
MIN
-
NOM
MAX
2
-
1.85
0.38
0.25
10.5
8.2
5.6
0.95
SYMBOL
A
A1
A2
b
c
D
E
E1
L
L1
ø
-
-
A2
A
0.05
1.65
0.22
0.09
9.9
7.4
5
Seating Plane
1.75
-
-
10.2
7.8
5.3
0.75
1.25 REF
4º
A1
b
0.55
WITH LEAD FINISH
0º
8º
e
0.65 BSC
Note: Dimensions in (mm)
c
BASE METAL
b
Section A-A
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
20
PACKAGE: 28 PIN TSSOP
D
e
Ø2
E
E1
Seaing Plane
L
Ø3
Ø1
L1
DETAIL A
1
2
INDEX AREA
D
2
E1
x
2
SEE DETAIL “A”
A2
A
Seating Plane
A1
b
B
B
28 Pin TSSOP JEDEC MO-153 (AE)
Variation
MIN
-
0.05
0.8
0.19
0.09
9.6
NOM
MAX
1.2
0.15
1.05
0.3
SYMBOL
A
A1
A2
b
c
D
-
-
1
-
-
9.7
b
0.2
9.8
e
E
E1
L
0.65 BSC
6.40 BSC
4.4
C
4.3
0.45
4.5
0.75
0.6
L1
Ø1
Ø2
Ø3
1.00 REF
-
12º REF
12º REF
Section B-B
0º
8º
Note: Dimensions in (mm)
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
21
PRODUCT NOMENCLATURE
SP 3243 E U EY L /TR
Tape and Reel options
Sipex
“L” suffix indicates Lead Free packaging
Package Type A= SSOP
P= PDIP
Y=TSSOP
Part Number
Temperature Range C= Commercial Range 0ºC to 70ºC
E= Extended Range -40ºC to 85ºC
Speed Indicator Blank= 120Kbps
B= 250Kbps
H= 450Kbps
U= 1Mbps
ESD Rating E= 15kV HBM and IEC 1000-4
Sipex Corporation
Headquarters and
Sales Office
Corporation
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Solved by Sipex
TM
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
22
ORDERING INFORMATION
Part Number
SP3243EBCA
SP3243EBCA/TR
SP3243EBCR
SP3243EBCR/TR
SP3243EBCT
SP3243EBCT/TR
SP3243EBCY
SP3243EBCY/TR
SP3243EBEA
SP3243EBEA/TR
SP3243EBET
SP3243EBET/TR
SP3243EBEY
SP3243EBEY/TR
SP3243ECA
SP3243ECA/TR
SP3243ECT
Speed (kbps)
250
Temp Range
Package
28 Pin SSOP
-0 to 70C
-0 to 70C
-0 to 70C
-0 to 70C
-0 to 70C
-0 to 70C
-0 to 70C
-0 to 70C
-40 to 85C
-40 to 85C
-40 to 85C
-40 to 85C
-40 to 85C
-40 to 85C
-0 to 70C
-0 to 70C
-0 to 70C
-0 to 70C
-0 to 70C
-0 to 70C
-40 to 85C
-40 to 85C
-40 to 85C
-40 to 85C
-40 to 85C
-40 to 85C
-0 to 70C
-0 to 70C
-0 to 70C
-0 to 70C
-0 to 70C
-0 to 70C
-0 to 70C
-0 to 70C
-40 to 85C
-40 to 85C
-40 to 85C
-40 to 85C
-40 to 85C
-40 to 85C
-40 to 85C
-40 to 85C
250
250
250
250
250
250
250
250
250
250
250
250
250
120
120
120
120
120
120
120
120
120
120
120
28 Pin SSOP
32 Pin QFN: see Note 2
32 Pin QFN: see Note 2
28 Pin WSOIC
28 Pin WSOIC
28 Pin TSSOP
28 Pin TSSOP
28 Pin SSOP
28 Pin SSOP
28 Pin WSOIC
28 Pin WSOIC
28 Pin TSSOP
28 Pin TSSOP
28 Pin SSOP
28 Pin SSOP
28 Pin WSOIC
28 Pin WSOIC
28 Pin TSSOP
28 Pin TSSOP
28 Pin SSOP
SP3243ECT/TR
SP3243ECY
SP3243ECY/TR
SP3243EEA
SP3243EEA/TR
SP3243EET
28 Pin SSOP
28 Pin WSOIC
28 Pin WSOIC
28 Pin TSSOP
28 Pin TSSOP
28 Pin SSOP
SP3243EET/TR
SP3243EEY
SP3243EEY/TR
SP3243EUCA
SP3243EUCA/TR
SP3243EUCR
SP3243EUCR/TR
SP3243EUCT
SP3243EUCT/TR
SP3243EUCY
SP3243EUCY/TR
SP3243EUEA
SP3243EUEA/TR
SP3243EUER
SP3243EUER/TR
SP3243EUET
120
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
28 Pin SSOP
32 Pin QFN: see Note 2
32 Pin QFN: see Note 2
28 Pin WSOIC
28 Pin WSOIC
28 Pin TSSOP
28 Pin TSSOP
28 Pin SSOP
28 Pin SSOP
32 Pin QFN: see Note 2
32 Pin QFN: see Note 2
28 Pin WSOIC
28 Pin WSOIC
28 Pin TSSOP
28 Pin TSSOP
SP3243EUET/TR
SP3243EUEY
SP3243EUEY/TR
Available in lead free packaging. To order add “-L” suffix to part number.
Example: SP3243EUEA/TR = standard; SP3243EUEA-L/TR = lead free
/TR = Tape and Reel. Pack quantity is 1,500 for SSOP, TSSOP and WSOIC.
Note 2: Not recommended for New Designs in QFN Package. See Factory for Availability.
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
23
ORDERING INFORMATION
Contact factory for availability of the following legacy part numbers. For long term availability
Sipexrecommendsupgradesaslistedbelow. Allupgradepartnumbersshownarefullypinout
and function compatible with legacy part numbers. Upgrade part numbers may contain
feature and/or performance enhancements or other changes to datasheet parameters.
Legacy Part Number Recommended Upgrade
Legacy Part Number Recommended Upgrade
SP3243BCA
SP3243EBCA
SP3243EHCA
SP3243EHCA/TR
SP3243EHCT
SP3243EUCA
SP3243BCA/TR
SP3243BCA-L
SP3243BCA-L/TR
SP3243BCR
SP3243EBCA/TR
SP3243EBCA-L
SP3243EBCA-L/TR
SP3243EBCR
SP3243EUCA/TR
SP3243EUCT
SP3243EHCT/TR
SP3243HCA
SP3243EUCT/TR
SP3243EUCA
SP3243BCR/TR
SP3243BCR-L
SP3243BCR-L/TR
SP3243BCT
SP3243EBCR/TR
SP3243EBCR-L
SP3243EBCR-L/TR
SP3243EBCT
SP3243HCA/TR
SP3243HCA-L
SP3243HCA-L/TR
SP3243HCT
SP3243EUCA/TR
SP3243EUCA-L
SP3243EUCA-L/TR
SP3243EUCT
SP3243BCT/TR
SP3243BCT-L
SP3243BCT-L/TR
SP3243BCY
SP3243EBCT/TR
SP3243EBCT-L
SP3243EBCT-L/TR
SP3243EBCY
SP3243HCT/TR
SP3243HCT-L
SP3243HCT-L/TR
SP3243UCA
SP3243EUCT/TR
SP3243EUCT-L
SP3243EUCT-L/TR
SP3243EUCA
SP3243BCY/TR
SP3243BCY-L
SP3243BCY-L/TR
SP3243BEA
SP3243EBCY/TR
SP3243EBCY-L
SP3243EBCY-L/TR
SP3243EBEA
SP3243UCA/TR
SP3243UCA-L
SP3243UCA-L/TR
SP3243UCR
SP3243EUCA/TR
SP3243EUCA-L
SP3243EUCA-L/TR
SP3243EUCR
SP3243BEA/TR
SP3243BEA-L
SP3243BEA-L/TR
SP3243BET
SP3243EBEA/TR
SP3243EBEA-L
SP3243EBEA-L/TR
SP3243EBET
SP3243UCR/TR
SP3243UCR-L
SP3243UCR-L/TR
SP3243UCT
SP3243EUCR/TR
SP3243EUCR-L
SP3243EUCR-L/TR
SP3243EUCT
SP3243BET/TR
SP3243BET-L
SP3243BET-L/TR
SP3243BEY
SP3243EBET/TR
SP3243EBET-L
SP3243EBET-L/TR
SP3243EBEY
SP3243UCT/TR
SP3243UCT-L
SP3243UCT-L/TR
SP3243UCY
SP3243EUCT/TR
SP3243EUCT-L
SP3243EUCT-L/TR
SP3243EUCY
SP3243BEY/TR
SP3243BEY-L
SP3243BEY-L/TR
SP3243CA
SP3243EBEY/TR
SP3243EBEY-L
SP3243EBEY-L/TR
SP3243ECA
SP3243UCY/TR
SP3243UCY-L
SP3243UCY-L/TR
SP3243UEA
SP3243EUCY/TR
SP3243EUCY-L
SP3243EUCY-L/TR
SP3243EUEA
SP3243CA/TR
SP3243CA-L
SP3243ECA/TR
SP3243ECA-L
SP3243UEA/TR
SP3243UEA-L
SP3243UEA-L/TR
SP3243UER
SP3243EUEA/TR
SP3243EUEA-L
SP3243EUEA-L/TR
SP3243EUER
SP3243CA-L/TR
SP3243CT
SP3243ECA-L/TR
SP3243ECT
SP3243CT/TR
SP3243CT-L
SP3243ECT/TR
SP3243ECT-L
SP3243UER/TR
SP3243UER-L
SP3243UER-L/TR
SP3243UET
SP3243EUER/TR
SP3243EUER-L
SP3243EUER-L/TR
SP3243EUET
SP3243CT-L/TR
SP3243EA
SP3243ECT-L/TR
SP3243EEA
SP3243EA/TR
SP3243EA-L
SP3243EEA/TR
SP3243EEA-L
SP3243UET/TR
SP3243UET-L
SP3243UET-L/TR
SP3243UEY
SP3243EUET/TR
SP3243EUET-L
SP3243EUET-L/TR
SP3243EUEY
SP3243EA-L/TR
SP3243ET
SP3243EEA-L/TR
SP3243EET
SP3243ET/TR
SP3243ET-L
SP3243EET/TR
SP3243EET-L
SP3243UEY/TR
SP3243UEY-L
SP3243UEY-L/TR
SP3243EUEY/TR
SP3243EUEY-L
SP3243EUEY-L/TR
SP3243ET-L/TR
SP3243EET-L/TR
Date: 2/05/06
SP3243 +3.0V to +5.5V RS-232 Transceivers
© Copyright 2006 Sipex Corporation
24
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