SP6137 [EXAR]

Wide Input, 900kHz Synchronous PWM Step Down Controller; 宽输入， 900kHz的PWM同步降压控制器


型号：	SP6137
厂家：	EXAR CORPORATION
描述：	Wide Input, 900kHz Synchronous PWM Step Down Controller 宽输入， 900kHz的PWM同步降压控制器二极管控制器局域网
文件：	总15页 (文件大小：707K)
中文：	中文翻译
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SP6137

Wide Input, 900kHz Synchronous PWM Step Down

Controller

January 2009

Rev. 2.0.0

GENERAL DESCRIPTION

APPLICATIONS

The SP6137 is a 900kHz constant frequency,

voltage mode, synchronous PWM step down

controller optimized for high efficiency.

• 12V DPA

• Communications Systems

• Graphics Cards

The SP6137 is adequately suited for split plane

applications utilizing a low power 5V rail to

power the controller circuitry, minimizing

power dissipation. Its wide input voltage range

of 3V to 15V allows for conversions from the

standard 3.3V, 5V, 9.6V and 12V power rails

to an output voltage adjustable down to 0.8V.

Developed around a wide bandwidth internal

amplifier, the SP6137 can accommodate type

II and type III compensation schemes.

FEATURES

• 2.5V to 20V Step Down Achieved Using

Dual Input

• On-Board 1.5Ω sink (2Ω source) NFET

Drivers

• Up to 10A Output Capability

• UVLO Detects Both VCC and VIN

Protection features include a programmable

UVLO, thermal shutdown and output short

circuit protection.

• Short-Circuit Protection with Auto-

Restart

The SP6137 is part of a larger family of step

• Supports Type II or III Compensation

• Programmable Soft Start

down

controllers

operating

various

switching frequencies up to 1300kHz and input

voltages up to 28V. Refer to Exar’s SP6132,

SP6132H, SP6134, SP6134H and SP6139 for

complete details.

• Fast Transient Response

• High Efficiency: Greater than 94%

• Non-synchronous Start-Up

• Small 10-Pin MSOP Package

• U.S. Patent #6,922,041

The SP6137 is available in lead free, RoHS

compliant,

space

saving

10-pin

MSOP

package.

TYPICAL APPLICATION DIAGRAM

2.5V -20V

22μF

7 6 5

16V

= 5V @ 30mA

FDS6676S

14.5A, 6mΩ

GND

C1, C2

RLF

3.0,5%

2 3

Ceramic

1210

X5R

CBST

0.1μF

DBST

OUT

≤

MBR0530

L1 SC5018-2R7M

2.7μH @ 12A

DCR=4.30mΩ

3.3V @ 10A

RZ3

7 6 5

Bead

VCC

BST

4.64k, 1%

SP6137

C_VCC

10μF

GND 3

47μF

GND

VFB

COMP

SWN

68.1k, 1%

6.3V

CZ3

220pF

221k, 1%

6.3V

0.8V

2 3

UVIN

FDS6676S

14.5A, 6.0mΩ

C_VCC

CSS

47nF

GND2

Ceramic

8050

CZ2

RZ2

820pF 40.2k, 1%

CP1

100k, 1%

21.5k, 1%

X5R

C3, C4

Ceramic

1210

CF1

100pF

56pF

X5R

Fig. 1: SP6137 Application Diagram

Exar Corporation

48720 Kato Road, Fremont CA 94538, USA

www.exar.com

Tel. +1 510 668-7000 – Fax. +1 510 668-7001

SP6137

Wide Input, 900kHz Synchronous PWM Step Down

Controller

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of

the device at these ratings or any other above those

indicated in the operation sections of the specifications

below is not implied. Exposure to absolute maximum

rating conditions for extended periods of time may affect

reliability.

GH, GL peak output current <10us..............................2A

Storage Temperature ..............................-65°C to 150°C

Power Dissipation.................................Internally Limited

ESD Rating BST Pin (HBM - Human Body Model)...... 1.5kV

ESD Rating All Other Pins (HBM)...............................2kV

Thermal Resistance θ_JA....................................41.9°C/W

Operating Voltage Range ..............................2.5V to 20V

V_cc.......................................................................... 7V

BST ...................................................................... 27V

BST-SWN ......................................................-0.3 to 7V

SWN............................................................-1V to 20V

GH................................................... -0.3V to BST+0.3V

GH-SWN.................................................................. 7V

All other pins ..................................... -0.3V to V_CC+0.3V

ELECTRICAL SPECIFICATIONS

Specifications with standard type are for an Operating Junction Temperature of T_J= 25°C only; limits applying over the full

Operating Junction Temperature range are denoted by a “•”. Minimum and Maximum limits are guaranteed through test,

design, or statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for

reference purposes only. Unless otherwise indicated, V_cc= 4.5V to 5.5V, BST= V_cc, SWN=GND=0V, UVIN=3V, CV_cc= 10µF,

_COMP=0.1uF, CGH=CGL=3.3nF, C_SS=50nF, T_A= –40°C to 85°C (SP6137EU) or T_A= –0°C to 70°C (SP6137CU)..

Parameter

V_CCSupply Current

Min.

Typ.

Max.

Units

Conditions

1.5

0.2

VFB =0.9V (No switching)

BST Supply Current

V_CCUVLO Start Threshold

V_CCUVLO Hysteresis

UVIN Start Threshold

UVIN Hysteresis

0.4

4.50

300

2.65

390

•

4.00

100

2.30

260

4.25

200

2.50

300

•

UVIN Input Current

UVIN=3.0V

2X Gain Config., Measure VFB, V_CC=5V,

T=25°C

Error Amplifier Reference

0.792

0.788

0.800

0.808

0.812

Error Amplifier Reference

Over Line and Temperature

•

Error Amplifier

Transconductance

Error Amplifier Gain

COMP Sink Current

COMP Source Current

VFB Input Bias Current

Internal Pole

150

No Load

VFB=0.9V, COMP=0.9V

VFB=0.7V, COMP=2.2V

VFB=0.8V

200

•

MHz

COMP Clamp

2.5

-2

VFB=0.7V, TA = 25°C

COMP Clamp Temp. Coefficient

Ramp Amplitude

mV/°C

0.92

1.10

1.28

180

TA = 25°C, RAMP COMP until GH starts

switching

RAMP Offset

1.1

RAMP Offset Temp. Coefficient

GH Minimum Pulse Width

-2

mV/°C

•

Maximum Duty Ratio Measured just

before pulse skipping begins

Maximum Controllable Duty

Ratio

Maximum Duty Ratio

Internal Oscillator Frequency

SS Charge Current:

100

760

kHz

Valid for 20 Cycles

900

1040

•

2/15

Rev. 2.0.0

SP6137

Wide Input, 900kHz Synchronous PWM Step Down

Controller

Parameter

Min.

Typ.

Max.

Units

Conditions

SS Discharge Current:

Short Circuit Threshold Voltage

Hiccup Timeout

•

Fault Present, SS = 0.2V

Measured VREF (0.8V) - VFB

VFB = 0.5V

0.20

0.25

0.30

Number of Allowable Clock

Cycles at 100% Duty Cycle

Cycles

Cycle

VFB = 0.7V

Minimum GL Pulse After 20

Cycles

0.5

Thermal Shutdown Temperature

Thermal Hysteresis

145

°C

Ω

GH & GL Rise Times

•

Measured 10% to 90%

GH & GL Fall Times

Measured 90% to 10%

GL to GH Non Overlap Time

SWN to GL Non Overlap Time

GH & GL Pull Down Resistance

Driver Pull Down Resistance

Driver Pull Up Resistance

GH & GL Measured at 2.0V

Measured SWN = 100mV to GL = 2.0V

1.5

2.5

Ω

BLOCK DIAGRAM

Fig. 2:SP6137 Block Diagram

3/15

Rev. 2.0.0

SP6137

Wide Input, 900kHz Synchronous PWM Step Down

Controller

PIN ASSIGNEMENT

Fig. 3: SP6137 Pin Assignment

PIN DESCRIPTION

Name

Pin Number

Description

Bias Supply Input. Connect to external 5V supply. Used to power internal circuits and

low side gate driver.

V_CC

High current driver output for the low side NFET switch. It is always low if GH is high or

during a fault. Resistor pull down ensure low state at low voltage.

Ground Pin. The control circuitry of the IC and lower power driver are referenced to this

pin. Return separately from other ground traces to the (-) terminal of COUT.

GND

Feedback Voltage and Short Circuit Detection pin. It is the inverting input of the Error

Amplifier and serves as the output voltage feedback point for the Buck Converter. The

output voltage is sensed and can be adjusted through an external resistor divider.

Whenever VFB drops 0.25V below the positive reference, a short circuit fault is detected

and the IC enters hiccup mode.

VFB

Output of the Error Amplifier. It is internally connected to the inverting input of the

PWM comparator. An optimal filter combination is chosen and connected to this pin and

either ground or VFB to stabilize the voltage mode loop.

COMP

UVIN

UVLO input for VIN voltage. Connect a resistor divider between VIN and UVIN to set

minimum operating voltage.

Soft Start. Connect an external capacitor between SS and GND to set the soft start rate

based on the 10μA source current. The SS pin is held low via a 1mA (min) current

during all fault conditions.

Lower supply rail for the GH high-side gate driver. Connect this pin to the switching

node at the junction between the two external power MOSFET transistors.

SWN

High current driver output for the high side NFET switch. It is always low if GL is high or

during a fault. Resistor pull down ensure low state at low voltage.

High side driver supply pin. Connect BST to the external boost diode and capacitor as

shown in the Typical Application Circuit on page 1. High side driver is connected

between BST pin and SWN pin.

BST

4/15

Rev. 2.0.0

SP6137

Wide Input, 900kHz Synchronous PWM Step Down

Controller

ORDERING INFORMATION

Temperature

Part Number

Packing

Quantity

Marking

Package

Note 1

Note 2

Range

SP6137CU

CXXX

SP6137CU-L

SP6137CU-L/TR

SP6137EU-L

0°C≤T_A≤+70°C

-40°C≤T_A≤+85°C

10 Pin MSOP

Bulk

Lead free

YWW

SP6137CU

CXXX

10 Pin MSOP

Tape & Reel

Bulk

Lead free

YWW

SP6137EU

EXXX

YWW

SP6137EU

EXXX

SP6137EU-L/TR

SP6137LEDEB

Tape & Reel

YWW

SP6137 LED Evaluation Board

“YY” = Year – “WW” = Work Week – “XXX” = Lot Number

5/15

Rev. 2.0.0

SP6137

Wide Input, 900kHz Synchronous PWM Step Down

Controller

THEORY OF OPERATION

SOFT START

“Soft Start” is achieved when a power

converter ramps up the output voltage while

GENERAL OVERVIEW

controlling the magnitude of the input supply

source current. In a modern step down

converter, ramping up the positive terminal of

the error amplifier controls soft start. As a

result, excess source current can be defined as

the current required to charge the output

capacitor.

The SP6137 is a fixed frequency, voltage

mode, synchronous PWM controller optimized

for high efficiency. The part has been designed

to be especially attractive for split plane

applications utilizing 5V to power the controller

and 3V to 20V for step down conversion. The

heart of the SP6137 is a wide bandwidth

transconductance

accommodate

amplifier

designed

and Type

III

IV_IN= C_OUT* DV_OUT/ DTSoft-start

Type

The SP6137 provides the user with the option

to program the soft start rate by tying a

capacitor from the SS pin to GND. The

selection of this capacitor is based on the

10uA pull up current present at the SS pin and

the 0.8V reference voltage. Therefore, the

excess source can be redefined as:

compensation schemes. A precision 0.8V

reference present on the positive terminal of

the error amplifier permits the programming

of the output voltage down to 0.8V via the VFB

pin. The output of the error amplifier, COMP,

compared to a 1.1V peak-to-peak ramp is

responsible for trailing edge PWM control. This

voltage ramp and PWM control logic are

governed by the internal oscillator that

accurately sets the PWM frequency to 300kHz.

The SP6137 contains two unique control

features that are very powerful in distributed

applications. First, non-synchronous driver

control is enabled during start up to prohibit

the low side NFET from pulling down the

output until the high side NFET has attempted

to turn on. Second, a 100% duty cycle timeout

ensures that the low side NFET is periodically

enhanced during extended periods at 100%

duty cycle. This guarantees the synchronized

refreshing of the BST capacitor during very

large duty ratios. The SP6137 also contains a

number of valuable protection features. A

programmable input (VIN) UVLO allows a user

to set the exact value at which the conversion

voltage is at a safe point to begin down

conversion, and an internal VCC UVLO ensures

that the controller itself has enough voltage to

properly operate. Other protection features

include thermal shutdown and short-circuit

detection. In the event that either a thermal,

short-circuit, or UVLO fault is detected, the

SP6137 is forced into an idle state where the

output drivers are held off for a finite period

before a re-start is attempted.

IV_IN= C_OUT* DV_OUT*10μA / (C_SS* 0.8V)

UNDER VOLTAGE LOCK OUT (UVLO)

The SP6137 contains two separate UVLO

comparators to monitor the bias (VCC) and

conversion (VIN) voltages independently. The

VCC UVLO threshold is internally set to 4.25V,

whereas

the

VIN

UVLO

threshold

programmable through the UVIN pin. When

the UVIN pin is greater than 2.5V, the SP6137

is permitted to start up pending the removal of

all other faults. Both the VCC and VIN UVLO

comparators have been designed with

hysteresis to prevent noise from resetting a

fault.

THERMAL AND SHORT-CIRCUIT PROTECTION

Because the SP6137 is designed to drive large

NFETs running at high current, there is a

chance that either the controller or power

converter will become too hot. Therefore, an

internal thermal shutdown (145°C) has been

included to prevent the IC from malfunctioning

at extreme temperatures.

A short-circuit detection comparator has also

been included in the SP6137 to protect against

the accidental short or sever build up of

current at the output of the power converter.

This comparator constantly monitors the

6/15

Rev. 2.0.0

SP6137

Wide Input, 900kHz Synchronous PWM Step Down

Controller

positive and negative terminals of the error

capability. The voltage loop also includes two

other very important features. One is an Non-

synchronous start up mode. Basically, the GL

driver can not turn on unless the GH driver

has attempted to turn on or the SS pin has

exceeded 1.7V. This feature prevents the

controller from “dragging down” the output

voltage during startup or in fault modes. The

second feature is a 100% duty cycle timeout

that ensures synchronized refreshing of the

BST capacitor at very high duty ratios. In the

event that the GH driver is on for 20

continuous clock cycles, a reset is given to the

PWM flip flop half way through the 21st cycle.

This forces GL to rise for the remainder of the

cycle, in turn refreshing the BST capacitor.

amplifier, and if the VFB pin ever falls more

than 250mV (typical) below the positive

reference, a short-circuit fault is set. Because

the SS pin overrides the internal 0.8V

reference during soft start, the SP6137 is

capable of detecting short-circuit faults

throughout the duration of soft start as well as

in regular operation.

HANDLING OF FAULTS

Upon the detection of power (UVLO), thermal,

or short-circuit faults, the SP6137 is forced

into an idle state where the SS and COMP pins

are pulled low and the gate drivers are held

off. In the event of UVLO fault, the SP6137

remains in this idle state until the UVLO fault

is removed. Upon the detection of a thermal or

short-circuit fault, an internal 200ms (typical)

timer is activated. In the event of a short-

GATE DRIVERS

The SP6137 contains a pair of powerful 2Ω

SOURCE and 1.5Ω SINK drivers. These state

of the art drivers are designed to drive

external NFETs capable of handling up to 30A.

Rise, fall, and non-overlap times have all been

minimized to achieve maximum efficiency. All

drive pins GH, GL & SWN are monitored

continuously to ensure that only one external

NFET is ever on at any given time.

circuit

fault,

restart

attempted

immediately after the 200ms timeout expires.

Whereas, when a thermal fault is detected the

200ms delay continuously recycles and a

restart cannot be attempted until the thermal

fault is removed and the timer expires.

ERROR AMPLIFIER AND VOLTAGE LOOP

As stated before, the heart of the SP6137

voltage error loop is a high performance, wide

bandwidth

transconductance

amplifier.

Because of the amplifier’s current limited

(±150μA) transconductance, there are many

ways to compensate the voltage loop or to

control the COMP pin externally. A simple,

single pole, single zero compensation can be a

RC to ground. However Exar recommends a

Type II or Type III compensation which

eliminates the g_mof the amplifier from the

control loop equations.

The amplifier has

enough bandwidth (45° at 4 MHz) and enough

gain (60dB) to run Type III compensation

schemes with adequate gain and phase

margins at cross over frequencies greater than

50kHz.

The common mode output of the error

amplifier is 0.9V to 2.2V. Therefore, the PWM

voltage ramp has been set between 1.1V and

2.2V to ensure proper 0% to 100% duty cycle

7/15

Rev. 2.0.0

SP6137

Wide Input, 900kHz Synchronous PWM Step Down

Controller

requirements. The core must be large enough

not to saturate at the peak inductor current

and provide low core loss at the high switching

frequency. Low cost powdered iron cores have

a gradual saturation characteristic but can

introduce considerable ac core loss, especially

when the inductor value is relatively low and

the ripple current is high. Ferrite materials, on

the other hand, are more expensive and have

an abrupt saturation characteristic with the

inductance dropping sharply when the peak

design current is exceeded. Nevertheless, they

are preferred at high switching frequencies

because they present very low core loss and

the design only needs to prevent saturation.

In general, ferrite or molypermalloy materials

are better choice for all but the most cost

sensitive applications. The power dissipated in

the inductor is equal to the sum of the core

and copper losses. To minimize copper losses,

the winding resistance needs to be minimized,

but this usually comes at the expense of a

larger inductor. Core losses have a more

significant contribution at low output current

where the copper losses are at a minimum,

and can typically be neglected at higher output

currents where the copper losses dominate.

Core loss information is usually available from

the magnetic vendor.

APPLICATIONS INFORMATION

INDUCTOR SELECTION

There are many factors to consider in selecting

the inductor including cost, efficiency, size and

EMI. In a typical SP6137 circuit, the inductor

is chosen primarily for value, saturation

current and DC resistance. Increasing the

inductor value will decrease output voltage

ripple, but degrade transient response. Low

inductor values provide the smallest size, but

cause large ripple currents, poor efficiency and

more output capacitance to smooth out the

larger ripple current. The inductor must also

be able to handle the peak current at the

switching frequency without saturating, and

the copper resistance in the winding should be

kept as low as possible to minimize resistive

power loss. A good compromise between size,

loss and cost is to set the inductor ripple

current to be within 20% to 40% of the

maximum output current.

The switching frequency and the inductor

operating point determine the inductor value

as follows:

V_OUT

(

V_IN₎−V_OUT

)

(

max

L =

The copper loss in the inductor can be

calculated using the following equation:

V_{IN )}F_SK_rI_OUT

(

max

(

max

P ₍= I ²

WINDING

(

RMS

)

where:

where IL(RMS) is the RMS inductor current

that can be calculated as follows:

Fs = switching frequency Kr = ratio of the ac

inductor ripple current to the maximum output

current

⎛

⎞

⎟

⎠

I_PP

⎜

)

I_L

₎− I_OUT

The peak to peak inductor ripple current is:

(

RMS

(

max

⎜

3 I_OUT

(

max

)

⎝

V_OUT

(

V_IN₎−V_OUT

)

(

max

L =

V_{IN )}F_SL

OUTPUT CAPACITOR SELECTION

The required ESR (Equivalent

Resistance) and capacitance drive

selection of the type and quantity of the

output capacitors. The ESR must be small

enough that both the resistive voltage

deviation due to a step change in the load

current and the output ripple voltage do not

(

max

Series

the

I_PP

I_PEAK= I_OUT

)

(

max

Once the required inductor value is selected,

the proper selection of core material is based

on peak inductor current and efficiency

8/15

Rev. 2.0.0

SP6137

Wide Input, 900kHz Synchronous PWM Step Down

Controller

exceed the tolerance limits expected on the

INPUT CAPACITOR SELECTION

output voltage. During an output load

transient, the output capacitor must supply all

the additional current demanded by the load

until the SP6137CU adjusts the inductor

current to the new value.

The input capacitor should be selected for

ripple current rating, capacitance and voltage

rating. The input capacitor must meet the

ripple current requirement imposed by the

switching current. In continuous conduction

mode, the source current of the high-side

MOSFET is approximately a square wave of

duty cycle VOUT/VIN. Most of this current is

supplied by the input bypass capacitors. The

RMS value of input capacitor current is

determined at the maximum output current

and under the assumption that the peak to

peak inductor ripple current is low, it is given

by:

Therefore the capacitance must be large

enough so that the output voltage is help up

while the inductor current ramps up or down

to the value corresponding to the new load

current. Additionally, the ESR in the output

capacitor causes a step in the output voltage

equal to the current. Because of the fast

transient response and inherent 100% and 0%

duty cycle capability provided by the

SP6137CU when exposed to output load

transient, the output capacitor is typically

chosen for ESR, not for capacitance value.

I_{CIN )}= I_OUT

(

1− D

)

(

rms

(

max

)

The worse case occurs when the duty cycle D

is 50% and gives an RMS current value equal

to I_OUT/2.

The output capacitor’s ESR, combined with the

inductor ripple current, is typically the main

contributor to output voltage ripple. The

maximum allowable ESR required to maintain

a specified output voltage ripple can be

calculated by:

Select input capacitors with adequate ripple

current rating to ensure reliable operation. The

power dissipated in the input capacitor is:

= I ²

)

ESR

ΔV_OUT

I_PP

CIN

(

rms

CIN

(

CIN

)

R_ESR

≤

This can become a significant part of power

losses in a converter and hurt the overall

energy transfer efficiency. The input voltage

ripple primarily depends on the input capacitor

ESR and capacitance. Ignoring the inductor

ripple current, the input voltage ripple can be

determined by:

ΔV_OUT= Peak to Peak Output Voltage Ripple

I_PP= Peak to Peak Inductor Ripple Current

The total output ripple is a combination of the

ESR and the output capacitance value and can

be calculated as follows:

I_OUT_maxV_OUT

(

V_IN−V_OUT

)

(

)

ΔV_IN= I_OUT₎R_ESR

)

(

max

(

CIN

F_SC_INV_IN

The capacitor type suitable for the output

capacitors can also be used for the input

capacitors. However, exercise extra caution

when tantalum capacitors are considered.

⎛

⎞

I_PP

(

1− D

)

⎜

⎟

ΔV_OUT

(

I_PPR_ESR

)

C_OUTF_S

⎝

⎠

Where:

Tantalum

capacitors

are

known

for

catastrophic failure when exposed to surge

current, and input capacitors are prone to

such surge current when power supplies are

connected “live” to low impedance power

sources.

FS = Switching Frequency

D = Duty Cycle

C_OUT= Output Capacitance Value

9/15

Rev. 2.0.0

SP6137

Wide Input, 900kHz Synchronous PWM Step Down

Controller

lowering the RDS(ON) of the MOSFETs always

improves efficiency even though it gives rise

to higher switching losses due to increased

Crss.

MOSFET SELECTION

The losses associated with MOSFETs can be

divided into conduction and switching losses.

Conduction losses are related to the on

resistance of MOSFETs, and increase with the

load current. Switching losses occur on each

Top and bottom MOSFETs experience unequal

conduction losses if their on time is unequal.

For applications running at large or small duty

cycle, it makes sense to use different top and

on/off

transition

when

the

MOSFETs

experience both high current and voltage.

Since the bottom MOSFET switches current

from/to a paralleled diode (either its own body

diode or a Schottky diode), the voltage across

the MOSFET is no more than 1V during

switching transition. As a result, its switching

losses are negligible. The switching losses are

difficult to quantify due to all the variables

affecting turn on/ off time. However, the

following equation provides an approximation

on the switching losses associated with the top

MOSFET driven by SP6137.

bottom

MOSFETs.

Alternatively,

parallel

multiple MOSFETs to conduct large duty

factor.

RDS(ON) varies greatly with the gate driver

voltage. The MOSFET vendors often specify

RDS(ON) on multiple gate to source voltages

(VGS), as well as provide typical curve of

RDS(ON) versus VGS. For 5V input, use the

RDS(ON) specified at 4.5V VGS. At the time of

this publication, vendors, such as Fairchild,

Siliconix and International Rectifier, have

started to specify RDS(ON) at VGS less than

3V. This has provided necessary data for

designs in which these MOSFETs are driven

with 3.3V and made it possible to use SP6137

in 3.3V only applications.

₎=12C_rssV_{IN )}I_{OUT )}F_S

( (

(

max

where

Crss = reverse transfer capacitance of the top

MOSFET

Thermal calculation must be conducted to

ensure the MOSFET can handle the maximum

load current. The junction temperature of the

MOSFET, determined as follows, must stay

below the maximum rating.

Switching losses need to be taken into account

for high switching frequency, since they are

directly proportional to switching frequency.

The conduction losses associated with top and

bottom MOSFETs are determined by:

P_MOSFET

(

max

)

₎= R_{DS )}I_OUT

²D

T_J₎= T_A

)

(

max

(

max

(

max

(

max

)

R_θJA

= R_{DS )}I_OUT

(

1− D

)

(

max

)

(

max

where

TA(max) = maximum ambient temperature

PCH(max) = conduction losses of the high side

MOSFET

PMOSFET(max) = maximum power dissipation

of the MOSFET

PCL(max) = conduction losses of the low side

MOSFET

RΘJA

junction to ambient thermal

resistance.

RDS(ON) = drain to source on resistance.

RΘJA of the device depends greatly on the

board layout, as well as device package.

Significant thermal improvement can be

achieved in the maximum power dissipation

through the proper design of copper mounting

pads on the circuit board. For example, in a

SO-8 package, placing two 0.04 square inches

The total power losses of the top MOSFET are

the sum of switching and conduction losses.

For synchronous buck converters of efficiency

over 90%, allow no more than 4% power

losses for high or low side MOSFETs. For input

voltages of 3.3V and 5V, conduction losses

often dominate switching losses. Therefore,

10/15

Rev. 2.0.0

SP6137

Wide Input, 900kHz Synchronous PWM Step Down

Controller

copper pad directly under the package,

without occupying additional board space, can

increase the maximum power from

approximately 1 to 1.2W. For DPAK package,

enlarging the tap mounting pad to 1 square

inches reduces the RΘJA from 96°C/W to

40°C/W.

LOOP COMPENSATION DESIGN

The open loop gain of the whole system can

be divided into the gain of the error amplifier,

PWM modulator, buck converter output stage,

and feedback resistor divider. In order to

crossover at the selected frequency FCO, the

gain of the error amplifier has to compensate

for the attenuation caused by the rest of the

loop at this frequency. The goal of loop

compensation is to manipulate loop frequency

response such that its gain crosses over 0db

at a slope of -20db/dec. The first step of

compensation design is to pick the loop

crossover frequency. High crossover frequency

is desirable for fast transient response, but

often jeopardizes the system stability.

Crossover frequency should be higher than the

ESR zero but less than 1/5 of the switching

frequency. The ESR zero is contributed by the

ESR associated with the output capacitors and

can be determined by:

SCHOTTKY DIODE SELECTION

When paralleled with the bottom MOSFET, an

optional Schottky diode can improve efficiency

and reduce noises. Without this Schottky

diode, the body diode of the bottom MOSFET

conducts the current during the non-overlap

time when both MOSFETs are turned off.

Unfortunately, the body diode has high

forward voltage and reverse recovery problem.

The reverse recovery of the body diode causes

additional switching noises when the diode

turns off. The Schottky diode alleviates these

noises and additionally improves efficiency

thanks to its low forward voltage. The reverse

voltage across the diode is equal to input

voltage, and the diode must be able to handle

the peak current equal to the maximum load

current.

f_Z

)

(

ESR

2πC_OUTR_ESR

The next step is to calculated the complex

conjugate poles contributed by the LC output

filter,

The power dissipation of the Schottky diode is

determined by

f_P

)

= 2V_FI_OUTT_NOLF_S

(

Diode

2π LC

where

When the output capacitors are of a Ceramic

Type, the SP6137CU Evaluation Board requires

a Type III compensation circuit to give a

phase boost of 180° in order to counteract the

effects of an under damped resonance of the

output filter at the double pole frequency.

TNOL = non-overlap time between GH and GL.

VF = forward voltage of the Schottky diode.

11/15

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SP6137

Wide Input, 900kHz Synchronous PWM Step Down

Controller

SP6137 Voltage Mode Control Loop with Loop Dynamic

Definitions:

Resr = Output Capacitor Equivalent Series Resistance

Rdc = Output Inductor DC Resistance

Vramp_pp = SP6137 internal RAMP Amplitude Peak to Peak Voltage

Conditions:

Cz2 >> Cp1 and R1 >> Rz3

Output Load Resistance >> Resr and Rdc

Bode Plot of Type III Error Amplifier Compensation.

12/15

Rev. 2.0.0

SP6137

Wide Input, 900kHz Synchronous PWM Step Down

Controller

TYPICAL APPLICATION DIAGRAM

2.5V -20V

22μF

7 6 5

16V

= 5V @ 30mA

FDS6676S

14.5A, 6mΩ

GND

C1, C2

RLF

3.0,5%

2 3

Ceramic

1210

X5R

CBST

0.1μF

DBST

OUT

≤

MBR0530

L1 SC5018-2R7M

2.7μH @ 12A

DCR=4.30mΩ

3.3V @ 10A

RZ3

7 6 5

Bead

VCC

BST

4.64k, 1%

SP6137

C_VCC

10μF

GND 3

SWN

47μF

GND

VFB

68.1k, 1%

6.3V

CZ3

220pF

221k, 1%

6.3V

0.8V

2 3

COMP

UVIN

FDS6676S

14.5A, 6.0mΩ

C_VCC

CSS

47nF

GND2

Ceramic

8050

CZ2

RZ2

820pF 40.2k, 1%

CP1

100k, 1%

21.5k, 1%

X5R

C3, C4

Ceramic

1210

CF1

100pF

56pF

X5R

Note: Components highlighted in bold are those used on the SP6137 Evaluation Board.

Table 1. Input and Output Stage Components Selection Charts.

13/15

Rev. 2.0.0

SP6137

Wide Input, 900kHz Synchronous PWM Step Down

Controller

PACKAGE SPECIFICATION

MSOP-10

14/15

Rev. 2.0.0

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Wide Input, 900kHz Synchronous PWM Step Down

Controller

REVISION HISTORY – TO BE DELETED PRIOR TO PUBLICATION -

Revision

Date

Description

Complete re-formatting

Changes from PCN #09-0120-01

2.0.0

1/20/2009

FOR FURTHER ASSISTANCE

Email:

customersupport@exar.com

Exar Technical Documentation:

http://www.exar.com/TechDoc/default.aspx?

EXAR CORPORATION

HEADQUARTERS AND SALES OFFICES

48720 Kato Road

Fremont, CA 94538 – USA

Tel.: +1 (510) 668-7000

Fax: +1 (510) 668-7030

www.exar.com

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve

design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein,

conveys no license under any patent or other right, and makes no representation that the circuits are free of patent

infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a

user’s specific application. While the information in this publication has been carefully checked; no responsibility, however,

is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or

malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its

safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in

writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all

such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

15/15

Rev. 2.0.0

SP6137 [EXAR]

相关型号：

SP6137A

SP6137AE3

SP6137CU

SP6137CU

SP6137CU-L

SP6137CU-L/TR

SP6137CU-L/TR

SP6137CU/TR

SP6137CU/TR-L

SP6137EU

SP6137EU-L

SP6137EU-L