SP6200EM5-3-3-L/TR_技术文档

SP6200/6201

Micropower, 100mA and 200mA CMOS LDO Regulators

FEATURES

1

2

3

4

8

7

6

5

NC

EN

SP6201

■ Low Dropout Voltage: 160mV @ 100mA

■ High Output Voltage Accuracy: 2%

■ Ultra Low Shutdown Current: 1µA Max

■ Ultra Low GND Current:

VIN

GND

NC

8 Pin DFN

VOUT

NC

RESET/ADJ

• 200µA @ 200mA Load

• 28µA @ 100µA Load

■ Extremely Tight Load and Line Regulation

■ Current and Thermal Limiting

■ RESET Output (V_OUTgood)

■ Logic-Controlled Electronic Enable

■ Unconditionally Stable with 1µF Ceramic

■ Fixed Outputs:

• 1.5V, 1.8V, 2.5V, 2.7V, 2.85V, 3.0V, 3.3V, 3.5V, 5V

■ Adjustable Output Available

■ Tiny DFN Package (2mmX3mm) or SOT23-5

APPLICATIONS

■ Cellular Telephones

■ Laptop, Notebooks and Palmtop Computers

■ Battery-Powered Equipment

■ Consumer/ Personal Electronics

■ SMPS Post-Regulator

■ DC-to-DC Modules

■ Medical Devices

■ Data Cable

■ Pagers

Now Available in Lead Free Packaging

DESCRIPTION

TheSP6200andSP6201areCMOSLowDropout(LDO)regulatorsdesignedtomeetabroadrangeofapplicationsthat

require accuracy, speed and ease of use. These LDOs offer extremely low quiescent current which only increases

slightly under load, thus providing advantages in ground current performance over bipolar LDOs. The LDOs handle an

extremely wide load range and guarantee stability with a 1µF ceramic output capacitor. They have excellent low

frequency Power Supply Rejection Ratio (PSRR), not found in other CMOS LDOs and thus offer exceptional Line

Regulation. High frequency PSRR is better than 40dB up to 400kHz. Load Regulation is excellent and temperature

stability is comparable to bipolar LDOs. An enable feature is provided on all versions.

The SP6200/6201 is available in fixed and adjustable output voltage versions in tiny DFN and small SOT-23-5

packages. A V_OUTgood indicator is provided on all fixed output versions.

TYPICAL APPLICATION CIRCUIT

Fixed Output Voltage

470kΩ

V_IN

V_OUT

1

2

5

4

C_IN= 1µF

C

_OUT= 1µF

SP6200

SP6201

Enable

Shutdown

3

(V_OUTgood)

RSN

EN

EN (pin 3) may be connected

directly to IN (pin 1).

Date: 5/5/06 Rev A

SP6200/6201 100/200mA CMOS LDO Regulator

1

ABSOLUTE MAXIMUM RATINGS, NOTE 1

These are stress ratings only and functional operation of

the device at these ratings or any other above those

indicated in the operation sections of the specifications

below is not implied. Exposure to absolute maximum

rating conditions for extended periods of time may affect

reliability.

OPERATING RATINGS, NOTE 2

Input Voltage (V_IN)..................................+2.5V to +6V

Enable Input Voltage (V_EN)..........................0V to +6V

Junction Temperature (T_J)................-40˚C to +125˚C

Thermal Resistance (See Note 3):

SOT-23-5 (θ_JA).................................................191˚C/W

8 Pin DFN (θ_JA)............................................ .....59˚C/W

(See Note 3)

Supply Input Voltage (V_IN) ............................. -2V to 7V

Output Voltage (V_OUT) ......................... -0.6 to (V_IN+1V)

Enable Input Voltage (V_EN) ............................ -2V to 7V

Power Dissipation (P_D).......... Internally Limited, Note 3

Lead Temperature (soldering 5s) ....................... 260°C

Storage Temperature ........................ -65˚C to +150˚C

ELECTRICAL CHARACTERISTICS

V_IN= V_OUT+1V, V_O= 5V for ADJ, I_L= 100µA, C_IN= 1.0µF, C_OUT= 1.0µF, T_J= 25^°C , unless otherwise specified. The ♦ denotes the specifications

which apply over the full operating temperature range, unless otherwise specified.

PARAMETER

MIN

TYP

MAX

UNIT

♦

CONDITIONS

Output Voltage Accuracy, (V_O)

-2

-3

2

3

%

Variation from specified V_OUT

♦

Reference Voltage

1.213 1.250 1.287

60

V

Adjustable version only

Output Voltage Temperature

ppm/ °C

Coefficient, Note 4, (∆V_O/∆T)

Minimum Supply Voltage

2.50

2.55

2.70

3.00

2.70

2.80

2.95

3.50

V

I_L= 100µA

I_L= 50mA

I_L= 100mA

I_C= 200mA

Line Regulation, (∆V_O/ V_IN

)

0.03

0.2

%/ V

♦

V_IN= (V_OUT+ 1V) to 6V

Load Regulation, Note 5, (∆V_{O /}V_O)

0.07

0.14

0.25

0.50

%

♦

I_L= 0.1mA to 100mA, SP6200

I_L= 0.1mA to 200mA, SP6201

SP6200-1.5V & 1.8 Load Regulation

SP6201-1.5V & 1.8 Load Regulation

0.3

1

%

I_L= 0.1mA to 100mA, V_IN= 2.95V

I_L= 0.1mA to 200mA, V_IN= 3.5V

Dropout Voltage, Note 6, (V_IN– V_O)

(Not applicable to voltage options below

0.2

4

7

mV

I_L= 100µA

♦

2.7V)

70

120

160

mV

I_L= 50mA

160

320

250

300

mV

I_L= 100mA

400

500

mV

I_L= 200mA, SP6201 Only

♦

Shutdown Quiescent Current, (I_GND

)

0.01

28

1

µA

V_EN≥ 0.4V

Ground Pin Current, Note 7, (I_GND

)

40

45

µA

V_EN≥ 2.0V, I_L= 100µA

♦

110

200

250

µA

V_EN≥2.0V, I_L= 100mA, SP6200

only (for 1.5 & 1.8, V_IN= 2.95)

400

500

µA

V_EN≥2.0V, I_L= 200mA, SP6201

Only (for 1.5 & 1.8, V_IN= 3.5)

Power Supply Rejection Ratio,

(PSRR)

78

40

Frequency =100Hz, I_L=10mA

Frequency = 400Hz, I_L=10mA

dB

Current Limit, (I_CL

)

100

300

140

420

200

600

mA

♦

SP6200

SP6201

Thermal Limit

162

147

°C

Turns On

Turns Off

Date: 5/5/06 Rev A

SP6200/6201 100/200mA CMOS LDO Regulator

2

ELECTRICAL CHARACTERISTICS: Continued

V_IN= V_OUT+1V, V_O= 5V for ADJ, I_L= 100µA, C_IN= 1.0µF, C_OUT= 1.0µF, T_J= 25^°C , unless otherwise specified. The ♦ denotes the

specifications which apply over the full operating temperature range, unless otherwise specified.

PARAMETER

MIN

TYP

MAX UNITS

♦

CONDITIONS

Thermal Regulation,

0.05

%/W

Note 8, (∆V_O/∆P_D)

Output Noise, (e _no

)

I_L= 50mA, C_L= 1µF

0.1µF from V_OUTto Adj.

10Hz to 100kHz

150

µVrms

ENABLE INPUT

Enable Input Logic-Low Voltage,

(V_IL)

0.4

V

♦

Regulator Shutdown

Regulator Enabled

Enable Input Logic-High Voltage,

(V_IH)

1.6

-2

Enable Input Current, (I_IL), (I_IH

)

0.01

-4

1

µA

%

♦

V_IL< 0.4V

V_IH> 2.0V

Threshold

Reset Not Output

-6

Note 1. Exceeding the absolute maximum rating may damage the device.

Note 2. The device is not guaranteed to function outside its operating rating.

Note 3. The maximum allowable power dissipation at any T_A(ambient temperature) is P_{D (MAX)}= (T_{J (MAX)}– T_A) / θ_ϑA.

Exceeding the maximum allowable power dissipation will result in excessive die temperature, and the regulator will

go into thermal shutdown. The θ_JAof the SP6200/6201 (all versions) is 191°C/W for the SOT-23-5 and 59°C/W for

the DFN package on a standard 4 layer board (see “Thermal Considerations” section for further details).

Note 4. Output voltage temperature coefficient is defined as the worst case voltage change divided by the total

temperature range.

Note 5. Load Regulation is measured at constant junction temperature using low duty cycle pulse testing. Parts are

testedforloadregulationintheloadrange;from0.1mAto100mA,SP6200;from0.1mAto200mA,SP6201. Changes

in output voltage due to heating effects are covered by the thermal regulation specification. Not applicable to output

voltages less than 2.5V.

Note 6. Dropout Voltage is defined as the input to output differential at which the output voltage drops 2% below

its nominal value measured at 1V differential. Not applicable to output voltages less than 2.7V.

Note 7. Ground pin current is the regulator quiescent current. The total current drawn from the supply is the sum

of the load current plus the ground pin current.

Note 8. Thermal regulation is defined as the change in output voltage at a time ”t” after a change in power dissipation

is applied, excluding load or line regulation effects. Specifications are for a 100mA load pulse at V_IN= 6V for t = 10ms.

Date: 5/5/06 Rev A

SP6200/6201 100/200mA CMOS LDO Regulator

3

OUT

V_OUT

C_OUT

V_IN

Current Limit

and Thermal

Shutdown

R2

Enable

-

+

V_REF

Bandgap

REF

R_PULL

1.25V

R1

RSN

RESET

1.20V

GND

Figure 1. Fixed Voltage Regulator

IN

OUT

V

V_OUT

IN

C_OUT

R2

Current Limit

and Thermal

Shutdown

EN

C_BYP

(option)

Enable

-

+

ADJ

V_REF

Bandgap

REF

1.25V

R1

RSN

1.20V

R2

R1

V_OUT= V_REF

+1

GND

Figure 2. Adjustable Voltage Regulator

Date: 5/5/06 Rev A

SP6200/6201 100/200mA CMOS LDO Regulator

4

PIN DESCRIPTION

SOT 23-5

PIN NUMBER

PIN CONFIGURATION

FUNCTION

NAME

IN

1

2

3

Supply Input

GND

EN

Ground

Enable/Shutdown (Input): CMOS or TTL compatible

input. Logic high = enable, logic low = shutdown

4

RSN (Reset Not)

ADJ

Open drain indicating that V_OUTis good

Adjustable (Input): Adjustable regulator feedback

input. Connect resistor voltage divider.

5

OUT

Regulator Output

8 PIN DFN

PIN CONFIGURATION

PIN NUMBER

NAME

NC

FUNCTION

No Connect

1

2

VIN

Supply Input

3

VOUT

NC

Regulator Input

4

No Connect

5 (Fixed)

5 (Adj.)

RSN

ADJ

Open drain indicating that V_OUTis good

Adjustable (Input): Adjustable regulator feedback

input. Connect resistor voltage divider.

6

7

8

NC

GND

EN

No Connect

Ground

Enable/Shutdown (Input): CMOS or TTL compatible

input. Logic high = enable, logic low = shutdown

Date: 5/5/06 Rev A

SP6200/6201 100/200mA CMOS LDO Regulator

5

THEORY OF OPERATION

An accurate 1.250V bandgap reference is

bootstrapped to the output in fixed output ver-

sionsof2.7Vandhigher. Thisincreasesboththe

low frequency and high frequency PSRR. The

adjustable version also has the bandgap refer-

ence bootstrapped to the output, thus the lowest

externallyprogrammableoutputvoltageis2.7V.

The 2.5V fixed output version has the bandgap

always connected to the Vin pin. Unlike many

LDOs, the bandgap reference is not brought out

for filtering by the user. This tradeoff was maid

tomaintaingoodPSRRathighfrequency(PSRR

can be degraded in a system due to switching

noise coupling into this pin). Also, often leak-

ages of the bypass capacitor or other compo-

nents cause an error on this high impedance

bandgap node. Thus, this tradeoff has been

made with "ease of use" in mind.

General Overview

The SP6200 and SP6201 are CMOS LDOs

designed to meet a broad range of applications

that require accuracy, speed and ease of use.

These LDOs offer extremely low quiescent cur-

rent which only increases slightly under load,

thus providing advantages in ground current

performance over bipolar LDOs. The LDOs

handle an extremely wide load range and guar-

antee stability with a 1µF ceramic output ca-

pacitor. They have excellent low frequency

PSRR, notfoundinotherCMOSLDOsandthus

offer exceptional Line Regulation. High fre-

quency PSRR is better than 40dB up to 400kHz.

Load Regulation is excellent and temperature

stability is comparable to bipolar LDOs. Thus,

overall system accuracy is maintained under all

DC and AC conditions. Enable feature is pro-

vided on all versions. A Vout good indicator

(RSN pin) is provided in all the fixed output

voltage devices. An adjustable output version is

also available. Current Limit and Thermal pro-

tection is provided internally and is well con-

trolled.

Protection

Current limit behavior is very well controlled,

providing less than 10% variation in the current

limitthresholdovertheentiretemperaturerange

for both SP6200 and SP6201. The SP6200 has a

current limit of 140mA, while the SP6201 has a

current limit of 420mA. Thermal shutdown ac-

tivates at 162°C and deactivates at 147°C. Ther-

mal shutdown is very repeatable with only a 2 to

3 degree variation from device to device. Ther-

mal shutdown changes by only 1 to 2 degrees

with Vin change from 4V to 7V.

Architecture

The SP6200 and SP6201 are only different in

their current limit threshold. The SP6200 has a

current limit of 140mA, while the SP6201 cur-

rent limit is 420mA. The SP6201 can provide

pulsed load current of 300mA. The LDOs have

a two stage amplifier which handles an ex-

tremely wide load range (10µA to 300mA) and

guarantees stability with a 1µF ceramic load

capacitor. TheLDOamplifierhasexcellentgain

and thus touts PSRR performance not found in

other CMOS LDOs. The amplifier guarantees

no overshoot on power up or while enabled

through the EN pin. The amplifier also contains

an active pull down, so that when the load is

removed quickly the output voltage transient is

minimal; thus output deviation due to load tran-

sient is small and fairly well matched when

connecting and disconnecting the load.

Enable (Shutdown Not) Input

The LDOs are turned off by pulling the EN pin

low and turned on by pulling it high. If it is not

necessary to shut down the LDO, the EN (pin 3)

should be tied to IN (pin 1) to keep the regulator

output on at all time. The enable threshold is

0.9V and does not change more than 100mV

over the entire temperature and Vin voltage

range. ThelottolotvariationsinEnableThresh-

old is also within 100mV. Shutdown current is

guaranteed to be <1uA without requiring the

user to pull enable all the way to 0V. Standard

TTL or CMOS levels will transition the device

from totally on to totally off.

Date: 5/5/06 Rev A

SP6200/6201 100/200mA CMOS LDO Regulator

6

THEORY OF OPERATION: Continued

Input Capacitor

Reset Not (VOUT good) Output

A small capacitor, 1µF or higher, is required

from V_INto GND to create a high frequency

bypass for the LDO amplifier. Any ceramic or

tantalum capacitor may be used at the input.

Capacitor ESR (effective series resistance)

should be smaller than 3Ω.

An accurate Vout good indicator is provided on

allthefixedoutputversiondevices,pin4(RSN),

Figure 1. This is an open drain, logic output that

can be used to hold a microprocessor or micro-

controllerinaRESETconditionwhenit'spower

supplied by Vout is 4% out of nominal regula-

tion. A 1% hysteresis is included in the Reset

Not function, so that false alarms are not issued

as a result of LDO's output noise. The Reset Not

function reacts in 10 to 50µs.

Output Capacitor

An output capacitor is required between V_OUT

and GND to prevent oscillation. A capacitance

as low as 0.22µF can fulfill stability require-

ments in most applications. A 1µF capacitor

will ensure unconditional stability from no load

to full load over the entire input voltage, output

voltageandtemperaturerange. Largercapacitor

valuesimprovetheregulator'stransientresponse.

The output capacitor value may be increased

without limit. The output capacitor should have

an ESR (effective series resistance) below 5Ω

and a resonant frequency above 1MHz.

Adjustable Output Version

The adjustable version can be programmed to

any voltage from 2.7V to 6V for the industrial

temperature range; 2.5V to 6V for the commer-

cial temperature range. The output can not be

programmed below 2.5V due a headroom re-

striction. Since the bandgap is bootstrapped to

the output, the output voltage must be above the

minimumbandgapsupplyvoltage.Thebandgap

requires 2.7V or greater at -40°C and requires

2.5V or greater at 0°C.

No Load Stability

The SP6200/6201 will remain stable and in

regulation with no external load (other than the

internal voltage driver) unlike many other volt-

age regulators. This is especially important in

CMOS RAM keep-alive applications.

The regulator's output can be adjusted to a

specific output voltage by using two external

resistors, Figure 2. The resistor's set the output

voltage based on the following equation:

V

_OUT= 1.25 (R2/R1 + 1)

Thermal Considerations

Resistor values are not critical because the ADJ

node has a high input impedance, but for best

results use resistors of 470kΩ or less. A capaci-

tor from ADJ to Vout pin provides improved

noise performance as is shown in the following

plot.

The SP6200 is designed to provide 100mA of

continuous current, while the SP6201 will pro-

vide 200mA of continuous current. Maximum

powerdissipationcanbecalculatedbasedonthe

output current and the voltage drop across the

part. Todeterminethemaximumpowerdissipa-

tion in the package, use the junction-to-ambient

thermal resistance of the device and the follow-

ing basic equation:

Noise Performance 10Hz to 100kHz

Adj, Vin = 4.3V, Vout = 3.3V (Cin = Cout = 1uF)

400

(T_J(max)- T_A)

P_D=

θ_JA

300

200

100

T_J(max)is the maximum junction temperature of

thedieandis125°C.T_Aistheambientoperating.

θ_JAisthejunction-to-ambientthermalresistance

for the regulator and is layout dependent.

The actual power dissipation of the regulator

circuit can be determined using one simple

1.0E+02

1.0E+03

1.0E+04

1.0E+05

1.0E+06

1.0E+07

Bypass Cap from Vout to FB (pF)

Date: 5/5/06 Rev A

SP6200/6201 100/200mA CMOS LDO Regulator

7

THEORY OF OPERATION: Continued

equation:

P_D= (V_IN- V_OUT)*I_OUT+ V_IN*I_GND

≅ (V_IN- V_OUT) * I_OUT

Substituting P_D(max)for P_Dand solving for the

operating conditions that are critical to the ap-

plication will give the maximum operating con-

ditions for the regulator circuit. For example, if

we are operating the SP6201- 3.0V at room

temperature, with a SOT-23-5 package on a 4

layerstandardboardwecandeterminethemaxi-

mum input voltage for a set output current.

(125°C -25°C)

(191°C/W)

P_D(max)

=

= 0.52W

To prevent the device from entering thermal

shutdown, maximum power dissipation can not

be exceeded. Using the output voltage of 3.0V

and an output current of 200 mA, the maximum

input voltage can be determined. Ground pin

current can be taken from the electrical spec’s-

table (I_GND=200uA at I_OUT=200mA). The maxi-

mum input voltage is determined as follows:

0.52W = (V_IN– 3.0V)*200mA + V_IN*0.2mA

Solving for V_IN, we get:

(0.52W + 0.6W)

V_IN

=

200.2mA

After calculations, we find that the maximum

input voltage of a 3.0V application at 200mA of

output currentinanSOT-23-5packageis5.59V.

Dual-Supply Operation

When used in dual supply systems where the

regulator load is returned to a negative supply,

the output voltage must be diode clamped to

ground.

Date: 5/5/06 Rev A

SP6200/6201 100/200mA CMOS LDO Regulator

8

TYPICAL CHARACTERISTICS

27°C, V_IN= 5.5V, I_O= 0.1mA, C_IN= C_OUT= 1µF unless otherwise specified.

Dropout vs. Temp (SP6201 fixed 3.0V)

Dropout vs. Io (SP6201 fixed 3.0V)

400

350

300

250

200

150

100

50

400

350

300

250

200

150

100

50

T=125 deg

T=27deg

Io=200mA

Io=100mA

Io=50mA

T=-40 deg

0

-50

-20

10

40

70

100

130

0

50

100

150

200

Io (mA)

Temp (deg)

Iq vs. Vin (fixed 3.0V, Io=0uA)

Dropout vs. Temp (SP6201 fixed 3.0V)

50

45

40

35

30

25

20

15

10

5

35

30

25

20

15

10

5

2.5

2.0

1.5

1.0

0.5

0.0

Io=1mA

Io=0.1mA

EN = Vin

EN = 0V

0

-50

-20

10

40

70

100

130

0

1

2

3

4

5

6

7

Vin (V)

Temp (deg)

Iq vs. Temp (SP6201 fixed 3.0V, EN=0V, Io=0uA)

Iq vs. Temp (SP6201 fixed 3.0V, EN=Vin, Io=0uA)

250

200

150

100

50

45

40

35

30

25

Vin = 7V

Vin = 5.5V

Vin = 4V

Vin = 7V

Vin =5.5V

Vin = 4V

0

-50

-20

10

40

70

100

130

-50

-20

10

40

70

100

130

Temp (deg)

Ignd vs. Io (SP6201 fixed 3.0V)

Vin = 7V

Ignd vs. Vin (SP6201 fixed 3.0V)

Io=200mA

Io=150mA

Io=100mA

Io=50mA

Io=0.1mA

350

300

250

200

150

100

50

220

195

170

145

120

95

Vin = 5.5V

Vin = 4V

70

45

0

20

3

4

5

6

7

0

50

100

150

200

Vin (V)

Io (mA)

Date: 5/5/06 Rev A

SP6200/6201 100/200mA CMOS LDO Regulator

9

TYPICAL CHARACTERISTICS: Continued

27°C, V_IN= 5.5V, I_O= 0.1mA, C_IN= C_OUT= 1µF unless otherwise specified.

Vout vs. Temp (fixed 3.3V)

Vout vs. Temp (fixed 3.0V)

3.33

3.32

3.31

3.30

3.29

3.28

3.27

3.03

3.02

3.01

3.00

2.99

2.98

2.97

Vin = 7V

Vin = 4V

Vin = 7V

Vin = 4V

-50

-20

10

40

70

100

130

-50

-20

10

40

70

100

130

Temp (deg)

Vout vs. Temp (adjustable)

2.90

2.85

2.80

2.75

2.70

2.65

3.35

3.25

3.15

3.05

2.95

3.3Vout

3.0Vout

2.85Vout

2.7Vout

-50

-20

10

40

70

100

130

-50

-20

10

40

70

100

130

Temp (deg)

Vout vs. Temp (adjustable)

2.525

2.520

2.515

2.510

2.505

2.500

2.495

2.490

2.485

2.480

2.475

5.05

5.04

5.03

5.02

5.01

5.00

4.99

4.98

4.97

4.96

4.95

5.0Vout

2.5Vout

-50

-20

10

40

70

100

130

-50

-20

10

40

70

100

130

Temp (deg)

Load Regulation (SP6201 fixed 3.0V)

Vin = 7V

Line Regulation (SP6201 fixed 3.0V)

Io=0.1mA

3.006

3.004

3.002

3.000

2.998

2.996

2.994

3.004

3.002

3.000

2.998

2.996

2.994

2.992

Io=1mA

Vin = 5.5V

Vin = 4V

Io=50mA

Io=100mA

Io=200mA

0

50

100

150

200

250

300

3

4

5

6

7

Vin (V)

Io (mA)

Date: 5/5/06 Rev A

SP6200/6201 100/200mA CMOS LDO Regulator

10

TYPICAL CHARACTERISTICS: Continued

27°C, V_IN= 5.5V, I_O= 0.1mA, C_IN= C_OUT= 1µF unless otherwise specified.

Current Limit vs. Temp (fixed 3.3V, Vin=4V)

600

500

400

300

200

150

100

SP6201-3.3

SP6200-3.3

-50

0

50

100

150

-50

0

50

100

150

Temp (deg)

Turn on time, Io=1mA, 4Vin

Turn on time, Io=100mA, 4Vin

V

OUT

V

OUT

3V

2V

1V

0V

4V

3V

2V

1V

0V

4V

SP6201 - 3.0Vout fixed

Ven is toggled, Vin = 4V

Iout = 100mA

SP6201 - 3.0Vout fixed

Ven is toggled, Vin = 4V

Iout = 1mA

Cin = Cout = 1uF Cer. Cap

V

EN

V

EN

2V

0V

2V

0V

Turn on time, Io=100mA, 7Vin

Turn on time, Io=300mA, 4Vin

V

OUT

V

OUT

3V

2V

1V

0V

4V

SP6201 - 3.0Vout fixed

Ven is toggled, Vin = 7V

Iout = 100mA

3V

SP6201 - 3.0Vout fixed

Ven is toggled, Vin = 4V

Iout = 300mA

2V

1V

0V

4V

Cin = Cout = 1uF Cer. Cap

V

EN

V

EN

2V

0V

2V

0V

Turn off time, Io=1mA, 4Vin

Turn off time, Io=50mA, 4Vin

V^OUT

3V

2V

SP6201 - 3.0Vout fixed

Ven is toggled, Vin = 4V

Iout= 1mA

SP6201 - 3.0Vout fixed

Ven is toggled, Vin = 4V

Iout = 50mA

3V

2V

VOUT

Cin = Cout = 1uF Cer. Cap

1V

0V

4V

2V

0V

1V

0V

V^EN

VEN

4V

2V

0V

Date: 5/5/06 Rev A

SP6200/6201 100/200mA CMOS LDO Regulator

11

TYPICAL CHARACTERISTICS: Continued

27°C, V_IN= 5.5V, I_O= 0.1mA, C_IN= C_OUT= 1µF unless otherwise specified.

Turn off time, Io=100mA, 4Vin

Turn off time, Io=100mA, 7Vin

3V

2V

SP6201 - 3.0Vout fixed

Ven is toggled, Vin = 7V

Iout = 100mA

3V

2V

SP6201 - 3.0Vout fixed

Ven is toggled, Vin = 4V

Iout = 100mA

VOUT

Cin = Cout = 1uF Cer. Cap

1V

0V

1V

0V

VEN

4V

2V

0V

4V

2V

0V

Inrush Current, Io=100uA

Inrush Current, Io=100mA

750mA

500mA

250mA

0mA

SP6201 - 3.0Vout fixed, Vin=4V

Ven is toggled, Iout = 100uA

Cin = Cout = 1uF Cer. Cap

SP6201 - 3.0Vout fixed, Vin=4V

Ven is toggled, Iout=100mA

Cin = Cout = 1uF Cer. Cap

650mA

500mA

250mA

0mA

2V

650mA

I

VOUT

2V

0V

VEN

4V

2V

0V

4V

2V

0V

Load Transient Response, 100mA step, 4Vin

Load Transient Response, 100mA step, 7Vin

80mV

60mV

80mV

60mV

SP6201 - 3.0Vout fixed

Vin = 4V, Iout = 100mA

Cin = Cout = 1uF Cer. Cap

SP6201 - 3.0Vout fixed

Vin = 7V , Iout = 100mA

Cin = Cout = 1uF Cer. Cap

VOUT

40mV

20mV

40mV

20mV

0mV

-20mV

-40mV

100mA

0mA

-40mV

Tr = Tf = 100ns

I

OUT

100uA

IOUT

100uA

100mA

0mA

Load Transient Response, 300mA step, 4Vin

Load Transient Response, 200mA step, 4Vin

200mV

150mV

100mV

50mV

0mV

200mV

150mV

100mV

50mV

SP6201 - 3.0Vout fixed

Vin = 4V , Iout = 200mA

Cin = Cout = 1uF Cer. Cap

SP6201 - 3.0Vout fixed

Vin = 4V, Iout = 300mA

Cin = Cout = 1uF Cer. Cap

VOUT

0mV

-50mV

I

OUT

200mA

100mA

0mA

I

OUT

Tr = Tf = 100ns

100uA

200mA

0mA

Date: 5/5/06 Rev A

SP6200/6201 100/200mA CMOS LDO Regulator

12

TYPICAL CHARACTERISTICS: Continued

27°C, V_IN= 5.5V, I_O= 0.1mA, C_IN= C_OUT= 1µF unless otherwise specified.

Power Supply Rejection Ratio

/DIV

10.000dB

Power Supply Rejection Ratio

/DIV

10.000dB

REF LEVEL

0.000dB

REF LEVEL

0.000dB

0

-20

-40

-60

-40

-60

I_OUT= 100µA

_OUT= 1µF

_IN= 4V

_OUT= 3V

-80

I_OUT= 1mA

C_OUT= 2.2µF

C

V

-80

-100

10

START 10.000Hz

100

1k

10k

100k

STOP 10 000 000.000Hz

1M

10M

10

START 10.000Hz

100

1k

10k

100k

STOP 10 000 000.000Hz

1M

10M

Frequency (HZ)

Power Supply Rejection Ratio

/DIV

10.000dB

REF LEVEL

0.000dB

/DIV

10.000dB

REF LEVEL

0.000dB

0

-20

-40

-60

-40

-60

-80

I_OUT= 100mA

C_OUT= 2.2µF

I_OUT= 10mA

C_OUT= 2.2µF

-80

-100

10

START 10.000Hz

100

1k

10k

100k

STOP 10 000 000.000Hz

1M

10M

-100

10

START 10.000Hz

100

1k

10k

100k

STOP 10 000 000.000Hz

1M

10M

Frequency (HZ)

Date: 5/5/06 Rev A

SP6200/6201 100/200mA CMOS LDO Regulator

13

PACKAGE: 5 PIN SOT-23

D

D/2

e1

SIDE VIEW

A2

5

4

E/2

E1/2

A

E

E1

Seating

Plane

A1

2

3

1

(L1)

Pin1 Designator

to be within this

INDEX AREA

(D/2 x E1/2)

e

b

TOP VIEW

ø1

FRONT VIEW

R1

Gauge Plane

R

L2

ø1

c

Seating

Plane

ø

L

5 Pin SOT-23

JEDEC MO-178

Variation AA

Dimensions in Inches

Conversion Factor:

1 Inch = 25.40 mm

Dimensions in Millimeters:

Controlling Dimension

SYMBOL

MIN

NOM

MAX

MIN

NOM

MAX

-

0.057

0.006

0.051

0.009

A

-

1.45

0.15

1.30

0.22

0.000

0.036

0.004

A1

A2

c

0.00

0.90

0.08

-

1.15

0.045

-

0.115 BSC

0.111 BSC

0.063 BSC

0.018

-

D

2.90 BSC

2.80 BSC

1.60 BSC

0.45

E

E1

L

0.012

0.024

0.30

0.60

L1

L2

R

0.60 REF

0.25 BSC

-

0.024 REF

0.010 BSC

-

0.004

0º

-

0.10

0º

-

4º

-

4º

0.010

8º

R1

Ø

0.25

8º

ø1

5º

10º

15º

0.50

5º

0.012

10º

-

0.038 BSC

0.075 BSC

15º

0.020

b

e

0.30

-

0.95 BSC

1.90 BSC

e1

SIPEX Pkg Signoff Date/Rev:

JL Oct3-05 / Rev A

Date: 5/5/06 Rev A

SP6200/6201 100/200mA CMOS LDO Regulator

14

PACKAGE: 8 PIN DFN

D2

D

D/2

D2/2

5

6

7

8

E/2

E2/2

E

E2

K

L

4

3

2

1

Pin1 Designator

to be within this

INDEX AREA

(D/2 x E/2)

INDEX AREA

(D/2 x E/2)

e

b

TOP VIEW

BOTTOM VIEW

ø

A

(A3)

A1

Seating Plane

SIDE VIEW

2x3 8 Pin DFN

JEDEC MO-229

VARIATION VCED-2

Dimensions in Inches

Conversion Factor:

1 Inch = 25.40 mm

Dimensions in Millimeters:

Controlling Dimension

SYMBOL

MIN

0.80

0.00

NOM

0.90

0.02

0.20 REF

MAX

1.00

0.05

MIN

0.032

0.000

NOM

0.036

0.001

0.008 REF

MAX

0.039

0.002

A

A1

A3

K

0.20

0º

0.18

-

0.008

0º

0.008

-

ø

-

0.25

14º

0.30

14º

0.012

b

0.010

D

D2

E

E2

e

L

2.00 BSC

-

3.00 BSC

-

0.50 BSC

0.40

0.079 BSC

-

0.118 BSC

-

0.020 BSC

0.016

1.50

1.60

0.30

1.75

1.90

0.50

0.059

0.063

0.012

0.069

0.075

0.020

SIPEX Pkg Signoff Date/Rev:

JL Aug18-05 / RevA

Date: 5/5/06 Rev A

SP6200/6201 100/200mA CMOS LDO Regulator

15

ORDERING INFORMATION

Temperature

Voltage

Option

ADJ

Package

Type

Part Number

Top Mark

Range

SP6200EM5

SP6200EM5/TR

-40˚C to +125˚C

5 Pin SOT-23

EADJ

E15

E18

E25

E27

E285

E30

E33

E35

E50

ADJ

SP6200EM5-1-5

SP6200EM5-1-5/TR

SP6200EM5-1-8

SP6200EM5-1-8/TR

SP6200EM5-2-5

SP6200EM5-2-5/TR

SP6200EM5-2-7

SP6200EM5-2-7/TR

SP6200EM5-2-85

SP6200EM5-2-85/TR

SP6200EM5-3-0

SP6200EM5-3-0/TR

SP6200EM5-3-3

SP6200EM5-3-3/TR

SP6200EM5-3-5

SP6200EM5-3-5/TR

SP6200EM5-5-0

SP6200EM5-5-0/TR

1.5V

1.8V

2.5V

2.7V

2.5V

2.85V 5 Pin SOT-23

3.0V

3.3V

3.5V

5.0V

5 Pin SOT-23

SP6201EM5

SP6201EM5/TR

-40˚C to +125˚C

ADJ

1.5V

1.8V

2.5V

2.7V

2.5V

5 Pin SOT-23

FADJ

F15

F18

F25

F27

F285

F30

F33

F35

F50

SP6201EM5-1-5

SP6201EM5-1-5/TR

SP6201EM5-1-8

SP6201EM5-1-8/TR

SP6201EM5-2-5

SP6201EM5-2-5/TR

SP6201EM5-2-7

SP6201EM5-2-7/TR

SP6201EM5-2-85

SP6201EM5-2-85/TR

SP6201EM5-3-0

SP6201EM5-3-0/TR

SP6201EM5-3-3

SP6201EM5-3-3/TR

SP6201EM5-3-5

SP6201EM5-3-5/TR

SP6201EM5-5-0

SP6201EM5-5-0/TR

2.85V 5 Pin SOT-23

3.0V

3.3V

3.5V

5.0V

5 Pin SOT-23

Available in lead free packaging. To order add "-L" suffix to part number.

Example: SP6200EM5-1-5/TR = standard; SP6200EM5-L-1-5/TR = lead free. Lead

Free SOT-23 packages can be identified by a Bar “|” to the left of the standard Top Marking.

/TR = Tape and Reel. Pack quantity is 2500 for SOT-23.

Sipex Corporation

Headquarters and

Sales Office

233 South Hillview Drive

Milpitas, CA 95035

TEL: (408) 934-7500

FAX: (408) 935-7600

Solved By SipexTM

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the

application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

Date: 5/5/06 Rev A

SP6200/6201 100/200mA CMOS LDO Regulator

16

ORDERING INFORMATION

Temperature

Voltage

Option

Package

Type

Part Number

Top Mark

Range

SP6200ER

SP6200ER/TR

SP6200ER-1-5

SP6200ER-1-5/TR

SP6200ER-1-8

SP6200ER-1-8/TR

SP6200ER-2-5

SP6200ER-2-5/TR

SP6200ER-2-7

SP6200ER-2-7/TR

SP6200ER-2-85

SP6200ER-2-85/TR

SP6200ER-3-0

SP6200ER-3-0/TR

SP6200ER-3-3

SP6200ER-3-3/TR

SP6200ER-3-5

SP6200ER-3-5/TR

SP6200ER-5-0

SP6200ER-5-0/TR

-40˚C to +125˚C

ADJ

8 Pin DFN

620-0ER

620-015

620-018

620-025

620-027

620-0285

620-030

620-033

620-035

620-050

1.5V

1.8V

2.5V

2.7V

2.5V

2.85V

3.0V

3.3V

3.5V

5.0V

SP6201ER

SP6201ER/TR

SP6201ER-1-5

SP6201ER-1-5/TR

SP6201ER-1-8

SP6201ER-1-8/TR

SP6201ER-2-5

SP6201ER-2-5/TR

SP6201ER-2-7

SP6201ER-2-7/TR

SP6201ER-2-85

SP6201ER-2-85/TR

SP6201ER-3-0

SP6201ER-3-0/TR

SP6201ER-3-3

SP6201ER-3-3/TR

SP6201ER-3-5

SP6201ER-3-5/TR

SP6201ER-5-0

SP6201ER-5-0/TR

-40˚C to +125˚C

ADJ

8 Pin DFN

620-1ER

620-115

620-118

620-125

620-127

620-1285

620-130

620-133

620-135

620-150

1.5V

1.8V

2.5V

2.7V

2.5V

2.85V

3.0V

3.3V

3.5V

5.0V

Available in lead free packaging. To order add "-L" suffix to part number.

Example: SP6200ER-1-5/TR = standard; SP6200ER-L-1-5/TR = lead free.

Lead Free DFN packages can be identified by a Bar “__” under the standard Top Marking.

/TR = Tape and Reel. Pack quantity is 3,000 for DFN.

Sipex Corporation

Headquarters and

Sales Office

233 South Hillview Drive

Milpitas, CA 95035

TEL: (408) 934-7500

FAX: (408) 935-7600

Solved By SipexTM

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the

application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

Date: 5/5/06 Rev A

SP6200/6201 100/200mA CMOS LDO Regulator

17


型号：	SP6200EM5-3-3-L/TR
厂家：	EXAR CORPORATION
描述：	Regulator,
文件：	总17页 (文件大小：479K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SP6200EM5-3-3-L/TR [EXAR]

相关型号：

SP6200EM5-3-3/TR

SP6200EM5-3-5

SP6200EM5-3-5

SP6200EM5-3-5-L

SP6200EM5-3-5-L/TR

SP6200EM5-3-5/TR

SP6200EM5-3.0

SP6200EM5-3.0-L

SP6200EM5-3.0/TR

SP6200EM5-3.3

SP6200EM5-3.3/TR

SP6200EM5-3.5