SP6205ER-L-2-8_技术文档

®

SP6203/6205

Low Noise, 300mA and 500mA CMOS LDO Regulators

FEATURES

FIXED

ADJUSTABLE

■ Very Low Dropout Voltage: 0.6Ω PMOS Pass

8

V_OUT

8

1

2

V_OUT

V

OUT

Device

ADJ

NC

SP6203

SP6205

SP6203

SP6205

■ Accurate Output Voltage: 2% over Temperature

■ Guaranteed 500mA Output Current: SP6205

■ Ultra Low Noise Output: 12µV_RMSwith 10nF

Bypass

BYP

7

6

5

2

3

4

NC

7

6

5

GND

EN

3

4

8 Pin DFN

V_IN

EN

V

IN

■ Unconditionally Stable with 2.2µF Ceramic

■ Low Quiescent Current: 45µA

■ Very Low Ground Current: 350µA at 500 mA

■ Power-Saving Shutdown Mode: < 1µA

■ Fast Turn-On and Turn-Off: 60µS

■ Fast Transient Response

Now Available in Lead Free Packaging

APPLICATIONS

■ Current Limit and Thermal Shutdown Protection

■ Very Good Load/Line Regulation: 0.07/0.04%

■ Excellent PSRR: 67dB < 1kHz

■ Industry Standard SOT-23-5 and Small 8 pin

2X3 DFN Package

■ Fixed Output Voltages: 2.5V, 2.7V, 2.8V,

■ Cellular / GSM Phones

■ Laptop / Palmtop Computers

■ Battery-Powered Systems

■ Pagers

■ Medical Devices

■ MP3/CD Players

2.85V, 3.0V and 3.3V

■ Adjustable Output Available

■ Digital Still Cameras

DESCRIPTION

The SP6203/6205 are ultra low noise CMOS LDOs with very low dropout and ground current. The noise

performance is achieved by means of an external bypass capacitor without sacrificing turn-on and turn-off

speedcriticaltoportableapplications.Extremelystableandeasytouse,thesedevicesofferexcellentPSRR

and Line/Load regulation. Target applications include battery-powered equipment such as portable and

wirelessproducts.Regulators'groundcurrentincreasesonlyslightlyindropout.Fastturn-on/turn-offenable

control and an internal 30Ω pull down on output allows quick discharge of output even under no load

conditions. Both LDOs are protected with current limit and thermal shutdown.

Both LDOs are available in fixed & adjustable output voltage versions and come in an industry standard

SOT-23 5-pin and small 2X3 8pin DFN packages. For SC-70 100mA CMOS LDO, SP6213 is available.

TYPICAL APPLICATION CIRCUIT

V

IN

V

OUT

1

2

3

5

4

1

2

3

5

4

C

2.2µF

IN

C

OUT

2.2µF Ceramic

C

OUT

2.2µF Ceramic

2.2µF

SP6203

SP6205

SP6203

SP6205

5-Pin

ADJUSTABLE

5-Pin

FIXED

ADJ

EN

BYP

Date: 12/19/05

SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators

1

OPERATING RATINGS

ABSOLUTE MAXIMUM RATINGS

Input Voltage (V_IN)...........................................+2.7V to +5.5V

Enable Input Voltage (V_EN)...........................................0 to 5.5V

Junction Temperature (T_J)...........................................-40°C to +125°C

Thermal Resistance, SOT-23-5 (θ_JA)...........................................Note 1

Thermal Resistance, SOT-23-6 (θ_JA)...........................................Note 1

Supply Input Voltage (V_IN)..........................................................-2V to 6V

Output Voltage (V_OUT).....................................................-0.6V to V_IN+1V

Enable Input Voltage (V_EN)........................................................-2V to 6V

Power Dissipation (P_D)......................................Internally Limited, Note 1

Lead Temperature (soldering 5s)...........................................+260°C

Storage Temperature.....................................................-65°C to +150°C

Junction Temperature..........................................................+150°C

Remark: The device is not guaranteed to function outside its operating rating.

Thesearestressratingsonlyandfunctionaloperationofthedeviceatthese

ratings or any other above those indicated in the operation sections of the

specifications below is not implied. Exposure to absolute maximum rating

conditions for extended periods of time may affect reliability.

ELECTRICAL SPECIFICATIONS

Unless otherwise specified: V_IN=V_OUT+ 0.5V to 6V, C_OUT= 2.2µF ceramic, C_IN= 2.2µF, I_OUT=100µA,

-40°C < T < 125°C. The ♦ denotes the specifications which apply over full operating temperature range -40°C to

+125°C, unless otherwise specified.

PARAMETER

MIN

TYP

MAX

6

UNITS

V

♦

CONDITIONS

Input Voltage

Output Voltage Accuracy

-2

+2

%

Variation from specified V_OUT

Output Voltage

50

ppm/°C

∆V_OUT/∆T

Temperature Coefficient, Note2

Reference Voltage

Line Regulation

1.225

1.25

0.04

1.275

0.3

V

%/V

%

♦

Adjustable version only

∆V_OUT(V_INbelow 6V)

Load Regulation, Note 3

0.07

0.13

0.3

0.5

I_OUT= 0.1mA to 300mA (SP6203)

I_OUT= 0.1mA to 500mA (SP6205)

Dropout Voltage for V_OUT> 3.0V,

Note 4

0.06

60

I_OUT= 0.1mA

I_OUT= 100mA

120

180

300

mV

I_OUT= 200mA

I_OUT= 300mA (SP6203)

I_OUT= 500mA (SP6205)

300

500

♦

Ground Pin Current, Note 5

45

100

♦

I_OUT= 0.1mA (I_QUIESCENT

)

110

175

235

350

I_OUT= 100mA

I_OUT= 200mA

I_OUT= 300mA (SP6203)

I_OUT= 500mA (SP6205)

µA

330

490

♦

Shutdown Supply Current

Current Limit

0.01

1

µA

♦

V_EN< 0.4V (shutdown)

0.33

0.55

0.50

0.85

0.8

1.4

A

V_OUT= ZeroV (SP6203)

V_OUT= ZeroV (SP6205)

Thermal Shutdown Junction

Temperature

170

°C

Regulator Turns off

Thermal Shutdown Hysteresis

Power Supply Rejection Ratio

Output Noise Voltage, Note 6

12

67

°C

Regulator turns on again at 158°C

f ≤ 1kHz

dB

150

630

12

C_BYP= 0nF, I_OUT= 0.1mA

C_BYP= 0nF, I_OUT=300mA

C_BYP= 10nF, I_OUT= 0.1mA

C_BYP= 10nF, I_OUT= 300mA

µV_RMS

50

75

Thermal Regulation, Note 7

0.05

25

%/W

∆V_OUT/∆P_D

Wake-Up Time (T_WU), Note 8

(from shutdown mode)

50

µs

V

_IN≥ 4V, Note 10

I_OUT= 30mA

V_IN≥ 4V, Note 10

Turn-On Time (T_ON), Note 9

(from shutdown mode)

60

120

µs

I_OUT= 30mA

Turn-Off Time (T_OFF),

100

15

250

25

I_OUT= 0.1mA, V_IN≥ 4V, Note 10

I_OUT= 300mA, V_IN≥ 4V, Note 10

Output Discharge Resistance

Enable Input Logic Low Voltage

Enable Input Logic High Voltage

30

Ω

V

No Load

0.4

♦

Regulator Shutdown

Regulator Enabled

1.6

Date: 12/19/05

SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators

2

ELECTRICAL SPECIFICATIONS NOTES

Note 1: Maximum power dissipation can be calculated using the formula: P_D= (T_J(max)- T_A) / θ_JA, where T_J(max)is

the junction temperature, T_Ais the ambient temperature and θ_JAis the junction-to-ambient thermal resistance. θ_JC

is 6°C/W for this package. Exceeding the maximum allowable power dissipation will result in excessive die

temperature and the regulator will go into thermal shutdown mode. θ_JAis 191°C/W for SOT-23-5, and is 59°C/W

for the 8-pin DFN. A part mounted on a PC board will deliver improved thermal performance based upon copper

surface area.

Note 2: Output voltage temperature coefficient is defined as the worst case voltage change divided by the total

temperature range.

Note 3: Regulation is measured at constant junction temperature using low duty cycle pulse testing. Changes in

output voltage due to heating effects are covered by the thermal regulation specification.

Note 4: Dropout-voltage is defined as the input to output differential at which the output voltage drops 2% below its

nominal value measured at 1V differential.

Note 5: Ground pin current is the regulator quiescent current. The total current drawn from the supply is the sum of

the load current plus the ground pin current.

Note 6: Output noise voltage is defined within a certain bandwidth, namely 10Hz < BW < 100kHz. An external

bypass cap (10nF) from reference output (BYP pin) to ground significantly reduces noise at output.

Note 7: Thermal regulation is defined as the change in output voltage at a time “t” after a change in power

dissipation is applied, excluding load and line regulation effects. Specifications are for a 300mA load pulse at V_IN

6V for t = 1ms.

=

Note 8: The wake-up time (T_WU) is defined as the time it takes for the output to start rising after enable is brought

high.

Note 9: The total turn-on time is called the settling time (T_S), which is defined as the condition when both the

output and the bypass node are within 2% of their fully enabled values when released from shutdown.

Note 10: For output voltage versions requiring VIN to be lower than 4V, timing (T_ON& T_OFF) increases slightly.

FUNCTIONAL DIAGRAM

V

OUT

V

IN

V

OUT

IN

EN

1.25V

bandgap

reference

1.25V

bandgap

reference

R1

BYP

ADJ

R2

current limit

Cbyp

(optional)

&

thermal shutdown

GND

Low Noise Fixed Regulator - 5 Pin

Low Noise Adjustable Regulator - 5 Pin

Date: 12/19/05

SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators

3

PIN DESCRIPTION

5 PIN OPTION

PIN NUMBER

NAME

V_IN

FUNCTION

1

2

3

Power Supply Input

Ground Terminal

GND

EN

Enable/Shutdown (Logic high = enable, logic

low = shutdown)

4 (Fixed)

4 (adj.)

5

BYP

ADJ

V_OUT

Reference bypass input for ultra-quiet operation.

Connecting a 10nF cap on this pin reduces

output noise.

Adjustable (Input): Adjustable regulator feed-

back input. Connect to a resistive voltage-

divider network.

Regulator Output Voltage

PINOUT 5 PIN SOT-23

V

EN GND

IN

V

1

GND

EN

3

IN

3

2

1

2

SIPEX

4

5

V

OUT

V

OUT

ADJ

BYP

Fixed Voltage Regulator

Adjustable Voltage Regulator

Date: 12/19/05

SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators

4

PIN DESCRIPTION

8 PIN OPTION

8 PIN DFN

PIN CONFIGURATION

PIN NUMBER

1(fixed)

NAME

FUNCTION

V_OUT

Regulator Output Voltage. Connect to Pin 8

V_OUT.

1(Adj)

ADJ

Adjustable (Input): Adjustable regulator feed-

back input. Connect to a resistive voltage-

divider network.

2(fixed)

BYP

Reference bypass input for ultra-quiet operation.

Connecting a 10nF cap on this pin reduces

output noise.

2(Adj)

NC

GND

EN

No Connect

Ground

3

4

Enable/Shutdown (Logic high = enable, logic

low = shutdown)

5

6

7

8

V_IN

NC

Power Supply Input

No Connect

NC

No Connect

V_OUT

Regulator Output VoltageA

PINOUT 8 PIN DFN

FIXED

ADJUSTABLE

V_OUT

8

1

2

V_OUT

V

ADJ

NC

OUT

SP6203

SP6205

SP6203

SP6205

BYP

7

6

5

2

3

4

NC

7

6

5

NC

GND

3

4

GND

EN

8 Pin DFN

V_IN

EN

V

IN

Date: 12/19/05

SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators

5

TYPICAL PERFORMANCE CHARACTERISTICS

V

OUT

V

OUT

I

(200mA/DIV)

O

V

EN

Current Limit

Turn on Time, R_LOAD= 50Ω (60mA)

V

OUT

V

OUT

V

EN

V

EN

Turn off Time, R_LOAD= 30K (0.1mA)

Turn off Time, R_LOAD= 6Ω (500mA)

V

OUT

(AC)

V

(AC)

OUT

V

IN

I

OUT

Load Regulation, I_O= 100µA ~ 500mA

Line Regulation, Line Step from 4V to 6V, I_O= 1mA

Date: 12/19/05

SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators

6

TYPICAL PERFORMANCE CHARACTERISTICS: Continued

V

IN

V

EN

V

OUT

V

OUT

V

= 3.5V, I = 500mA

O

IN

BYP

Start Up Waveform, V_IN= 3.5V, I_O= 500mA

Start Up Waveform, Slow V_IN, No Load

V

IN

V

OUT

V

OUT

BYP

Start Up Waveform, Slow V_IN, 500mA Output Load

Start Up Waveform, Slow V_IN, C_OUT=1000µF, I_O=0mA

V

IN

V

IN

V

OUT

V

OUT

BYP

Start Up Waveform, Slow V_IN, C_OUT=1000µF, I_O=500mA

Fast V_IN, No Load

Date: 12/19/05

SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators

7

TYPICAL PERFORMANCE CHARACTERISTICS: Continued

V

IN

V

OUT

BYP

Fast V_IN, 500mA Output Load

Fast V_IN= 1000µF Output Load

V

IN

V

OUT

BYP

Fast V_IN, C_OUT=1000µF, I_O=500mA

Date: 12/19/05

SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators

8

THEORY OF OPERATION

General Overview

Output Capacitor

The SP6203/6205 is intended for applications

where very low dropout voltage, low supply

current and low output noise are critical, even

with high load conditions (500mA maximum).

An output capacitor is required between V_OUT

and GND to prevent oscillation. A 2.2µF output

capacitor is recommended.

Larger values make the chip more stable which

means an improvement of the regulator’s tran-

sient response. Also, when operating from other

sources than batteries, supply-noise rejection

can be improved by increasing the value of the

input and output capacitors and using passive

filtering techniques.

Unlike bipolar regulators, the SP6203/6205

(CMOS LDO) supply current increases only

slightly with load current.

The SP6203/6205 contains an internal bandgap

reference which is fed into the inverting input of

the LDO-amplifier. The output voltage is then

set by means of a resistor divider and compared

to the bandgap reference voltage. The error

LDO-amplifier drives the gate of a P-channel

MOSFET pass device that has a R_DS(ON)of 0.6Ω

at 500mA producing a 300mV drop at the out-

put.

For a lower output current, a smaller output

capacitance can be chosen.

Finally, the output capacitor should have an

effectiveseriesresistance(ESR)of0.5Ωorless.

Therefore, the use of good quality ceramic or

tantalum capacitors is advised.

Furthermore, the SP6203/6205 has its own cur-

rent limit circuitry (500mA/850mA) to ensure

that the output current will not damage the

device during output short, overload or start-up.

Bypass Capacitor

A bypass pin (BYP) is provided to decouple the

bandgap reference. A 10nF external capacitor

connected from BYP to GND reduces noise

present on the internal reference, which in turn

significantly reduces output noise and also im-

proves power supply rejection. Note that the

minimum value of C_OUTmust be increased to

maintain stability when the bypass capacitor is

used because C_BYPreduces the regulator phase

margin. If output noise is not a concern, this

input may be left unconnected. Larger capacitor

values may be used to further improve power

supply rejection, but result in a longer time

period (slower turn on) to settle output voltage

when power is initially applied.

Also, the SP6203/6205 includes thermal shut-

down circuitry to turn off the device when the

junction temperature exceeds 170°C and it re-

mains off until the temperature drops by 12°C.

Enable/Shutdown Operation

The SP6203/6205 is turned off by pulling the

V

_ENpin below 0.4V and turned on by pulling it

above 1.6V.

If this enable/shutdown feature is not required,

it should be tied directly to the input supply

voltage to keep the regulator output on at all

time.

While in shutdown, V_OUTquickly falls to zero

(turn-off time is dependent on load conditions

and output capacitance on V_OUT) and power

consumption drops nearly to zero.

No Load Stability

The SP6203/6205 will remain stable and in

regulation with no external load (other than the

internal voltage driver) unlike many other volt-

age regulators. This is especially important in

CMOS RAM battery back-up applications.

Input Capacitor

A small capacitor of 2.2µF is required from V_IN

to GND if a battery is used as the power

source. Any good quality electrolytic, ceramic

or tantalum capacitor may be used at the input.

Date: 12/19/05

SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators

9

THEORY OF OPERATION: Continued

Turn On Time

T

_J(max)is the maximum junction temperature of

the die and is 125°C. T_Ais the ambient tempera-

ture. θ_JAis the junction-to-ambient thermal re-

sistance for the regulator and is layout depen-

dent. The SOT-23-5 package has a θJ_Aof

approximately 256°C/W for minimum PCB

copper footprint area.

The turn on response is split up in two separate

response categories: the wake up time (T_WU

)

and the settlling time (T_S). The wake up time is

defined as the time it takes for the output to rise

to 2% of its total value after being released from

shutdown (E_N> 0.4V). The settling time is

definedastheconditionwheretheoutputreaches

98% of its total value after being released from

shutdown. The latter is also called the turn on

time and is dependent on the output capacitor, a

little bit on load and, if present, on a bypass

capacitor.

This results in a maximum power dissipation of:

P_D(max)= [(125°C - 25°C)/(191°C/W)] = 523mW

The actual power dissipation of the regulator

circuit can be determined using one simple

equation:

P_D= (V_IN- V_OUT) * I_OUT+ V_IN* I_GND

t(s) = T(on)

V

ENABLE

To prevent the device from entering thermal

shutdown. maximum power dissipation can not

be exceeded.

98%

2%

t(wu)

V

OUT

Substituting P_D(max)for P_Dand solving for the

operating conditions that are critical to the ap-

plication will give the maximum operating con-

ditions for the regulator circuit. For example, if

we are operating the SP6203 3.0V at room

temperature, with a minimum footprint layout

and and output current of 300mA, the maximum

input voltage can be determined, based on the

equationbelow.Groundpincurrentcanbetaken

from the electrical specifications table (0.23mA

at 300mA).

Turn Off Time

The turn off time is defined as the condition

where the output voltage drops about 66% (θ) of

its total value. 5θ to 7θ is the constant where the

output voltage drops nearly to zero. There will

always be a small voltage drop in shutdown

because of the switch unless we short-circuit it.

The turn off time of the output voltage is depen-

dent on load conditions, output capacitance on

V_OUT(time constant τ = R_LC_L) and also on the

difference in voltage between input and output.

390mW = (V_IN-3.0V) * 300mA + V_IN*0.23mA

After calculations, we find that the maximum

input voltage of a 3.0V application at 300mA of

output current in a SOT-23-5 package is 4.7V.

Thermal Considerations

The SP6203/6205 is designed to provide 300/

500 mA of continuous current in a tiny package.

Maximum power dissipation can be calculated

based on the output current and the voltage drop

across the part. To determine the maximum

power dissipation of the package, use the junc-

tion-to-ambient thermal resistance of the device

and the following basic equation:

So if the intend is to operate a 5V output version

from a 6V supply at 300mA load and at a 25°C

ambienttemperature,thentheactualtotalpower

dissipation will be:

P_D=([6V-5V]*[300mA])+(6V*0.23mA)=301.4mW

This is well below the 523mW package maxi-

mum. Therefore, the regulator can be used.

P_D= (T_J(max)- T_A) / θJ_A

Date: 12/19/05

SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators

10

THEORY OF OPERATION: Continued

Layout Considerations

Note that the regulator cannot always be used at

its maximum current rating. For example, in a

5V input to 3.0V output application at an ambi-

ent temperature of 25°C and operating at the full

500mA (I_GND= 0.355mA) load, the regulator is

limited to a much lower load current, deter-

mined by the following equation:

The primary path of heat conduction out of the

package is via the package leads. Therefore,

careful considerations have to be taken into

account:

1) Attaching the part to a larger copper footprint

will enable better heat transfer from the device,

especially on PCB’s where there are internal

ground and power planes.

523mW = ( [5V-3V]*[ I_load(max)]) +(5V*0.350mA)

After calculation, we find that in such an appli-

cation (SP6205) the regulator is limited to

260.6mA. Doing the same calculations for the

300mALDO(SP6203)willlimittheregulator’s

output current to 260.9mA.

2) Place the input, output and bypass capacitors

close to the device for optimal transient re-

sponse and device behavior.

3) Connect all ground connections directly to

the ground plane. In case there’s no ground

plane, connect to a common local ground point

before connecting to board ground.

Also, taking advantage of the very low dropout

voltage characteristics of the SP6203/6205,

power dissipation can be reduced by using the

lowest possible input voltage to minimize the

input-to-output drop.

Such layouts will provide a much better thermal

conductivity (lower θ_JA) for, a higher maximum

allowable power dissipation limit.

Adjustable Regulator Applications

The SP6203/6205 can be adjusted to a specific

output voltage by using two external resistors

(see functional diagram). The resistors set the

output voltage based on the following equation:

V_OUT= V_REF*(R1/R2 + 1)

Resistor values are not critical because ADJ

(adjust) has a high input impedance, but for best

performance use resistors of 470KΩ or less. A

bypass capacitor from ADJ to V_OUTprovides

improved noise performance.

Dual-Supply Operation

When used in dual supply systems where the

regulator load is returned to a negative supply,

the output voltage must be diode clamped to

ground.

Date: 12/19/05

SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators

11

PACKAGE: 5 PIN SOT-23

D

D/2

e1

SIDE VIEW

5

4

E/2

E1/2

A2

A

E

E1

Seating

Plane

A1

2

3

1

(L1)

Pin1 Designator

to be within this

INDEX AREA

(D/2 x E1/2)

e

b

TOP VIEW

ø1

FRONT VIEW

R1

Gauge Plane

R

L2

ø1

c

Seating

Plane

ø

L

5 Pin SOT-23

JEDEC MO-178

Variation AA

Dimensions in Inches

Conversion Factor:

1 Inch = 25.40 mm

Dimensions in Millimeters:

Controlling Dimension

SYMBOL

MIN

NOM

MAX

MIN

NOM

MAX

-

0.057

0.006

0.051

0.009

A

-

1.45

0.15

1.30

0.22

0.000

0.036

0.004

A1

A2

c

D

E

0.00

0.90

0.08

-

1.15

-

2.90 BSC

2.80 BSC

1.60 BSC

0.45

0.045

-

0.115 BSC

0.111 BSC

0.063 BSC

0.018

E1

L

0.012

0.024

0.30

0.60

L1

L2

R

R1

Ø

0.60 REF

0.25 BSC

-

0.024 REF

0.010 BSC

-

0.004

0º

-

0.10

0º

-

4º

-

4º

0.010

8º

0.25

8º

ø1

5º

0.30

10º

-

0.95 BSC

1.90 BSC

15º

0.50

5º

0.012

10º

-

0.038 BSC

0.075 BSC

15º

0.020

b

e

e1

SIPEX Pkg Signoff Date/Rev:

JL Oct3-05 / Rev A

Date: 12/19/05

SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators

12

PACKAGE: 8 PIN DFN

D2

D

D/2

D2/2

5

6

7

8

E/2

E2/2

E

E2

K

L

4

3

2

1

Pin1 Designator

to be within this

INDEX AREA

(D/2 x E/2)

INDEX AREA

(D/2 x E/2)

e

b

TOP VIEW

BOTTOM VIEW

ø

A

(A3)

A1

Seating Plane

SIDE VIEW

2x3 8 Pin DFN

JEDEC MO-229

VARIATION VCED-2

Dimensions in Inches

Conversion Factor:

1 Inch = 25.40 mm

Dimensions in Millimeters:

Controlling Dimension

SYMBOL

MIN

0.80

0.00

NOM

0.90

0.02

0.20 REF

MAX

1.00

0.05

MIN

0.032

0.000

NOM

0.036

0.001

0.008 REF

MAX

0.039

0.002

A

A1

A3

K

Ø

b

0.20

0º

0.18

-

0.008

0º

0.008

-

0.25

14º

0.30

14º

0.012

0.010

D

D2

E

E2

e

2.00 BSC

-

3.00 BSC

-

0.50 BSC

0.40

0.079 BSC

-

0.118 BSC

-

0.020 BSC

0.016

1.50

1.60

0.30

1.75

1.90

0.50

0.059

0.063

0.012

0.069

0.075

0.020

L

SIPEX Pkg Signoff Date/Rev:

JL Aug18-05 / RevA

Date: 12/19/05

SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators

13

ORDERING INFORMATION

Top

Marking

Temperature Voltage Package

Part Number

Range

Option

Type

SP6203EM5-1-8

SP6203EM5-1-8/TR

SP6203EM5-2-5

SP6203EM5-2-5/TR

SP6203EM5-2-7

SP6203EM5-2-7/TR

SP6203EM5-2-8

SP6203EM5-2-8/TR

SP6203EM5-2-85

SP6203EM5-2-85/TR

SP6203EM5-3-0

SP6203EM5-3-0/TR

SP6203EM5-3-3

SP6203EM5-3-3/TR

SP6203EM5

N2WW

L2WW

G2WW

Q3WW

H2WW

M2WW

J2WW

Q2WW

-40˚C to +125˚C

1.8

V

5 Pin SOT-23

2.5V

2.7V

2.8V

2.85V

3.0V

3.3V

ADJ

SP6203EM5 /TR

ADJ

SP6203ER-1-8

SP6203ER-1-8/TR

SP6203ER-2-5

SP6203ER-2-5/TR

SP6203ER-2-7

SP6203ER-2-7/TR

SP6203ER-2-8

SP6203ER-2-8/TR

SP6203ER-2-85

SP6203ER-2-85/TR

SP6203ER-3-0

SP6203ER-3-0/TR

SP6203ER-3-3

SP6203ER-3-3/TR

SP6203ER

620318YWW

620325YWW

620327YWW

620328YWW

620385YWW

620330YWW

620333YWW

-40˚C to +125˚C

1.8

V

8 Pin DFN

2.5V

2.7V

2.8V

2.85V

3.0V

3.3V

ADJ

6203ERYWW -40˚C to +125˚C

SP6203ER /TR

ADJ

Available in lead free packaging. To order add "-L" suffix to part number.

Example: SP6203ER-ADJ/TR = standard; SP6203ER-L-ADJ/TR = lead free.

/TR = Tape and Reel.

Pack quantity is 2,500 for SOT-23 and 3,000 for DFN.

TOP MARKING note: "WW" for SOT-23 package is datecode Work Week. "YWW for DFN package is

datecode Year & Work Week. Lead Free SOT-23 packages can be identified by a Bar "|" to the left of the standard

__

Top Marking. Lead Free DFN packages can be identified by a Bar " " under the standard Top Marking.

Sipex Corporation

Headquarters and

Corporation

Sales Office

233 South Hillview Drive

Milpitas, CA 95035

TEL: (408) 934-7500

FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products

described herein. Sipex does not assume any liability arising out of the

application or use of any product or circuit described herein; neither

does it convey any license under its patent rights nor the rights of others.

ANALOG EXCELLENCE

Date: 12/19/05

SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators

14

ORDERING INFORMATION

Top

Temperature Voltage Package

Part Number

Marking

X2WW

V2WW

R2WW

E3WW

S2WW

W2WW

T2WW

A3WW

Range

Option

Type

SP6205EM5-1-8

SP6205EM5-1-8/TR

SP6205EM5-2-5

SP6205EM5-2-5/TR

SP6205EM5-2-7

SP6205EM5-2-7/TR

SP6205EM5-2-8

SP6205EM5-2-8/TR

SP6205EM5-2-85

SP6205EM5-2-85/TR

SP6205EM5-3-0

SP6205EM5-3-0/TR

SP6205EM5-3-3

SP6205EM5-3-3/TR

SP6205EM5

-40˚C to +125˚C

1.8

V

5 Pin SOT-23

1

.8

2.5V

2.7V

2.8V

2.85V

3.0V

3.3V

ADJ

SP6205EM5 /TR

ADJ

SP6205ER-1-8

SP6205ER-1-8/TR

SP6205ER-2-5

SP6205ER-2-5/TR

SP6205ER-2-7

SP6205ER-2-7/TR

SP6205ER-2-8

SP6205ER-2-8/TR

SP6205ER-2-85

SP6205ER-2-85/TR

SP6205ER-3-0

SP6205ER-3-0/TR

SP6205ER-3-3

SP6205ER-3-3/TR

SP6205ER

520518YWW

520525YWW

520527YWW

520528YWW

520585YWW

520530YWW

520533YWW

-40˚C to +125˚C

1

.8

V

8 Pin DFN

2.5V

2.7V

2.8V

2.85V

3.0V

3.3V

ADJ

5205ERYWW -40˚C to +125˚C

SP6205ER /TR

ADJ

Available in lead free packaging. To order add "-L" suffix to part number.

Example: SP6205ER-ADJ/TR = standard; SP6205ER-L-ADJ/TR = lead free.

/TR = Tape and Reel.

Pack quantity is 2,500 for SOT-23 and 3,000 for DFN.

TOP MARKING note: "WW" for SOT-23 package is datecode Work Week. "YWW for DFN package is

datecode Year & Work Week. Lead Free SOT-23 packages can be identified by a Bar "|" to the left of the standard

__

Top Marking. Lead Free DFN packages can be identified by a Bar " " under the standard Top Marking.

Sipex Corporation

Corporation

Headquarters and

Sales Office

233 South Hillview Drive

ANALOG EXCELLENCE

Sipex Corporation reserves the right to make changes to any products

described herein. Sipex does not assume any liability arising out of the

Milpitas, CA 95035

application or use of any product or circuit described herein; neither

TEL: (408) 934-7500

does it convey any license under its patent rights nor the rights of others.

FAX: (408) 935-7600

Date: 12/19/05

SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators

15


型号：	SP6205ER-L-2-8
厂家：	EXAR CORPORATION
描述：	Fixed Positive LDO Regulator, 2.8V, CMOS, PDSO8, 2 X 3 MM, LEAD FREE, MO-229VCED-2, DFN-8 光电二极管输出元件调节器
文件：	总15页 (文件大小：219K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SP6205ER-L-2-8 [EXAR]

相关型号：

SP6205ER-L-2-8/TR

SP6205ER-L-2-8/TR

SP6205ER-L-2-85/TR

SP6205ER-L-2-85/TR

SP6205ER-L-2.5/TR

SP6205ER-L-2.7/TR

SP6205ER-L-2.8

SP6205ER-L-2.8/TR

SP6205ER-L-2.85

SP6205ER-L-2.85/TR

SP6205ER-L-3-3

SP6205ER-L-3-3