SP6330EK1-LZFDTR [EXAR]
4-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, LEAD FREE, MO-193BA, TSOT-8;
| 型号： | SP6330EK1-LZFDTR |
| 厂家： | 
EXAR CORPORATION |
| 描述： | 4-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, LEAD FREE, MO-193BA, TSOT-8 光电二极管 |
| 文件： | 总13页 (文件大小：296K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SP6330, SP6332
and SP6334
Quad µPower Supervisory Circuits
with Manual Reset & Watchdog
FEATURES
1
8
7
6
5
RSTB
WDI
V1
■ Low operating voltage of 1.6V
■ Low operating current of 20µA typical
■ Monitors up to four supplies simultaneously
■ Adjustable inputs monitor down to 0.5V
■ Reset asserted down to 0.9V
SP6330
2
3
4
V2
MRIB
V3
8 Pin TSOT
GND
V4
■ 2% accuracy over temperature range
■ Open Drain (OD) or CMOS RSTB output or
CMOS RST output
Open Drain RESET
■ 4 Reset Timeout Periods:
SEE PAGE 2 FOR OTHER
AVAILABLE PINOUTS
50ms, 100ms, 200ms and 400 ms
■ Watch Dog Input Functionality -- WDI
■ Manual Reset Input (Active Low) -- MRIB
■ 8 Pin TSOT package
Available in Lead Free Packaging
DESCRIPTION
SP6330-SP6332- SP6334 Quad Power Supervisory Circuit Family is a family of
microprocessor reset supervisory circuits with multiple reset voltages. The family provides
low voltage monitoring ability for up-to four supplies with two precision factory-set thresholds
and two user defined custom thresholds. These circuits perform a single function: if any of
the input supply voltages drops below its associated threshold, reset outputs are asserted.
The SP6330, SP6332, and SP6334 are packaged in an 8-pin TSOT package. All devices are
fully specified over -40oC to +85oC temperature range.
TYPICAL APPLICATION CIRCUIT
Date: 4/10/06 Rev K
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
1
PINOUT DIAGRAMS
1
2
3
4
8
7
6
5
RSTB
WDI
1
2
3
4
8
7
6
5
RST
WDI
1
2
3
4
8
7
6
5
RSTB
WDI
V1
V2
V1
V2
V1
V2
SP6332
8 Pin TSOT
SP6334
8 Pin TSOT
SP6330
8 Pin TSOT
MRIB
V3
GND
V4
MRIB
V3
GND
V4
MRIB
V3
GND
V4
CMOS RESET
Reset
CMOS RESET
WDI
Open Drain RESET
PART
V1 V2 V3 V4
MRIB
NUMBER
SP6330
SP6332
SP6334
√
√
√
√
√
√
√
√
√
√
√
√
OD Active Low
√
√
√
√
√
√
CMOS Active Low
CMOS Active High
Feature and Pinout Diagram
Representative Samples Available
Sipex
Product
Product
V1
V2
V3
V4
Reset
Package
Ordering #
(Volts)
(Volts)
(Volts)
(Volts)
(ms)
Description
Quad Supervisor
Open Drain low
Quad Supervisor
Open Drain low
Quad Supervisor
Open Drain low
Quad Supervisor
CMOS low
SP6330
SP6330
SP6330
SP6332
8 Pin TSOT
8 Pin TSOT
8 Pin TSOT
8 Pin TSOT
2.925
3.075
4.625
2.625
1.575
2.313
2.313
1.575
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
200
200
200
200
SP6330EK1-L-W-G-C
SP6330EK1-L-X-J-C
SP6330EK1-L-Z-J-C
SP6330EK1-L-V-G-C
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections
of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability
and cause permanent damage to the device.
Operating Temperature
Terminal Voltage (with respect to GND)
Range...............................................-40°C to +85°C
V1, V2..................................................... -0.3 to +6V
Storage Temperature
Open-DrainRSTB.......................................-0.3to+6V
Range...............................................-65°C to 150°C
CMOS RST, RSTB, ..................... -0.3 to (V1+0.3V)
Input Current/Output
Current..................................,,........................20mA
Thermal Resistance QJA..............................134°C/W
V3, V4, MRIB, WDI........................-0.3 to (V1+0.3V)
Date: 4/10/06 Rev K
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
2
ELECTRICAL CHARACTERISTICS
PARAMETER MIN
TYP MAX UNITS
CONDITIONS
V1 =1.6V to 5.5V; TA = -40ºC to +85ºC; unless otherwise noted. Typical values are at TA =+25ºC
Operating Voltage
Range
0.9
5.5
30
25
V
T = -40ºC to +85ºC
A
V1 < 5.5V, V2 < 3.60V, all I/O
pins open
V1 < 3.6V, V2 < 2.75V, all I/O
pins open
20
15
uA
Supply Current
4.532
4.287
3.013
2.866
2.572
2.273
2.146
1.636
1.548
2.266
2.144
1.631
1.543
1.360
1.286
1.087
1.029
0.816
0.772
4.625
4.375
3.075
2.925
2.625
2.320
2.190
1.670
1.580
2.313
2.188
1.665
1.575
1.388
1.313
1.110
1.050
0.833
0.788
4.718
4.463
3.137
2.984
2.678
2.367
2.234
1.704
1.612
2.360
2.232
1.698
1.607
1.416
1.340
1.133
1.071
0.850
0.804
Z (valid for V1 falling)
Y (valid for V1 falling)
X (valid for V1 falling)
W (valid for V1 falling)
V (valid for V1 falling)
U (valid for V1 falling)
T (valid for V1 falling)
S (valid for V1 falling)
R (valid for V1 falling)
J (valid for V2 falling)
I (valid for V2 falling)
H (valid for V2 falling)
G (valid for V2 falling)
F (valid for V2 falling)
E (valid for V2 falling)
D (valid for V2 falling)
C (valid for V2 falling)
B (valid for V2 falling)
A (valid for V2 falling)
V1 Reset
Threshold
V
V2 Reset
Threshold
V
Threshold 1
Tempco
Threshold 2
Tempco
Threshold 1
Hysteresis
Threshold 2
Hysteresis
0.06
0.04
0.65
0.5
mV/ºC
mV/ºC
%
reference to Vth1 typical
reference to Vth2 typical
%
V1 to RST/RSTB
Delay
V1 = Vth1 to (Vth1-0.1V), Vth1
= 3.075
50
us
V2 to RST/RSTB
Delay
V2 = Vth2 to (Vth2-0.1V), Vth2
= 1.575
50
us
Reset Timeout
Period (T1)
Reset Timeout
Period (T2)
Reset Timeout
Period (T3)
Reset Timeout
Period (T4)
37
74
50
63
ms
TOPT-1
TOPT-2
TOPT-3
TOPT-4
100
200
400
126
252
504
ms
148
296
ms
ms
Date: 4/10/06 Rev K
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
3
ELECTRICAL CHARACTERISTICS
PARAMETER MIN
TYP MAX UNITS
CONDITIONS
V1 =1.6V to 5.5V; TA = -40ºC to +85ºC; unless otherwise noted. Typical values are at TA =+25ºC
V3 RESET COMPARATOR INPUT
V3 Input Threshold
V3 Input Current
V3 Threshold
Hysteresis
V4 RESET COMPARATOR INPUT
V4 Input Threshold
V4 Input Current
V4 Threshold
490
-50
500
1.5
500
1.5
510
50
mV
nA
T
A
= +25ºC
= +25ºC
mV
490
-50
510
50
mV
nA
TA
mV
Hysteresis
MRIB - MANUAL RESET INPUT
MRIB Input
Threshold
0.2*V1
V
V
Vil
Vih
MRIB Input
Threshold
0.8*V1
MRIB Minimum
Input Pulse Width
MRIB Glitch
Rejection
MRIB to RST/RSTB
Delay
MRIB Pull-Up
Resistance
WDI - WATCHDOG INPUT
Watchdog Timeout
1
us
ns
ns
kΩ
150
100
55
30
85
1.9
1.3
1.6
sec
ns
V
Period
WDI Pulse Width
WDI Input
0.1
0.2*V1
Vil
Threshold
WDI Input
Threshold
WDI Input Current
0.8*V1
-500
V
Vih
500
nA
WDI = 0.0V or V1
RESET OUTPUTS RST / RSTB
RSTB
(CMOS or OD)
V1 = Vth1 - 0.1V, Isink = 1mA,
output asserted
0.2*V1
V
V1 = Vth1 + 0.1V, Isource =
1mA, output not asserted
V1 = Vth1 - 0.1V, Isource =
1mA, output asserted
RSTB (CMOS)
RST (CMOS)
0.8*V1
0.8*V1
V
V
V1 = Vth1 + 0.1V, V2 > Vth2,
V3 > 0.5, V4 > 0.5, Isource =
1mA, output not asserted
RST (CMOS)
0.2*V1
V
RSTB Output OD
Leakage Current
2
nA
TA = +25ºC
Date: 4/10/06 Rev K
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
4
PIN DESCRIPTION
Pin #
Name
V1
Description
First supply voltage input. Also powers internal circuitry. Trip threshold
voltage internally set.
1
2
V2
Second supply voltage input. Trip threshold voltage internally set.
Manual Reset Input pin. Active low. It has an internal pull-up resistor.
Reset asserted when MRIB is pulled low and is kept asserted for
200ms after MRIB is released or pulled high. Leave open if not used.
3
MRIB
4
5
V3
V4
Input for the third supply voltage. Trip threshold is 0.5V.
Input for the fourth supply voltage. Trip threshold is 0.5V.
6
GND
Common ground reference pin.
Watch-Dog Input pin. When no transition is detected at the WDI pin for
the duration of WDI timeout period, reset is asserted. Leave open if
not used. RST/RSTB output is used to signal watchdog timeout
overflow. RST/RSTB output pulses high/low (depending on the active
reset polarity) for the reset timeout period after each watchdog timeout
overflow. The watchdog timer clears whenever the reset is asserted
or manual reset is asserted or a transition is observed at WDI pin.
Watchdog timer functionality can be disabled in parts by leaving this
input floating.
7
WDI
Reset output. Open-Drain or CMOS, active high or low. Reset is
asserted when any of the four supply inputs is below its trip threshold.
It stays asserted for 200 ms (typical / default) after the last supply input
traverses its trip threshold. Reset is guaranteed to be in the correct
state for V1>0.9V. RST/RSTB asserts when V1 or V2 or V3 or V4 drop
below their corresponding reset thresholds, or MRIB is pulled
“LOW” or the watchdog timer triggers a reset (devices without
WDOB). RST/RSTB remains asserted for the reset timeout period
after V1 and V2 and V3 and V4 exceed their corresponding reset
thresholds or MRIB goes “LOW” to “HIGH”. Open-drain outputs
require an external pull-up resistor. CMOS outputs are referenced to
V1.
8
RST/RSTB
Date: 4/10/06 Rev K
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
5
THEORY OF OPERATION
V1
V2
V3
WDI
V4
WDI
OSC
LOGIC
Bandgap
Ref
1.25V
CONTROL
LOGIC
RSTB (RST)
0.5V
MRIB
GND
Block Diagram
The SP6330, SP6332, and SP6334 include
a low-voltage precision bandgap reference,
four precision comparators, an oscillator, a
digital counter chain, a logic control block,
trimmed resistor divider chains and
additionalsupportingcircuitry. Thefamilyis
designed to supervise up to 4 independent
supply voltages. V1 and V2 supply inputs
have their resistor dividers on the chip.
Their trip thresholds are factory trimmed.
V3 and V4 inputs allow user to customize
two additional supply thresholds to be
monitored by means of external resistor
dividers. The devices also feature manual
reset and watchdog functionalities.
As these devices do not have watchdog
outputs, the watchdog timer is serviced
internally during the watchdog timeout
period when WDI is left unconnected. The
watchdog functionality can be disabled by
leaving the WDI input floating.
Date: 4/10/06 Rev K
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
6
THEORY OF OPERATION
Vth1
V1
V2
Vth2
Vth3=0.5V
Vth4=0.5V
V3
V4
T<Twd
T<Twd
T<Twd
T<Twd
T<Twd
MRIB
WDI
Trp
Trp
Trp
Twd
RSTB
Figure 1: Functionality of a SP63XX family member with manual reset and watchdog
capabilities but without WDOB output.
• V1 > Vth1, V2 > Vth2 , V3 > Vth3 and V4 > Vth4 (all supplies over their corresponding
thresholds)---> RSTB is de-asserted after reset timeout period (Trp).
• MRIB goes to “LOW” to force “Reset” ----> RSTB is asserted immediately.
• WDI does not make any transition during watchdog timeout period (Twd) ---->RSTB is
asserted for a duration of reset timeout period (Trp).
• One of the supplies drops below its corresponding threshold (in this case V3)---->RSTB
is asserted immediately.
Date: 4/10/06 Rev K
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
7
APPLICATION INFORMATION
V1
RSTB
ResetB Timeout Delay
WDI = GND, V1=V2=V3=V4=5V,
MRIB = open.
Watchdog Timeout Period = 1.52S
Watchdog Timeout Period
Date: 4/10/06 Rev K
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
8
APPLICATION INFORMATION
Reset Timeout vs. Temperature
500
400
300
200
100
0
85 80 70 60 50 40 30 20 10
0 -10 -20 -30 -40
Deg C
ResetTimeout Delay Vs. Temperature
R S T B vs. V 1 (V 2 = G N D )
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V1 (Vdc)
Reset Good
Date: 4/10/06 Rev K
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
9
APPLICATION INFORMATION
V 1 an d V 2 G litc h rejectio n
250
200
150
100
50
RSTB asserted
above line
0
0
20
40
60
80
100
120
Overdrive (mV)
V1 and V2 Glitch Rejection
V 3 an d V 4 g litch rejectio n
120
100
80
RSTB asserted
above line
60
40
20
0
0
20
40
60
80
100
120
O verdrive (mV)
V3 and V4 Glitch Rejection
Date: 4/10/06 Rev K
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
10
PACKAGE: 8 PIN TSOT
D
D/2
e1
7
8
6
5
E/2
SIDE VIEW
A2
E1/2
E
E1
A
Seating
Plane
3
4
2
A1
1
(L1)
Pin1 Designator
to be within this
INDEX AREA
(D/2 x E1/2)
e
b
TOP VIEW
ø1
FRONT VIEW
R1
Gauge Plane
R
L2
ø1
c
Seating
Plane
ø
L
8 Pin TSOT
JEDEC MO-193
Variation BA
Dimensions in Inches
Conversion Factor:
1 Inch = 25.40 mm
Dimensions in Millimeters:
Controlling Dimension
SYMBOL
MIN
-
0.00
0.70
0.08
NOM
-
-
0.90
-
MAX
1.10
0.10
1.00
0.20
MIN
-
0.000
0.028 0.036
NOM
-
-
MAX
0.043
0.004
0.039
0.008
A
A1
A2
c
0.003
-
D
E
E1
L
2.90 BSC
2.80 BSC
1.60 BSC
0.45
0.114 BSC
0.110 BSC
0.063 BSC
0.30
0.60
0.012 0.018
0.024
L1
L2
Ø
Ø1
R
0.60 REF
0.25 BSC
4º
10º
-
0.024 REF
0.010 BSC
4º
10º
0˚
4˚
0.10
0.10
0.22
8º
12º
-
0.25
0.38
0º
4º
0.004
0.004
0.009
8º
12º
-
-
R1
-
-
-
-
0.010
0.015
b
e
e1
0.65 BSC
1.95 BSC
0.026 BSC
0.077 BSC
SIPEX Pkg Signoff Date/Rev:
JL Oct3-05 / Rev A
Date: 4/10/06 Rev K
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
11
Part Naming Nomenclature
SP63NN - Th1 - Th2 - TOPT
T1 -- 50 ms
A
-- 100 ms
B
-- 200 ms
{
C
-- 400 ms
D
A -- 0.788 V
B -- 0.833 V
C -- 1.050 V
D -- 1.110 V
E -- 1.313 V
F -- 1.388 V
G -- 1.575 V
Example:
{
H -- 1.665 V
I -- 2.188 V
J -- 2.313 V
AZJD means:
SP6330 in TSOT-8 lead package
V1 Threshold is 4.625V
V2 Threshold is 2.313V
Reset Timeout is 400ms
Z -- 4.625 V
Y -- 4.375 V
X -- 3.075 V
W -- 2.925 V
V -- 2.625 V
U -- 2.320 V
T -- 2.190 V
S -- 1.670 V
R -- 1.580 V
AZJD
Pin 1
{
30 -- Quad Sp, MR, WDI, OD RSTB
31 -- Quad Sp, OD RSTB
32 -- Quad Sp, MR, WDI, CMOS RSTB
33 -- Quad Sp, CMOS RSTB
34 -- Quad Sp, MR, WDI, CMOS RST
35 -- Quad Sp, CMOS RST
36 -- Triple Sp, WDI, PF, OD RSTB
37 -- Triple Sp, WDI, PF, CMOS RSTB
A
B
C
D
E
F
G
H
38 -- Triple Sp, WDI, PF, CMOS RST
I
39 -- Triple Sp, MR, WDI, OD RSTB - WDOB
40 -- Dual Sp, WDI, OD RSTB - WDOB
41 -- Triple Sp, WDI, PF, CMOS RSTB - WDOB
42 -- Dual Sp, WDI, CMOS RSTB - WDOB
J
K
L
M
Date: 4/10/06 Rev K
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
12
ORDERING INFORMATION
Model
Temperature Range
Package Types
SP6330EK1-L-X-X-X...........................................-40°C to +85°C.................................Lead Free 8-Pin TSOT
SP6330EK1-L-X-X-X/TR......................................-40°Cto+85°C.................................LeadFree8-PinTSOT
SP6332EK1-L-X-X-X............................................-40°Cto+85°C.................................LeadFree8-PinTSOT
SP6332EK1-L-X-X-X/TR......................................-40°Cto+85°C.................................LeadFree8-PinTSOT
SP6334EK1-L-X-X-X............................................-40°Cto+85°C.................................LeadFree8-PinTSOT
SP6334EK1-L-X-X-X/TR......................................-40°Cto+85°C.................................LeadFree8-PinTSOT
Available in lead free packaging only. /TR = Tape and Reel
Pack quantity 2,500 forTSOT-8
Contact Factory for availability of particular voltage threshold and reset timeout options. Note that the
Ordering Information denoting those options corresponds to the Part Naming Nomenclature shown on the
previous page.
Ordering example: SP6330EK1-L-W-G-C/TR == W -- 2.925V for Voltage Threshold 1; G -- 1.575V for
Voltage Threshold 2; and C -- 200ms reset timeout.
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
Solved By SipexTM
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Date: 4/10/06 Rev K
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
13
相关型号：
©2020 ICPDF网 联系我们和版权申明