SP703EN/TR [EXAR]
Power Supply Support Circuit, Adjustable, 2 Channel, PDSO8, SOIC-8;
| 型号： | SP703EN/TR |
| 厂家： | 
EXAR CORPORATION |
| 描述： | Power Supply Support Circuit, Adjustable, 2 Channel, PDSO8, SOIC-8 光电二极管 |
| 文件： | 总16页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
SP703/SP704
Low Power Microprocessor Supervisory
with Battery Switch-Over
■ Precision Voltage Monitor:
SP703 at 4.65V
SP704 at 4.40V
■ Reset Time Delay - 200ms
■ Debounced TTL/CMOS -
Compatible Manual - Reset Input
■ Minimum component count
■ 60µA Maximum Operating Supply Current
■ 0.6µA Maximum Battery Backup Current
■ 0.1µA Maximum Battery Standby Current
■ Power Switching
250mA Output in VCC Mode (0.6Ω)
25mA Output in Battery Mode (5Ω)
■ Voltage Monitor for Power Fail or
Low Battery Warning
■ Available in 8 pin SO and DIP packages
■ RESET asserted down to VCC = 1V
■ Pin Compatible Upgrades to
MAX703/MAX704
Now available in Lead Free
DESCRIPTION
The SP703/704 devices are microprocessor (µP) supervisory circuits that integrate a myriad
of components involved in discrete solutions to monitor power-supply and battery-control
functions in µP and digital systems. The series will significantly improve system reliability and
operational efficiency when compared to discrete solutions. The features of the SP703/704
devices include a manual reset input, a µP reset and backup-battery switchover, and power-
failure warning. The series is ideal for applications in computers, controllers, intelligent
instruments and automotive systems. All designs where it is critical to monitor the power
supply to the µP and its related digital components will find the series to be an ideal solution.
BATTERY SWITCHOVER
CIRCUITRY
V
BATT
V
OUT
1
2
3
4
8
7
6
5
VCC
V
OUT
V
BATT
RESET
GENERATOR
RESET
RESET
MR
V
CC
1.25V
GND
PFI
MR
PFI
PFO
PFO
1.25V
PINOUT
INTERNAL BLOCK DIAGRAM
SP703/704DS/07
SP703/704 Low Power Microprocessor Supervisory
© Copyright 2000 Sipex Corporation
1
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation
of the device at these ratings or any other above those
indicated in the operation sections of the specifica-
tions below is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods of time
may affect reliability and cause permanent damage to
the device.
VCC........................................................-0.3V to 6.0V
VBATT.....................................................-0.3V to 6.0V
All Other Inputs......................................-0.3V to (VCC +0.3V)
Input Current:
V
CC.........................................................250mA
VBATT........................................................50mA
GND........................................................20mA
Output Current:
VOUT.....Short-Circuit Protected for up to 10sec
All Other Inputs.................................20mA
Rate of Rise, VCC,VBATT..................100V/µs
Continuous Power Dissipation.......500mW
Storage Temperature.......-65°C to +160°C
Lead Temperature(soldering,10sec).................+300°C
ESD Rating.............................4kV Human Body Model
SPECIFICATIONS
Vcc=4.75v to 5.50V for SP703, VCC = 4.50V to 5.50V for SP704, VBATT=2.80V, TA=TMIN to TMAX, typical specified at 25OC, unless otherwise noted.
PARAMETERS
MIN.
TYP.
MAX. UNITS CONDITIONS
Operating Voltage Range,
0
5.5
Volts
VCC or VBATT, NOTE 1
Supply Current, ISUPPLY
ISUPPLY in Battery Backup Mode,
CC = 0V, VBATT = 2.8V
VBATT Standby Current, NOTE 2
,
35
60
µA
µA
excluding IOUT
0.001
0.6
V
-0.1
VCC > VBATT + 0.2V
IOUT = 50mA
0.02
µA
V
OUT Output
VCC - 0.1
VCC - 0.03
Volts
V
CC - 0.15
I
OUT = 250mA
IOUT = 5mA
IOUT = 25mA
VOUT in Battery-Backup Mode
CC < VBATT - 0.2V
VBATT -0.15 VBATT - 0.04
Volts
V
V
BATT - 0.20
Battery Switch Threshold,
VCC to VBATT
20
Power-up
mV
mV
-20
Power-down
Battery Switchover Hysteresis
Reset Threshold
40
Peak to Peak
4.50
4.25
4.65
4.40
4.75
4.50
SP703
SP704
Volts
SP703/704DS/07
SP703/704 Low Power Microprocessor Supervisory
© Copyright 2000 Sipex Corporation
2
SPECIFICATIONS (continued)
Vcc=4.75V to 5.50V for SP703, VCC = 4.5 0V to 5.50V for SP704, VBATT=2.80V, TA=TMIN to TMAX, typical specified at 25OC, unless otherwise noted.
PARAMETERS
MIN.
TYP. MAX. UNITS CONDITIONS
Reset Threshold Hysteresis
Reset Pulse Width, tRS
RESET Output Voltage
40
mV
ms
Peak to Peak
140
200
280
V
CC - 1.5
ISOURCE = 800µA
0.1
0.4
0.3
Volts
V
I
SINK = 3.2mA
0.004
I
SINK = 50µA, VCC = 1.0V
MR Input Threshold
LOW
HIGH
0.8
2.0
MR Minimum Pulse Width
MR to RESET Delay
MR Pull Up Current
PFI Input Threshold
PFI Input Current
150
ns
ns
µA
250
600
100
1.200
-25
250
MR=0V
1.250 1.300 Volts
0.01
25
nA
PFO Output Voltage
VCC - 1.5
ISOURCE = 800µA
Volts
0.1
0.4
ISINK = 3.2mA
NOTE 1: Either VCC or VBATT can go to 0V if the other is greater than 2.0V.
NOTE 2: "-" equals the battery-charging current, "+" equals the battery-discharging current.
SP703/704DS/07
SP703/704 Low Power Microprocessor Supervisory
© Copyright 2000 Sipex Corporation
3
PINOUT
INTERNAL BLOCK DIAGRAM
BATTERY SWITCHOVER
CIRCUITRY
VBATT
V
OUT
1
2
3
4
8
7
6
5
V
OUT
V
BATT
V
CC
RESET
GENERATOR
RESET
RESET
MR
V
CC
GND
PFI
1.25V
PFO
MR
PFI
PIN ASSIGNMENTS
PFO
Pin 1 —VOUT — Output Supply Voltage. VOUT
connects to VCC when VCC is greater than
VBATT and VCC is above the reset thresh-
old. When VCC falls below VBATT and
VCC is below the reset threshold, VOUT
connects to VBATT. Connect a 0.1µF ca-
pacitor from VOUT to GND.
1.25V
Pin8—VBATT — Backup-BatteryInput. When
VCC fallsbelowtheresetthreshold,VBATT
will be switched to VOUT if VBATT is
20mV greater than VCC. When VCC rises
20mV above VBATT, VOUT will be recon-
nected to VCC. The 40mV hysteresis pre-
vents repeated switching if VCC falls
slowly.
Pin 2 — VCC — +5V Supply Input
Pin3 — GND — Ground reference for all signals
Pin 4 — PFI — Power-Fail Input. This is the
noninverting input to the power-fail com-
parator. When PFI is less than 1.25V,
PFO goes low. Connect PFI to GND or
VOUT when not used.
Pin 5 — PFO — Power-Fail Output.
Pin 6 — MR — Manual Reset Input. This input
generatesaresetpulsewhenpulledbelow
0.8V. This active LOW input is TTL/
CMOS compatible and can be shorted to
ground with a switch. It has an internal
250µA (typical) pull-up current. Leave
this pin floating when not used.
Pin 7 — RESET (Active Low)– Reset Output.
RESET Output goes low whenever
VCC falls below the reset threshold or
whenever MR is pulled below 0.8V for
longer than 150nS. RESET remains low
for 200ms after VCC crosses the reset
threshold voltage on power-up or after
being triggered by MR.
SP703/704DS/07
SP703/704 Low Power Microprocessor Supervisory
© Copyright 2000 Sipex Corporation
4
TYPICAL CHARACTERISTICS (25oC, unless otherwise noted)
PFI Threshold
vs. Temperature
V
CC Supply Current vs.
Battery Supply Current vs.
Temperature (Backup Mode)
Temperature (Normal Mode)
1.256
1.254
1.252
1.250
1.248
1.246
2.9
2.4
1.9
1.4
0.9
V =5V
51
47
43
39
35
31
27
23
19
CC
V =5V
V =0V
CC
CC
V
BATT=0
VBATT=2.8V
VBATT=2.8V
NO LOAD ON PFO
0.4
-0.1
20 40 60 80 100 120140
-60 -40 -20 0
-60 -30
0
30 60 90 120 150
-60 -30
0
30 60 90 120 150
Temperature Deg. C
Temperature Deg. C
Temperature Deg. C
V
CC to VOUT On
V
BATT to VOUT ON
Reset Threshold
vs. Temperature
Resistance vs. Temperature
Resistance vs. Temperature
0.9
0.8
0.7
0.6
0.5
0.4
0.3
15
10
5
4.70
V
BATT=0V
V =0V
VBATT=2V
V =5V
4.69
4.68
4.67
4.66
4.65
4.64
4.63
4.62
4.61
4.60
CC
VBCACTT=0V
SP703
Power Down
VBATT=2.8V
VBATT=4.5V
0
-60 -30
0
30
60
90
120 150
-60 -30
0
30 60 90 120 150
-60 -30
0
30 60 90 120 150
Temperature Deg. C
Temperature Deg. C
Temperature Deg. C
Reset Output Resistance
vs. Temperature
Reset Delay
vs. Temperature
Battery Current vs. VCC Voltage
212
600
V =5V,VBATT=2.8V
V =0V to 5V Step,
IE+2
IE+1
IE+0
IE-1
IE-2
IE-3
IE-4
IE-5
IE-6
IE-7
IE-8
CC
CC
210
208
206
204
202
200
Soucing Current
V
BATT=2.8V
500
400
300
200
100
0
VBATT=2.8V
V =0V,VBATT=2.8V
CC
Sink Current
.0000
5.000
-60 -30
0
30 60 90 120 150
-60 -30
0
30 60 90 120 150
VCC (0.5V/div)
Temperature Deg. C
Temperature Deg. C
SP703/704DS/07
SP703/704 Low Power Microprocessor Supervisory
© Copyright 2000 Sipex Corporation
5
1000
100
10
1000
100
10
V =4.5V
VBATT=4.5V
CC
V
BATT=0V
V =0V
SloCpCe=5Ω
Slope=0.6Ω
1
1
1
10
100
1
10
100
1000
IOUT (mA)
IOUT (mA)
Figure 1. VCC to VOUT Vs. Output Current
Figure 2. VBATT to VOUT Vs. Output Current
V
CC
V
BATT = 0V
T
A
= +25 C
VCC
V
TA
BATT = 0V
2V
div
= 25oC
V
CC
0V
RESET
2KΩ
RESET
RESET
0V
330pF
GND
1sec/div
Figure 3A. SP703 RESET Output Voltage vs.
Supply Voltage
Figure 3B. Circuit for the RESET Output Voltage
vs. Supply Voltage
SP703/704DS/07
SP703/704 Low Power Microprocessor Supervisory
© Copyright 2000 Sipex Corporation
6
V
CC
VCC
+5V
+4V
T
A
= +25 C
RESET
V
CC
RESET
+5V
10KΩ
0V
30pF
GND
2µs/div
Figure 4B. Circuit for the RESET Response Time
Figure 4A. SP703 RESET Response Time
+5V
V
CC = 5V
VBATT = 0V
+1.3V
+1.2V
PFI
V
CC = +5V
T
A
= +25 C
1KΩ
PFO
5V
PFI
PFO
0V
30pF
+1.25V
500ns/div
Figure 5B. Circuit for the Power-Fail Comparator
Response Time (FALL)
Figure 5A. Power-Fail Comparator Response Time (FALL)
SP703/704DS/07
SP703/704 Low Power Microprocessor Supervisory
© Copyright 2000 Sipex Corporation
7
V
CC = 5V
VBATT = 0V
PFI
+5V
+1.3V
+1.2V
V
CC = +5V
T
A
= +25 C
PFI
PFO
3V
0V
PFO
1KΩ
30pF
+1.25V
2µs/div
Figure 6A. Power-Fail Comparator Response Time (RISE)
Figure 6B. Circuit for the Power-Fail Comparator
Response Time (RISE)
+5V
V
CC
0V
+5V
t
RS
RESET
0V
+5V
V
OUT
3.0V
0V
+5V
0V
PFO
V
BATT = PFI = 3.0V
Figure 7. Timing Diagram
SP703/704DS/07
SP703/704 Low Power Microprocessor Supervisory
© Copyright 2000 Sipex Corporation
8
FEATURES
THEORY OF OPERATION
Reset Output
The SP703/704 devices provide four key func-
tions:
1. AbatterybackupswitchingforCMOSRAM,
CMOS microprocessors, or other logic.
2. Aresetoutputduringpower-up, power-down
and brownout conditions.
3. A reset pulse if the manual reset has been
pulled below 0.8V for at least 150ns.
4. A 1.25V threshold detector for power-fail
warning, low battery detection, or to monitor a
power supply other than +5V.
The microprocessor's (µP's) reset input starts
the µP in a known state. When the µP is in an
unknown state, it should be held in reset. The
SP703/704 assert reset during power-up and
prevent code execution errors during power-
down or brownout conditions.
On power-up, once VCC reaches 1V, RESET is
guaranteed to be a logic low. As VCC rises,
RESET remains low. When VCC exceeds the
reset threshold, RESET will remain low for
200ms, Figure 9. If a brownout condition
occurs and VCC dips below the reset threshold,
RESET is triggered. Each time RESET is trig-
gered, it stays low for the reset pulse width
interval. If a brownout condition interrupts a
previously initiated reset pulse, the reset pulse
continues for another 200ms. On power-down,
once VCC goes below the threshold, RESET is
guaranteed to be logic low until VCC drops
below 1V. RESET is also triggered by a
manual reset
The SP703/704 devices differ only in their
supply voltage monitor level. The SP703
generates a reset when VCC drops below 4.65V
while the SP704 generates a reset below 4.4V.
The SP703/704 devices are ideally suited for
applications in automotive systems, intelligent
instruments,andbattery-poweredcomputersand
controllers. All designs into an environment
where it is critical to monitor the power supply
to the µP and its related digital components will
find the SP703/704 ideal.
Regulated +5V
Unregulated
DC
0.1µF
V
CC
VCC
R1
RESET RESET
µP
PFI
NMI
PFO
MR
R2
VOUT
V
BATT
GND
GND
BUS
Pushbutton
Switch
3.6V
Lithium
Battery
V
CC
CMOS
RAM
GND
Figure 8. Typical Operating Circuit
SP703/704DS/07
SP703/704 Low Power Microprocessor Supervisory
© Copyright 2000 Sipex Corporation
9
Backup-Battery Switchover
Power-Fail Comparator
In the event of a brownout or power failure, it
may be necessary to preserve the contents of
The Power-Fail Comparator can be used as an
under-voltage detector to signal the failing of a
power supply (it is completely separate from the
rest of the circuitry and does not need to be
dedicated to this function). The PFI input is
compared to an internal 1.25V reference. If PFI
is less than 1.25V, PFO goes low. The external
voltage divider drives PFI to sense the unregu-
lated DC input to the +5V regulator. The volt-
age-divider ratio can be chosen such that the
voltage at PFI falls below 1.25V just before the
+5V regulator drops out. PFO then triggers an
interrupt which signals the µP to prepare for
power-down.
RAM. WithabackupbatteryinstalledatVBATT
,
the RAM is assured to have power if VCC fails.
As long as VCC exceeds the reset threshold,
VOUT connects to VCC through a 0.6Ω PMOS
power switch. Once VCC falls below the reset
threshold, VCC or VBATT, whichever is higher,
switches to VOUT. VBATT connects to VOUT
througha 5Ω switchonlywhenVCC isbelowthe
reset threshold and VBATT is greater than VCC
.
When VCC exceeds the reset threshold, it is
connected to VOUT, regardless of the voltage
applied to VBATT Figure 9. During this time,
the diode (D1) between VBATT and VOUT will
conduct current from VBATT to VOUT if VBATT is
When VBATT connects to VOUT, the power-fail
comparator is turned off and PFO is forced low
to conserve backup-battery power.
more than .6V above VOUT
.
When VBATT connects to VOUT, backup mode is
activated and the internal circuitry will be
powered from the battery Figure 10. When VCC
is just below VBATT, in the backup mode the
current drawn from VBATT will be typically
30µA. When VCC drops to more than 1V below
VBATT,theinternalswitchovercomparatorshuts
off and the supply current falls to less than 0.6µA.
V
BATT
V
CC
D2
D1
SW2
SW1
D3
V
OUT
GND
CONDITION
SW1
Open
SW2
Closed
Closed
Open
VCC > Reset Threshold
VCC < Reset Threshold and
VCC > VBATT
Open
VCC < Reset Threshold and
VCC < VBATT
Closed
Reset Threshold = 4.65V in SP703
Reset Threshold = 4.40V in SP704
Figure 9. BACKUP-BATTERY Switchover Block Diagram
SP703/704DS/07
SP703/704 Low Power Microprocessor Supervisory
© Copyright 2000 Sipex Corporation
10
SIGNAL
STATUS
+5V
V
VCC
Disconnected from VOUT
CC
Connected to VBATT through
VOUT
VBATT
PFI
an internal 8Ω PMOS switch
CONNECT TO
STATIC RAM
V
OUT
V
BATT
SP703
Connected to VOUT. Current
drawn from the battery is
less than 0.6µA, as long as
CONNECT
TO µP
RESET
0.1F
VCC < VBATT - 1V.
GND
Power-fail comparator is
disabled.
Figure 12. Backup Power Source Using High Capacity
Capacitor with SP703 and a +5V ±5% Supply
PFO
RESET
MR
Logic low
Logic low
If VCC is above the reset threshold and VBATT
Manual Reset is disabled
is 0.5V above VCC, current flows to V
and
VCC from VBATT until the voltage at VBOUATTT is
less than 0.5V above VCC.
Figure 10. Input and Output Status in Battery-Backup Mode.
To enter the Battery-Backup mode, VCC must be less than the
Reset threshold and less than VBATT
.
Leakage current through the capacitor charging
diode and the SP703/704 internal power
diode eventually discharges the capacitor to
VCC. Also, if VCC and VBATT start from 0.5V
above the reset threshold and power is lost
at VCC, the capacitor on VBATT discharges
through VCC until VBATT reaches the reset
threshold; the SP703/704 then switches to
battery-backup mode.
Using a High Capacity Capacitor
as a Backup Power Source
VBATT has the same operating voltage range as
VCC, and the battery-switchover threshold volt-
ages are typically +20mV centered at VBATT,
allowing use of a capacitor and a simple charg-
ing circuit as a backup source (see Figure 12).
+5V
MAXIMUM
PART
BACKUP-BATTERY
NUMBER
V
CC
VOLTAGE [V]
CONNECT TO
STATIC RAM
V
OUT
VBATT
SP704
SP703
SP704
4.80
4.55
0.1F
CONNECT
RESET
TO µP
100KΩ
Figure 11. Allowable BACKUP-BATTERY Voltages
GND
Figure 13. Backup Power Source Using High Capacity
Capacitor with SP704 and a +5V ±10% Supply
SP703/704DS/07
SP703/704 Low Power Microprocessor Supervisory
© Copyright 2000 Sipex Corporation
11
Operation Without a Backup Power
Source
+5V
V
V
IN
If a backup power source is not used, ground
VBATT and connect VOUT to VCC. Since there is
no need to switch over to any backup power
source, VOUT does not need to be switched. A
direct connection to VCC eliminates any voltage
drops across the switch which may push VOUT
CC
R
1
PFI
R
2
R
3
*C
1
PFO
below VCC
.
*optional
connect to µP
1.25
GND
Replacing the Backup Battery
V
TRIP
=
The backup battery can be removed while VCC
remains valid, without danger of triggering
RESET/RESET. AslongasVCC staysabovethe
reset threshold, battery-backup mode cannot be
entered.
R
2
R
1
+ R
2
1.25
V
=
L
- 1.25
5.0 - 1.25
+
=
R
3
R1
R2
1.25
2
VH
Adding Hysteresis to the Power-Fail
Comparator
R
1
|| R
3
PFO
R
+ R
2
|| R
3
Hysteresis adds a noise margin to the power-fail
comparator and prevents repeated triggering
of PFO when VIN is close to its trip point.
Figure 14 shows how to add hysteresis to the
power-fail comparator. Select the ratio of R1
and R2 such that PFI sees 1.25V when VIN falls
to its trip point (VTRIP). R3 adds the hysteresis.
Itwilltypicallybeanorderofmagnitudegreater
(about 10 times) than R1 or R2. The current
through R1 and R2 should be at least 1µA to
ensure that the 25nA (max) PFI input current
does not shift the trip point. R3 should be larger
than10KΩsoitdoesnotloaddownthePFOpin.
Capacitor C1 adds additional noise rejection.
+5V
0V
V
IN
0V
V
L
V
TRIP
V
H
Figure 14. Adding Hysteresis to the POWER-FAIL
Comparator
Allowable Backup Power-Source
Batteries
Lithium batteries work very well as backup
batteries due to very low self-discharge rate and
high energy density. Single lithium batteries
with open-circuit voltages of 3.0V to 3.6V are
ideal. Any battery with an open-circuit voltage
less than the minimum reset threshold plus 0.3V
can be connected directly to the VBATT input
of this series with no additional circuitry; see
Figure 8. However, batteries with open-circuit
voltages that are greater than this value cannot
be used for backup, as current is sourced into
Monitoring a Negative Voltage
The power-fail comparator can be used to
monitor a negative supply rail using the circuit
of Figure 15. When the negative rail is valid,
PFO is low. When the negative supply voltage
drops, PFO goes high. This circuit's accuracy
is affected by the PFI threshold tolerance, the
V
OUT through the diode (D1 in Figure 9) when
VCC is close to the reset threshold.
V
CC voltage, and the resistors, R1 and R2.
SP703/704DS/07
SP703/704 Low Power Microprocessor Supervisory
© Copyright 2000 Sipex Corporation
12
+5V
V
Buffered RESET connects to System Components
CC
R1
+5V
V
+5V
V
PFI
CC
CC
R2
PFO
µP
RESET
RESET
V-
4.7KΩ
GND
1.25 - VTRIP
GND
GND
5.0 - 1.25
=
R2
R
1
PFO
Figure 16. Interfacing to Microprocessors with
Bidirectional RESET I/O
+5V
0V
0V
V-
*VTRIP
*VTRIP is a negative voltage
Figure 15. Monitoring a Negative Voltage
Interfacing to Microprocessors with
Bidirectional Reset Pins
Microprocessors with bidirectional reset pins,
such as the Motorola 68HC11 series, can
contend with this series' RESET output. If, for
example, the RESET output is driven high and
the µP wants to pull it low, indeterminate logic
levels may result. To correct this, connect a
4.7KΩ resistor between the RESET output and
the µP reset I/O, as in Figure 16. Buffer the
RESET output to other system components.
SP703/704DS/07
SP703/704 Low Power Microprocessor Supervisory
© Copyright 2000 Sipex Corporation
13
PACKAGE: PLASTIC
DUAL–IN–LINE
(NARROW)
E1
E
D1 = 0.005" min.
(0.127 min.)
A1 = 0.015" min.
(0.381min.)
D
A = 0.210" max.
(5.334 max).
C
A2
Ø
L
B1
B
e
= 0.300 BSC
(7.620 BSC)
e = 0.100 BSC
(2.540 BSC)
A
ALTERNATE
END PINS
(BOTH ENDS)
DIMENSIONS (Inches)
Minimum/Maximum
(mm)
8–PIN
0.115/0.195
(2.921/4.953)
A2
0.014/0.022
(0.356/0.559)
B
0.045/0.070
B1
C
(1.143/1.778)
0.008/0.014
(0.203/0.356)
0.355/0.400
(9.017/10.160)
D
0.300/0.325
(7.620/8.255)
E
0.240/0.280
E1
L
(6.096/7.112)
0.115/0.150
(2.921/3.810)
0°/ 15°
(0°/15°)
Ø
SP703/704DS/07
SP703/704 Low Power Microprocessor Supervisory
© Copyright 2000 Sipex Corporation
14
PACKAGE: PLASTIC
SMALL OUTLINE (SOIC)
(NARROW)
E
H
h x 45°
D
A
Ø
A1
L
e
B
DIMENSIONS (Inches)
Minimum/Maximum
(mm)
8–PIN
A
A1
B
D
E
0.053/0.069
(1.346/1.748)
0.004/0.010
(0.102/0.249
0.014/0.019
(0.35/0.49)
0.189/0.197
(4.80/5.00)
0.150/0.157
(3.802/3.988)
e
0.050 BSC
(1.270 BSC)
H
h
0.228/0.244
(5.801/6.198)
0.010/0.020
(0.254/0.498)
L
0.016/0.050
(0.406/1.270)
Ø
0°/8°
(0°/8°)
SP703/704DS/07
SP703/704 Low Power Microprocessor Supervisory
© Copyright 2000 Sipex Corporation
15
ORDERING INFORMATION
Model
Temperature Range
Package Types
SP703CN..........................................................0°C to +70°C....................................................8-Pin NSOIC
SP703CP........................................................0°C to +70°C.........................................................8-Pin PDIP
SP703EN......................................................-40°C to +85°C.....................................................8-Pin NSOIC
SP703EP.......................................................-40°C to +85°C.......................................................8-Pin PDIP
SP704CN........................................................0°C to +70°C......................................................8-Pin NSOIC
SP704CP........................................................0°C to +70°C.........................................................8-Pin PDIP
SP704EN......................................................-40°C to +85°C.....................................................8-Pin NSOIC
SP704EP.......................................................-40°C to +85°C.......................................................8-Pin PDIP
Please consult the factory for pricing and availability on a Tape-On-Reel option.
Available in lead free packaging. To order, add "-L" suffix to the part number.
Example: SP6660EU/TR=Tape & Reel. SP6660EU-L/TR = lead free.
Co rp o ra tio n
SIGNAL PROCESSING EXCELLENCE
Sipex Corporation
Headquarters and
Sales Office
22 Linnell Circle
Billerica, MA 01821
TEL: (978) 667-8700
FAX: (978) 670-9001
e-mail: sales@sipex.com
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.
SP703/704DS/07
SP703/704 Low Power Microprocessor Supervisory
© Copyright 2000 Sipex Corporation
16
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