SP705CN-L [EXAR]
Low Power Microprocessor Supervisory Circuits;
| 型号： | SP705CN-L |
| 厂家： | 
EXAR CORPORATION |
| 描述： | Low Power Microprocessor Supervisory Circuits 输入元件 光电二极管 |
| 文件： | 总17页 (文件大小：1302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SP705-SP708-SP813L
Low Power Microprocessor Supervisory Circuits
June 2010
Rev. 2.0.0
GENERAL DESCRIPTION
APPLICATIONS
The SP705-708/813L series is a family of
microprocessor (µP) supervisory circuits that
integrate myriad components involved in
discrete solutions which monitor power-supply
and battery in mP and digital systems.
• Processors & DSPs Based Systems
• Industrial & Medical Instruments
FEATURES
The SP705-708/813L series will significantly
improve system reliability and operational
efficiency when compared to solutions
obtained with discrete components. The
features of the SP705-708/813L series include
a watchdog timer, a µP reset, a Power Fail
Comparator, and a manual-reset input.
• Precision Voltage Monitor
− SP705/SP707/SP813L: 4.65V
− SP706/SP708: 4.40V
• 200ms RESET Pulse Width
• Independent Watchdog Timer
− 1.6s Timeout (SP705/SP706/SP813L)
The SP705-708/813L series is ideal for
• 60µA Maximum Supply Current
applications
computers,
in
automotive
and
systems,
intelligent
controllers,
• Debounced TTL/CMOS Manual Reset
instruments. The SP705-708/813L series is an
ideal solution for systems in which critical
monitoring of the power supply to the µP and
related digital components is demanded.
Input
• RESET Asserted Down to VCC=1.1V
• Voltage Monitor for Power Failure or
Low Battery Warning
• 8-Pin PDIP, NSOIC and MSOP Packages
• Pin Compatible with Industry
Standards 705-708-813L Series
• Functionally Compatible to Industry
Standard 1232 Series
Part Number
RESET Threshold
RESET Active
Manual RESET
Watchdog
PFI Accuracy
Yes
Yes
No
SP705
SP706
SP707
SP708
SP813L
Low
Low
Yes
Yes
Yes
Yes
Yes
4%
4%
4%
4%
4%
4.65V
4.40V
4.65V
4.40V
4.65V
Low and High
Low and High
High
No
Yes
Exar Corporation
www.exar.com
48720 Kato Road, Fremont CA 94538, USA
Tel. +1 510 668-7000 – Fax. +1 510 668-7001
SP705-SP708-SP813L
Low Power Microprocessor Supervisory Circuits
ESD Rating (HBM - Human Body Model) ....................4kV
Continuous Power Dissipation
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of
the device at these ratings or any other above those
indicated in the operation sections of the specifications
below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may affect
reliability.
Plastic DIP (derate 9.09mW/°C above +70°C)....727mW
SO (derate 5.88mW/°C above +70°C)...............471mW
Mini SO (derate 4.10mW/°C above +70°C)........330mW
Storage Temperature ..............................-65°C to 160°C
Lead Temperature (Soldering, 10 sec)....................300°C
VCC ..........................................................-0.3V to 6.0V
All Other Inputs (Note 1)...................-0.3V to (VCC+0.3V)
Input Current
VCC.................................................................20mA
GND ................................................................20mA
Output Current (All outputs)...............................20mA
ELECTRICAL SPECIFICATIONS
Unless otherwise indicated, VCC = 4.75V to 5.5V (SP705-SP707-SP813L), VCC = 4.50V to 5.5V (SP706-SP708), TA= TMIN to
T
MAX, typical at 25°C.
Parameter
Min.
Typ.
Max.
Units
Conditions
Operating Voltage Range VCC
Supply Current ISUPPLY
5.5
60
V
1.1
40
4.65
4.40
40
µA
MR=VCC or floating, WDI floating
SP705, SP707, SP813L
SP706, SP708 (Note 2)
Note 2
4.75
4.50
4.50
4.25
Reset Threshold
V
Reset Threshold Hysteresis
Reset Pulse Width tRS
mV
ms
200
280
Note 2
140
VCC-1.5
0.8
I
SOURCE=800µA, Note 2
ISOURCE=4µA, VCC=1.1V, Note 2
ISINK=3.2mA, Note 2
RESET Output Voltage
V
0.4
0.3
I
SINK=100µA, VCC=1.2V, Note 2
Watchdog Timeout Period tWD
WDI Pulse Width tWP
1.60
2.25
s
µs
V
SP705, SP707, SP813L
VIL=0.4V, VIH=0.8xVCC
1.00
1
WDI Input Threshold Low
WDI Input Threshold High
0.8
75
SP705, SP707, SP813L
VCC=5V
V
3.5
30
µA
µA
SP705, SP707, SP813L, WDI=VCC
SP705, SP707, SP813L, WDI=0V
ISOURCE=800µA
WDI Input Current
-20
-75
VCC-1.5
WDO Output Voltage
V
0.4
ISINK=3.2mA
MR Pull-up Current
250
600
µA
ns
MR = 0V
100
150
MR Pulse Width tMR
MR Input Threshold Low
MR Input Threshold High
MR to Reset Out Delay tMD
PFI Input Threshold
PFI Input Current
0.8
V
2.0
250
1.30
ns
V
Note 2
1.25
0.01
VCC=5V
1.20
25.00
nA
-25.00
VCC-1.5
ISOURCE=800µA
PFO Output Voltage
V
0.4
ISINK=3.2mA
Note 1: The input voltage limits on PFI and MR can be exceeded if the input current is less than 10mA.
Note 2: Applies to both RESET in the SP705-SP708 and RESET in the SP707/708/813L/813M.
© 2010 Exar Corporation
2/17
Rev. 2.0.0
SP705-SP708-SP813L
Low Power Microprocessor Supervisory Circuits
BLOCK DIAGRAM
Fig. 1: SP705-SP706-SP813L Block Diagram
Fig. 2: SP707-SP708 Block Diagram
© 2010 Exar Corporation
3/17
Rev. 2.0.0
SP705-SP708-SP813L
Low Power Microprocessor Supervisory Circuits
PIN ASSIGNMENT
Fig. 3: Pin Assignment
PIN DESCRIPTION
Pin Number
SP705-SP706
SP707-SP708
SP813L
DIP
SOIC
Name
Description
SOIC
MSOP
SOIC
MSOP
Manual Reset
This input triggers a reset pulse when pulled below 0.8V. This
active LOW input has an internal 250µA pull-up current. It
can be driven from a TTL or CMOS logic line or shorted to
ground with a switch.
1
1
3
1
MR
3
2
3
+5V power supply
Ground reference for all signals
2
3
4
5
2
3
VCC
GND
4
5
Power-Fail Input
When this voltage monitor input is less than 1.25V, PFO goes
LOW. Connect PFI to ground or VCC when not in use.
Power-Fail Output
This output is LOW until PFI is less then 1.25V
4
5
4
5
6
7
4
5
PFI
6
-
PFO
Watchdog Input
If this input remains HIGH or LOW for 1.6s, the internal
watchdog timer times out and WDO goes LOW. Floating WDI
or connecting WDI to a high-impedance tri-state buffer
disables the watchdog feature. The internal watchdog timer
clears whenever RESET is asserted, WDI is tri-stated, or
whenever WDI sees a rising or falling edge.
6
-
-
-
6
-
WDI
N.C.
8
-
No Connect
Active-LOW RESET Output
6
7
8
1
This output pulses LOW for 200ms when triggered and stays
LOW whenever VCC is below the reset threshold (4.65V for the
SP705/707/813L and 4.40V for the SP706/708). It remains
LOW for 200ms after Vcc rises above the reset threshold or
MR goes from LOW to HIGH. A watchdog timeout will not
trigger RESET unless WDO is connected to MR.
7
-
RESET
1
© 2010 Exar Corporation
4/17
Rev. 2.0.0
SP705-SP708-SP813L
Low Power Microprocessor Supervisory Circuits
Pin Number
SP705-SP706
SP707-SP708
SP813L
DIP
SOIC
Name
WDO
Description
SOIC
MSOP
SOIC
MSOP
Watchdog Output
This output pulls LOW when the internal watchdog timer
finishes its 1.6s count and does not go HIGH again until the
watchdog is cleared. WDO also goes LOW during low-line
conditions. Whenever VCC is below the reset threshold, WDO
stays LOW. However, unlike RESET, WDO does not have a
minimum pulse width. As soon as VCC is above the reset
threshold, WDO goes HIGH with no delay.
8
-
-
8
7
2
-
Active-HIGH RESET Output
This output is the complement of RESET. Whenever RESET is
HIGH, RESET is LOW and vice-versa. Note that the SP813L
has a reset output only.
-
8
2
RESET
ORDERING INFORMATION
Temperature
Part Number
Packing
Quantity
Marking
Package
Note 1
Lead Free
Note 2
Range
SP705C
YYWWL
#
Bulk
SP705CN-L
8-pin NSOIC
8-pin NSOIC
8-pin NSOIC
8-pin NSOIC
8-pin MSOP
8-pin MSOP
0°C≤TA≤+70°C
0°C≤TA≤+70°C
-40°C≤TA≤+85°C
-40°C≤TA≤+85°C
0°C≤TA≤+70°C
0°C≤TA≤+70°C
2.5K/Tape & Reel
Bulk
SP705CN-L/TR
SP705EN-L
Lead Free
Lead Free
Lead Free
Lead Free
Lead Free
SP705E
YYWWL
#
2.5K/Tape & Reel
Bulk
SP705EN-L/TR
SP705CU-L
705C
#
YWW
2.5K/Tape & Reel
SP705CU-L/TR
SP706C
YYWWL
#
Bulk
SP706CN-L
8-pin NSOIC
8-pin NSOIC
8-pin NSOIC
8-pin NSOIC
8-pin MSOP
8-pin MSOP
0°C≤TA≤+70°C
0°C≤TA≤+70°C
-40°C≤TA≤+85°C
-40°C≤TA≤+85°C
0°C≤TA≤+70°C
0°C≤TA≤+70°C
Lead Free
Lead Free
Lead Free
Lead Free
Lead Free
Lead Free
2.5K/Tape & Reel
Bulk
SP706CN-L/TR
SP706EN-L
SP706E
YYWWL
#
2.5K/Tape & Reel
Bulk
SP706EN-L/TR
SP706CU-L
706C
#
YWW
2.5K/Tape & Reel
SP706CU-L/TR
SP707C
YYWWL
#
Bulk
SP707CN-L
8-pin NSOIC
8-pin NSOIC
8-pin NSOIC
8-pin NSOIC
8-pin MSOP
8-pin MSOP
0°C≤TA≤+70°C
0°C≤TA≤+70°C
-40°C≤TA≤+85°C
-40°C≤TA≤+85°C
0°C≤TA≤+70°C
0°C≤TA≤+70°C
Lead Free
Lead Free
Lead Free
Lead Free
Lead Free
Lead Free
2.5K/Tape & Reel
Bulk
SP707CN-L/TR
SP707EN-L
SP707E
YYWWL
#
2.5K/Tape & Reel
Bulk
SP707EN-L/TR
SP707CU-L
707C
#
YWW
2.5K/Tape & Reel
SP707CU-L/TR
SP708C
YYWWL
#
Bulk
SP708CN-L
8-pin NSOIC
8-pin NSOIC
8-pin NSOIC
8-pin NSOIC
0°C≤TA≤+70°C
0°C≤TA≤+70°C
-40°C≤TA≤+85°C
-40°C≤TA≤+85°C
Lead Free
Lead Free
Lead Free
Lead Free
2.5K/Tape & Reel
Bulk
SP708CN-L/TR
SP708EN-L
SP708E
YYWWL
#
2.5K/Tape & Reel
SP708EN-L/TR
SP813LC
YYWWL
#
Bulk
SP813LCN-L
8-pin NSOIC
8-pin NSOIC
8-pin NSOIC
8-pin NSOIC
0°C≤TA≤+70°C
0°C≤TA≤+70°C
-40°C≤TA≤+85°C
-40°C≤TA≤+85°C
Lead Free
Lead Free
Lead Free
Lead Free
2.5K/Tape & Reel
Bulk
SP813LCN-L/TR
SP813LEN-L
SP813LE
YYWWL
#
2.5K/Tape & Reel
SP813LEN-L/TR
SP813LC
YWWL#
SP813LE
YWWL#
Bulk
Bulk
SP813LCP-L
SP813LEP-L
8-pin PDIP
8-pin PDIP
0°C≤TA≤+70°C
Lead Free
Lead Free
-40°C≤TA≤+85°C
“YY” = Year – “WW” = Work Week – “#” = Lot Number
© 2010 Exar Corporation
5/17
Rev. 2.0.0
SP705-SP708-SP813L
Low Power Microprocessor Supervisory Circuits
TYPICAL PERFORMANCE CHARACTERISTICS
All data taken at VIN = 2.7V to 5.5V, TJ = TA = 25°C, unless otherwise specified - Schematic and BOM from Application
Information section of this datasheet.
Fig. 5: Power-Fail Comparator
De-Assertion Response Time Circuit
Fig. 4: Power-Fail Comparator
De-Assertion Response Time
Fig. 7: Power-Fail Comparator
Assertion Response Time Circuit
Fig. 6: Power-Fail Comparator
Assertion Response Time
Fig. 9: SP705/707 RESET Output Voltage
Fig. 8: SP705/707 RESET Output Voltage
vs. Supply Voltage Circuit
vs. Supply Voltage
© 2010 Exar Corporation
6/17
Rev. 2.0.0
SP705-SP708-SP813L
Low Power Microprocessor Supervisory Circuits
Fig. 10: SP705/707 RESET Response Time
Fig. 11: SP705/707 RESET Response Time Circuit
Fig. 12: SP707 RESET and RESET Assertion
Fig. 13: SP707 RESET and RESET De-Assertion
Fig. 14: SP707 RESET and RESET Assertion and De-Assertion Circuit
© 2010 Exar Corporation
7/17
Rev. 2.0.0
SP705-SP708-SP813L
Low Power Microprocessor Supervisory Circuits
Fig. 15: SP707/708/813L RESET Output Voltage
vs. Supply Voltage
Fig. 16: SP813L RESET Response Time
Fig. 17: SP707/708/813L RESET Output Voltage vs. Supply Voltage
and SP813L RESET Response Time Circuit
© 2010 Exar Corporation
8/17
Rev. 2.0.0
SP705-SP708-SP813L
Low Power Microprocessor Supervisory Circuits
FEATURES
RESET OUTPUT
The SP705-708/813L series provides four key
functions:
A microprocessor's reset input starts the µP in
a known state. The SP705-708/813L series
asserts reset during power-up and prevents
code execution errors during power down or
brownout conditions.
1. A reset output during power-up, power-
down and brownout conditions.
2. An independent watchdog output that goes
LOW if the watchdog input has not been
toggled within 1.6 seconds.
On power-up, once VCC reaches 1.1V, RESET is
a guaranteed logic LOW of 0.4V or less. As VCC
rises, RESET stays LOW. When VCC rises above
the reset threshold, an internal timer releases
RESET after 200ms. RESET pulses LOW
whenever VCC dips below the reset threshold,
such as in a brownout condition. When a
brownout condition occurs in the middle of a
previously initiated reset pulse, the pulse
continues for at least another 140ms. On
power down, once VCC falls below the reset
3. A 1.25V threshold detector for power-fail
warning, low battery detection, or monitoring
a power supply other than +5V.
4. An active-LOW manual-reset that allows
RESET to be triggered by a pushbutton switch.
The SP707/708 devices are the same as the
SP705/706 devices except for the active-HIGH
RESET substitution of the watchdog timer. The
SP813L is the same as the SP705 except an
active-HIGH RESET is provided rather than an
active-LOW RESET. The SP705/707/813L
devices generate a reset when the supply
voltage drops below 4.65V. The SP706/708
devices generate a reset below 4.40V.
threshold,
RESET
stays
LOW
and
is
guaranteed to be 0.4V or less until VCC drops
below 1.1V.
The SP707/708/813L active-HIGH RESET
output is simply the complement of the RESET
output and is guaranteed to be valid with VCC
down to 1.1V. Some µPs, such as Intel's
80C51, require an active-HIGH reset pulse.
The SP705-708/813L series is ideally suited
for applications in automotive systems,
intelligent instruments, and battery-powered
computers and controllers. The SP705-
708/813L series is ideally applied in
environments where monitoring of power
supply to a µP and its related components is
critical.
W
ATCHDOG TIMER
The
SP705/706/813L
watchdog
circuit
monitors the µP's activity. If the µP does not
toggle the watchdog input (WDI) within 1.6
seconds and WDI is not tri-stated, WDO goes
LOW. As long as RESET is asserted or the WDI
input is tri-stated, the watchdog timer will stay
cleared and will not count. As soon as RESET
is released and WDI is driven HIGH or LOW,
the timer will start counting. Pulses as short as
50ns can be detected.
THEORY OF OPERATION
The
SP705-708/813L
series
is
a
microprocessor (µP) supervisory circuit that
monitors the power supplied to digital circuits
such as microprocessors, microcontrollers, or
memory. The series is an ideal solution for
portable, battery-powered equipment that
Typically, WDO will be connected to the non-
maskable interrupt input (NMI) of a µP. When
VCC drops below the reset threshold, WDO will
go LOW whether or not the watchdog timer
had timed out. Normally this would trigger an
NMI but RESET goes LOW simultaneously and
thus overrides the NMI.
requires
power
supply
monitoring.
Implementing this series will reduce the
number of components and overall complexity.
The watchdog functions of this product family
will continuously oversee the operational
status of a system. The operational features
and benefits of the SP705-708/813L series are
described in more detail below.
If WDI is left unconnected, WDO can be used
as a low-line output. Since floating WDI
disables the internal timer, WDO goes LOW
only when VCC falls below the reset threshold,
thus functioning as a low-line output.
© 2010 Exar Corporation
9/17
Rev. 2.0.0
SP705-SP708-SP813L
Low Power Microprocessor Supervisory Circuits
Fig. 18: SP705/706/813L Watchdog Timing Waveforms
Fig. 20: Typical Operating Circuit
MANUAL RESET
The manual-reset input (MR) allows RESET to
be triggered by a pushbutton switch. The
switch is effectively debounced by the 140ms
minimum RESET pulse width. MR is TTL/CMOS
logic compatible, so it can be driven by an
external logic line. MR can be used to force a
watchdog timeout to generate a RESET pulse
in the SP705/706/813L. Simply connect WDO
to MR.
Fig. 19: SP705/706 Timing Diagrams with WDI tri-stated.
P
OWER-FAIL COMPARATOR
The power-fail comparator can be used for
various purposes because its output and non
inverting input are not internally connected.
The inverting input is internally connected to a
1.25V reference.
Ensuring a Valid Reset Output Down to
VCC=0V
When
VCC
falls
below
1.1V,
the
SP705/706/707/708 RESET output no longer
sinks current, it becomes an open circuit.
High-impedance CMOS logic inputs can drift to
undetermined voltages if left undriven. If a
pull-down resistor is added to the RESET pin,
any stray charge or leakage currents will be
shunted to ground, holding RESET LOW. The
resistor value is not critical. It should be about
100KW, large enough not to load RESET and
small enough to pull RESET to ground.
To build an early-warning circuit for power
failure, connect the PFI pin to a voltage divider
as shown in Figure 20. Choose the voltage
divider ratio so that the voltage at PFI falls
below 1.25V just before the +5V regulator
drops out. Use PFO to interrupt the µP so it
can prepare for an orderly power-down.
© 2010 Exar Corporation
10/17
Rev. 2.0.0
SP705-SP708-SP813L
Low Power Microprocessor Supervisory Circuits
the SP705-708/813L will keep RESET asserted
(where RESET = LOW and RESET = HIGH).
Note that this circuit's accuracy depends on
the PFI threshold tolerance, the VCC line, and
the resistors.
M
ONITORING
VOLTAGES OTHER THAN THE
U
NREGULATED DC INPUT
Monitor voltages other than the unregulated
DC by connecting a voltage divider to PFI and
adjusting the ratio appropriately. If required,
add hysteresis by connecting a resistor (with a
value approximately 10 times the sum of the
two resistors in the potential divider network)
between PFI and PFO. A capacitor between PFI
and GND will reduce the power-fail circuit's
sensitivity to high-frequency noise on the line
being monitored. RESET can be used to
monitor voltages other than the +5V VCC line.
Connect PFO to MR to initiate a RESET pulse
when PFI drops below 1.25V. Figure 21 shows
the SP705/706/707/708 configured to assert
RESET when the +5V supply falls below the
RESET threshold, or when the +12V supply
falls below approximately 11V.
Fig. 22: Monitoring a Negative Voltage Supply
I
NTERFACING TO µPS WITH BIDIRECTIONAL
RESET PINS
µPs with bidirectional RESET pins, such as the
Motorola 68HC11 series, can contend with the
SP705/706/707/708 RESET output. If, for
example, the RESET output is driven HIGH and
the µP wants to pull it LOW, indeterminate
logic levels may result. To correct this,
connect a 4.7KΩ resistor between the RESET
output and the µP reset I/O, as shown if
Figure 23. Buffer the RESET output to other
system components.
Fig. 21: Monitoring +5V and +12V Power Supplies
MONITORING A NEGATIVE VOLTAGE SUPPLY
The power-fail comparator can also monitor a
negative supply rail, shown in Figure 22. When
the negative rail is good (a negative voltage of
large magnitude), PFO is LOW. By adding the
resistors and transistor as shown, a HIGH PFO
triggers RESET. As long as PFO remains HIGH,
© 2010 Exar Corporation
11/17
Rev. 2.0.0
SP705-SP708-SP813L
Low Power Microprocessor Supervisory Circuits
applications, the fixed functions will be
preferred, with the benefit of reduced cost due
to a less complex part. In addition, the SP705-
708/ 813L series has a power fail input and
output function not available with the DS1232
that is useful for monitoring systems with
unregulated supply voltages. The SP705-
708/813L series is available in one of the
industry's smallest space-saving package
sizes, the MSOP.
Fig. 23: Interfacing to Microprocessors
with Bidirectional REST I/O (SP705/706/708)
APPLICATIONS
The SP705-708/813L series offers unmatched
performance and the lowest power
Fig. 24: Supply Current vs. Temperature
consumption for these industry standard
devices. Refer to Figures 24 and 25 for supply
current performance characteristics rated
against temperature and supply voltages.
Table 2 shows how the SP705-708/813L series
can
be
used
instead
of
the
Dallas
Semiconductor
DS1232LP/LPS.
Table
2
illustrates to a designer the advantages and
tradeoffs of the SP705-708/813L series
compared to the Dallas Semiconductor device.
While the names of the pin descriptions may
differ, the functions are the same or very
similar. Unlike the DS1232, the SP705-
708/813L series has a separate watchdog
output pin WDO which can be simply
connected to the MR input to generate a Reset
signal. The DS1232 has pin selectable
features, while the SP705-708/813L series has
more fixed functions of reset threshold and
Fig. 25: Supply Current vs. Supply Voltage
watchdog
time-out
delay.
For
most
© 2010 Exar Corporation
12/17
Rev. 2.0.0
SP705-SP708-SP813L
Low Power Microprocessor Supervisory Circuits
Fig. 26: Device Overviw on Maxim/Dallas Semiconductor
© 2010 Exar Corporation
13/17
Rev. 2.0.0
SP705-SP708-SP813L
Low Power Microprocessor Supervisory Circuits
PACKAGE SPECIFICATION
8-PIN NSOIC
© 2010 Exar Corporation
14/17
Rev. 2.0.0
SP705-SP708-SP813L
Low Power Microprocessor Supervisory Circuits
8-PIN MSOP
© 2010 Exar Corporation
15/17
Rev. 2.0.0
SP705-SP708-SP813L
Low Power Microprocessor Supervisory Circuits
8-PIN PDIP
© 2010 Exar Corporation
16/17
Rev. 2.0.0
SP705-SP708-SP813L
Low Power Microprocessor Supervisory Circuits
REVISION HISTORY
Revision
Date
Description
06/03/2010
Reformat of datasheet
2.0.0
FOR FURTHER ASSISTANCE
Email:
customersupport@exar.com
Exar Technical Documentation:
http://www.exar.com/TechDoc/default.aspx?
E
XAR
CORPORATION
H
EADQUARTERS AND
SALES OFFICES
48720 Kato Road
Fremont, CA 94538 – USA
Tel.: +1 (510) 668-7000
Fax: +1 (510) 668-7030
www.exar.com
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein,
conveys no license under any patent or other right, and makes no representation that the circuits are free of patent
infringement. Charts and schedules contained herein are only for illustration purposes and may vary depending upon a
user’s specific application. While the information in this publication has been carefully checked; no responsibility, however,
is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its
safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in
writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all
such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
© 2010 Exar Corporation
17/17
Rev. 2.0.0
相关型号：
©2020 ICPDF网 联系我们和版权申明