ST16C2552 [EXAR]
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO; 具有16字节FIFO 2.97V至5.5V双路UART
| 型号： | ST16C2552 |
| 厂家： | 
EXAR CORPORATION |
| 描述： | 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO |
| 文件： | 总35页 (文件大小：356K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ST16C2552
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
SEPTEMBER 2003
REV. 4.2
FEATURES
GENERAL DESCRIPTION
Added feature in devices with top marking "A2
YYWW" and newer:
The ST16C2552 (2552) is
a
dual universal
asynchronous receiver and transmitter (UART). The
ST16C2552 is an improved version of the PC16552
UART. The 2552 provides enhanced UART functions
with 16 byte FIFOs, a modem control interface, and
data rates up to 4 Mbps. Onboard status registers
provide the user with error indications and operational
■ 5 Volt Tolerant Inputs
• Pin-to-pin and functionally compatible to National
PC16552 and Exar’s XR16L2752 and XR16C2852
• 4 Mbps transmit/receive operation (64 MHz
status.
features may be tailored by external software to meet
specific user requirements. Indepedendent
System interrupts and modem control
External Clock Frequency)
• 2 Independent UART Channels
■ Register Set Compatible to 16C550
programmable baud rate generators are privded to
select transmit and receive clock rates from 50 Bps to
4 Mbps. The baud rate generator can be configured
for either crystal or external clock input. An internal
loop-back capability allows onboard diagnostics. The
2552 provides block mode data transfers (DMA)
through FIFO controls. DMA transfer monitoring is
provided through the signals TXRDY# and RXRDY#.
An Alternate Function Register provides the user with
the ability to initialize both UARTs concurrently. The
2552 is available in the 44-PLCC package.
■ 16 byte Transmit FIFO to reduce the bandwidth
requirement of the external CPU
■ 16 byte Receive FIFO with error tags to reduce
the bandwidth requirement of the external CPU
■ 4 selectable RX FIFO Trigger Levels
■ Fixed Transmit FIFO interrupt trigger level
■ Full Modem Interface (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
• DMA operation and DMA monitoring via TXRDY#
and RXRDY# pins
APPLICATIONS
• Portable Appliances
• UART internal register sections A & B may be
written to concurrently
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Multi-Function output allows more package
functions with few I/O pins
• Programmable character lengths (5, 6, 7, 8) with
even, odd, or no parity
• Factory Automation and Process Controls
• Crystal oscillator or external clock input
FIGURE 1. ST16C2552 BLOCK DIAGRAM
3.3V or 5V VCC
GND
A2:A0
D7:D0
IOR#
UART Channel A
IOW#
CS#
CHSEL
TXA (or TXIRA)
16 Byte TX FIFO
TX & RX
UART
Regs
INTA
INTB
BRG
16 Byte RX FIFO
RXA (or RXIRA)
8-bit Data
TXRDYA#
Bus
TXRDYB#
TXB (or TXIRB)
RXB (or RXIRB)
UART Channel B
(same as Channel A)
Interface
MFA#
(OP2A#,
BAUDOUTA#, or
RXRDYA#)
XTAL1
XTAL2
Crystal Osc/Buffer
MFB#
(OP2B#,
BAUDOUTB#, or
RXRDYB#)
CTS#A/B, RI#A/B,
CD#A/B, DSR#A/B
Modem Control Logic
Reset
DTR#A/B, RTS#A/B
2552BLK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
ST16C2552
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REV. 4.2
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
FIGURE 2. PIN OUT ASSIGNMENT
7
39 RXA
D5
D6
8
38 TXA
D7
9
37 DTRA#
36 RTSA#
35 MFA#
34 INTA
10
11
12
A0
XTAL1
GND
ST16C2552
44-pin PLCC
VCC
XTAL2 13
A1 14
33
32 TXRDYB#
31 RIB#
A2 15
16
17
30 CDB#
CHSEL
INTB
29 DSRB#
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
0°C to +70°C
DEVICE STATUS
ST16C2552CJ
ST16C2552IJ
44-Lead PLCC
44-Lead PLCC
Active
Active
-40°C to +85°C
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ST16C2552
REV. 4.2
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
PIN DESCRIPTIONS
Pin Description
44-PLCC
NAME
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
15
14
10
I
Address data lines [2:0]. These 3 address lines select one of the internal registers in
UART channel A/B during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
9
8
7
6
5
4
3
2
I/O
Data bus lines [7:0] (bidirectional).
IOR#
24
I
Input/Output Read Strobe (active low). The falling edge instigates an internal read
cycle and retrieves the data byte from an internal register pointed to by the address
lines [A2:A0]. The data byte is placed on the data bus to allow the host processor to
read it on the rising edge.
IOW#
CS#
20
18
16
I
I
I
Input/Output Write Strobe (active low). The falling edge instigates an internal write
cycle and the rising edge transfers the data byte on the data bus to an internal regis-
ter pointed by the address lines.
UART chip select (active low). This function selects channel A or B in accordance
with the logical state of the CHSEL pin. This allows data to be transferred between
the user CPU and the 2552.
CHSEL
Channel Select - UART channel A or B is selected by the logical state of this pin when
the CS# pin is a logic 0. A logic 0 on the CHSEL selects the UART channel B while a
logic 1 selects UART channel A. Normally, CHSEL could just be an address line from
the user CPU such as A3. Bit-0 of the Alternate Function Register (AFR) can tempo-
rarily override CHSEL function, allowing the user to write to both channel register
simultaneously with one write cycle when CS# is low. It is especially useful during the
initialization routine.
INTA
INTB
34
17
1
O
O
O
UART channel A Interrupt output (active high). A logic high indicates channel A is
requesting for service. For more details, see Figures 16- 21.
UART channel B Interrupt output (active high). A logic high indicates channel B is
requesting for service. For more details, see Figures 16- 21.
UART channel A Transmitter Ready (active low). The output provides the TX
FIFO/THR status for transmit channel A. If it is not used, leave it
unconnected.
TXRDYA#
TXRDYB#
32
O
UART channel B Transmitter Ready (active low). The output provides the TX FIFO/
THR status for transmit channel B. If it is not used, leave it unconnected.
MODEM OR SERIAL I/O INTERFACE
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2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
Pin Description
44-PLCC
NAME
TYPE
DESCRIPTION
PIN #
MFA#
35
O
Multi-Function Output Channel A. This output pin can function as the OP2A#, BAUD-
OUTA#, or RXRDYA# pin. One of these output signal functions can be selected by
the user programmable bits 1-2 of the Alternate Function Register (AFR). These sig-
nal functions are described as follows:
1) OP2A# - When OP2A# (active low) is selected, the MF# pin is a logic 0 when MCR
bit-3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults to a logic 1 condition after
a reset or power-up.
2) BAUDOUTA# - When BAUDOUTA# function is selected, the 16X Baud rate clock
output is available at this pin.
3) RXRDYA# - RXRDYA# (active low) is intended for monitoring DMA data transfers.
See Table 2 for more details.
If it is not used, leave it unconnected.
MFB#
19
O
Multi-Function Output ChannelB. This output pin can function as the OP2B#, BAUD-
OUTB#, or RXRDYB# pin. One of these output signal functions can be selected by
the user programmable bits 1-2 of the Alternate Function Register (AFR). These sig-
nal functions are described as follows:
1) OP2B# - When OP2B# (active low) is selected, the MF# pin is a logic 0 when MCR
bit-3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults to a logic 1 condition after
a reset or power-up.
2) BAUDOUTB# - When BAUDOUTB# function is selected, the 16X Baud rate clock
output is available at this pin.
3) RXRDYB# - RXRDYB# (active low) is intended for monitoring DMA data transfers.
See Table 2 for more details.
If it is not used, leave it unconnected.
TXA
RXA
38
39
O
I
UART channel A Transmit Data. If it is not used, leave it unconnected.
UART channel A Receive Data. Normal receive data input must idle at logic 1 condi-
tion. If it is not used, tie it to VCC or pull it high via a 100k ohm resistor.
RTSA#
CTSA#
DTRA#
DSRA#
CDA#
36
40
37
41
42
O
I
If it is not
UART channel A Request-to-Send (active low) or general purpose output.
used, leave it unconnected.
UART channel A Clear-to-Send (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
O
I
If it is
UART channel A Data-Terminal-Ready (active low) or general purpose output.
not used, leave it unconnected.
UART channel A Data-Set-Ready (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
I
UART channel A Carrier-Detect (active low) or general purpose input.
This input
should be connected to VCC when not used. This input has no effect on the UART.
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2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
Pin Description
44-PLCC
NAME
TYPE
DESCRIPTION
PIN #
RIA#
43
I
UART channel A Ring-Indicator (active low) or general purpose input.
This input
should be connected to VCC when not used. This input has no effect on the UART.
TXB
RXB
26
25
O
I
UART channel B Transmit Data. If it is not used, leave it unconnected.
UART channel B Receive Data. Normal receive data input must idle at logic 1 condi-
tion. If it is not used, tie it to VCC or pull it high via a 100k ohm resistor.
RTSB#
CTSB#
DTRB#
DSRB#
CDB#
23
28
27
29
30
31
O
I
If it is not
UART channel B Request-to-Send (active low) or general purpose output.
used, leave it unconnected.
UART channel B Clear-to-Send (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
O
I
If it is
UART channel B Data-Terminal-Ready (active low) or general purpose output.
not used, leave it unconnected.
UART channel B Data-Set-Ready (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
I
UART channel B Carrier-Detect (active low) or general purpose input.
This input
should be connected to VCC when not used. This input has no effect on the UART.
RIB#
I
UART channel B Ring-Indicator (active low) or general purpose input.
This input
should be connected to VCC when not used. This input has no effect on the UART.
ANCILLARY SIGNALS
XTAL1
XTAL2
RESET
11
13
21
I
O
I
Crystal or external clock input.
Crystal or buffered clock output.
Reset (active high) - A longer than 40 ns logic 1 pulse on this pin will reset the internal
registers and all outputs. The UART transmitter output will be held at logic 1, the
receiver input will be ignored and outputs are reset during reset period (see External
Reset Conditions).
VCC
GND
44, 33
22, 12
Pwr 3.3V to 5V power supply.
"A2 YYWW" and newer.
All inputs are 5V tolerant for devices with top marking of
Pwr Power supply common, ground.
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
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ST16C2552
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REV. 4.2
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
1.0 PRODUCT DESCRIPTION
The 2552 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel
data conversions for both the transmitter and receiver sections. These functions are necessary for converting
the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial
data stream is accomplished by adding start and stops bits to the transmit data to form a data character
(character orientated protocol). Data integrity is ensured by attaching a parity bit to the data character. The
parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to provide all these
functions is fairly complex especially when manufactured on a single integrated silicon chip. The 2552
represents such an integration with greatly enhanced features. The 2552 is fabricated with an advanced
CMOS process.
The 2552 is an upward solution that provides a dual UART capability with 16 bytes of transmit and receive
FIFO memory, instead of none in the 16C2450. The 2552 is designed to work with high speed modems and
shared network environments, that require fast data processing time. Increased performance is realized in the
2552 by the transmit and receive FIFO’s. This allows the external processor to handle more networking tasks
within a given time. For example, the ST16C2450 without a receive FIFO, will require unloading of the RHR in
93 microseconds (This example uses a character length of 11 bits, including start/stop bits at 115.2 Kbps). This
means the external CPU will have to service the receive FIFO less than every 100 microseconds. However
with the 16 byte FIFO in the 2552, the data buffer will not require unloading/loading for 1.53 ms. This increases
the service interval giving the external CPU additional time for other applications and reducing the overall
UART interrupt servicing time. In addition, the 4 selectable receive FIFO trigger interrupt levels is uniquely
provided for maximum data throughput performance especially when operating in a multi-channel
environment. The FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU,
increases performance, and reduces power consumption.
The 2552 is capable of operation up to 4 Mbps with a 64 MHz clock. With a crystal or external clock input of
14.7456 MHz the user can select data rates up to 921.6 Kbps.
The rich feature set of the 2552 is available through internal registers. Selectable receive FIFO trigger levels,
selectable TX and RX baud rates, and modem interface controls are all standard features. Following a power
on reset or an external reset, the 2552 is software compatible with the 16L2752 and 16C2852.
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2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
2.0 FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The 2552 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share
the same data bus for host operations. The data bus interconnections are shown in Figure 3.
FIGURE 3. ST16C2552 DATA BUS INTERCONNECTIONS
VCC
VCC
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
TXA
RXA
DTRA#
RTSA#
CTSA#
UART
Channel A
Serial Interface of
RS-232, RS-485
DSRA#
CDA#
A0
A1
A0
A1
A2
RIA#
A2
(OP2A#)
IOR#
IOR#
(BAUDOUTA#)
IOW#
IOW#
TXB
RXB
CS#
UART_CS#
CHSEL
UART_CHSEL
DTRB#
UART_INTA
UART_INTB
INTA
INTB
RTSB#
CTSB#
DSRB#
CDB#
UART
Channel B
Serial Interface of
RS-232, RS-485
TXRDYA#
(RXRDYA#)
TXRDYB#
TXRDYA#
(RXRDYA#)
TXRDYB#
(RXRDYB#)
RIB#
(OP2B#)
(RXRDYB#)
(BAUDOUTB#)
UART_RESET
RESET
GND
2750int
Pins in parentheses become available through the MF# pin. MF# A/B becomes RXRDY# A/B when AFR[2:1] = '10'. MF# A/B becomes OP2# A/B
when AFR[2:1] = '00'. MF# A/B becomes BAUDOUT# A/B when AFR[1:0] = '01'.
.
2.2
Device Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see the Table 11). An active high pulse of longer than 40 ns duration will be required to activate the reset
function in the device.
2.3
Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external CPU
and an external serial communication device. A logic 0 on chip select pin (CS#) allows the user to select the
UART and then using the channel select (CHSEL) pin, the user can select channel A or B to configure, send
transmit data and/or unload receive data to/from the UART. Individual channel select functions are shown in
Table 1.
TABLE 1: CHANNEL A AND B SELECT
CS#
CHSEL
FUNCTION
1
0
0
X
1
0
UART de-selected
Channel A selected
Channel B selected
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ST16C2552
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REV. 4.2
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
2.4
Channel A and B Internal Registers
Each UART channel in the 2552 has a set of enhanced registers for controlling, monitoring and data loading
and unloading. The configuration register set is compatible to those already available in the standard single
16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status
and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/
LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/
DLM), and a user accessible scratchpad register (SPR).
Beyond the general 16C2550 features and capabilities, the 2552 offers the Alternate Function Register which
allows simultaneous writes to both channels. All the register functions are discussed in full detail later in
“Section 3.0, UART INTERNAL REGISTERS” on page 15.
2.5
Simultaneous Write to Channel A and B
During a write mode cycle, the setting of Alternate Function Register (AFR) bit-0 to a logic 1 will override the
CHSEL selection and allows a simultaneous write to both UART channel sections. This functional capability
allow the registers in both UART channels to be modified concurrently, saving individual channel initialization
time. Caution should be exercised, however, when using this capability. Any in-process serial data transfer
may be disrupted by changing an active channel’s mode.
2.6
DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B (MF# A/B becomes RXRDY# A/B output when AFR[2:1] = ‘10’) and TXRDY# A/B output pins.
The transmit and receive FIFO trigger levels provide additional flexibility to the user for block mode operation.
The LSR bits 5-6 provide an indication when the transmitter is empty or has an empty location(s) for more data.
The user can optionally operate the transmit and receive FIFO in the DMA mode (FCR bit-3=1). When the
transmit and receive FIFO are enabled and the DMA mode is disabled (FCR bit-3 = 0), the 2552 is placed in
single-character mode for data transmit or receive operation. When DMA mode is enabled (FCR bit-3 = 1), the
user takes advantage of block mode operation by loading or unloading the FIFO in a block sequence
determined by the programmed trigger level. The following table show their behavior. Also see Figures 16
through 21.
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
FCR BIT-0=0
PINS
FCR BIT-0=1 (FIFO ENABLED)
(FIFO DISABLED)
FCR Bit-3 = 0
FCR Bit-3 = 1
(DMA Mode Disabled)
(DMA Mode Enabled)
0 = 1 byte.
RXRDY# A/B
TXRDY# A/B
0 = at least 1 byte in FIFO
1 = FIFO empty.
1 to 0 transition when FIFO reaches the trigger
level, or timeout occurs.
1 = no data.
0 to 1 transition when FIFO empties.
0 = THR empty.
1 = byte in THR.
0 = FIFO empty.
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
1 = at least 1 byte in FIFO.
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2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
2.7
INTA and INTB Ouputs
The INTA and INTB interrupt outputs change according to the operating mode and enahnced features setup.
Tables 3 and 4 summarize the operating behavior for the transmitter and receiver. Also see Figures 16
through 21.
TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER
FCR BIT-0 = 0
FCR BIT-0 = 1
(FIFO DISABLED)
(FIFO ENABLED)
0 = at least 1 byte in FIFO
1 = FIFO empty
INTA/B Pin 0 = a byte in THR
1 = THR empty
TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
0 = FIFO below trigger level
1 = FIFO above trigger level
INTA/B Pin 0 = no data
1 = 1 byte
2.8
Crystal Oscillator or Ext. Clock Input
The 2552 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. See “Programmable Baud Rate
Generator” on page 10.
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS
XTAL1
XTAL2
R1
Ω
0-120
(Optional)
R2
500 ΚΩ − 1 ΜΩ
1.8432 MHz
to
Y1
24 MHz
C1
C2
22-47 pF
22-47 pF
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 2),
Ω
with an external 500k to
. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal
Ω
1 M resistor across it
baud rate generator for standard or custom rates. Typical oscillator connections are shown in Figure 4. For
further reading on oscillator circuit please see application note DAN108 on EXAR’s web site.
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2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
2.9
Programmable Baud Rate Generator
A single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel
control. The programmable Baud Rate Generator is capable of operating with a crystal frequency of up to 24
MHz. However, with an external clock input on XTAL1 pin and a 2K ohms pull-up resistor on XTAL2 pin (as
shown in Figure 5) it can extend its operation up to 64 MHz (4Mbps serial data rate) at room temperature and
5.0V.
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE
External C lock
vcc
XTAL1
gnd
VCC
R1
2K
XTAL2
To obtain maximum data rate, it is necessary to use full rail swing on the clock input. See external clock
operating frequency over power supply voltage chart in Figure 6.
FIGURE 6. OPERATING FREQUENCY CHART. REQUIRES A 2K OHMS PULL-UP RESISTOR ON XTAL2 PIN TO INCREASE
OPERATING SPEED.
Operating frequency for ST16C2550
with external clock and a 2K ohms
pull-up resistor on XTAL2 pin.
80
-40oC
25oC
70
60
85oC
50
40
30
3.0 3.5 4.0 4.5 5.0 5.5
Suppy Voltage
The 2552 divides the basic external clock by 16. The basic 16X clock provides table rates to support standard
and custom applications using the same system design. The Baud Rate Generator divides this 16X clock by
any divisor from 1 to 216 -1. The rate table is configured via the DLL and DLM internal register functions.
Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections
of baud rate generator.
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2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
Table 5 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling
rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for
DLL/DLM with the following equation.
divisor (decimal) = (XTAL1 or External clock frequency ) / (serial data rate x 16)
TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
DATA RATE
ERROR (%)
OUTPUT Data Rate
MCR Bit-7=0
DIVISOR FOR 16x
Clock (Decimal)
DIVISOR FOR 16x
Clock (HEX)
DLM PROGRAM
VALUE (HEX)
DLL PROGRAM
VALUE (HEX)
400
2304
384
192
96
48
24
12
6
900
180
C0
60
09
01
00
00
00
00
00
00
00
00
00
00
80
C0
60
30
18
0C
06
04
02
01
0
0
0
0
0
0
0
0
0
0
0
2400
4800
9600
19.2k
38.4k
76.8k
153.6k
230.4k
460.8k
921.6k
30
18
0C
06
4
04
2
02
1
01
2.10 Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal clock.
A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits, inserts
the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in the
Line Status Register (LSR bit-5 and bit-6).
2.10.1 Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.10.2 Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
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FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE
Transmit
Holding
Register
(THR)
Data
Byte
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
16X
Clock
M
S
B
L
S
B
Transmit Shift Register (TSR)
TXNOFIFO1
2.10.3 Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when the FIFO and the TSR
become empty.
FIGURE 8. TRANSMITTER OPERATION IN FIFO MODE
Transmit FIFO
THR
Data Byte
THR Interrupt (ISR bit-1) when TX
FIFO becomes empty. FIFO is
enabled by FCR bit-0=1.
16X Clock
Transmit Data Shift Register
(TSR)
TXFIFO1
2.11 Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X for timing. It verifies and validates every bit
on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an
internal receiver counter starts counting at the 16X. After 8 clocks the start bit period should be at the center of
the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in
this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are
sampled and validated in this same manner to prevent false framing. If there were any error(s), they are
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reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the receive FIFO pointer
is bumped and the error tags are immediately updated to reflect the status of the data byte in RHR register.
RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the FIFO
trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt
when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-
4.6 character times. The RHR interrupt is enabled by IER bit-0.
2.11.1 Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register.
It provides the receive data interface to the host processor. The RHR register is part of the receive FIFO of 16
bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When the FIFO is
enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the RHR is read,
the next character byte is loaded into the RHR and the errors associated with the current data byte are
immediately updated in the LSR bits 2-4.
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE
16X Clock
Receive Data Shift
Register (RSR)
Data Bit
Validation
Receive Data Characters
Error
Receive
Data Byte
and Errors
Receive Data
Holding Register
(RHR)
Tags in
LSR bits
4:2
RHR Interrupt (ISR bit-2)
RXFIFO1
FIGURE 10. RECEIVER OPERATION IN FIFO MODE
16X Clock
Receive Data Shift
Register (RSR)
Data Bit
Validation
Receive Data Characters
16 bytes by 11-bit
wide FIFO
RHR Interrupt (ISR bit-2) when FIFO fills
up to trigger level.
RX FIFO
FIFO is Enabled by FCR bit-0=1
RHR
Receive Data
Byte and Errors
RXFI
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2.12
Internal Loopback
The 2552 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 11 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback
test else upon exiting the loopback test the UART may detect and report a false “break” signal.
FIGURE 11. INTERNAL LOOP BACK IN CHANNEL A AND B
VCC
TXA/TXB
Transmit Shift Register
(THR/FIFO)
MCR bit-4=1
Receive Shift Register
RXA/RXB
(RHR/FIFO)
VCC
RTSA#/RTSB#
RTS#
CTS#
CTSA#/CTSB
VCC
DTRA#/DTRB#
DTR#
DSR#
RI#
DSRA#/DSRB#
RIA#/RIB#
OP1#
VCC
(OP2A#/OP2B#)
OP2#
CD#
CDA#/CDB#
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3.0 UART INTERNAL REGISTERS
Each of the UART channel in the 2552 has its own set of configuration registers selected by address lines A0,
A1 and A2 with CS# and CHSEL selecting the channel. The registers are 16C550 compatible. The complete
register set is shown in Table 6 and Table 7.
TABLE 6: UART CHANNEL A AND B UART INTERNAL REGISTERS
A2,A1,A0 ADDRESSES
REGISTER
READ/WRITE
COMMENTS
16C550 COMPATIBLE REGISTERS
0
0 0
RHR - Receive Holding Register
Read-only
Write-only
LCR[7] = 0
THR - Transmit Holding Register
0
0
0
0
0
0 0
0 1
1 0
0 1
1 0
DLL - Div Latch Low Byte
Read/Write
Read/Write
Read/Write
Read/Write
LCR[7] = 1
LCR[7] = 1
LCR[7] = 1
LCR[7] = 0
LCR[7] = 0
DLM - Div Latch High Byte
AFR - Alternate Function Register
IER - Interrupt Enable Register
ISR - Interrupt Status Register
FCR - FIFO Control Register
Read-only
Write-only
0
1
1
1 1
0 0
0 1
LCR - Line Control Register
Read/Write
Read/Write
MCR - Modem Control Register
LSR - Line Status Register
Reserved
Read-only
Write-only
1
1
1 0
1 1
MSR - Modem Status Register
Reserved
Read-only
Write-only
SPR - Scratch Pad Register
Read/Write
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.
TABLE 7: INTERNAL REGISTERS DESCRIPTION.
ADDRESS
REG
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
A2-A0
NAME
16C550 Compatible Registers
0 0 0
0 0 0
0 0 1
RHR
THR
RD
Bit-7
Bit-7
0
Bit-6
Bit-6
0
Bit-5
Bit-5
0
Bit-4
Bit-4
0
Bit-3
Bit-3
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0
Bit-0
WR
IER RD/WR
Modem RXLine
Stat.
Int.
TX
Empty
Int
RX
Data
Int.
Stat.
Int.
Enable Enable Enable Enable
LCR[7] = 0
0 1 0
0 1 0
0 1 1
ISR
RD
FIFOs
Enabled Enabled
FIFOs
0
0
0
0
INT
INT
INT
INT
Source Source Source Source
Bit-3
Bit-2
Bit-1
RX
Bit-0
FCR
WR RXFIFO RXFIFO
Trigger Trigger
DMA
Mode
TX
FIFO
FIFOs
FIFO Enable
Bit-1
Bit-0
Enable Reset Reset
LCR RD/WR Divisor Set TX Set Par-
Even
Parity Enable
Parity
Stop
Bits
Word
Length Length
Bit-1 Bit-0
Word
Enable
0
Break
0
ity
0
1 0 0
1 0 1
MCR RD/WR
Internal OP2#
Loop- Output
back
Rsvd
RTS# DTR#
Output Output
Control Control
(OP1#)
Control
Enable
LSR
RD
RD
RXFIFO THR &
Global
Error
THR
Empty
RX
Break
RX
RX
RX
RX
Data
Ready
TSR
Empty
Fram- Parity Over-
ing
Error
Error
run
Error
1 1 0
1 1 1
MSR
CD#
Input
RI#
Input
DSR#
Input
CTS#
Input
Delta
CD#
Delta
RI#
Delta
DSR# CTS#
Delta
SPR RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Baud Rate Generator Divisor
0 0 0
0 0 1
0 1 0
DLL RD/WR
DLM RD/WR
AFR RD/WR
Bit-7
Bit-7
0
Bit-6
Bit-6
0
Bit-5
Bit-5
0
Bit-4
Bit-4
0
Bit-3
Bit-3
0
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0
Bit-0
LCR[7] = 1
RXRDY# Baudout# Concur-
Select Select rent Write
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1 Receive Holding Register (RHR) - Read- Only
See “Receiver” on page 12.
4.2
Transmit Holding Register (THR) - Write-Only
See “Transmitter” on page 11.
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4.3
Baud Rate Generator Divisors (DLL and DLM) - Read/Write
The Baud Rate Generator (BRG) is a 16-bit counter that generates the data rate for the transmitter. The rate is
programmed through registers DLL and DLM which are only accessible when LCR bit-7 is set to ‘1’. See
“Programmable Baud Rate Generator” on page 10. for more details.
4.4
Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
4.4.1
IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A.
B.
C.
The receive data available interrupts are issued to the host when the FIFO has reached the programmed
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the FIFO is empty.
4.4.2
IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the ST16C2552 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting respective transmit or receive control bit(s).
A.
B.
C.
D.
E.
F.
LSR BIT-0 indicates there is data in RHR or RX FIFO.
LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
LSR BIT-5 indicates transmit FIFO is empty.
LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
• Logic 0 = Disable the receive data ready interrupt (default).
• Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the TX FIFO becomes empty.
• Logic 0 = Disable Transmit Ready interrupt (default).
• Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when the
character has been received. LSR bits 2-4 generate an interrupt when the character with errors is read out of
the FIFO.
• Logic 0 = Disable the receiver line status interrupt (default).
• Logic 1 = Enable the receiver line status interrupt.
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IER[3]: Modem Status Interrupt Enable
• Logic 0 = Disable the modem status register interrupt (default).
• Logic 1 = Enable the modem status register interrupt.
IER[7:4]: Reserved
4.5
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 8, shows the data values (bits 0-3) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
4.5.1
Interrupt Generation:
• LSR is by any of the LSR bits 1, 2, 3 and 4.
• RXRDY is by RX trigger level.
• RXRDY Time-out is by a 4-char plus 12 bits delay timer.
• TXRDY is by TX trigger level or TX FIFO empty.
• MSR is by any of the MSR bits 0, 1, 2 and 3.
4.5.2
Interrupt Clearing:
• LSR interrupt is cleared by a read to the LSR register.
• RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
• RXRDY Time-out interrupt is cleared by reading RHR.
• TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
• MSR interrupt is cleared by a read to the MSR register.
]
TABLE 8: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF INTERRUPT
LEVEL
BIT-3
BIT-2
BIT-1
BIT-0
1
2
3
4
5
-
0
1
0
0
0
0
1
1
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0
1
LSR (Receiver Line Status Register)
RXRDY (Receive Data Time-out)
RXRDY (Received Data Ready)
TXRDY (Transmit Ready)
MSR (Modem Status Register)
None (default)
ISR[0]: Interrupt Status
• Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
• Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 8).
ISR[5:4]: Reserved
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ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.6
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
• Logic 0 = Disable the transmit and receive FIFO (default).
• Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
• Logic 0 = No receive FIFO reset (default)
• Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
• Logic 0 = No transmit FIFO reset (default).
• Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
• Logic 0 = Normal Operation (default).
• Logic 1 = DMA Mode.
FCR[5:4]: Reserved
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 9 shows the complete selections.
TABLE 9: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION
RECEIVE
TRIGGER
LEVEL
FCR
BIT-7
FCR
BIT-6
COMPATIBILITY
0
0
1
1
0
1
0
1
1 (default)
Table-A. 16C550,
16C2550, 16C2552,
16C554, 16C580 com-
patible.
4
8
14
4.7
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
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LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
BIT-1
BIT-0
WORD LENGTH
0
0
1
1
0
1
0
1
5 (default)
6
7
8
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
STOP BIT LENGTH
(BIT TIME(S))
WORD
LENGTH
BIT-2
0
1
1
5,6,7,8
5
1 (default)
1-1/2
2
6,7,8
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 10 for parity selection summary below.
• Logic 0 = No parity.
• Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
• Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
• Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
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LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
• LCR[5] = logic 0, parity is not forced (default).
• LCR[5] = logic 1 and LCR[4] = logic 0, parity bit is forced to a logical 1 for the transmit and receive data.
• LCR[5] = logic 1 and LCR[4] = logic 1, parity bit is forced to a logical 0 for the transmit and receive data.
TABLE 10: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3
PARITY SELECTION
No parity
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Odd parity
Even parity
Force parity to mark, “1”
Forced parity to space, “0”
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
• Logic 0 = No TX break condition (default).
• Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
• Logic 0 = Data registers are selected. (default)
• Logic 1 = Divisor latch registers are selected.
4.8
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
• Logic 0 = Force DTR# output to a logic 1 (default).
• Logic 1 = Force DTR# output to a logic 0.
MCR[1]: RTS# Output
The RTS# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
• Logic 0 = Force RTS# output to a logic 1 (default).
• Logic 1 = Force RTS# output to a logic 0.
MCR[2]: OP1# Output
OP1# is not available as an output pin on the 2552. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
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MCR[3]: OP2# Output
OP2# is available as an output pin on the 2552 when AFR[2:1] = ‘00’. In the Loopback Mode, MCR[3] is used
to write the state of the modem CD# interface signal. Also see pin descriptions for MF# pins.
• Logic 0 = Forces OP2# output to a logic 1 (default).
• Logic 1 = Forces OP2# output to a logic 0.
MCR[4]: Internal Loopback Enable
• Logic 0 = Disable loopback mode (default).
• Logic 1 = Enable local loopback mode, see loopback section and Figure 11.
MCR[7:5]: Reserved
4.9
Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host.
LSR[0]: Receive Data Ready Indicator
• Logic 0 = No data in receive holding register or FIFO (default).
• Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
LSR[1]: Receiver Overrun Flag
• Logic 0 = No overrun error (default).
• Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register is
overwritten. Note that under this condition the data byte in the receive shift register is not transferred into the
FIFO, therefore the data in the FIFO is not corrupted by the error.
LSR[2]: Receive Data Parity Error Tag
• Logic 0 = No parity error (default).
• Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR.
LSR[3]: Receive Data Framing Error Tag
• Logic 0 = No framing error (default).
• Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
LSR[4]: Receive Break Tag
• Logic 0 = No break condition (default).
• Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time). In the
FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX input
returns to the idle condition, “mark” or logic 1.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. This bit indicates that the transmitter is ready to
accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to the host
when the THR interrupt enable is set. The THR bit is set to a logic 1 when the last data byte is transferred from
the transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently with the data
loading to the transmit holding register by the host. In the FIFO mode this bit is set when the transmit FIFO is
empty, it is cleared when the transmit FIFO contains at least 1 byte.
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or TSR
contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and transmit
shift register are both empty.
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LSR[7]: Receive FIFO Data Error Flag
• Logic 0 = No FIFO error (default).
• Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in the FIFO.
4.10 Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface signals, or other peripheral device that the
UART is connected. Lower four bits of this register are used to indicate the changed information. These bits are
set to a logic 1 whenever a signal from the modem changes state. These bits may be used as general purpose
inputs/outputs when they are not used with modem signals.
MSR[0]: Delta CTS# Input Flag
• Logic 0 = No change on CTS# input (default).
• Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[1]: Delta DSR# Input Flag
• Logic 0 = No change on DSR# input (default).
• Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
• Logic 0 = No change on RI# input (default).
• Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[3]: Delta CD# Input Flag
• Logic 0 = No change on CD# input (default).
• Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[4]: CTS Input Status
Normally MSR bit-4 bit is the compliment of the CTS# input. However in the loopback mode, this bit is
equivalent to the RTS# bit in the MCR register. The CTS# input may be used as a general purpose input when
the modem interface is not used.
MSR[5]: DSR Input Status
Normally this bit is the compliment of the DSR# input. In the loopback mode, this bit is equivalent to the DTR#
bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is
not used.
MSR[6]: RI Input Status
Normally this bit is the compliment of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the
MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.
MSR[7]: CD Input Status
Normally this bit is the compliment of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the
MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.
4.11 Scratch Pad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
23
ST16C2552
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REV. 4.2
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
4.12 Baud Rate Generator Registers (DLL and DLM) - Read/Write
The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the
baud rate:
• Baud Rate = (Clock Frequency / 16) / Divisor
See MCR bit-7 and the baud rate table also.
4.13 Alternate Function Register (AFR) - Read/Write
This register is used to select specific modes of MF# operation and to allow both UART register sets to be
written concurrently.
AFR[0]: Concurrent Write Mode
When this bit is set, the CPU can write concurrently to the same register in both UARTs. This function is
intended to reduce the dual UART initialization time. It can be used by the CPU when both channels are
initialized to the same state. The external CPU can set or clear this bit by accessing either register set. When
this bit is set, the channel select pin still selects the channel to be accessed during read operations. The user
should ensure that LCR Bit-7 of both channels are in the same state before executing a concurrent write to the
registers at address 0, 1, or 2.
• Logic 0 = No concurrent write (default).
• Logic 1 = Register set A and B are written concurrently with a single external CPU I/O write operation.
AFR[2:1]: MF# Output Select
These bits select a signal function for output on the MF# A/B pins. These signal function are described as:
OP2#, BAUDOUT#, or RXRDY#. Only one signal function can be selected at a time.
BIT-2
BIT-1
MF# FUNCTION
OP2# (default)
BAUDOUT#
RXRDY#
0
0
1
1
0
1
0
1
Reserved
AFR[7:3]: Reserved
All are initialized to logic 0.
24
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ST16C2552
REV. 4.2
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
TABLE 11: UART RESET CONDITIONS FOR CHANNEL A AND B
REGISTERS
DLL
RESET STATE
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0x00
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x01
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x60
Bits 3-0 = Logic 0
DLM
AFR
RHR
THR
IER
FCR
ISR
LCR
MCR
LSR
MSR
Bits 7-4 = Logic levels of the inputs inverted
SPR
I/O SIGNALS
TX
Bits 7-0 = 0xFF
RESET STATE
Logic 1
MF#
Logic 1
RTS#
Logic 1
DTR#
Logic 1
TXRDY#
INT
Logic 0
Logic 0
25
ST16C2552
áç
REV. 4.2
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
ABSOLUTE MAXIMUM RATINGS
Power Supply Range
Voltage at Any Pin
7 Volts
GND-0.3 V to VCC+0.3 V
-40o to +85oC
Operating Temperature
-65o to +150oC
500 mW
Storage Temperature
Package Dissipation
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)
theta-ja = 50oC/W, theta-jc = 21oC/W
Thermal Resistance (44-PLCC)
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97V TO
5.5V
TOP MARKING "A2 YYWW"
AND NEWER
SYMBOL
PARAMETER
UNITS
LIMITS
3.3V
LIMITS
5.0V
LIMITS
3.3V
LIMITS
5.0V
CONDITIONS
MIN
MAX MIN
MAX MIN
MAX MIN
MAX
VILCK
VIHCK
VIL
Clock Input Low Level
Clock Input High Level
Input Low Voltage
-0.3
0.6
VCC
0.8
-0.5
3.0
0.6
VCC
0.8
-0.3
2.4
0.6
5.5
0.8
5.5
-0.5
3.0
0.6
5.5
0.8
5.5
0.4
V
V
2.4
-0.3
2.0
-0.5
2.2
-0.3
2.0
-0.5
2.2
V
VIH
Input High Voltage
Output Low Voltage
Output Low Voltage
Output High Voltage
Output High Voltage
VCC
VCC
0.4
V
VOL
VOL
VOH
VOH
IIL
V
IOL = 6 mA
IOL = 4 mA
IOH = -6 mA
IOH = -1 mA
0.4
0.4
V
2.4
2.4
V
2.0
2.0
V
Input Low Leakage
Current
±10
±10
±10
±10
±10
±10
±10
±10
uA
IIH
Input High Leakage
Current
uA
CIN
ICC
Input Pin Capacitance
Power Supply Current
5
5
3
5
5
3
pF
1.2
1.2
mA
26
áç
ST16C2552
REV. 4.2
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
AC ELECTRICAL CHARACTERISTICS
TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97 TO 5.5V
70 PF LOAD WHERE APPLICABLE
LIMITS
LIMITS
5.0
SYMBOL
PARAMETER
3.3
UNIT
MIN
MAX MIN
MAX
-
Crystal Frequency
20
24
MHz
ns
CLK
OSC
TAS
Clock Pulse Duration
External Clock Frequency
Address Setup Time
17
8
30
64
MHz
ns
5
0
TAH
TCS
Address Hold Time
Chip Select Width
IOR# Strobe Width
Read Cycle Delay
Data Access Time
Data Disable Time
IOW# Strobe Width
Write Cycle Delay
Data Setup Time
Data Hold Time
10
66
35
40
5
ns
ns
50
TRD
25
ns
TDY
30
ns
TRDV
TDD
35
25
15
ns
0
25
0
ns
TWR
TDY
40
40
20
5
25
30
15
5
ns
ns
TDS
ns
TDH
ns
TWDO
TMOD
TRSI
TSSI
TRRI
TSI
Delay From IOW# To Output
50
40
40
1
40
35
35
1
ns
Delay To Set Interrupt From MODEM Input
Delay To Reset Interrupt From IOR#
Delay From Stop To Set Interrupt
Delay From IOR# To Reset Interrupt
Delay From Start To Interrupt
ns
ns
Bclk
ns
45
45
24
45
1
40
40
24
40
1
ns
TINT
TWRI
TSSR
TRR
Delay From Initial INT Reset To Transmit Start
Delay From IOW# To Reset Interrupt
Delay From Stop To Set RXRDY#
Delay From IOR# To Reset RXRDY#
Delay From IOW# To Set TXRDY#
Delay From Center of Start To Reset TXRDY#
Reset Pulse Width
8
8
Bclk
ns
Bclk
ns
45
45
8
40
40
8
TWT
TSRT
TRST
ns
Bclk
ns
40
40
27
ST16C2552
áç
REV. 4.2
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
AC ELECTRICAL CHARACTERISTICS
TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97 TO 5.5V
70 PF LOAD WHERE APPLICABLE
LIMITS
LIMITS
SYMBOL
PARAMETER
3.3
5.0
UNIT
MIN
MAX MIN
MAX
16-1
1
216-1
N
Baud Rate Divisor
Baud Clock
1
-
2
Bclk
16X of data rate
Hz
FIGURE 12. CLOCK TIMING
CLK
CLK
EXTERNAL
CLOCK
OSC
FIGURE 13. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B
IOW#
Active
TWDO
RTS#
DTR#
Change of state
Change of state
CD#
CTS#
DSR#
Change of state
Change of state
TMOD
TMOD
INT
Active
Active
Active
Active
TRSI
IOR#
Active
Active
TMOD
Change of state
RI#
28
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ST16C2552
REV. 4.2
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
FIGURE 14. DATA BUS READ TIMING
A0-A2
Valid Address
Valid Address
TAS
TAS
TAH
TCS
TAH
TCS
CSA#/
CSB#
TDY
TRD
TRD
IOR#
TDD
TDD
TRDV
TRDV
D0-D7
Valid Data
Valid Data
RDTm
FIGURE 15. DATA BUS WRITE TIMING
A0-A2
Valid Address
TCS
Valid Address
TAS
TAS
TAH
TCS
TAH
CSA#/
CSB#
TDY
TWR
TWR
IOW#
TDH
TDH
TDS
Valid Data
TDS
Valid Data
D0-D7
16Write
29
ST16C2552
áç
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
REV. 4.2
FIGURE 16. RECEIVE READY AND INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
RX
Stop
Bit
Start
Bit
D0:D7
D0:D7
D0:D7
TSSR
TSSR
TSSR
1 Byte
1 Byte
1 Byte
in RHR
in RHR
in RHR
INT
TSSR
TSSR
TSSR
Active
Data
Active
Data
Active
Data
RXRDY#
Ready
Ready
Ready
TRR
TRR
TRR
IOR#
(Reading data
out of RHR)
RXNFM
FIGURE 17. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
TX
(Unloading)
Stop
Bit
Start
Bit
D0:D7
D0:D7
D0:D7
IER[1]
enabled
ISR is read
ISR is read
ISR is read
INT*
TWRI
TWRI
TWRI
TSRT
TSRT
TSRT
TXRDY#
TWT
TWT
TWT
IOW#
(Loading data
into THR)
*INT is cleared when the ISR is read or when data is loaded into the THR.
TXNonFIFO
30
áç
ST16C2552
REV. 4.2
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
FIGURE 18. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B
Start
Bit
RX
S
S
S
S
S
T
S
D0:D7
D0:D7
D0:D7
T
D0:D7
TSSI
D0:D7
T
T
T
D0:D7
D0:D7
Stop
Bit
RX FIFO drops
below RX
Trigger Level
INT
TSSR
FIFO
Empties
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RXRDY#
First Byte is
Received in
RX FIFO
TRRI
TRR
IOR#
(Reading data out
of RX FIFO)
RXINTDMA#
FIGURE 19. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B
Start
Bit
Stop
Bit
RX
S
S
S
S
T
D0:D7
T
T
S
T
S
T
D0:D7
D0:D7
D0:D7
D0:D7
TSSI
D0:D7
D0:D7
RX FIFO drops
below RX
Trigger Level
INT
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
TSSR
FIFO
Empties
RXRDY#
TRRI
TRR
IOR#
(Reading data out
of RX FIFO)
RXFIFODMA
31
ST16C2552
áç
REV. 4.2
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
FIGURE 20. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B
Stop
Bit
Start
Bit
Last Data Byte
Transmitted
TX FIFO
Empty
TX
(Unloading)
T
S
S
S
S
T
D0:D7
D0:D7
T
S
D0:D7
T
D0:D7
T
D0:D7
T
S
D0:D7
T
TSRT
IER[1]
enabled
ISR is read
TX FIFO no
longer empty
INT*
TSI
TWRI
TX FIFO
Empty
Data in
TX FIFO
TXRDY#
TWT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when there is at least one character in the FIFO.
TXDMA#
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B
Stop
Bit
Start
Bit
Last Data Byte
Transmitted
TX FIFO
Empty
TX
(Unloading)
T
S
S
S
S
T
D0:D7
T
S
T
T
T
S
T
D0:D7
D0:D7
D0:D7
D0:D7
D0:D7
IER[1]
enabled
ISR is read
TSRT
TX FIFO no
longer empty
TSI
INT*
TWRI
TX FIFO
Empty
At least 1
empty location
in FIFO
TX FIFO
Full
TXRDY#
TWT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when there is at least one character in the FIFO.
TXDMA
32
áç
ST16C2552
REV. 4.2
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
PACKAGE DIMENSIONS (44 PIN PLCC)
44 LEAD PLASTIC LEADED CHIP CARRIER
(PLCC)
Rev. 1.00
C
D
Seating Plane
A2
D 1
45° x H
1
45° x H
2
2
1
44
B1
B
D
D1
D3
D2
e
R
D3
A1
A
Note: The control dimension is the millimeter column
INCHES
MAX
MILLIMETERS
SYMBOL
MIN
MIN
MAX
4.57
3.05
---
A
A1
A2
B
0.165
0.090
0.020
0.013
0.026
0.008
0.685
0.650
0.590
0.180
0.120
---
4.19
2.29
0.51
0.021
0.032
0.013
0.695
0.656
0.630
0.33
0.53
0.81
0.32
17.65
16.66
16.00
B1
0.66
C
D
0.19
17.40
16.51
14.99
D1
D2
D3
0.500 typ.
0.050 BSC
12.70 typ.
1.27 BSC
1.07
e
H1
0.042
0.056
0.048
0.045
1.42
1.22
1.14
H2
R
0.042
0.025
1.07
0.64
33
ST16C2552
áç
REV. 4.2
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
34
áç
ST16C2552
REV. 4.2
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
Revision History
Date
Revision
4.0
Description
February 2002
Changed to standard style format. Text descriptions were clarified and
simplified (eg. DMA operation, FIFO mode vs. Non-FIFO mode opera-
tions etc). Clarified timing diagrams. Renamed Rclk (Receive Clock) to
Bclk (Baud Clock) and timing symbols. Added TAH, TCS and OSC.
March 2002
4.1
4.2
Minor clarifications in text descriptions. Changed A0-A7 in Figures 14
and 15 to A0-A2.
September 2003
Changed to single column format. Corrected A2 and A0 pin numbers in
Pin Descriptions. Added Device Status to Ordering Information. Devices
with top markings of "A2 YYWW" and newer have 5V tolerant inputs. Devices
with top markings of "CC YYWW" and older do not have 5V tolerant inputs.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to
significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2003 EXAR Corporation
Datasheet September 2003.
Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
35
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