ST16C450IQ48 [EXAR]
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART); 通用异步接收器/发送器（UART）
| 型号： | ST16C450IQ48 |
| 厂家： | 
EXAR CORPORATION |
| 描述： | UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) |
| 文件： | 总28页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST16C450
UNIVERSAL ASYNCHRONOUS
RECEIVER/TRANSMITTER (UART)
September2003
GENERAL DESCRIPTION
PLCC Package
The ST16C450 is a universal asynchronous receiver
and transmitter. The ST16C450 is an improved ver-
sion of the NS16450 UART with higher operating
speed and lower access time. A programmable baud
rate generator is provided to select transmit and
receive clock rates from 50 Bps to 1.5 Mbps.
TheST16C450onboardstatusregisters providesthe
error conditions, type and status of the transfer
operation being performed. Included is complete
MODEM control capability, and a processor interrupt
system that may be software tailored to the user’s
requirements. The ST16C450 provides internal loop-
back capability for on board diagnostic testing.
The ST16C450 is available in 40 pin PDIP, 44 pin
PLCC, and 48 pin TQFP packages. It is fabricated in
an advanced CMOS process to achieve low drain
power and high speed requirements.
7
39
38
37
36
35
34
33
32
31
30
29
D5
D6
RESET
-OP1
-DTR
-RTS
-OP2
N.C.
INT
8
9
D7
10
11
12
13
14
15
16
17
RCLK
RX
N.C.
ST16C450CJ44
TX
CS0
N.C.
A0
CS1
-CS2
-BAUDOUT
A1
A2
FEATURES
• Pin to pin and functionally compatible to the Indus-
tryStandard16450
• 2.97 to 5.5 volt operation
• 1.5Mbpstransmit/receiveoperation(24MHz)
• Programmable word lengths (5, 6, 7, 8)
• Even, odd, force, or no parity generation and
detection
• Independent transmit and receive control
• Standard modem interface
• Low operating current ( 1.2mA typ.)
ORDERING INFORMATION
Part number
Package
Operating temperature
Device Status
ST16C450CP40
ST16C450CJ44
ST16C450CQ48
ST16C450IP40
ST16C450IJ44
ST16C450IQ48
40-Lead PDIP
44-Lead PLCC 0° C to + 70° C
48-Lead TQFP 0° C to + 70° C
40-Lead PDIP
44-Lead PLCC -40° C to + 85° C
48-Lead TQFP -40° C to + 85° C
0° C to + 70° C
Active. See the ST16C450CQ48 for new designs.
Active
Active
Active. See the ST16C450IQ48 for new designs.
Active
Active
-40° C to + 85° C
Rev.4.20
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017
ST16C450
Figure1,PACKAGEDESCRIPTION,ST16C450
48 Pin TQFP Package
40 Pin DIP Package
VCC
D0
D1
1
2
3
4
5
6
7
8
9
40
39
38
37
36
-RI
-CD
D2
N.C.
RESET
-OP1
-DTR
-RTS
-OP2
INT
N.C.
D5
1
2
36
35
34
33
32
31
30
29
28
27
26
25
-DSR
-CTS
D3
D4
D6
3
D5
35 RESET
D7
4
-OP1
-DTR
-RTS
-OP2
INT
D6
34
33
32
31
30
29
28
27
26
RCLK
N.C.
5
D7
6
ST16C450CQ48
RCLK
RX
7
N.C.
A0
TX
8
RX 10
TX 11
CS0
9
A1
CS1
10
11
12
N.C.
A0
CS0 12
A2
-CS2
-BAUDOUT
CS1 13
N.C.
A1
-CS2 14
A2
-BAUDOUT 15
XTAL1 16
25 -AS
17
CSOUT
XTAL2
24
23
22
21
-DDIS
IOR
-IOW 18
IOW 19
GND 20
-IOR
Rev.4.20
2
ST16C450
Figure 2, BLOCK DIAGRAM
Transmit
Shift
Register
TX
D0-D7
-IOR,IOR
-IOW,IOW
RESET
Receive
Shift
RX
Register
A0-A2
-AS
CS0,CS1
-CS2
-DDIS
CSOUT
-DTR,-RTS
-OP1,-OP2
Modem
Control
Logic
-CTS
-RI
-CD
-DSR
Clock
&
Baud Rate
Generator
INT
Rev.4.20
3
ST16C450
SYMBOL DESCRIPTION
Symbol
Pin
44
Signal
type
Pin Description
40
48
A0
28
31
30
29
25
28
I
I
I
I
Address-0 Select Bit Internal registers address selection.
Address-1 Select Bit Internal registers address selection.
Address-2 Select Bit Internal registers address selection.
A1
27
26
22
27
26
20
A2
IOR
Read data strobe. Its function is the same as -IOR (see -
IOR), except it is active high. Either an active -IOR or IOR
is required to transfer data from 16C450 to CPU during a
read operation.
CS0
CS1
-CS2
IOW
12
13
14
19
14
15
16
21
9
I
I
I
I
Chip Select-0. Logical 1 on this pin provides the chip select-
0 function.
10
11
17
Chip Select-1. Logical 1 on this pin provides the chip select-
1 function.
Chip Select -2. Logical 0 on this pin provides the chip select-
2 function.
Write data strobe. Its function is the same as -IOW (see -
IOW), but it acts as an active high input signal. Either -IOW
or IOW is required to transfer data from the CPU to
ST16C450 during a write operation.
-AS
25
28
24
I
Address Strobe. A logic 0 transition on -AS latches the state
of the chip selects and the register select bits, A0-A2. This
input is used when address and chip selects are not stable
for the duration of a read or write operation, i.e., a micropro-
cessor that needs to de-multiplex the address and data bits.
If not required, the -AS input can be permanently tied to a
logic 0 (it is edge triggered).
D0-D7
GND
1-8
20
2-9
22
43-47
2-4
I/O
Data Bus (Bi-directional) - These pins are the eight bit, tri-
state data bus for transferring information to or from the
controlling CPU. D0 is the least significant bit and the first
data bit in a transmit or receive serial data stream.
18
Pwr
SignalandPowerGround.
Rev.4.20
4
ST16C450
SYMBOL DESCRIPTION
Symbol
Pin
44
Signal
type
Pin Description
40
48
-IOR
21
24
20
33
19
I
Read data strobe (active low strobe). A logic 0 on this pin
transfers the contents of the ST16C450 data bus to the
CPU.
-IOW
INT
18
30
16
30
I
Write data strobe (active low strobe). A logic 0 on this pin
transfers the contents of the CPU data bus to the addressed
internal register.
O
InterruptRequest(activehigh). Interruptsareenabledinthe
interrupt enable register (IER), and when an interrupt con-
dition exists. Interrupt conditions include: receiver errors,
available receiver buffer data, transmit buffer empty, or
when a modem status flag is detected.
CSOUT
24
15
27
17
23
12
O
O
Chip select out. A high on this pin indicates that the
ST16C450 has been enabled by the chip select pin.
-BAUDOUT
Baud Rate Generator Output. This pin provides the 16X
clock of the selected data rate from the baud rate generator.
The RCLK pin must be connected externally to -BAUDOUT
when the receiver is operating at the same data rate.
-DDIS
23
26
22
O
Drive Disable. This pin goes to a logic 0 when the external
CPU is reading data from the ST16C450. This signal can be
used to disable external transceivers or other logic func-
tions.
-OP1
34
35
38
39
34
35
O
I
Output-1 (User Defined) - See bit-2 of modem control
register (MCR bit-2).
RESET
Reset. (active high) - A logic 1 on this pin will reset the
internal registers and all the outputs. The UART transmitter
output and the receiver input will be disabled during reset
time. (See ST16C450 External Reset Conditions for initial-
ization details.)
RCLK
9
10
5
I
Receive Clock Input. This pin is used as external 16X clock
input to the receiver section. External connection to -
Baudout pin is required in order to utilize the internal baud
rategenerator.
Rev.4.20
5
ST16C450
SYMBOL DESCRIPTION
Symbol
Pin
44
Signal
type
Pin Description
40
48
-OP2
31
35
31
O
Output-2(UserDefined).Thispinprovidestheuserageneral
purpose output. See bit-3 modem control register (MCR bit-
3).
VCC
40
16
44
18
42
Pwr
I
Power Supply Input.
XTAL1
14
Crystal or External Clock Input - Functions as a crystal input
or as an external clock input. A crystal can be connected
between this pin and XTAL2 to form an internal oscillator
circuit. An external 1 MW resistor is required between the
XTAL1 and XTAL2 pins (see figure 3). Alternatively, an
external clock can be connected to this pin to provide
custom data rates (Programming Baud Rate Generator
section).
XTAL2
-CD
17
38
36
19
42
40
15
40
38
O
I
OutputoftheCrystalOscillatororBufferedClock-(Seealso
XTAL1). Crystal oscillator output or buffered clock output.
Carrier Detect (active low) - A logic 0 on this pin indicates
that a carrier has been detected by the modem.
-CTS
I
Clear to Send (active low) - A logic 0 on the -CTS pin
indicates the modem or data set is ready to accept transmit
data from the ST16C450. Status can be tested by reading
MSR bit-4. This pin has no effect on the UART’s transmit or
receive operation.
-DSR
-DTR
37
33
41
37
39
33
I
Data Set Ready (active low) - A logic 0 on this pin indicates
the modem or data set is powered-on and is ready for data
exchange with the UART. This pin has no effect on the
UART’s transmit or receive operation.
O
Data Terminal Ready (active low) - A logic 0 on this pin
indicates that the ST16C450 is powered-on and ready. This
pin can be controlled via the modem control register.
Writing a logic 1 to MCR bit-0 will set the -DTR output to
logic 0, enabling the modem. This pin will be a logic 1 after
writing a logic 0 to MCR bit-0, or after a reset. This pin has
no effect on the UART’s transmit or receive operation.
Rev.4.20
6
ST16C450
SYMBOL DESCRIPTION
Symbol
Pin
44
Signal
type
Pin Description
40
48
-RI
39
43
41
I
RingIndicator(activelow)-Alogic0onthispinindicatesthe
modem has received a ringing signal from the telephone
line. A logic 1 transition on this input pin will generate an
interrupt.
-RTS
32
36
32
O
Request to Send (active low) - A logic 0 on the -RTS pin
indicatesthetransmitterhasdatareadyandwaitingtosend.
Writing a logic 1 in the modem control register (MCR bit-1)
will set this pin to a logic 0 indicating data is available. After
a reset this pin will be set to a logic 1. This pin has no effect
on the UART’s transmit or receive operation.
RX
TX
10
11
11
13
7
8
I
Receive Data - This pin provides the serial receive data
inputtotheST16C450. TheRXsignalwillbealogic1during
reset, idle (no data). During the local loop-back mode, the
RX input pin is disabled and TX data is internally connected
to the UART RX Input, internally, see figure 12.
O
Transmit Data - This pin provides the serial transmit data
from the ST16C450, the TX signal will be a logic 1 during
reset, idle (no data). During the local loop-back mode, the
TX input pin is disabled and TX data is internally connected
to the UART RX Input, see figure 12.
GENERAL DESCRIPTION
provide all these functions is fairly complex especially
whenmanufacturedonasingleintegratedsiliconchip.
The ST16C450 represents such an integration with
greatlyenhancedfeatures.TheST16C450isfabricated
with an advanced CMOS process. The ST16C450 is
designedtoworkwithhighspeedmodemsandshared
networkenvironments.
The ST16C450 provides serial asynchronous receive
data synchronization, parallel-to-serial and serial-to-
parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for
convertingtheserialdatastreamintoparalleldatathat
is required with digital data systems. Synchronization
for the serial data stream is accomplished by adding
start and stops bits to the transmit data to form a data
character (character orientated protocol). Data integ-
rity is insured by attaching a parity bit to the data
character. The parity bit is checked by the receiver for
any transmission bit errors. The electronic circuitry to
The ST16C450 is capable of operation to 1.5Mbps
with a 24 MHz crystal or external clock input.
With a crystal of 14.7464 MHz and through a software
option, the user can select data rates up to 460.8Kbps
or 921.6Kbps.
Rev.4.20
7
ST16C450
FUNCTIONAL DESCRIPTIONS
Internal Registers
The ST16C450 provides 11 internal registers for
monitoring and control. These registers are shown in
Table2below.Theseregisters functionasdataholding
registers (THR/RHR), interrupt status and control
registers (IER/ISR), line status and control registers,
(LCR/LSR),modemstatusandcontrolregisters(MCR/
MSR),programmabledatarate(clock)controlregisters
(DLL/DLM),andauserassessablescratchpadregister
(SPR).
Table 2, INTERNAL REGISTER DECODE
A2
A1
A0
READ MODE
WRITE MODE
General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR):
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Receive Holding Register
Interrupt Status Register
Transmit Holding Register
Interrupt Enable Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Scratchpad Register
Scratchpad Register
Baud Rate Register Set (DLL/DLM): Note *3
0
0
0
0
0
1
LSB of Divisor Latch
MSB of Divisor Latch
LSB of Divisor Latch
MSB of Divisor Latch
Note *3: These registers are accessible only when LCR bit-7 is set to a logic 1.
Rev.4.20
8
ST16C450
Programmable Baud Rate Generator
Alternatively,anexternalclockcanbeconnectedtothe
XTAL1 pin to clock the internal baud rate generator for
standard or custom rates. See figure 3 for crystal
oscillator connection.
The ST16C450 supports high speed modem tech-
nologies that have increased input data rates by
employing data compression schemes. For example
a 33.6Kbps modem that employs data compression
mayrequirea115.2Kbpsinputdatarate. A128.0Kbps
ISDN modem that supports data compression may
need an input data rate of 460.8Kbps. The ST16C450
can support a standard data rate of 921.6Kbps.
The generator divides the input 16X clock by any
divisor from 1 to 216 -1. The ST16C450 divides the
basic crystal or external clock by 16. The frequency of
the -BAUDOUT output pin is exactly 16X (16 times) of
theselectedbaudrate(-BAUDOUT=16xBaudRate).
Customized Baud Rates can be achieved by selecting
theproperdivisorvaluesfortheMSBandLSBsections
ofbaudrategenerator.
TheprogrammableBaudRateGeneratoriscapableof
accepting an input clock up to 24 MHz, as required for
supportinga1.5Mbpsdatarate.TheST16C450canbe
configured for internal or external clock operation. For
internalclockoscillatoroperation,anindustrystandard
microprocessor crystal (parallel resonant/ 22-33 pF
load) is connected externally between the XTAL1 and
XTAL2 pins, with an external 1 MΩ resistor across it.
ProgrammingtheBaudRateGeneratorRegistersDLM
(MSB) and DLL (LSB) provides a user capability for
selecting the desired final baud rate. The example in
Table3below.
Table3,BAUDRATEGENERATORPROGRAMMINGTABLE(1.8432MHzCLOCK):
Output
User
User
DLM
Program
Value
DLL
Program
Value
Baud Rate 16 x Clock 16 x Clock
Divisor
(Decimal)
Divisor
(HEX)
(HEX)
(HEX)
50
75
150
300
600
1200
2400
4800
7200
9600
19.2k
38.4k
57.6k
115.2k
2304
1536
768
384
192
96
48
24
16
12
900
600
300
180
C0
60
30
18
10
0C
09
06
03
01
00
00
00
00
00
00
00
00
00
00
00
00
00
80
C0
60
30
18
10
0C
06
03
02
01
6
3
2
1
06
03
02
01
Rev.4.20
9
ST16C450
Figure3,EXTERNALCRYSTALOSCILLATOR
CONNECTION
associated interface pins, and instead are connected
togetherinternally(SeeFigure4).The-CTS,-DSR,-CD,
and -RI are disconnected from their normal modem
control inputs pins, and instead are connected inter-
nally to -DTR, -RTS, -OP1 and -OP2. Loop-back test
dataisenteredintothetransmitholdingregisterviathe
user data bus interface, D0-D7. The transmit UART
serializes the data and passes the serial data to the
receiveUARTviatheinternalloop-backconnection.The
receiveUARTconvertstheserialdatabackintoparallel
data that is then made available at the user data
interface, D0-D7. The user optionally compares the
receiveddatatotheinitialtransmitteddataforverifying
errorfreeoperationoftheUARTTX/RXcircuits.
R1
50-120
Inthismode,thereceiverandtransmitterinterruptsare
fullyoperational.TheModemControlInterruptsarealso
operational. However, the interrupts can only be read
using lower four bits of the Modem Control Register
(MCR bits 0-3) instead of the four Modem Status
Register bits 4-7. The interrupts are still controlled by
the IER.
R2
1M
X1
1.8432 MHz
C1
22pF
C2
33pF
Loopback Mode
The internal loop-back capability allows onboard diag-
nostics. In the loop-back mode the normal modem
interface pins are disconnected and reconfigured for
loop-back internally. In this mode MSR bits 4-7 are
also disconnected. However, MCR register bits 0-3
can be used for controlling loop-back diagnostic test-
ing. In the loop-back mode -OP1 and -OP2 in the MCR
register (bits 0-1) control the modem -RI and -CD
inputs respectively. MCR signals -DTR and -RTS (bits
0-1) are used to control the modem -CTS and -DSR
inputs respectively. The transmitter output (TX) and
the receiver input (RX) are disconnected from their
Rev.4.20
10
ST16C450
Figure4,INTERNALLOOPBACKMODEDIAGRAM
Transmit
Holding
Registers
Transmit
Shift
Register
TX
D0-D7
-IOR,IOR
-IOW,IOW
RESET
Receive
Holding
Registers
Receive
Shift
Register
RX
A0-A2
-AS
CS0,CS1
-CS2
-RTS
-DDIS
CSOUT
-CD
-DTR
INT
-RI
-OP1
Clock
&
Baud Rate
-DSR
-OP2
Generator
-CTS
Rev.4.20
11
ST16C450
REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the twelve ST16C450 internal registers. The as-
signed bit functions are more fully defined in the following paragraphs.
Table 4, ST16C450 INTERNAL REGISTERS
A2 A1 A0
Register
[Default]
Note *5
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
General Register Set
0
0
0
0
0
0
0
0
1
RHR [XX]
THR [XX]
IER [00]
bit-7
bit-7
0
bit-6
bit-6
0
bit-5
bit-5
0
bit-4
bit-4
0
bit-3
bit-3
bit-2
bit-2
bit-1
bit-1
bit-0
bit-0
modem
status
interrupt
receive
line
status
interrupt
transmit
holding
register
receive
holding
register
0
0
1
1
1
1
0
0
0
1
0
1
ISR [01]
LCR [00]
MCR [00]
LSR [60]
0
0
0
0
INT
priority
bit-2
INT
priority
bit-1
INT
priority
bit-0
INT
status
divisor
latch
enable
set
break
set
parity
even
parity
parity
enable
stop
bits
word
length
bit-1
word
length
bit-0
0
0
0
0
loop
back
-OP2
-OP1
-RTS
-DTR
trans.
empty
trans.
holding
empty
break
interrupt
framing
error
parity
error
overrun
error
receive
data
ready
1
1
1
1
0
1
MSR [X0]
SPR [FF]
CD
RI
DSR
bit-5
CTS
bit-4
delta
-CD
delta
-RI
delta
-DSR
delta
-CTS
bit-7
bit-6
bit-3
bit-2
bit-1
bit-0
Special Register Set: Note *3
0
0
0
0
0
1
DLL[XX]
DLM[XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-9
bit-0
bit-8
bit-15
bit-14
bit-13
bit-12
bit-11
bit-10
Note *3: The Special register set is accessible only when LCR bit-7 is set to a logic 1.
Note *5: The value represents the register’s initialized HEX value. An “X” signifies a 4-bit un-initialized nibble.
Rev.4.20
12
ST16C450
Transmit and Receive Holding Register
IER BIT-2:
Logic 0 = Disable the receiver line status interrupt.
(normaldefaultcondition)
Logic 1 = Enable the receiver line status interrupt.
The serial transmitter section consists of an 8-bit
Transmit Hold Register (THR) and Transmit Shift
Register (TSR). The status of the THR is provided in
the Line Status Register (LSR). Writing to the THR
transfers the contents of the data bus (D7-D0) to the
THR, providing that the THR or TSR is empty. The
THR empty flag in the LSR register will be set to a logic
1 when the transmitter is empty or when data is
transferred to the TSR. Note that a write operation can
be performed when the transmit holding register
empty flag is set.
IER BIT-3:
Logic 0 = Disable the modem status register interrupt.
(normal default condition)
Logic 1 = Enable the modem status register interrupt.
IER BIT 4-7: Not used and set to “0”.
Interrupt Status Register (ISR)
The serial receive section also contains an 8-bit
Receive Holding Register, RHR. Receive data is
removed from the ST16C450 and receive by reading
the RHR register. The receive section provides a
mechanism to prevent false starts. On the falling edge
of a start or false start bit, an internal receiver counter
starts counting clocks at 16x clock rate. After 7 1/2
clocks the start bit time should be shifted to the center
of the start bit. At this time the start bit is sampled and
if it is still a logic 0 it is validated. Evaluating the start
bit in this manner prevents the receiver from assem-
bling a false character. Receiver status codes will be
posted in the LSR.
The ST16C450 provides four levels of prioritized
interrupts to minimize external software interaction.
The Interrupt Status Register (ISR) provides the user
with four interrupt status bits. Performing a read cycle
on the ISR will provide the user with the highest
pending interrupt level to be serviced. No other inter-
rupts are acknowledged until the pending interrupt is
serviced. Whenever the interrupt status register is
read, the interrupt status is cleared. However it should
be noted that only the current pending interrupt is
clearedbytheread.Alowerlevelinterruptmaybeseen
after rereading the interrupt status bits. The Interrupt
SourceTable5(below)showsthedatavalues(bit0-3)
for the four prioritized interrupt levels and the interrupt
sourcesassociatedwitheachoftheseinterruptlevels:
Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the inter-
rupts from receiver ready, transmitter empty, line
status and modem status registers. These interrupts
would normally be seen on the ST16C450 INT output
pin.
IER BIT-0:
Logic 0 = Disable the receiver ready interrupt. (normal
defaultcondition)
Logic 1 = Enable the receiver ready interrupt.
IER BIT-1:
Logic 0 = Disable the transmitter empty interrupt.
(normal default condition)
Logic 1 = Enable the transmitter empty interrupt.
Rev.4.20
13
ST16C450
Table5, INTERRUPTSOURCETABLE
Priority
Level
[ISR]
Bit-3 Bit-2Bit-1 Bit-0 Source of the interrupt
1
2
3
4
0
0
0
0
1
1
0
0
1
0
1
0
0
0
0
0
LSR (Receiver Line Status Register)
RXRDY(ReceivedDataReady)
TXRDY(TransmitterHoldingRegisterEmpty)
MSR (Modem Status Register)
LCR BIT-2: (logic 0 or cleared is the default condition)
The length of stop bit is specified by this bit in conjunc-
tion with the programmed word length.
ISR BIT-0:
Logic 0 = An interrupt is pending and the ISR contents
may be used as a pointer to the appropriate interrupt
serviceroutine.
Logic 1 = No interrupt pending. (normal default condi-
tion)
BIT-2
Word length
Stop bit
length
(Bittime(s))
ISRBIT1-3:(logic0orclearedisthedefaultcondition)
These bits indicate the source for a pending interrupt
at interrupt priority levels 1, 2, and 3 (See Interrupt
Source Table).
0
1
1
5,6,7,8
5
6,7,8
1
1-1/2
2
ISR BIT 4-7: Not used and set to “0”.
LCR BIT-3:
Line Control Register (LCR)
Parity or no parity can be selected via this bit.
Logic 0 = No parity (normal default condition)
Logic 1 = A parity bit is generated during the transmis-
sion, receiver checks the data and parity for transmis-
sion errors.
The Line Control Register is used to specify the
asynchronous data communication format. The word
length, the number of stop bits, and the parity are
selected by writing the appropriate bits in this register.
LCR BIT-4:
LCR BIT 0-1: (logic 0 or cleared is the default condi-
If the parity bit is enabled with LCR bit-3 set to a logic
1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd
number of logic 1’s in the transmitted data. The
receiver must be programmed to check the same
format.(normaldefaultcondition)
Logic 1 = EVEN Parity is generated by forcing an even
the number of logic 1’s in the transmitted. The receiver
must be programmed to check the same format.
tion)
These two bits specify the word length to be transmit-
ted or received.
BIT-1
BIT-0
Word length
0
0
1
1
0
1
0
1
5
6
7
8
LCR BIT-5:
If the parity bit is enabled, LCR BIT-5 selects the
forced parity format.
Rev.4.20
14
ST16C450
LCRBIT-5=logic0,parityisnotforced(normaldefault
condition)
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit
is forced to a logical 1 for the transmit and receive
data.
MCRBIT-1:
Logic0=Force-RTSoutputtoalogic1.(normaldefault
condition)
Logic 1 = Force -RTS output to a logic 0.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit
is forced to a logical 0 for the transmit and receive
data.
MCRBIT-2:
Logic 0 = Set -OP1 output to a logic 1. (normal default
condition)
Logic 1 = Set -OP1 output to a logic 0.
LCR
LCR
LCR
Parity selection
MCR BIT-3:
Bit-5 Bit-4 Bit-3
Logic 0 = Set -OP2 output to a logic 1. (normal default
condition)
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
No parity
Odd parity
Even parity
Force parity”1”
Forced parity “0”
Logic 1 = Set -OP2 output to a logic 0.
MCR BIT-4:
Logic 0 = Disable loop-back mode. (normal default
condition)
Logic 1 = Enable local loop-back mode (diagnostics).
LCR BIT-6:
MCR BIT 5-7: Not used and set to “0”.
When enabled the Break control bit causes a break
condition to be transmitted (the TX output is forced to
a logic 0 state). This condition exists until disabled by
setting LCR bit-6 to a logic 0.
Logic 0 = No TX break condition. (normal default
condition)
Line Status Register (LSR)
This register provides the status of data transfers
between. the ST16C450 and the CPU.
LSR BIT-0:
Logic 1 = Forces the transmitter output (TX) to a logic
0 for alerting the remote receiver to a line break
condition.
Logic 0 = No data in receive holding register. (normal
default condition)
Logic 1 = Data has been received and is saved in the
receive holding register.
LCR BIT-7:
The internal baud rate counter latch and Enhance
Feature mode enable.
LSR BIT-1:
Logic 0 = Divisor latch disabled. (normal default
condition)
Logic 1 = Divisor latch and enhanced feature register
enabled.
Logic 0 = No overrun error. (normal default condition)
Logic 1 = Overrun error. A data overrun error occurred
in the receive shift register. This happens when addi-
tionaldataarriveswhiletheRHRisfull. Inthiscasethe
previous data in the shift register is overwritten. Note
that under this condition the data byte in the receive
shift register is not transfer into the RHR, therefore the
data in the RHR is not corrupted by the error.
Modem Control Register (MCR)
Thisregistercontrolstheinterfacewiththemodemora
peripheraldevice.
LSR BIT-2:
MCR BIT-0:
Logic 0 = No parity error (normal default condition)
Logic 1 = Parity error. The receive character does not
have correct parity information and is suspect.
Logic 0 = Force -DTR output to a logic 1. (normal
default condition)
Logic 1 = Force -DTR output to a logic 0.
Rev.4.20
15
ST16C450
LSR BIT-3:
MSR BIT-1:
Logic 0 = No framing error (normal default condition).
Logic 1 = Framing error. The receive character did not
have a valid stop bit(s).
Logic 0 = No -DSR Change (normal default condition)
Logic 1 = The -DSR input to the ST16C450 has
changed state since the last time it was read. A
modem Status Interrupt will be generated.
LSR BIT-4:
Logic 0 = No break condition (normal default condi-
tion)
MSR BIT-2:
Logic 1 = The receiver received a break signal.
Logic 0 = No -RI Change (normal default condition)
Logic 1 = The -RI input to the ST16C450 has changed
from a logic 0 to a logic 1. A modem Status Interrupt
will be generated.
LSR BIT-5:
ThisbitindicatesthattheST16C450isreadytoaccept
new characters for transmission. This bit causes the
ST16C450 to issue an interrupt to the CPU when the
transmit holding register is empty and the interrupt
enable is set.
MSR BIT-3:
Logic 0 = No -CD Change (normal default condition)
Logic 1 = Indicates that the -CD input to the has
changed state since the last time it was read. A
modem Status Interrupt will be generated.
Logic 0 = Transmit holding register is not empty.
(normal default condition)
Logic 1 = Transmit holding register is empty. When
this bit is a logic 1, the CPU can load a new characters
into the Transmit Holding Register for transmission.
MSR BIT-4:
CTS (active high, logical 1). Normally this bit is the
compliment of the -CTS input. In the loop-back mode,
this bit is equivalent to the RTS bit in the MCR register.
LSR BIT-6:
Logic 0 = Transmitter holding and shift registers are
MSR BIT-5:
full.
Logic 1 = Transmitter holding and shift registers are
empty.
DSR (active high, logical 1). Normally this bit is the
compliment of the -DSR input. In the loop-back mode,
this bit is equivalent to the DTR bit in the MCR register.
LSR BIT-7: Not used and set to “0”.
MSR BIT-6:
Modem Status Register (MSR)
RI (active high, logical 1). Normally this bit is the
complimentofthe-RIinput. Intheloop-backmodethis
bit is equivalent to the OP1 bit in the MCR register.
This register provides the current state of the control
interface signals from the modem, or other peripheral
device that the ST16C450 is connected to. Four bits
of this register are used to indicate the changed
information. These bits are set to a logic 1 whenever
a control input from the modem changes state. These
bits are set to a logic 0 whenever the CPU reads this
register.
MSR BIT-7:
CD (active high, logical 1). Normally this bit is the
compliment of the -CD input. In the loop-back mode
this bit is equivalent to the OP2 bit in the MCR register.
MSR BIT-0:
Logic 0 = No -CTS Change (normal default condition)
Logic 1 = The -CTS input to the ST16C450 has
changed state since the last time it was read. A
modem Status Interrupt will be generated.
Rev.4.20
16
ST16C450
Scratchpad Register (SPR)
The ST16C450 provides a temporary data register to
store 8 bits of user information.
ST16C450EXTERNALRESETCONDITIONS
REGISTERS
RESET STATE
IER
ISR
IER BITS 0-7 = logic 0
ISR BIT-0=1, ISR BITS 1-7 = logic
0
LCR, MCR
LSR
BITS 0-7 = logic 0
LSR BITS 0-4 = logic 0,
LSR BITS 5-6 = logic 1 LSR, BIT
7 = logic 0
MSR
MSR BITS 0-3 = logic 0,
MSR BITS 4-7 = logic levels of the
input signals
SIGNALS
RESET STATE
TX
Logic 1
Logic 1
Logic 1
Logic 1
Logic 1
Logic 0
Logic 0
-OP1
-OP2
-RTS
-DTR
CSOUT
INT
Rev.4.20
17
ST16C450
AC ELECTRICAL CHARACTERISTICS
TA=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified.
Symbol
Parameter
Limits
3.3
Limits
5.0
Units Conditions
Min
Max
Min
Max
T1w,T2w Clock pulse duration
17
17
ns
MHz
ns
ns
ns
T3w
T4w
Oscillator/Clockfrequency
Address strobe width
8
24
35
5
5
25
0
5
T
T
5s
5h
Address setup time
Address hold time
T6s
Address setup time
5
0
ns
T
6h
Chip select hold time
0
0
ns
T7d
T7w
T7h
T8d
-IOR delay from chip select
-IOR strobe width
Chip select hold time from -IOR
-IOR delay from address
Read cycle delay
CSOUT delay from chip select
-IOR to -DDIS delay
Delay from -IOR to data
Data disable time
-IOW delay from chip select
-IOW strobe width
Chip select hold time from -IOW
-IOW delay from address
Write cycle delay
10
35
0
10
40
10
25
0
10
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1:
Note 1:
Note 1:
T9d
T10d
T11d
T12d
T12h
T13d
T13w
T13h
T14d
T15d
T16s
T16h
T17d
T18d
15
15
35
25
10
10
25
15
100 pF load
100 pF load
10
40
0
10
40
20
5
10
25
0
10
30
15
5
Note 1:
Note 1:
Data setup time
Data hold time
Delay from -IOW to output
Delay to set interrupt from MODEM
input
50
40
40
35
100 pF load
100 pF load
T19d
T20d
T21d
T22d
T23d
Delay to reset interrupt from -IOR
Delay from stop to set interrupt
Delay from -IOR to reset interrupt
Delay from stop to interrupt
Delay from initial INT reset to transmit
start
40
1
45
45
24
35
1
40
40
24
ns
Rclk
ns
ns
Rclk
100 pF load
100 pF load
8
8
T24d
TR
N
Delay from -IOW to reset interrupt
Reset pulse width
Baud rate devisor
45
40
ns
ns
Rclk
40
1
40
1
216-1
216-1
Note 1: Applicable only when -AS is tied low.
Rev.4.20
18
ST16C450
ABSOLUTE MAXIMUM RATINGS
Supply range
7 Volts
GND - 0.3 V to VCC +0.3 V
-40° C to +85° C
Voltage at any pin
Operating temperature
Storage temperature
Package dissipation
-65° C to 150° C
500 mW
DC ELECTRICAL CHARACTERISTICS
TA=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified.
Symbol
Parameter
Limits
3.3
Limits
5.0
Units Conditions
Min
Max
Min
Max
VILCK
VIHCK
VIL
Clock input low level
Clock input high level
Inputlowlevel
-0.3
2.4
-0.3
2.0
0.6
VCC
0.8
-0.5
3.0
-0.5
2.2
0.6
VCC
0.8
VCC
0.4
V
V
V
V
V
V
V
V
µA
µA
mA
pF
VIH
Inputhighlevel
VOL
VOL
VOH
VOH
IIL
ICL
ICC
CP
Output low level on all outputs
Output low level on all outputs
Output high level
Output high level
Input leakage
Clock leakage
Avg power supply current
Input capacitance
IOL= 5 mA
IOL= 4 mA
IOH= -5 mA
IOH= -1 mA
0.4
2.4
2.0
±10
±10
1.3
5
±10
±10
3
5
Rev.4.20
19
ST16C450
T1w
T2w
EXTERNAL
CLOCK
T3w
-BAUDOUT
1/2 -BAUDOUT
1/3 -BAUDOUT
1/3> -BAUDOUT
X450-CK-1
Clock timing
Rev.4.20
20
ST16C450
T4w
-AS
T5h
T6h
T5s
Valid
Address
A0-A2
T6s
-CS2
CS1-CS0
Valid
T7d
T7h
T7w
T8d
T9d
-IOR
IOR
Active
T10d
T10d
Active
CSOUT
-DDIS
T11d
T11d
T12h
Active
T12d
Data
D0-D7
X450-RD-1
General read timing
Rev.4.20
21
ST16C450
T4w
-AS
T5h
T6h
T5s
Valid
Address
A0-A2
T6s
-CS2
CS1-CS0
Valid
T13d
T14d
T13h
T16h
T13w
T15d
-IOW
IOW
Active
T16s
Data
D0-D7
X550-WD-1
General write timing
Rev.4.20
22
ST16C450
-IOW
IOW
Active
T17d
Change of state
-RTS
-DTR
Change of state
-CD
-CTS
Change of state
Change of state
-DSR
T18d
T18d
Active
INT
Active
Active
Active
Active
T19d
-IOR
IOR
Active
T18d
Change of state
X450-MD-1
-RI
Modem input/output timing
Rev.4.20
23
ST16C450
START
BIT
STOP
BIT
DATA BITS (5-8)
RX
D0
D1
D2
D3
D4
D5
D6 D7
PARITY
BIT
NEXT
DATA
START
BIT
5 DATA BITS
6 DATA BITS
7 DATA BITS
T20d
Active
INT
T21d
-IOR
IOR
16 BAUD RATE CLOCK
X450-RX-1
Receive timing
Rev.4.20
24
ST16C450
START
BIT
STOP
BIT
DATA BITS (5-8)
TX
D0
D1
D2
D3
D4
D5
D6 D7
PARITY
BIT
NEXT
DATA
START
BIT
5 DATA BITS
6 DATA BITS
7 DATA BITS
T22d
Active
Tx Ready
INT
T24d
T23d
-IOW
IOW
Active
Active
16 BAUD RATE CLOCK
X450-TX-1
Transmit timing
Rev.4.20
25
ST16C450
PACKAGE OUTLINE DRAWING
44LEAD PLASTIC LEADED CHIP CARRIER
(PLCC)
C
D
Seating Plane
A2
D 1
45° x H1
45° x H2
2
1
44
B1
B
D
D1
D3
D2
e
R
D3
A1
A
Note: The control dimension is the inch column
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
A1
A2
B
0.165
0.090
0.020
0.013
0.026
0.008
0.685
0.650
0.590
0.180
0.120
-----
4.19
2.29
4.57
3.05
0.51
------
0.53
0.021
0.032
0.013
0.695
0.656
0.630
0.33
B1
C
0.66
0.81
0.19
0.32
D
17.40
16.51
14.99
17.65
16.66
16.00
D1
D2
D3
e
0.500 typ
0.50 BSC
12.70 typ
1.27BSC
1.07
H1
H2
R
0.042
0.056
0.048
0.045
1.42
1.22
1.14
0.042
0.025
1.07
0.64
Rev.4.20
26
ST16C450
PACKAGEOUTLINEDRAWING
48 LEAD THIN QUAD FLAT PACK
(TQFP)
D
D1
36
25
37
24
D1
D
48
13
1
1
2
B
e
A2
C
A
Seating
Plane
α
A1
L
Note: The control dimension is the millimeter column
INCHES MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
A1
A2
B
0.039
0.002
0.037
0.007
0.004
0.346
0.272
0.047
0.006
0.041
0.011
0.008
0.362
0.280
1.00
0.05
0.95
0.17
0.09
8.80
6.90
1.20
0.15
1.05
0.27
0.20
9.20
7.10
C
D
D1
e
0.20 BSC
0.50BSC
L
0.018
0.030
7°
0.45
0°
0.75
7°
α
0°
Rev.4.20
27
ST16C450
EXPLANATIONOFDATASHEETREVISIONS:
FROM
4.10
TO
CHANGES
DATE
4.20
Added revision history. Added Device Status to front page.
Sept 2003
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improvedesign,performanceorreliability.EXARCorporationassumesnoresponsibilityfortheuseofanycircuits
describedherein,conveysnolicenseunderanypatentorotherright,andmakesnorepresentationthatthecircuits
arefreeofpatentinfringement.Chartsandschedulescontainedhereinareonlyforillustrationpurposesandmay
vary depending upon a user's specific application. While the information in this publication has been carefully
checked; no responsibility, however, is assumed for inaccuracies.
EXARCorporationdoesnotrecommendtheuseofanyofitsproductsinlifesupportapplicationswherethefailure
of the product can reasonably be expected to cause failure of the life support system or to significantly affect its
safetyoreffectiveness.ProductsarenotauthorizedforuseinsuchapplicationsunlessEXARCorporationreceives,
in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user
assumesallsuchrisks;(c)potentialliabilityofEXARCorporationisadequatelyprotectedunderthecircumstances.
Copyright 2003 EXARCorporation
Datasheet September 2003
Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com
Reproduction, in part or whole, without prior written consent of EXAR Corporation is prohibited.
Rev.4.20
28
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