ST16C550IJ44-F_技术文档

ST16C550

UART WITH 16-BYTE FIFO’s

September 2003

GENERAL DESCRIPTION

PLCC Package

The ST16C550 (550) is a universal asynchronous re-

ceiverandtransmitterwith16bytetransmitandreceive

FIFO. It operates at 2.97 to 5.5 volts. A programmable

baud rate generator can select transmit and receive

clock rates from 50 bps to 1.5 Mbps.

7

39

38

37

36

35

34

33

32

31

30

29

D5

D6

RESET

-OP1

-DTR

-RTS

-OP2

N.C.

INT

TheST16C550isanimprovedversionofthe NS16C550

UART with higher operating speed and lower access

time.TheST16C550onboardstatusregisters provides

the error conditions, type and status of the transfer

operation being performed. Included is complete MO-

DEM control capability, and a processor interrupt

system that may be software tailored to the user’s

requirements. The ST16C550 provides internal loop-

back capability for on board diagnostic testing.

TheST16C550isavailablein40pinPDIP,44pinPLCC,

and 48 pin TQFP packages. It is fabricated in an

advanced CMOS process to achieve low drain power

andhighspeedrequirements.

8

9

D7

10

11

12

13

14

15

16

17

RCLK

RX

N.C.

ST16C550CJ44

TX

CS0

-RXRDY

A0

CS1

-CS2

-BAUDOUT

A1

A2

FEATURES

• PintopinandfunctionallycompatibletotheIndustry

Standard16C550

• 2.97 to 5.5 volt operation

• 24MHz clock operation at 5V

• 16MHz clock operation at 3.3V

• 16 byte transmit FIFO

• 16 byte receive FIFO with error flags

• Fullduplexoperation

• Transmitandreceivecontrol

• FourselectablereceiveFIFOinterrupttriggerlevels

• Standardmodeminterface

• Compatible with ST16C450

• Low operating current ( 1.2mA typ.)

ORDERING INFORMATION

Part number

Package

Operating temperature

Device Status

ST16C550CP40

ST16C550CJ44

ST16C550CQ48

ST16C550IP40

ST16C550IJ44

ST16C550IQ48

40-Lead PDIP

44-Lead PLCC 0° C to + 70° C

48-Lead TQFP 0° C to + 70° C

40-Lead PDIP

44-Lead PLCC -40° C to + 85° C

48-Lead TQFP -40° C to + 85° C

0° C to + 70° C

Active. See the ST16C550CQ48 for new designs.

Active

Active. See the ST16C550IQ48 for new designs.

Active

-40° C to + 85° C

Rev.4.30

EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017

ST16C550

Figure1,PACKAGEDESCRIPTION,ST16C550

48 Pin TQFP Package

40 Pin DIP Package

VCC

-RI

D0

D1

1

2

3

4

5

6

7

8

9

40

39

38

37

36

35

34

33

32

-CD

D2

N.C.

RESET

-OP1

-DTR

-RTS

-OP2

INT

N.C.

D5

1

2

36

35

34

33

32

31

30

29

28

27

26

25

-DSR

-CTS

RESET

-OP1

-DTR

-RTS

D3

D4

D6

3

D5

D7

4

D6

RCLK

N.C.

5

D7

6

ST16C550CQ48

RCLK

RX

7

-RXRDY

A0

TX

8

RX 10

TX 11

31 -OP2

30 INT

CS0

9

A1

CS1

10

11

12

13

-RXRDY

CS0

CS1

29

28

27

26

A2

-CS2

-BAUDOUT

A0

A1

A2

N.C.

-CS2 14

-BAUDOUT 15

XTAL1 16

XTAL2 17

-IOW 18

25 -AS

-TXRDY

24

23

22

-DDIS

IOR

IOW 19

20

21 -IOR

GND

Rev.4.30

2

ST16C550

Figure 2, BLOCK DIAGRAM

Transmit

FIFO

Registers

Transmit

Shift

Register

TX

D0-D7

-IOR,IOR

-IOW,IOW

RESET

Receive

FIFO

Receive

Shift

RX

Registers

Register

A0-A2

-AS

CS0,CS1

-CS2

-DDIS

-DTR,-RTS

-OP1,-OP2

Modem

Control

Logic

-CTS

-RI

-CD

-DSR

Clock

&

Baud Rate

Generator

INT

-RXRDY

-TXRDY

Rev.4.30

3

ST16C550

SYMBOL DESCRIPTION

Symbol

44

Signal

type

Pin Description

40

48

A0

28

31

30

29

25

28

I

Address-0 Select Bit Internal registers address selection.

Address-1 Select Bit Internal registers address selection.

Address-2 Select Bit Internal registers address selection.

A1

27

26

22

27

26

20

A2

IOR

Read data strobe. Its function is the same as -IOR (see -

IOR), except it is active high. Either an active -IOR or IOR

is required to transfer data from 16C550 to CPU during a

read operation. Connect to logic 0 when using -IOR.

CS0

CS1

-CS2

IOW

12

13

14

19

14

15

16

21

9

I

Chip Select-0. Logical 1 on this pin provides the chip select-

0 function. Connect CS0 to logic 1 if using CS1 or -CS2.

10

11

17

Chip Select-1. Logical 1 on this pin provides the chip select-

1 function. Connect CS1 to logic 1 if using CS0 or -CS2.

Chip Select -2. Logical 0 on this pin provides the chip select-

2 function. Connect to logic 0 if using CS0 or CS1.

Write data strobe. Its function is the same as -IOW (see -

IOW), but it acts as an active high input signal. Either -IOW

or IOW is required to transfer data from the CPU to

ST16C550duringawriteoperation.Connecttologic0when

using -IOW.

-AS

25

28

24

I

Address Strobe. A logic 1 transition on -AS latches the state

of the chip selects and the register select bits, A0-A2. This

input is used when address and chip selects are not stable

for the duration of a read or write operation, i.e., a micropro-

cessor that needs to de-multiplex the address and data bits.

If not required, the -AS input can be permanently tied to a

logic 0.

D0-D7

GND

1-8

20

2-9

22

43-47

2-4

I/O

Data Bus (Bi-directional) - These pins are the eight bit, tri-

state data bus for transferring information to or from the

controlling CPU. D0 is the least significant bit and the first

data bit in a transmit or receive serial data stream.

18

Pwr

SignalandPowerGround.

Rev.4.30

4

ST16C550

SYMBOL DESCRIPTION

Symbol

44

Signal

type

Pin Description

40

48

-IOR

21

24

20

33

19

I

Read data strobe (active low strobe). A logic 0 on this pin

transfersthecontentsoftheST16C550databustotheCPU.

Connect to logic 1 when using IOR.

-IOW

INT

18

30

16

30

I

Write data strobe (active low strobe). A logic 0 on this pin

transfers the contents of the CPU data bus to the addressed

internal register. Connect to logic 1 when using IOW.

O

InterruptRequest(activehigh). Interruptsareenabledinthe

interrupt enable register (IER), and when an interrupt con-

dition exists. Interrupt conditions include: receiver errors,

available receiver buffer data, transmit buffer empty, or

when a modem status flag is detected.

-RXRDY

29

32

29

O

Receive Ready. When operating in the FIFO mode, one of

two types of DMA signaling can be selected using the FIFO

control register bit-3. When operating in the ST16C450

mode, only DMA mode “0” is allowed. Mode “0” supports

single transfer DMA in which a transfer is made between

CPU bus cycles. Mode “1” supports multi-transfer DMA in

which multiple transfers are made continuously until the

receiverFIFOhasbeenemptied. InDMAmode“0”-RXRDY

is low, when there is at least one character in the receiver

FIFOorreceiveholdingregister. InDMAmode“1”, -RXRDY

is low, when the trigger level or the time-out has been

reached.

-TXRDY

24

27

23

O

Transmit Ready. When operating in the FIFO mode, one of

two types of DMA signaling can be selected using the FIFO

control register bit-3. When operating in the ST16C450

mode, only DMA mode “0” is allowed. Mode “0” supports

single transfer DMA in which a transfer is made between

CPU bus cycles. Mode “1” supports multi-transfer DMA in

which multiple transfers are made continuously until the

transmit FIFO has been filled.

-BAUDOUT

15

17

12

O

Baud Rate Generator Output. This pin provides the 16X

clock of the selected data rate from the baud rate generator.

The RCLK pin must be connected externally to -BAUDOUT

when the receiver is operating at the same data rate.

Rev.4.30

5

ST16C550

SYMBOL DESCRIPTION

Symbol

44

Signal

type

Pin Description

40

48

-DDIS

23

26

22

O

Drive Disable. This pin goes to a logic 0 when the external

CPU is reading data from the ST16C550. This signal can be

used to disable external transceivers or other logic func-

tions.

-OP1

34

35

38

39

34

35

O

I

Output-1 (User Defined) - See bit-2 of modem control

register (MCR bit-2).

RESET

Reset. (active high) - A logic 1 on this pin will reset the

internal registers and all the outputs. The UART transmitter

output and the receiver input will be disabled during reset

time. (See ST16C550 External Reset Conditions for initial-

ization details.)

RCLK

-OP2

9

10

35

5

I

Receive Clock Input. This pin is used as external 16X clock

input to the receiver section. External connection to -

Baudout pin is required in order to utilize the internal baud

rate generator.

31

O

Output-2 (User Defined). This pin provides the user a

general purpose output. See bit-3 modem control register

(MCR bit-3).

VCC

40

16

44

18

42

Pwr

I

Power Supply Input.

XTAL1

14

Crystal or External Clock Input - Functions as a crystal input

or as an external clock input. A crystal can be connected

between this pin and XTAL2 to form an internal oscillator

circuit. An external 1 MΩ resistor is required between the

XTAL1 and XTAL2 pins (see figure 3). Alternatively, an

external clock can be connected to this pin to provide

custom data rates (Programming Baud Rate Generator

section).

XTAL2

-CD

17

38

19

42

15

40

O

I

OutputoftheCrystalOscillatororBufferedClock-(Seealso

XTAL1). Crystal oscillator output or buffered clock output.

Carrier Detect (active low) - A logic 0 on this pin indicates

that a carrier has been detected by the modem.

Rev.4.30

6

ST16C550

SYMBOL DESCRIPTION

Symbol

44

Signal

type

Pin Description

40

48

-CTS

36

40

38

I

CleartoSend(activelow)-Alogic0onthe-CTSpinindicates

the modem or data set is ready to accept transmit data from

the ST16C550. Status can be tested by reading MSR bit-4.

This pin has no effect on the UART’s transmit or receive

operation.

-DSR

-DTR

37

33

41

37

39

33

I

Data Set Ready (active low) - A logic 0 on this pin indicates

the modem or data set is powered-on and is ready for data

exchange with the UART. This pin has no effect on the

UART’s transmit or receive operation.

O

Data Terminal Ready (active low) - A logic 0 on this pin

indicates that the ST16C550 is powered-on and ready. This

pin can be controlled via the modem control register.

Writing a logic 1 to MCR bit-0 will set the -DTR output to

logic 0, enabling the modem. This pin will be a logic 1 after

writing a logic 0 to MCR bit-0, or after a reset. This pin has

no effect on the UART’s transmit or receive operation.

-RI

39

32

43

36

41

I

RingIndicator(activelow)-Alogic0onthispinindicatesthe

modem has received a ringing signal from the telephone

line. A logic 1 transition on this input pin will generate an

interrupt.

-RTS

32

O

Request to Send (active low) - A logic 0 on the -RTS pin

indicatesthetransmitterhasdatareadyandwaitingtosend.

Writing a logic 1 in the modem control register (MCR bit-1)

will set this pin to a logic 0 indicating data is available. After

a reset this pin will be set to a logic 1. This pin has no effect

on the UART’s transmit or receive operation.

RX

TX

10

11

13

7

8

I

Receive Data - This pin provides the serial receive data

input to the ST16C550. A logic 1 indicates no data or an idle

channel.Duringthelocalloop-backmode,theRXinputpinis

disabledandTXdataisinternallyconnectedtotheUARTRX

Input, internally, see figure 12.

O

Transmit Data - This pin provides the serial transmit data

from the ST16C550, the TX signal will be a logic 1 during

reset, idle (no data). During the local loop-back mode, the

TX pin is set to a logic 1 and TX data is internally connected

to the UART RX Input, see figure 12.

Rev.4.30

7

ST16C550

GENERALDESCRIPTION

FUNCTIONALDESCRIPTIONS

Internal Registers

The ST16C550 provides serial asynchronous receive

data synchronization, parallel-to-serial and serial-to-

parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for

convertingtheserialdatastreamintoparalleldatathat

is required with digital data systems. Synchronization

for the serial data stream is accomplished by adding

start and stops bits to the transmit data to form a data

character (character orientated protocol). Data integ-

rity is insured by attaching a parity bit to the data

character. The parity bit is checked by the receiver for

any transmission bit errors. The electronic circuitry to

provide all these functions is fairly complex especially

when manufactured on a single integrated silicon

chip. The ST16C550 represents such an integration

with greatly enhanced features. The ST16C550 is

fabricated with an advanced CMOS process.

The ST16C550 provides 12 internal registers for

monitoring and control. These registers are shown in

Table 3 below. These registers function as data hold-

ing registers (THR/RHR), interrupt status and control

registers (IER/ISR), a FIFO control register (FCR),

line status and control registers, (LCR/LSR), modem

status and control registers (MCR/MSR), program-

mable data rate (clock) control registers (DLL/DLM),

and a user assessable scratchpad register (SPR).

The ST16C550 is an upward solution that provides 16

bytes of transmit and receive FIFO memory, instead

of 1 byte provided in the 16C450. The ST16C550 is

designedtoworkwithhighspeedmodemsandshared

network environments, that require fast data process-

ing time. Increased performance is realized in the

ST16C550 by the larger transmit and receive FIFO’s.

This allows the external processor to handle more

networking tasks within a given time. The 4 selectable

levels of FIFO trigger provided for maximum data

throughput performance especially when operating in

a multi-channel environment. The combination of the

above greatly reduces the bandwidth requirement of

the external controlling CPU, increases performance,

and reduces power consumption.

The ST16C550 is capable of operation to 1.5Mbps

with a 24 MHz crystal or external clock input.

With a crystal of 14.7464 MHz and through a software

option, the user can select data rates up to 460.8Kbps

or 921.6Kbps.

Rev.4.30

8

ST16C550

Table2,INTERNALREGISTERDECODE

A2

A1

A0

READ MODE

WRITE MODE

General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR):

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Receive Holding Register

InterruptEnableRegister

Interrupt Status Register

LineControlRegister

ModemControlRegister

Line Status Register

Transmit Holding Register

InterruptEnableRegister

FIFO Control Register

LineControlRegister

ModemControlRegister

Reserved

Modem Status Register

ScratchpadRegister

Reserved

ScratchpadRegister

Baud Rate Generator Registers (DLL/DLM). Accessible only when LCR bit-7 is set to 1.

0

1

LSB of Divisor Latch

MSB of Divisor Latch

LSB of Divisor Latch

MSB of Divisor Latch

FIFO Operation

The 16 byte transmit and receive data FIFO’s are

enabled by the FIFO Control Register (FCR) bit-0.

With 16C550 devices, the user can set the receive

trigger level but not the transmit trigger level. The

receiver FIFO section includes a time-out function to

ensure data is delivered to the external CPU. An

interrupt is generated whenever the Receive Holding

Register (RHR) has not been read following the load-

ing of a character or the receive trigger level has not

been reached.

In this case the ST16C550 FIFO may hold more char-

actersthantheprogrammedtriggerlevel.Followingthe

removalofadatabyte,theusershouldrecheckLSRbit-

0foradditionalcharacters.AReceiveTimeOutwillnot

occurifthereceiveFIFOisempty.Thetimeoutcounter

is reset at the center of each stop bit received or each

time the receive holding register (RHR) is read (see

Figure10,ReceiveTime-outInterrupt).Theactualtime

out value is T (Time out length in bits) = 4 X P

(Programmedwordlength)+12.Toconvertthetimeout

valuetoacharactervalue, theuserhastoconsiderthe

complete word length, including data information

length, start bit, parity bit, and the size of stop bit, i.e.,

1X, 1.5X, or 2X bit times.

Time-out Interrupts

When two interrupt conditions have the same priority,

it is important to service these interrupts correctly.

Receive Data Ready and Receive Time Out have the

same interrupt priority (when enabled by IER bit-0).

The receiver issues an interrupt after the number of

charactershavereachedtheprogrammedtriggerlevel.

Example -A: If the user programs a word length of 7,

with no parity and one stop bit, the time out will be:

T=4X7(programmedwordlength)+12=40bittimes.

The character time will be equal to 40 / 9 = 4.4

characters,orasshowninthefullyworkedoutexample:

Rev.4.30

9

ST16C550

T = [(programmed word length = 7) + (stop bit = 1) +

(start bit = 1) = 9]. 40 (bit times divided by 9) = 4.4

characters.

For internal clock oscillator operation, an industry

standardmicroprocessorcrystal(parallelresonant/22

pF load) is connected externally between the XTAL1

and XTAL2 pins, with an external 1 MΩ resistor across

it. Alternatively, an external clock can be connected to

theXTAL1pintoclocktheinternalbaudrategenerator

for standard or custom rates. See figure 3 for crystal

oscillator connection.

Example -B: If the user programs the word length = 7,

with parity and one stop bit, the time out will be:

T=4X7(programmedwordlength)+12=40bittimes.

Character time = 40 / 10 [ (programmed word length

= 7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4

characters.

The generator divides the input 16X clock by any

divisor from 1 to 2¹⁶-1. The ST16C550 divides the

basic crystal or external clock by 16. The frequency of

the -BAUDOUT output pin is exactly 16X (16 times) of

theselectedbaudrate(-BAUDOUT=16xBaudRate).

Customized Baud Rates can be achieved by selecting

the proper divisor values for the MSB and LSB sec-

tions of baud rate generator.

Programmable Baud Rate Generator

The ST16C550 supports high speed modem tech-

nologies that have increased input data rates by

employing data compression schemes. For example

a 33.6Kbps modem that employs data compression

mayrequirea115.2Kbpsinputdatarate. A128.0Kbps

ISDN modem that supports data compression may

need an input data rate of 460.8Kbps. The ST16C550

can support a standard data rate of 921.6Kbps.

Programming the Baud Rate Generator Registers

DLM (MSB) and DLL (LSB) provides a user capability

for selecting the desired final baud rate. The example

in Table 3 below shows selectable baud rates when

using a 1.8432 MHz crystal.

The programmable Baud Rate Generator is capable

of accepting an input clock up to 24 MHz, as required

forsupportinga1.5Mbpsdatarate.TheST16C550can

be configured for internal or external clock operation.

For custom baud rates, the divisor value can be calcu-

lated using the following equation:

Divisor (in decimal) = (XTAL1 clock frequency) / (serial data rate x 16)

Table3,BAUDRATEGENERATORPROGRAMMINGTABLE(1.8432MHzCLOCK):

Output

User

DLM

Program

Value

DLL

Program

Value

Baud Rate 16 x Clock 16 x Clock

Divisor

(Decimal)

Divisor

(HEX)

50

75

150

300

600

1200

2400

4800

7200

9600

19.2k

38.4k

57.6k

115.2k

2304

1536

768

384

192

96

48

24

16

12

900

600

300

180

C0

60

30

18

10

0C

06

09

06

03

01

00

80

C0

60

30

18

10

0C

06

03

02

01

6

3

2

1

03

02

01

Rev.4.30

10

ST16C550

DMA Operation

D0-D7.Theuseroptionallycomparesthereceiveddata

to the initial transmitted data for verifying error free

operationoftheUARTTX/RXcircuits.

The ST16C550 FIFO trigger level provides additional

flexibilitytotheuserforblockmodeoperation.Theuser

canoptionallyoperatethetransmitandreceiveFIFO’s

in the DMA mode (FCR bit-3). The DMA mode affects

the state of the -RXRDY and -TXRDY output pins. The

following tables show this:

Inthismode,thereceiverandtransmitterinterruptsare

fullyoperational.TheModemControlInterruptsarealso

operational. The interrupts are still controlled by the

IER.

-RXRDYpin:

Non-DMAmode

1 = FIFO empty

DMAmode

0 to 1 transition when FIFO

empties

0 = at least 1 byte

in FIFO

1 to 0 transition when FIFO

reachestriggerlevel,or

timeout occurs

-TXRDYpin:

Non-DMAmode

DMAmode

1 = at least 1 byte

in FIFO

1 = FIFO is full

0 = FIFO empty

0 = FIFO has at least 1

empty location

Figure3, TYPICALEXTERNALCRYSTALOSCILLA-

TORCONNECTION

Loop-back Mode

The internal loop-back capability allows onboard diag-

nostics. In the loop-back mode the normal modem

interface pins are disconnected and reconfigured for

loop-back internally. In this mode MSR bits 4-7 are

also disconnected. However, MCR register bits 0-3

can be used for controlling loop-back diagnostic test-

ing. In the loop-back mode -OP1 and -OP2 in the MCR

register (bits 0-1) control the modem -RI and -CD

inputs respectively. MCR signals -DTR and -RTS (bits

0-1) are used to control the modem -CTS and -DSR

inputsrespectively.Thetransmitteroutput(TX)andthe

receiverinput(RX)aredisconnectedfromtheirassoci-

atedinterfacepins,andinsteadareconnectedtogether

internally(SeeFigure4).The-CTS,-DSR,-CD,and-RI

are disconnected from their normal modem control

inputs pins, and instead are connected internally to -

DTR, -RTS, -OP1 and -OP2. Loop-back test data is

entered into the transmit holding register via the user

data bus interface, D0-D7. The transmit UART serial-

izes the data and passes the serial data to the receive

UARTviatheinternalloop-backconnection.Thereceive

UART converts the serial data back into parallel data

that is then made available at the user data interface,

XTAL1

XTAL2

R1

0-120

(O ptional)

R2

1M

Y1

1.8432 - 24 M Hz

C1

C2

22-47pF

Rev.4.30

11

ST16C550

Figure4,INTERNALLOOP-BACKMODEDIAGRAM

VCC

Transm it

F IF O

R egisters

Transm it

Shift

R egister

TX

D 0-D 7

-IO R ,IO R

-IO W ,IO W

R E SE T

R eceive

F IF O

R eceive

Shift

R egisters

R egister

R X

A 0-A 2

-A S

C S0,C S1

-C S2

VCC

-D D IS

-R TS

VCC

-C TS

-D TR

IN T

-TX R D Y

-R X R D Y

-D SR

-O P1

VCC

-R I

C lock

&

B aud R ate

G enerator

-O P2

-C D

Rev.4.30

12

ST16C550

REGISTERFUNCTIONALDESCRIPTIONS

The following table delineates the assigned bit functions for the twelve ST16C550 internal registers. The assigned

bit functions are more fully defined in the following paragraphs.

Table 4, ST16C550 INTERNAL REGISTERS

A2 A1 A0

Register

[Default]

Note *2

BIT-7

BIT-6

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

General Register Set

0

1

RHR [XX]

THR [XX]

IER [00]

bit-7

0

bit-6

0

bit-5

0

bit-4

0

bit-3

bit-2

bit-1

bit-0

modem

status

interrupt

receive

line

status

interrupt

transmit

holding

register

receive

holding

register

0

1

0

1

FCR [00]

ISR [01]

LCR [00]

RCVR

trigger

(MSB)

RCVR

trigger

(LSB)

0

DMA

mode

select

XMIT

FIFO

reset

RCVR

FIFO

reset

FIFO

enable

FIFO’s

enabled

FIFO’s

enabled

INT

priority

bit-2

INT

priority

bit-1

INT

priority

bit-0

INT

status

divisor

latch

enable

set

break

set

parity

even

parity

enable

stop

bits

word

length

bit-1

word

length

bit-0

1

0

1

MCR[00]

LSR [60]

0

loopback

enable

-OP2

-OP1

-RTS

-DTR

FIFO

data

error

trans.

empty

trans.

holding

empty

break

interrupt

framing

error

parity

error

overrun

error

receive

data

ready

1

0

1

MSR [X0]

SPR [FF]

CD

RI

DSR

bit-5

CTS

bit-4

delta

-CD

delta

-RI

delta

-DSR

delta

-CTS

bit-7

bit-6

bit-3

bit-2

bit-1

bit-0

Baud Rate Generator Divisor Registers. Accessible when LCR bit-7 is set to logic 1. Note 1*

0

1

DLL [XX]

DLM[XX]

bit-7

bit-6

bit-5

bit-4

bit-3

bit-2

bit-1

bit-9

bit-0

bit-8

bit-15

bit-14

bit-13

bit-12

bit-11

bit-10

Note *1: The BRG registers are accessible only when LCR bit-7 is set to a logic 1.

Note *2: The value represents the register’s initialized HEX value. An “X” signifies a 4-bit un-initialized nibble.

Rev.4.30

13

ST16C550

Transmit and Receive Holding Register

B) FIFO status will also be reflected in the user acces-

sibleISRregisterwhentheFIFOtriggerlevelisreached.

Both the ISR register status bit and the interrupt will be

cleared when the FIFO drops below the trigger level.

The serial transmitter section consists of an 8-bit

Transmit Hold Register (THR) and Transmit Shift

Register (TSR). The status of the THR is provided in

the Line Status Register (LSR). Writing to the THR

transfers the contents of the data bus (D7-D0) to the

THR, providing that the THR or TSR is empty. The

THR empty flag in the LSR register will be set to a logic

1 when the transmitter is empty or when data is

transferred to the TSR. Note that a write operation can

be performed when the transmit holding register

empty flag is set (logic 0 = at least one byte in FIFO /

THR, logic 1= FIFO/THR empty).

C) The data ready bit (LSR BIT-0) is set as soon as a

character is transferred from the shift register to the

receive FIFO. It is reset when the FIFO is empty.

IER Vs Receive/Transmit FIFO Polled Mode Op-

eration

When FCR BIT-0 equals a logic 1; resetting IER bits

0-3 enables the ST16C550 in the FIFO polled mode of

operation. Since the receiver and transmitter have

separate bits in the LSR either or both can be used in

the polled mode by selecting respective transmit or

receive control bit(s).

The serial receive section also contains an 8-bit

Receive Holding Register, RHR. Receive data is

removed from the ST16C550 and receive FIFO by

reading the RHR register. The receive section pro-

vides a mechanism to prevent false starts. On the

falling edge of a start or false start bit, an internal

receiver counter starts counting clocks at 16x clock

rate. After 7 1/2 clocks the start bit time should be

shiftedtothecenterofthestartbit. Atthistimethestart

bit is sampled and if it is still a logic 0 it is validated.

Evaluating the start bit in this manner prevents the

receiver from assembling a false character. Receiver

status codes will be posted in the LSR.

A) LSR BIT-0 will be a logic 1 as long as there is one

byte in the receive FIFO.

B) LSR BIT 1-4 will indicate if an overrun error

occurred.

C) LSR BIT-5 will indicate when the transmit FIFO is

empty.

D) LSR BIT-6 will indicate when both the transmit

FIFO and transmit shift register are empty.

Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the inter-

rupts from receiver ready, transmitter empty, line

status and modem status registers. These interrupts

would normally be seen on the ST16C550 INT output

pin.

E) LSR BIT-7 will indicate any FIFO data errors.

IER BIT-0:

Logic 0 = Disable the receiver ready interrupt. (normal

default condition)

IER Vs Receive FIFO Interrupt Mode Operation

Logic 1 = Enable the receiver ready interrupt.

When the receive FIFO (FCR BIT-0 = a logic 1) and

receive interrupts (IER BIT-0 = logic 1) are enabled,

the receive interrupts and register status will reflect

the following:

IER BIT-1:

Logic 0 = Disable the transmitter empty interrupt.

(normal default condition)

Logic 1 = Enable the transmitter empty interrupt.

A) The receive data available interrupts are issued to

the external CPU when the FIFO has reached the

programmed trigger level. It will be cleared when the

FIFO drops below the programmed trigger level.

IER BIT-2:

Logic 0 = Disable the receiver line status interrupt.

(normal default condition)

Logic 1 = Enable the receiver line status interrupt.

Rev.4.30

14

ST16C550

IERBIT-3:

logic0)andwhentherearenocharactersinthetransmit

FIFOortransmitholdingregister,the-TXRDYpinwillbe

a logic 0. Once active the -TXRDY pin will go to a logic

1 after the first character is loaded into the transmit

holdingregister.

Logic 0 = Disable the modem status register interrupt.

(normal default condition)

Logic 1 = Enable the modem status register interrupt.

IER BIT 4-7: Not used and set to “0”.

Receive operation in mode “0”:

FIFO Control Register (FCR)

When the ST16C550 is in mode “0” (FCR bit-0 = logic

0) or in the FIFO mode (FCR bit-0 = logic 1, FCR bit-

3 = logic 0) and there is at least one character in the

receive FIFO, the -RXRDY pin will be a logic 0. Once

active the -RXRDY pin will go to a logic 1 when there

are no more characters in the receiver.

This register is used to enable the FIFO’s, clear the

FIFO’s, set the transmit/receive FIFO trigger levels,

and select the DMA mode. The DMA, and FIFO

modes are defined as follows:

DMA MODE:

Transmit operation in mode “1”:

See description and DMA tables on page 11.

When the ST16C550 is in FIFO mode ( FCR bit-0 =

logic 1, FCR bit-3 = logic 1 ), the -TXRDY pin will be

a logic 1 when the transmit FIFO is completely full. It

will be a logic 0 if one or more FIFO locations are

empty.

FCR BIT-0:

Logic 0 = Disable the transmit and receive FIFO.

(normal default condition)

Logic 1 = Enable the transmit and receive FIFO. This

bit must be a “1” when other FCR bits are written to or

they will not be programmed.

Receive operation in mode “1”:

When the ST16C550 is in FIFO mode (FCR bit-0 =

logic 1, FCR bit-3 = logic 1) and the trigger level has

been reached, or a Receive Time Out has occurred,

the -RXRDY pin will go to a logic 0. Once activated, it

will go to a logic 1 after there are no more characters

in the FIFO.

FCR BIT-1:

Logic 0 = No FIFO receive reset. (normal default

condition)

Logic 1 = Clears the contents of the receive FIFO and

resets the FIFO counter logic (the receive shift regis-

ter is not cleared or altered). This bit will return to a

logic 0 after clearing the FIFO.

FCR BIT 4-5: Not used.

FCR BIT-2:

FCRBIT6-7:Thesebitsareusedtosetthetriggerlevel

forthereceiveFIFOinterrupt.

Logic 0 = No FIFO transmit reset. (normal default

condition)

Logic 1 = Clears the contents of the transmit FIFO and

resets the FIFO counter logic (the transmit shift regis-

ter is not cleared or altered). This bit will return to a

logic 0 after clearing the FIFO.

Aninterruptisgeneratedwhenthenumberofcharacters

intheFIFOequalstheprogrammedtriggerlevel.How-

ever the FIFO will continue to be loaded until it is full.

FCR BIT-3:

BIT-7

BIT-6

RX FIFO trigger level

Logic 0 = Set DMA mode “0”. (normal default condi-

tion)

Logic 1 = Set DMA mode “1.”

0

1

0

1

0

1

4

8

Transmit operation in mode “0”:

When the ST16C550 is in the ST16C450 mode

(FIFO’s disabled, FCR bit-0 = logic 0) or in the FIFO

mode(FIFO’senabled,FCRbit-0=logic1,FCRbit-3=

14

Rev.4.30

15

ST16C550

Interrupt Status Register (ISR)

TheST16C550providesfourlevelsofprioritizedinter-

rupts to minimize external software interaction. The

InterruptStatusRegister(ISR)providestheuserwithsix

interruptstatusbits.PerformingareadcycleontheISR

will provide the user with the highest pending interrupt

level to be serviced. No other interrupts are acknowl-

edgeduntilthependinginterruptisserviced.Whenever

the interrupt status register is read, the interrupt status

is cleared. However it should be noted that only the

currentpendinginterruptisclearedbytheread.Alower

levelinterruptmaybeseenafterrereadingtheinterrupt

statusbits.TheInterruptSourceTable5(below)shows

thedatavalues(bit0-3)forthefourprioritizedinterrupt

levelsandtheinterruptsourcesassociatedwitheachof

theseinterruptlevels:

Table5, INTERRUPTSOURCETABLE

Priority

Level

[ISR]

Bit-3 Bit-2 Bit-1 Bit-0

Source of the interrupt

Nointerruptpending

LSR(ReceiverLineStatusRegister)

RXRDY(ReceivedDataReady)

RXRDY(ReceiveDatatimeout)

TXRDY(TransmitterHoldingRegisterEmpty)

MSR (Modem Status Register)

X

1

2

3

4

0

1

0

1

0

1

0

1

0

1

0

Rev.4.30

16

ST16C550

ISRBIT-0:

Logic 0 = An interrupt is pending and the ISR contents

may be used as a pointer to the appropriate interrupt

serviceroutine.

BIT-2

Word length

Stop bit

length

(Bittime(s))

Logic 1 = No interrupt pending. (normal default condi-

tion)

0

1

5,6,7,8

5

6,7,8

1

1-1/2

2

ISRBIT1-3:(logic0orclearedisthedefaultcondition)

Thesebitsindicatethesourceforapendinginterruptat

interruptprioritylevels1,2,and3(SeeInterruptSource

Table).

LCR BIT-3:

Parity or no parity can be selected via this bit.

Logic 0 = No parity (normal default condition)

Logic 1 = A parity bit is generated during the transmis-

sion, receiver checks the data and parity for transmis-

sionerrors.

ISR BIT 4-5: Not used and set to “0”.

ISRBIT6-7:(logic0orclearedisthedefaultcondition)

Thesebitsaresettoalogic0whentheFIFOisnotbeing

used. They are set to a logic 1 when the FIFO’s are

enabled

LCR BIT-4:

If the parity bit is enabled with LCR bit-3 set to a logic

1, LCR BIT-4 selects the even or odd parity format.

Logic 0 = ODD Parity is generated by forcing an odd

number of logic 1’s in the transmitted data. The

receiver must be programmed to check the same

format. (normal default condition)

Logic 1 = EVEN Parity is generated by forcing an even

the number of logic 1’s in the transmitted. The receiver

must be programmed to check the same format.

Line Control Register (LCR)

The Line Control Register is used to specify the

asynchronous data communication format. The word

length, the number of stop bits, and the parity are

selected by writing the appropriate bits in this register.

LCR BIT 0-1: (logic 0 or cleared is the default condi-

tion)

These two bits specify the word length to be transmit-

ted or received.

LCR BIT-5:

If the parity bit is enabled, LCR BIT-5 selects the

forced parity format.

LCR BIT-5 = logic 0, parity is not forced (normal

default condition)

BIT-1

BIT-0

Word length

LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit

is forced to a logical 1 for the transmit and receive

data.

LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit

is forced to a logical 0 for the transmit and receive

data.

0

1

0

1

0

1

5

6

7

8

LCR BIT-2: (logic 0 or cleared is the default condition)

The length of stop bit is specified by this bit in

conjunctionwiththeprogrammedwordlength.

LCR

Parity selection

Bit-5 Bit-4 Bit-3

X

0

1

X

0

1

0

1

0

1

No parity

Odd parity

Even parity

Force parity “1”

Forced “0”

Rev.4.30

17

ST16C550

LCRBIT-6:

MCR BIT 5-7: Not used and set to “0”.

When enabled the Break control bit causes a break

conditiontobetransmitted(theTXoutputisforcedtoa

logic 0 state). This condition exists until disabled by

setting LCR bit-6 to a logic 0.

Logic 0 = No TX break condition. (normal default

condition)

Line Status Register (LSR)

This register provides the status of data transfers

between. the ST16C550 and the CPU.

Logic 1 = Forces the transmitter output (TX) to a logic

0 for alerting the remote receiver to a line break

condition.

LSR BIT-0:

Logic 0 = No data in receive holding register or FIFO.

(normal default condition)

Logic 1 = Data has been received and is saved in the

receive holding register or FIFO.

LCR BIT-7:

The internal baud rate counter latch and Enhance

Featuremodeenable.

LSR BIT-1:

Logic 0 = Divisor latch disabled. (normal default condi-

tion)

Logic 1 = Divisor latch and enhanced feature register

enabled.

Logic 0 = No overrun error. (normal default condition)

Logic 1 = Overrun error. A data overrun error occurred

in the receive shift register. This happens when addi-

tional data arrives while the FIFO is full. In this case

the previous data in the shift register is overwritten.

Note that under this condition the data byte in the

receive shift register is not transfer into the FIFO,

therefore the data in the FIFO is not corrupted by the

error.

Modem Control Register (MCR)

This register controls the interface with the modem or

a peripheral device.

MCR BIT-0:

LSR BIT-2:

Logic 0 = Force -DTR output to a logic 1. (normal

default condition)

Logic 1 = Force -DTR output to a logic 0.

Logic 0 = No parity error (normal default condition)

Logic 1 = Parity error. The receive character does not

have correct parity information and is suspect. In the

FIFO mode, this error is associated with the character

at the top of the FIFO.

MCR BIT-1:

Logic 0 = Force -RTS output to a logic 1. (normal

default condition)

LSR BIT-3:

Logic 1 = Force -RTS output to a logic 0.

Logic 0 = No framing error (normal default condition).

Logic 1 = Framing error. The receive character did not

have a valid stop bit(s). In the FIFO mode this error is

associated with the character at the top of the FIFO.

MCR BIT-2:

Logic 0 = Set -OP1 output to a logic 1. (normal default

condition)

Logic 1 = Set -OP1 output to a logic 0.

LSR BIT-4:

Logic 0 = No break condition (normal default condi-

tion)

MCR BIT-3:

Logic 0 = Set -OP2 output to a logic 1. (normal default

condition)

Logic 1 = Set -OP2 output to a logic 0.

Logic 1 = The receiver received a break signal (RX

was a logic 0 for one character frame time). In the

FIFO mode, only one break character is loaded into

the FIFO.

MCR BIT-4:

Logic 0 = Disable loop-back mode. (normal default

condition)

Logic 1 = Enable local loop-back mode (diagnostics).

LSR BIT-5:

This bit is the Transmit Holding Register Empty indi-

cator. This bit indicates that the UART is ready to

accept a new character for transmission. In addition,

Rev.4.30

18

ST16C550

this bit causes the UART to issue an interrupt to CPU

whentheTHRinterruptenableisset.TheTHRbitisset

to a logic 1 when a character is transferred from the

transmitholdingregisterintothetransmittershiftregis-

ter. The bit is reset to logic 0 concurrently with the

loading of the transmitter holding register by the CPU.

In the FIFO mode this bit is set when the transmit FIFO

is empty; it is cleared when at least 1 byte is written to

the transmit FIFO.

MSR BIT-2:

Logic 0 = No -RI Change (normal default condition)

Logic 1 = The -RI input to the ST16C550 has changed

from a logic 0 to a logic 1. A modem Status Interrupt

will be generated.

MSR BIT-3:

Logic 0 = No -CD Change (normal default condition)

Logic 1 = Indicates that the -CD input to the has

changed state since the last time it was read. A

modem Status Interrupt will be generated.

LSR BIT-6:

This bit is the Transmit Empty indicator. This bit is set

to a logic 1 whenever the transmit holding register and

the transmit shift register are both empty. It is reset to

logic 0 whenever either the THR or TSR contains a

data character. In the FIFO mode this bit is set to one

whenever the transmit FIFO and transmit shift register

are both empty.

MSR BIT-4:

CTS (active high, logical 1). Normally this bit is the

compliment of the -CTS input. In the loop-back mode,

this bit is equivalent to the RTS bit in the MCR register.

MSR BIT-5:

LSR BIT-7:

DSR (active high, logical 1). Normally this bit is the

compliment of the -DSR input. In the loop-back mode,

this bit is equivalent to the DTR bit in the MCR register.

Logic 0 = No Error (normal default condition)

Logic 1 = At least one parity error, framing error or

break indication is in the current FIFO data. This bit is

cleared when there are no remaining LSR errors in the

RXFIFO.

MSR BIT-6:

RI (active high, logical 1). Normally this bit is the

compliment of the -RI input. In the loop-back mode

this bit is equivalent to the OP1 bit in the MCR register.

Modem Status Register (MSR)

This register provides the current state of the control

interface signals from the modem, or other peripheral

device that the ST16C550 is connected to. Four bits

of this register are used to indicate the changed

information. These bits are set to a logic 1 whenever

a control input from the modem changes state. These

bits are set to a logic 0 whenever the CPU reads this

register.

MSR BIT-7:

CD (active high, logical 1). Normally this bit is the

compliment of the -CD input. In the loop-back mode

this bit is equivalent to the OP2 bit in the MCR register.

Scratchpad Register (SPR)

The ST16C550 provides a temporary data register to

store 8 bits of user information.

MSR BIT-0:

Logic 0 = No -CTS Change (normal default condition)

Logic 1 = The -CTS input to the ST16C550 has

changed state since the last time it was read. A

modem Status Interrupt will be generated.

MSR BIT-1:

Logic 0 = No -DSR Change (normal default condition)

Logic 1 = The -DSR input to the ST16C550 has

changed state since the last time it was read. A

modem Status Interrupt will be generated.

Rev.4.30

19

ST16C550

ST16C550EXTERNALRESETCONDITIONS

REGISTERS

RESETSTATE

IER

ISR

IER BITS 0-7 = logic 0

ISR BIT-0=1, ISR BITS 1-7 = logic

0

LCR, MCR

LSR

BITS 0-7 = logic 0

LSR BITS 0-4 = logic 0,

LSR BITS 5-6 = logic 1 LSR, BIT

7 = logic 0

MSR

FCR

MSR BITS 0-3 = logic 0,

MSR BITS 4-7 = logic levels of the

input signals

BITS 0-7 = logic 0

SIGNALS

RESET STATE

TX

Logic 1

Logic 0

-OP1

-OP2

-RTS

-DTR

-RXRDY

-TXRDY

INT

Rev.4.30

20

ST16C550

AC ELECTRICAL CHARACTERISTICS

T_A=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified.

Symbol

Parameter

Limits

3.3

Limits

5.0

Units Conditions

Min

Max

Min

Max

T_1w,T_2wClock pulse duration

17

ns

MHz

ns

T_3w

T4w

Oscillator/Clockfrequency

Address strobe width

16

24

35

5

25

0

5

T

5s

5h

Address setup time

Address hold time

T_6s

T_6s'

T6h

T_7d

T_7w

T_7h

T_7h'

Address setup time

Chip select hold time

-IOR delay from chip select

-IORstrobewidth

Chip select hold time from -IOR

Address hold time

-IORdelayfromaddress

Read cycle delay

-IOR to -DDIS delay

Delay from -IOR to data

Data disable time

-IOW delay from chip select

-IOW strobe width

Chip select hold time from -IOW

-IOW delay from address

Write cycle delay

Data setup time

Data hold time

Delay from -IOW to output

Delay to set interrupt from MODEM

input

5

10

0

10

35

0

5

10

40

0

5

0

10

25

0

5

10

30

ns

see Note 1

T_8d

T_9d

T_11d

T_12d

T_12h

T_13d

T_13w

T_13h

T_14d

T_15d

T_16s

T_16h

T_17d

T_18d

15

35

25

10

25

15

100 pF load

10

40

0

10

40

20

5

10

25

0

10

30

15

5

50

40

35

100 pF load

T_19d

T_20d

T_21d

T_22d

T_23d

Delay to reset interrupt from -IOR

Delay from stop to set interrupt

Delay from -IOR to reset interrupt

Delay from stop to interrupt

Delay from initial INT reset to transmit

start

40

1

45

24

35

1

40

24

ns

Rclk

ns

Rclk

100 pF load

8

T_24d

T_25d

T_26d

T_27d

T_28d

T_R

Delay from -IOW to reset interrupt

Delay from stop to set -RxRdy

Delay from -IOR to reset -RxRdy

Delay from -IOW to set -TxRdy

Delay from start to reset -TxRdy

Reset pulse width

45

1

45

8

40

1

40

8

ns

Rclk

ns

Rclk

40

1

40

1

ns

Rclk

N

Baudratedevisor

2¹⁶-1

Note 1: Applicable only when -AS is tied low.

Rev.4.30

21

ST16C550

ABSOLUTE MAXIMUM RATINGS

Supply range

7 Volts

GND - 0.3 V to VCC +0.3 V

-40° C to +85° C

Voltage at any pin

Operating temperature

Storage temperature

Package dissipation

-65° C to 150° C

500 mW

DC ELECTRICAL CHARACTERISTICS

T_A=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified.

Symbol

Parameter

Limits

3.3

Limits

5.0

Units Conditions

Min

Max

Min

Max

V_ILCK

V_IHCK

V_IL

Clock input low level

Clock input high level

Inputlowlevel

-0.3

2.4

-0.3

2.0

0.6

VCC

0.8

-0.5

3.0

-0.5

2.2

0.6

VCC

0.8

VCC

0.4

V

µA

mA

pF

V_IH

Inputhighlevel

V_OL

V_OH

I_IL

I_CL

I_CC

C_P

Output low level on all outputs

Output high level

Input leakage

Clock leakage

Avg power supply current

Input capacitance

I_OL= 5 mA

I_OL= 4 mA

I_OH= -5 mA

I_OH= -1 mA

0.4

2.4

2.0

±10

1.3

5

±10

3

5

Rev.4.30

22

ST16C550

T1w

T2w

EXTERNAL

CLOCK

T3w

-BAUDOUT

1/2 -BAUDOUT

1/3 -BAUDOUT

1/3> -BAUDOUT

X450-CK-1

Clock timing

Rev.4.30

23

ST16C550

T4w

-AS

T5h

T6h

T5s

Valid

Address

A0-A2

T6s

-CS2

CS1-CS0

Valid

T7d

T8d

T7h

T7w

T9d

-IOR

IOR

Active

T11d

Active

-DDIS

D0-D7

T12h

T12d

Data

X550-RD-1

General Read Timing when using -AS signal

T4w

-AS

T5h

T5s

Valid

Address

A0-A2

T6h

T6s

-CS2

CS1-CS0

Valid

T13d

T13h

T13w

T14d

T15d

-IOW

IOW

Active

T16s

T16h

Data

D0-D7

X550-WD-1

General Write Timing when using -AS signal.

Rev.4.30

24

ST16C550

Valid

Address

Valid

Address

A0-A2

-CS

T7h'

T6s'

T7w

Active

T7w

T9d

-IOR

Active

T12h

T12d

T12h

D0-D7

Data

General Read Timing when -AS is tied to GND

Valid

Address

Valid

Address

A0-A2

-CS

T7h'

T6s'

Active

T13w

T15d

-IOW

D0-D7

Active

T16h

T16s

T16h

Data

General Write Timing when -AS is tied to GND

Rev.4.30

25

ST16C550

-IOW

IOW

Active

T17d

Change of state

-RTS

-DTR

Change of state

-CD

-CTS

Change of state

-DSR

T18d

INT

Active

T19d

-IOR

IOR

Active

T18d

Change of state

X450-MD-1

-RI

Modem input/output timing

Rev.4.30

26

ST16C550

START

BIT

STOP

BIT

DATA BITS (5-8)

RX

D0

D1

D2

D3

D4

D5

D6 D7

PARITY

BIT

START

BIT

5 DATA BITS

6 DATA BITS

7 DATA BITS

T20d

Active

INT

T21d

-IOR

IOR

16 BAUD RATE CLOCK

X450-RX-1

Receive timing

Rev.4.30

27

ST16C550

START

BIT

STOP

BIT

DATA BITS (5-8)

RX

D0

D1

D2

D3

D4

D5

D6 D7

PARITY

BIT

START

BIT

T25d

Active

Data

-RXRDY

Ready

T26d

-IOR

IOR

Active

X550-RX-2

Receive ready timing in non FIFO mode

Rev.4.30

28

ST16C550

START

BIT

STOP

BIT

DATA BITS (5-8)

RX

D0

D1

D2

D3

D4

D5

D6 D7

PARITY

First byte

BIT

that reaches

the trigger

level

T25d

Active

Data

-RXRDY

Ready

T26d

-IOR

IOR

Active

X550-RX-3

Receive ready timing in FIFO mode

Rev.4.30

29

ST16C550

STOP

BIT

START

BIT

DATA BITS (5-8)

TX

D0

D1

D2

D3

D4

D5

D6

D7

PARITY

BIT

5 DATA BITS

6 DATA BITS

7 DATA BITS

T22d

INT

Active TX Ready

T24d

T23d

IOW /

-IOW

A ctive

Active

16 BAUD RATE CLOCK

Transmit timing

Rev.4.30

30

ST16C550

START

BIT

STOP

BIT

DATA BITS (5-8)

TX

D0

D1

D2

D3

D4

D5

D6 D7

PARITY

BIT

START

BIT

-IOW

IOW

Active

T28d

BYTE #1

T27d

Active

Transmitter ready

-TXRDY

Transmitter

not ready

X550-TX-2

Transmit ready timing in non FIFO mode

Rev.4.30

31

ST16C550

START BIT

DATA BITS (5-8)

STOP BIT

TX

D0

D1

D2

D3

D4

D5

D6 D7

5 DATA BITS

PARITY BIT

6 DATA BITS

7 DATA BITS

-IOW

IOW

Active

T28d

D0-D7

BYTE #16

T27d

-TXRDY

FIFO Full

X550-TX-3

Transmit ready timing in FIFO mode

Rev.4.30

32

ST16C550

PACKAGE OUTLINE DRAWING

44LEAD PLASTIC LEADED CHIP CARRIER

(PLCC)

C

D

Seating Plane

A₂

D ₁

45° x H₁

45° x H₂

2

1

44

B₁

B

D

D₁

D₃

D₂

e

R

D₃

A₁

A

Note: The control dimension is the inch column

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

MIN

MAX

A

A₁

A₂

B

0.165

0.090

0.020

0.013

0.026

0.008

0.685

0.650

0.590

0.180

0.120

-----

4.19

2.29

4.57

3.05

0.51

------

0.53

0.021

0.032

0.013

0.695

0.656

0.630

0.33

B₁

C

0.66

0.81

0.19

0.32

D

17.40

16.51

14.99

17.65

16.66

16.00

D₁

D₂

D₃

e

0.500 typ

0.50 BSC

12.70 typ

1.27BSC

1.07

H₁

H₂

R

0.042

0.056

0.048

0.045

1.42

1.22

1.14

0.042

0.025

1.07

0.64

Rev.4.30

33

ST16C550

PACKAGEOUTLINEDRAWING

48 LEAD THIN QUAD FLAT PACK

(TQFP)

D

D₁

36

25

37

24

D₁

D

48

13

1

2

B

e

A₂

C

A

Seating

Plane

α

A₁

L

Note: The control dimension is the millimeter column

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

MIN

MAX

A

A₁

A₂

B

0.039

0.002

0.037

0.007

0.004

0.346

0.272

0.047

0.006

0.041

0.011

0.008

0.362

0.280

1.00

0.05

0.95

0.17

0.09

8.80

6.90

1.20

0.15

1.05

0.27

0.20

9.20

7.10

C

D

D₁

e

0.20 BSC

0.50BSC

L

0.018

0.030

7°

0.45

0°

0.75

7°

α

0°

Rev.4.30

34

ST16C550

EXPLANATIONOFDATASHEETREVISIONS:

FROM

4.20

TO

CHANGES

DATE

4.30

Added revision history. Added Device Status to front page.

Sept 2003

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to

improvedesign,performanceorreliability.EXARCorporationassumesnoresponsibilityfortheuseofanycircuits

describedherein,conveysnolicenseunderanypatentorotherright,andmakesnorepresentationthatthecircuits

arefreeofpatentinfringement.Chartsandschedulescontainedhereinareonlyforillustrationpurposesandmay

vary depending upon a user's specific application. While the information in this publication has been carefully

checked; no responsibility, however, is assumed for inaccuracies.

EXARCorporationdoesnotrecommendtheuseofanyofitsproductsinlifesupportapplicationswherethefailure

of the product can reasonably be expected to cause failure of the life support system or to significantly affect its

safetyoreffectiveness.ProductsarenotauthorizedforuseinsuchapplicationsunlessEXARCorporationreceives,

in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user

assumesallsuchrisks;(c)potentialliabilityofEXARCorporationisadequatelyprotectedunderthecircumstances.

Datasheet September 2003

Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com

Reproduction, in part or whole, without prior written consent of EXAR Corporation is prohibited.

Rev.4.30

35


型号：	ST16C550IJ44-F
厂家：	EXAR CORPORATION
描述：	Serial I/O Controller, 1 Channel(s), 0.1875MBps, CMOS, PQCC44, GREEN, PLASTIC, LCC-44 外围集成电路先进先出芯片数据传输通信时钟
文件：	总35页 (文件大小：228K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ST16C550IJ44-F [EXAR]

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