ST16C580IP40 [EXAR]
UART WITH 16-BYTE FIFO’s AND INFRARED (IrDA) ENCODER/DECODER; UART具有16字节FIFO的和红外（ IrDA）的编码/解码器
| 型号： | ST16C580IP40 |
| 厂家： | 
EXAR CORPORATION |
| 描述： | UART WITH 16-BYTE FIFO’s AND INFRARED (IrDA) ENCODER/DECODER |
| 文件： | 总41页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST16C580
UART WITH 16-BYTE FIFO’s AND
INFRARED (IrDA) ENCODER/DECODER
September 2003
GENERAL DESCRIPTION
TheST16C5801 isauniversalasynchronousreceiverandtransmitter(UART)andispincompatiblewiththeST16C550
UART.The580isanenhancedUARTwith16byteFIFO’s,automatichardware/softwareflowcontrol,anddatarates
up to 1.5Mbps. Onboard status registers provide the user with error indications and operational status. Modem
interfacecontrolisincludedandcanbeoptionallyconfiguredtooperatewiththeInfrared(IrDA)encoder/decoder.The
system interrupts may be tailored to meet user requirements. An internal loop-back capability allows onboard
diagnostics. The 580 is available in 40 pin PDIP, 44 pin PLCC, and 48 pin TQFP packages. It is fabricated in an
advancedCMOSprocesstoachievelowdrainpowerandhighspeedrequirements.
FEATURES
PLCC Package
• PintopinandfunctionallycompatibletotheIndustry
Standard16550
• 2.97 to 5.5 volt operation
• 1.5Mbpstransmit/receiveoperation(24MHz)
• 16 byte transmit FIFO
7
39
38
37
36
35
34
33
32
31
30
29
D5
D6
RESET
-OP1
-DTR
-RTS
-OP2
N.C.
INT
8
• 16 byte receive FIFO with error flags
• Automatichardware/softwareflowcontrol
• ProgrammableXon/Xoffcharacters
• Independenttransmitandreceivecontrol
• Software selectable Baud Rate Generator pre-
scaleable clock rates of 1X or 4X
• Fourselectabletransmit/receiveFIFOinterrupttrig-
gerlevels
• StandardmodeminterfaceorInfraredIrDAencode/
decoderinterface
9
D7
10
11
12
13
14
15
16
17
RCLK
RX
N.C.
XR16C580CJ44
TX
CS0
-RXRDY
A0
CS1
-CS2
-BAUDOUT
A1
A2
• Sleep mode ( 200µA stand-by )
• Low operating current ( 1.2mA typ.)
ORDERING INFORMATION
Part number
Package
Operating temp
Device Status
ST16C580CP40
ST16C580CJ44
ST16C580CQ48
ST16C580IP40
ST16C580IJ44
ST16C580IQ48
40-Lead PDIP
44-Lead PLCC 0° C to + 70° C
48-Lead TQFP 0° C to + 70° C
40-Lead PDIP
44-Lead PLCC -40° C to + 85° C
48-Lead TQFP -40° C to + 85° C
0° C to + 70° C
Discontinued. See the ST16C580CQ48 for a replacement.
Discontinued. See the ST16C580CQ48 for a replacement.
Active
Discontinued. See the ST16C580IQ48 for a replacement.
Discontinued. See the ST16C580IQ48 for a replacement.
Active
-40° C to + 85° C
*Note 1 Covered by U.S. Patent #5,649,122.
Rev.1.20
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017
ST16C580
Figure1,PACKAGEDESCRIPTION,16C580
48 Pin TQFP Package
40 Pin DIP Package
VCC
-RI
D0
D1
1
2
3
4
5
6
7
8
9
40
39
38
37
1
2
36
35
34
33
32
31
30
29
28
27
26
25
N.C.
RESET
-OP1
-DTR
-RTS
-OP2
INT
N.C.
D5
-CD
-DSR
D2
D3
D6
3
D4
36 -CTS
D7
4
D5
35 RESET
RCLK
N.C.
5
-OP1
-DTR
-RTS
D6
34
33
32
6
XR16C580CQ48
D7
RX
7
RCLK
8
-RXRDY
A0
TX
RX 10
TX 11
31 -OP2
30 INT
CS0
9
10
11
12
A1
CS1
A2
-CS2
-BAUDOUT
-RXRDY
CS0 12
29
28
27
26
N.C.
13
A0
A1
A2
CS1
-CS2 14
-BAUDOUT 15
XTAL1 16
XTAL2 17
-IOW 18
25 -AS
-TXRDY
24
23
22
21
-DDIS
IOR
IOW 19
-IOR
GND 20
Rev.1.20
2
ST16C580
Figure 2, BLOCK DIAGRAM
Transmit
FIFO
Registers
Transmit
Shift
Register
TX
D0-D7
-IOR,IOR
-IOW,IOW
RESET
Flow
Control
Logic
Ir
Encoder
A0-A2
-AS
CS0,CS1
-CS2
Receive
FIFO
Registers
Receive
Shift
Register
RX
-DDIS
Flow
Control
Logic
Ir
Decoder
INT
-RXRDY
-TXRDY
-DTR,-RTS
-OP1,-OP2
Modem
Control
Logic
-CTS
-RI
-CD
-DSR
XTAL1
RCLK
XTAL2
-BAUDOUT
Rev.1.20
3
ST16C580
SYMBOL DESCRIPTION
Symbol
Pin
44
Signal
type
Pin Description
40
48
A0
28
31
30
29
25
28
I
I
I
I
Address-0 Select Bit - Internal registers address selection.
Address-1 Select Bit Internal registers address selection.
Address-2 Select Bit Internal registers address selection.
A1
27
26
22
27
26
20
A2
IOR
Read strobe. Its function is the same as -IOR (see -IOR),
except it is active high. Either an active -IOR or IOR is
required to transfer data from 580 to CPU during a read
operation.
CS0
CS1
-CS2
IOW
12
13
14
19
14
15
16
21
9
I
I
I
I
Chip Select-0. A logical 1 on this pin provides the chip select
0 function.
10
11
17
Chip Select-1. A logical 1 on this pin provides the chip select
1 function.
ChipSelect-2. Alogical0onthispinprovidesthechipselect
2 function.
Write strobe. A logic 1 transition creates a write strobe. Its
function is the same as -IOW (see -IOW), but it acts as an
active high input signal. Either -IOW or IOW is required to
transfer data from the CPU to 580 during a write operation.
-AS
25
28
24
I
Address Strobe. A logic 0 transition on -AS latches the state
of the chip selects and the register select bits, A0-A2. This
input is used when address and chip selects are not stable
for the duration of a read or write operation, i.e., a micropro-
cessor that needs to de-multiplex the address and data bits.
If not required, the -AS input can be permanently tied to a
logic 0 (it is edge triggered).
D0-D7
GND
1-8
20
2-9
22
43-47
2-4
I/O
Data Bus (Bi-directional) - These pins are the eight bit, three
state data bus for transferring information to or from the
controlling CPU. D0 is the least significant bit and the first
data bit in a transmit or receive serial data stream.
18
Pwr
Signal and Power Ground.
Rev.1.20
4
ST16C580
SYMBOL DESCRIPTION
Symbol
Pin
44
Signal
type
Pin Description
40
48
-IOR
21
24
19
I
Readstrobe(activelowstrobe).Alogic0onthispintransfers
the contents of the 580 data bus to the CPU.
-IOW
18
20
16
I
Write strobe (active low strobe) - A logic 0 on this pin
transfers the contents of the CPU data bus to the addressed
internal register.
INT
30
29
33
32
30
29
O
O
Interrupt Request.
-RXRDY
Receive Ready. A logic 0 indicates receive data ready
status, i.e. the RHR is full or the FIFO has one or more RX
characters available for unloading. This pin goes to a logic
0 when the FIFO/RHR is full or when there are more
characters available in either the FIFO or RHR.
-TXRDY
-BAUDOUT
-DDIS
24
15
23
27
17
26
23
12
22
O
O
O
Transmit Ready. Buffer ready status is indicated by a logic
0, i.e., at least one location is empty and available in the
FIFO or THR. This pin goes to a logic 1 when there are no
more empty locations in the FIFO or THR.
Baud Rate Generator Output. This pin provides the 16X
clock of the selected data rate from the baud rate generator.
The RCLK pin must be connected externally to -BAUDOUT
when the receiver is operating at the same data rate.
Drive Disable. This pin goes to a logic 0 when the external
CPU is reading data from the 580. This signal can be used
to disable external transceivers or other logic functions.
-OP1
-OP2
34
31
38
35
34
31
O
O
Output-1 (User Defined) - See bit-2 of modem control
register (MCR bit-2).
Output-2 (User Defined). This pin provides the user a
general purpose output. See bit-3 modem control register
(MCR bit-3).
RCLK
9
10
5
I
Receive Clock Input. This pin is used as external 16X clock
input to the receiver section. External connection to -
Baudout pin is required in order to utilize the internal baud
rate generator.
Rev.1.20
5
ST16C580
SYMBOL DESCRIPTION
Symbol
Pin
44
Signal
type
Pin Description
40
48
RESET
35
39
35
I
Reset.(activehigh)-Alogic1onthispinwillresettheinternal
registers and all the outputs. The UART transmitter output
andthereceiverinputwillbedisabledduringresettime.(See
ST16C580 External Reset Conditions for initialization de-
tails.)
VCC
40
16
44
18
42
Pwr
I
Power Supply Input.
XTAL1
14
Crystal or External Clock Input - Functions as a crystal input
or as an external clock input. A crystal can be connected
between this pin and XTAL2 to form an internal oscillator
circuit. An external 1 M resistor is required between the
XTAL1 and XTAL2 pins (see figure 9). Alternatively, an
external clock can be connected to this pin to provide
custom data rates (Programming Baud Rate Generator
section).
XTAL2
-CD
17
38
36
19
42
40
15
40
38
O
I
OutputoftheCrystalOscillatororBufferedClock-(Seealso
XTAL1). Crystal oscillator output or buffered clock output.
Carrier Detect (active low) - A logic 0 on this pin indicates
that a carrier has been detected by the modem.
-CTS
I
Clear to Send (active low) - A logic 0 on the -CTS pin
indicates the modem or data set is ready to accept transmit
data from the 580. Status can be tested by reading MSR bit-
4. This pin only affects the transmit and receive operations
when Auto CTS function is enabled via the Enhanced
Feature Register (EFR) bit-7, for hardware flow control
operation.
-DSR
-DTR
37
33
41
37
39
33
I
Data Set Ready (active low) - A logic 0 on this pin indicates
the modem or data set is powered-on and is ready for data
exchange with the UART. This pin has no effect on the
UART’s transmit or receive operation.
O
Data Terminal Ready (active low) - A logic 0 on this pin
indicatesthatthe580ispowered-onandready. Thispincan
be controlled via the modem control register. Writing a logic
1 to MCR bit-0 will set the -DTR output to logic 0, enabling
the modem. This pin will be a logic 1 after writing a logic 0
to MCR bit-0, or after a reset. This pin has no effect on the
Rev.1.20
6
ST16C580
SYMBOL DESCRIPTION
Symbol
Pin
44
Signal
type
Pin Description
40
48
UART’stransmitorreceiveoperation.
-RI
39
43
36
41
I
RingIndicator(activelow)-Alogic0onthispinindicatesthe
modem has received a ringing signal from the telephone
line. A logic 1 transition on this input pin will generate an
interrupt.
-RTS
32
32
O
Request to Send (active low) - A logic 0 on the -RTS pin
indicatesthetransmitterhasdatareadyandwaitingtosend.
Writing a logic 1 in the modem control register (MCR bit-1)
will set this pin to a logic 0 indicating data is available. After
a reset this pin will be set to a logic 1. This pin only affects
the transmit and receive operations when Auto RTS func-
tion is enabled via the Enhanced Feature Register (EFR)
bit-6, for hardware flow control operation.
RX / IRRX
10
11
7
I
Receive Data - This pin provides the serial receive data
input to the 580. Two user selectable interface options are
available. The first option supports the standard modem
interface. The second option provides an Infrared decoder
interface, see figures 2/3. When using the standard modem
interface, the RX signal will be a logic 1 during reset, idle (no
data), or when the transmitter is disabled. The inactive state
(no data) for the Infrared decoder interface is a logic 0. MCR
bit-6 selects the standard modem or infrared interface.
During the local loop-back mode, the RX input pin is
disabled and TX data is internally connected to the UART
RX Input, internally, see figure 12.
TX / IRTX
11
13
8
O
Transmit Data - This pin provides the serial transmit data
from the 580. Two user selectable interface options are
available. The first user option supports a standard modem
interface. The second option provides an Infrared encoder
interface, see figures 2/3. When using the standard modem
interface, the TX signal will be a logic 1 during reset, idle (no
data), or when the transmitter is disabled. The inactive state
(no data) for the Infrared encoder/ decoder interface is a
Logic 0. MCR bit-6 selects the standard modem or infrared
interface. During the local loop-back mode, the TX input pin
is disabled and TX data is internally connected to the UART
RX Input, see figure 12.
Rev.1.20
7
ST16C580
GENERAL DESCRIPTION
encoder/decoderinterface,modeminterfacecontrols,
andasleepmodeareallstandardfeatures.Followinga
poweronresetoranexternalreset,the580issoftware
compatiblewithpreviousgenerationofUARTs,16C450
and16C550.
The 580 provides serial asynchronous receive data
synchronization, parallel-to-serial and serial-to-paral-
lel data conversions for both the transmitter and
receiver sections. These functions are necessary for
convertingtheserialdatastreamintoparalleldatathat
is required with digital data systems. Synchronization
for the serial data stream is accomplished by adding
start and stops bits to the transmit data to form a data
character (character orientated protocol). Data integ-
rity is insured by attaching a parity bit to the data
character. The parity bit is checked by the receiver for
any transmission bit errors. The electronic circuitry to
provide all these functions is fairly complex especially
when manufactured on a single integrated silicon
chip. The ST16C580 represents such an integration
with greatly enhanced features. The 580 is fabricated
with an advanced CMOS process.
FUNCTIONAL DESCRIPTIONS
Internal Registers
The 580 provides 15 internal registers for monitoring
andcontrol.TheseregistersareshowninTable3below.
Twelveregistersaresimilartothosealreadyavailablein
thestandard16C550.Theseregistersfunctionasdata
holdingregisters(THR/RHR),interruptstatusandcon-
trol registers (IER/ISR), a FIFO control register (FCR),
line status and control registers, (LCR/LSR), modem
status and control registers (MCR/MSR), program-
mable data rate (clock) control registers (DLL/DLM),
and a user assessable scratchpad register (SPR).
Beyond the general 16C550 features and capabilities,
the 580 offers an enhanced feature register set (EFR,
Xon/Xoff1-2)thatprovidesonboardhardware/software
flowcontrol.Registerfunctionsaremorefullydescribed
inthefollowingparagraphs.
The 580 is an upward solution that provides 16 bytes
of transmit and receive FIFO memory, instead of 16
bytes provided in the 16C550, or none in the 16C450.
The 580 is designed to work with high speed modems
and shared network environments, that require fast
data processing time. Increased performance is real-
ized in the 580 by the larger transmit and receive
FIFO’s. This allows the external processor to handle
more networking tasks within a given time. In addition,
the 4 selectable levels of FIFO trigger interrupt and
automatic hardware/software flow control is uniquely
provided for maximum data throughput performance
especially when operating in a multi-channel environ-
ment. The combination of the above greatly reduces
the bandwidth requirement of the external controlling
CPU, increases performance, and reduces power
consumption.
Table 3, INTERNAL REGISTER
The 580 is capable of operation to 1.5Mbps with a 24
MHz crystal or external clock input.
With a crystal of 7.3728 MHz and through a software
option, theusercanselectdataratesupto460.8Kbps.
The rich feature set of the 580 is available through
internal registers. Automatic hardware/software flow
control, selectable transmit and receive FIFO trigger
levels, selectable TX and RX baud rates, infrared
Rev.1.20
8
ST16C580
DECODE
A2
A1
A0
READ MODE
WRITE MODE
General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR):
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Receive Holding Register
Interrupt Status Register
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Scratchpad Register
Scratchpad Register
Baud Rate Register Set (DLL/DLM): Note *3
0
0
0
0
0
1
LSB of Divisor Latch
MSB of Divisor Latch
LSB of Divisor Latch
MSB of Divisor Latch
Enhanced Register Set (EFR, Xon/off 1-2): Note *4
0
1
1
1
1
1
0
0
1
1
0
0
1
0
1
Enhanced Feature Register
Xon-1 Word
Xon-2 Word
Xoff-1 Word
Xoff-2 Word
Enhanced Feature Register
Xon-1 Word
Xon-2 Word
Xoff-1 Word
Xoff-2 Word
Note *3: These registers are accessible only when LCR bit-7 is set to a logic 1.
Note *4: Enhanced Feature Register, Xon 1,2 and Xoff 1,2 are accessible only when the LCR is set to “BF” (HEX).
Rev.1.20
9
ST16C580
FIFO Operation
Hardware Flow Control
The 16 byte transmit and receive data FIFO’s are
enabled by the FIFO Control Register (FCR) bit-0.
With 16C550 devices, the user can set the receive
trigger level but not the transmit trigger level. The 580
provides independent trigger levels for both receiver
and transmitter. To remain compatible with
ST16C550, the transmit interrupt trigger level is set to
1 following a reset. It should be noted that the user can
set the transmit trigger levels by writing to the FCR
register, but activation will not take place until EFR bit-
4 is set to a logic 1. The receiver FIFO section includes
a time-out function to ensure data is delivered to the
external CPU. An interrupt is generated whenever the
Receive Holding Register (RHR) has not been read
following the loading of a character or the receive
triggerlevelhasnotbeenreached. (seehardwareflow
control for a description of this timing).
When automatic hardware flow control is enabled, the
580monitorsthe-CTSpinforaremotebufferoverflow
indication and controls the -RTS pin for local buffer
overflows. Automatic hardware flow control is se-
lected by setting bits 6 (RTS) and 7 (CTS) of the EFR
register to a logic 1. If -CTS transitions from a logic 0
to a logic 1 indicating a flow control request, ISR bit-
5 will be set to a logic 1 (if enabled via IER bit 6-7), and
the 580 will suspend TX transmissions as soon as the
stop bit of the character in process is shifted out.
Transmission is resumed after the -CTS input returns
to a logic 0, indicating more data may be sent.
With the Auto RTS function enabled, an interrupt is
generated when the receive FIFO reaches the pro-
grammed trigger level. The -RTS pin will not be forced
to a logic 1 (RTS Off), until the receive FIFO reaches
the next trigger level. However, the -RTS pin will
return to a logic 0 after the data buffer (FIFO) is
unloaded to the next trigger level below the pro-
grammed trigger level. However, under the above
described conditions the 580 will continue to accept
data until the receive FIFO is full.
Selected
Trigger
INT
Pin
-RTS
Logic “1”
-RTS
Logic “0”
Level
Activation
(characters) (characters)
(characters)
1
4
8
1
4
8
4
8
14
14
0
1
4
8
14
14
Rev.1.20
10
ST16C580
Software Flow Control
placed on the user accessible data stack along with
normal incoming RX data. This condition is selected in
conjunction with EFR bits 0-3. Note that software flow
control should be turned off when using this special
mode by setting EFR bit 0-3 to a logic 0.
When software flow control is enabled, the 580 com-
pares one or two sequential receive data characters
with the programmed Xon or Xoff-1,2 character
value(s). If receive character(s) (RX) match the pro-
grammed values, the 580 will halt transmission (TX)
as soon as the current character(s) has completed
transmission. When a match occurs, the receive
ready (if enabled via Xoff IER bit-5) flags will be set
and the interrupt output pin (if receive interrupt is
enabled) will be activated. Following a suspension
due to a match of the Xoff characters values, the 580
will monitor the receive data stream for a match to the
Xon-1,2 character value(s). If a match is found, the
580 will resume operation and clear the flags (ISR bit-
4).
The 580 compares each incoming receive character
with Xoff-2 data. If a match exists, the received data
will be transferred to FIFO and ISR bit-4 will be set to
indicate detection of special character (see Figure 9).
Although the Internal Register Table shows each X-
Register with eight bits of character information, the
actual number of bits is dependent on the pro-
grammed word length. Line Control Register (LCR)
bits 0-1 defines the number of character bits, i.e.,
either 5 bits, 6 bits, 7 bits, or 8 bits. The word length
selected by LCR bits 0-1 also determines the number
of bits that will be used for the special character
comparison. Bit-0 in the X-registers corresponds with
the LSB bit for the receive character.
Reset initially sets the contents of the Xon/Xoff 8-bit
flow control registers to a logic 0. Following reset the
user can write any Xon/Xoff value desired for software
flow control. Different conditions can be set to detect
Xon/Xoff characters and suspend/resume transmis-
sions. When double 8-bit Xon/Xoff characters are
selected, the 580 compares two consecutive receive
characters with two software flow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmis-
sions accordingly. Under the above described flow
control mechanisms, flow control characters are not
placed (stacked) in the user accessible RX data buffer
or FIFO.
Time-out Interrupts
Three special interrupts have been added to monitor
the hardware and software flow control. The interrupts
are enabled by IER bits 5-7. Care must be taken when
handling these interrupts. Following a reset the trans-
mitter interrupt is enabled, the 580 will issue an
interrupt to indicate that transmit holding register is
empty. This interrupt must be serviced prior to con-
tinuing operations. The LSR register provides the
current singular highest priority interrupt only. It could
be noted that CTS and RTS interrupts have lowest
interrupt priority. A condition can exist where a higher
priority interrupt may mask the lower priority CTS/
RTS interrupt(s). Only after servicing the higher pend-
ing interrupt will the lower priority CTS/ RTS
interrupt(s) be reflected in the status register. Servic-
ing the interrupt without investigating further interrupt
conditions can result in data errors.
In the event that the receive buffer is overfilling and
flow control needs to be executed, the 580 automati-
cally sends an Xoff message (when enabled) via the
serial TX output to the remote modem. The 580 sends
the Xoff-1,2 characters as soon as received data
passes the programmed trigger level. To clear this
condition, the 580 will transmit the programmed Xon-
1,2 characters as soon as receive data drops below
the programmed trigger level.
When two interrupt conditions have the same priority,
it is important to service these interrupts correctly.
Receive Data Ready and Receive Time Out have the
same interrupt priority (when enabled by IER bit-3).
The receiver issues an interrupt after the number of
characters have reached the programmed trigger
Special Feature Software Flow Control
A special feature is provided to detect an 8-bit charac-
ter when bit-5 is set in the Enhanced Feature Register
(EFR). When this character is detected, it will be
Rev.1.20
11
ST16C580
level. Inthiscasethe580FIFOmayholdmorecharac-
ters than the programmed trigger level. Following the
removalofadatabyte,theusershouldrecheckLSRbit-
0foradditionalcharacters.AReceiveTimeOutwillnot
occurifthereceiveFIFOisempty.Thetimeoutcounter
is reset at the center of each stop bit received or each
time the receive holding register (RHR) is read (see
Figure10,ReceiveTime-outInterrupt).Theactualtime
out value is T (Time out length in bits) = 4 X P
(Programmedwordlength)+12.Toconvertthetimeout
valuetoacharactervalue, theuserhastoconsiderthe
complete word length, including data information
length, start bit, parity bit, and the size of stop bit, i.e.,
1X, 1.5X, or 2X bit times.
The580canbeconfiguredforinternalorexternalclock
operation. For internal clock oscillator operation, an
industrystandardmicroprocessorcrystal(parallelreso-
nant/ 22-33 pF load) is connected externally between
the XTAL1 and XTAL2 pins, with an external 1 M
resistor across it. Alternatively, an external clock can
beconnectedtotheXTAL1pintoclocktheinternalbaud
rate generator for standard or custom rates.
The generator divides the input 16X clock by any
divisor from 1 to 216 -1. The 580 divides the basic
crystal or external clock by 16. Further division of this
16X clock provides two table rates to support low and
high data rate applications using the same system
design. The two rate tables are selectable through the
internal register, MCR bit-7. Setting MCR bit-7 to a
logic 1 provides an additional divide by 4 whereas,
setting MCR bit-7 to a logic 0 only divides by 1. (See
Table 4 and Figure 11). The frequency of the -
BAUDOUT output pin is exactly 16X (16 times) of the
selected baud rate (-BAUDOUT =16 x Baud Rate).
Customized Baud Rates can be achieved by selecting
the proper divisor values for the MSB and LSB sec-
tions of baud rate generator.
Example -A: If the user programs a word length of 7,
with no parity and one stop bit, the time out will be:
T=4X7(programmedwordlength)+12=40bittimes.
The character time will be equal to 40 / 9 = 4.4
characters, or as shown in the fully worked out ex-
ample: T = [(programmed word length = 7) + (stop bit
= 1) + (start bit = 1) = 9]. 40 (bit times divided by 9) =
4.4 characters.
Example -B: If the user programs the word length = 7,
with parity and one stop bit, the time out will be:
T=4X7(programmedwordlength)+12=40bittimes.
Character time = 40 / 10 [ (programmed word length
= 7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4
characters.
Programming the Baud Rate Generator Registers
Crystal oscillator connection
Programmable Baud Rate Generator
The 580 supports high speed modem technologies
that have increased input data rates by employing
data compression schemes. For example a 33.6Kbps
modem that employs data compression may require a
115.2Kbpsinputdatarate. A128.0KbpsISDNmodem
that supports data compression may need an input
data rate of 460.8Kbps. The 580 can support a stan-
dard data rate of 921.6Kbps.
R1
50-120
R2
1M
X1
1.8432 MHz
C1
22pF
C2
33pF
Single baud rate generator is provided for the trans-
mitter and receiver, allowing independent TX/RX
channel control. The programmable Baud Rate Gen-
erator is capable of accepting an input clock up to 24
MHz, as required for supporting a 1.5Mbps data rate.
Rev.1.20
12
ST16C580
DLM (MSB) and DLL (LSB) provides a user capability
for selecting the desired final baud rate. The example
in Table 4 below, shows the two selectable baud rate
tables available when using a 7.3728 MHz crystal.
Table4,BAUDRATEGENERATORPROGRAM-
MINGTABLE(7.3728MHzCLOCK):
Output
Output
User
User
DLM
Program
Value
DLL
Program
Value
Baud Rate Baud Rate 16 x Clock 16 x Clock
MCR
BIT-7=1
MCR
Bit-7=0
Divisor
(Decimal)
Divisor
(HEX)
(HEX)
(HEX)
50
75
150
300
600
1200
2400
4800
7200
9600
19.2k
38.4k
57.6k
115.2k
200
300
600
2304
1536
768
384
192
96
48
24
16
12
900
600
300
180
C0
60
30
18
10
0C
06
09
06
03
01
00
00
00
00
00
00
00
00
00
00
00
00
00
80
C0
60
30
18
10
0C
06
03
02
01
1200
2400
4800
9600
19.2K
28.8K
38.4k
76.8k
153.6k
230.4k
460.8k
6
3
2
1
03
02
01
Crystal oscillator or External clock 1X / 4X selection
MCR
Bit-7=0
Divide
by
1 logic
Clock
Oscillator
Logic
Baudrate
Generator
Logic
XTAL1
XTAL2
-BAUDOUT
Divide
by
4 logic
MCR
Bit-7=1
Rev.1.20
13
ST16C580
DMA Operation
ing. In the loop-back mode OP1 and OP2 in the MCR
register (bits 0-1) control the modem -RI and -CD
inputs respectively. MCR signals -DTR and -RTS (bits
0-1) are used to control the modem -CTS and -DSR
inputs respectively. The transmitter output (TX) and
the receiver input (RX) are disconnected from their
associated interface pins, and instead are connected
together internally (See Figure 12). The -CTS, -DSR,
-CD, and -RI are disconnected from their normal
modemcontrolinputspins, andinsteadareconnected
internally to -DTR, -RTS, -OP1 and -OP2. Loop-back
test data is entered into the transmit holding register
via the user data bus interface, D0-D7. The transmit
UART serializes the data and passes the serial data to
the receive UART via the internal loop-back connec-
tion. The receive UART converts the serial data back
into parallel data that is then made available at the
user data interface, D0-D7. The user optionally com-
pares the received data to the initial transmitted data
for verifying error free operation of the UART TX/RX
circuits.
The 580 FIFO trigger level provides additional flexibil-
ity to the user for block mode operation. LSR bits 5-6
provide an indication when the transmitter is empty or
has an empty location(s). The user can optionally
operate the transmit and receive FIFO’s in the DMA
mode (FCR bit-3). When the transmit and receive
FIFO’s are enabled and the DMA mode is deactivated
(DMA Mode “0”), the 580 activates the interrupt output
pin for each data transmit or receive operation. When
DMA mode is activated (DMA Mode “1”), the user
takes the advantage of block mode operation by
loading or unloading the FIFO in a block sequence
determined by the preset trigger level. In this mode,
the 580 sets the interrupt output pin when characters
in the transmit FIFO’s are below the transmit trigger
level, or the characters in the receive FIFO’s are
above the receive trigger level.
Sleep Mode
The 580 is designed to operate with low power con-
sumption. A special sleep mode is included to further
reduce power consumption when the chip is not being
used. With EFR bit-4 and IER bit-4 enabled (set to a
logic 1), the 580 enters the sleep mode but resumes
normaloperationwhenastartbitisdetected,achange
of state on any of the modem input pins RX, -RI, -CTS,
-DSR, -CD, or transmit data is provided by the user. If
thesleepmodeisenabledandthe580isawakenedby
one of the conditions described above, it will return to
the sleep mode automatically after the last character
is transmitted or read by the user. In any case, the
sleep mode will not be entered while an interrupt(s) is
pending. The 580 will stay in the sleep mode of
operation until it is disabled by setting IER bit-4 to a
logic 0.
In this mode , the receiver and transmitter interrupts
are fully operational. The Modem Control Interrupts
are also operational. However, the interrupts can only
be read using lower four bits of the Modem Control
Register (MCR bits 0-3) instead of the four Modem
Status Register bits 4-7. The interrupts are still con-
trolled by the IER.
Loop-back Mode
The internal loop-back capability allows onboard diag-
nostics. In the loop-back mode the normal modem
interface pins are disconnected and reconfigured for
loop-back internally. In this mode MSR bits 4-7 are
also disconnected. However, MCR register bits 0-3
can be used for controlling loop-back diagnostic test-
Rev.1.20
14
ST16C580
Figure12,INTERNALLOOP-BACKMODEDIAGRAM
Transmit
FIFO
Registers
Transmit
Shift
Register
TX
D0-D7
-IOR,IOR
-IOW,IOW
RESET
Flow
Control
Logic
Ir
Encoder
Receive
FIFO
Receive
Shift
Registers
Register
RX
A0-A2
-AS
CS0,CS1
-CS2
Flow
Control
Logic
Ir
Decoder
-DDIS
-RTS
-CD
-DTR
INT
-RXRDY
-TXRDY
-RI
-OP1
XTAL1
RCLK
XTAL2
-DSR
-OP2
-BAUDOUT
-CTS
Rev.1.20
15
ST16C580
REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the fifteen 580 internal registers. The assigned
bit functions are more fully defined in the following paragraphs.
Table 5, ST16C580 INTERNAL REGISTERS
A2 A1 A0
Register
[Default]
Note *5
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
General Register Set
0
0
0
0
0
0
0
0
1
RHR [XX]
THR [XX]
IER [00]
bit-7
bit-7
bit-6
bit-6
bit-5
bit-5
bit-4
bit-4
bit-3
bit-3
bit-2
bit-2
bit-1
bit-1
bit-0
bit-0
CTS
interrupt
RTS
interrupt
Xoff
interrupt
Sleep
mode
modem
status
interrupt
receive
line
status
interrupt
transmit
holding
register
receive
holding
register
0
0
0
1
1
1
1
1
0
0
0
0
1
0
1
FCR [00]
ISR [01]
LCR [00]
MCR [00]
LSR [60]
RCVR
trigger
(MSB)
RCVR
trigger
(LSB)
TX
trigger
(MSB)
TX
trigger
(LSB)
DMA
mode
select
XMIT
FIFO
reset
RCVR
FIFO
reset
FIFO
enable
FIFO’s
enabled
FIFO’s
enabled
INT
priority
bit-4
INT
priority
bit-3
INT
priority
bit-2
INT
priority
bit-1
INT
priority
bit-0
INT
status
divisor
latch
enable
set
break
set
parity
even
parity
parity
enable
stop
bits
word
length
bit-1
word
length
bit-0
Clock
select
IR
enable
0
loop
back
-OP2
-OP1
-RTS
-DTR
FIFO
data
error
trans.
empty
trans.
holding
empty
break
interrupt
framing
error
parity
error
overrun
error
receive
data
ready
1
1
1
1
0
1
MSR [X0]
SPR [FF]
CD
RI
DSR
bit-5
CTS
bit-4
delta
-CD
delta
-RI
delta
-DSR
delta
-CTS
bit-7
bit-6
bit-3
bit-2
bit-1
bit-0
Special Register Set: Note *3
0
0
0
0
0
1
DLL[XX]
DLM[XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-9
bit-0
bit-8
bit-15
bit-14
bit-13
bit-12
bit-11
bit-10
Rev.1.20
16
ST16C580
A2 A1 A0
Register
[Default]
Note *5
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
Enhanced Register Set: Note *4
0
1
0
EFR [00]
Auto
CTS
Auto
RTS
Special
Char.
Enable
IER
Cont-3
Tx,Rx
Cont-2
Tx,Rx
Cont-1
Tx,Rx
Cont-0
Tx,Rx
select
Bits 4-7,
ISR, FCR
Bits 4-5,
MCR
Control
Control
Control
Control
Bits 5-7
1
1
1
1
0
0
1
1
0
1
0
1
Xon-1[00]
Xon-2[00]
Xoff-1 [00]
Xoff-2 [00]
bit-7
bit-15
bit-7
bit-6
bit-14
bit-6
bit-5
bit-13
bit-5
bit-4
bit-12
bit-4
bit-3
bit-11
bit-3
bit-2
bit-10
bit-2
bit-1
bit-9
bit-1
bit-9
bit-0
bit-8
bit-0
bit-8
bit-15
bit-14
bit-13
bit-12
bit-11
bit-10
Note *3: The Special register set is accessible only when LCR bit-7 is set to a logic 1.
Note *4: Enhanced Feature Register, Xon 1,2 and Xoff 1,2 are accessible only when LCR is set to “BF“ Hex
Note *5: The value represents the register’s initialized HEX value. An “X” signifies a 4-bit un-initialize nibble.
Rev.1.20
17
ST16C580
Transmit and Receive Holding Register
B) FIFO status will also be reflected in the user
accessible ISR register when the FIFO trigger level is
reached. Both the ISR register status bit and the
interrupt will be cleared when the FIFO drops below
the trigger level.
The serial transmitter section consists of an 8-bit
Transmit Hold Register (THR) and Transmit Shift
Register (TSR). The status of the THR is provided in
the Line Status Register (LSR). Writing to the THR
transfers the contents of the data bus (D7-D0) to the
THR, providing that the THR or TSR is empty. The
THR empty flag in the LSR register will be set to a logic
1 when the transmitter is empty or when data is
transferred to the TSR. Note that a write operation can
be performed when the transmit holding register
empty flag is set (logic 0 = FIFO full, logic 1= at least
one FIFO location available).
C) The data ready bit (LSR BIT-0) is set as soon as a
character is transferred from the shift register to the
receive FIFO. It is reset when the FIFO is empty.
IER Vs Receive/Transmit FIFO Polled Mode Op-
eration
When FCR BIT-0 equals a logic 1; resetting IER bits
0-3 enables the 580 in the FIFO polled mode of
operation. Since the receiver and transmitter have
separate bits in the LSR either or both can be used in
the polled mode by selecting respective transmit or
receive control bit(s).
The serial receive section also contains an 8-bit
Receive Holding Register, RHR. Receive data is
removed from the 580 and receive FIFO by reading
the RHR register. The receive section provides a
mechanism to prevent false starts. On the falling edge
of a start or false start bit, an internal receiver counter
starts counting clocks at 16x clock rate. After 7 1/2
clocks the start bit time should be shifted to the center
of the start bit. At this time the start bit is sampled and
if it is still a logic 0 it is validated. Evaluating the start
bit in this manner prevents the receiver from assem-
bling a false character. Receiver status codes will be
posted in the LSR.
A) LSR BIT-0 will be a logic 1 as long as there is one
byte in the receive FIFO.
B) LSR BIT 1-4 will indicate if an overrun error
occurred.
C) LSR BIT-5 will indicate when the transmit FIFO is
empty.
Interrupt Enable Register (IER)
D) LSR BIT-6 will indicate when both the transmit
FIFO and transmit shift register are empty.
The Interrupt Enable Register (IER) masks the inter-
rupts from receiver ready, transmitter empty, line
status and modem status registers. These interrupts
would normally be seen on the 580 INT output pin.
E) LSR BIT-7 will indicate any FIFO data errors.
IER BIT-0:
IER Vs Receive FIFO Interrupt Mode Operation
Logic 0 = Disable the receiver ready interrupt. (normal
default condition)
When the receive FIFO (FCR BIT-0 = a logic 1) and
receive interrupts (IER BIT-0 = logic 1) are enabled,
the receive interrupts and register status will reflect
the following:
Logic 1 = Enable the receiver ready interrupt.
IER BIT-1:
Logic 0 = Disable the transmitter empty interrupt.
(normal default condition)
A) The receive data available interrupts are issued to
the external CPU when the FIFO has reached the
programmed trigger level. It will be cleared when the
FIFO drops below the programmed trigger level.
Logic 1 = Enable the transmitter empty interrupt.
IER BIT-2:
Logic 0 = Disable the receiver line status interrupt.
Rev.1.20
18
ST16C580
(normaldefaultcondition)
Logic 1 = Enable the receiver line status interrupt.
go to a logic 0 when ever an empty transmit space is
available in the Transmit Holding Register (THR).
Receive Ready (-RXRDY) will go to a logic 0 when-
ever the Receive Holding Register (RHR) is loaded
with a character.
Mode 1 Set and enable the interrupt in a block
mode operation. The transmit interrupt is set when the
transmit FIFO is below the programmed trigger level.
-TXRDY remains a logic 0 as long as one empty FIFO
location is available. The receive interrupt is set when
the receive FIFO fills to the programmed trigger level.
However the FIFO continues to fill regardless of the
programmed level until the FIFO is full. -RXRDY
remains a logic 0 as long as the FIFO fill level is above
the programmed trigger level.
IER BIT-3:
Logic 0 = Disable the modem status register interrupt.
(normal default condition)
Logic 1 = Enable the modem status register interrupt.
IER BIT -4:
Logic 0 = Disable sleep mode. (normal default condi-
tion)
Logic1=Enablesleepmode.SeeSleepModesection
for details
IER BIT-5:
Logic 0 = Disable the software flow control, receive
Xoff interrupt. (normal default condition)
Logic 1 = Enable the software flow control, receive
Xoff interrupt. See Software Flow Control section for
details.
FCR BIT-0:
Logic 0 = Disable the transmit and receive FIFO.
(normal default condition)
Logic 1 = Enable the transmit and receive FIFO. This
bit must be a “1” when other FCR bits are written to or
they will not be programmed.
IER BIT-6:
Logic 0 = Disable the RTS interrupt. (normal default
condition)
FCR BIT-1:
Logic 1 = Enable the RTS interrupt. The 580 issues an
interrupt when the RTS pin transitions from a logic 0
to a logic 1.
Logic 0 = No FIFO receive reset. (normal default
condition)
Logic 1 = Clears the contents of the receive FIFO and
resets the FIFO counter logic (the receive shift regis-
ter is not cleared or altered). This bit will return to a
logic 0 after clearing the FIFO.
IER BIT-7:
Logic 0 = Disable the CTS interrupt. (normal default
condition)
FCR BIT-2:
Logic 1 = Enable the CTS interrupt. The 580 issues an
interrupt when CTS pin transitions from a logic 0 to a
logic 1.
Logic 0 = No FIFO transmit reset. (normal default
condition)
Logic 1 = Clears the contents of the transmit FIFO and
resets the FIFO counter logic (the transmit shift regis-
ter is not cleared or altered). This bit will return to a
logic 0 after clearing the FIFO.
FIFO Control Register (FCR)
This register is used to enable the FIFO’s, clear the
FIFO’s, set the transmit/receive FIFO trigger levels,
and select the DMA mode. The DMA, and FIFO
modes are defined as follows:
FCR BIT-3:
Logic 0 = Set DMA mode “0”. (normal default condi-
tion)
Logic 1 = Set DMA mode “1.”
DMA MODE
Transmit operation in mode “0”:
When the 580 is in the ST16C450 mode (FIFO’s
disabled, FCR bit-0 = logic 0) or in the FIFO mode
Mode 0 Set and enable the interrupt for each
single transmit or receive operation, and is similar to
the ST16C450 mode. Transmit Ready (-TXRDY) will
Rev.1.20
19
ST16C580
(FIFO’s enabled, FCR bit-0 = logic 1, FCR bit-3 = logic
0) and when there are no characters in the transmit
FIFO or transmit holding register, the -TXRDY pin will
be a logic 0. Once active the -TXRDY pin will go to a
logic 1 after the first character is loaded into the
transmit holding register.
Thesebitsareusedtosetthetriggerlevelforthereceive
FIFOinterrupt.
An interrupt is generated when the number of charac-
ters in the FIFO equals the programmed trigger level.
However the FIFO will continue to be loaded until it is
full.
Receive operation in mode “0”:
When the 580 is in mode “0” (FCR bit-0 = logic 0) or
in the FIFO mode (FCR bit-0 = logic 1, FCR bit-3 =
logic 0) and there is at least one character in the
receive FIFO, the -RXRDY pin will be a logic 0. Once
active the -RXRDY pin will go to a logic 1 when there
are no more characters in the receiver.
BIT-7
BIT-6
RX FIFO trigger level
0
0
1
1
0
1
0
1
1
4
8
14
Transmit operation in mode “1”:
When the 580 is in FIFO mode ( FCR bit-0 = logic 1,
FCR bit-3 = logic 1 ), the -TXRDY pin will be a logic 1
when the transmit FIFO is completely full. It will be a
logic 0 if one or more FIFO locations are empty.
Interrupt Status Register (ISR)
The 580 provides six levels of prioritized interrupts to
minimize external software interaction. The Interrupt
Status Register (ISR) provides the user with six inter-
ruptstatusbits. PerformingareadcycleontheISRwill
provide the user with the highest pending interrupt
level to be serviced. No other interrupts are acknowl-
edged until the pending interrupt is serviced. When-
ever the interrupt status register is read, the interrupt
status is cleared. However it should be noted that only
the current pending interrupt is cleared by the read. A
lower level interrupt may be seen after rereading the
interrupt status bits. The Interrupt Source Table 6
(below) shows the data values (bit 0-5) for the six
prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels:
Receive operation in mode “1”:
When the 580 is in FIFO mode (FCR bit-0 = logic 1,
FCR bit-3 = logic 1) and the trigger level has been
reached, or a Receive Time Out has occurred, the -
RXRDY pin will go to a logic 0. Once activated, it will
go to a logic 1 after there are no more characters in the
FIFO.
FCR BIT 4-5: (logic 0 or cleared is the default condi-
tion, TX trigger level = 1)
These bits are used to set the trigger level for the
transmit FIFO interrupt. The ST16C580 will issue a
transmit empty interrupt when the number of charac-
ters in FIFO drops below the selected trigger level.
BIT-5
BIT-4
TX FIFO trigger level
0
0
1
1
0
1
0
1
1
4
8
14
FCR BIT 6-7: (logic 0 or cleared is the default condi-
tion, RX trigger level =8)
Rev.1.20
20
ST16C580
Table6, INTERRUPTSOURCETABLE
Priority
[ ISR BITS ]
Level
Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Source of the interrupt
1
2
2
3
4
5
6
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time out)
TXRDY ( Transmitter Holding Register Empty)
MSR (Modem Status Register)
RXRDY (Received Xoff signal)/ Special character
CTS, RTS change of state
ISR BIT-0:
LCRBIT0-1:(logic0orclearedisthedefaultcondition)
Thesetwobitsspecifythewordlengthtobetransmitted
orreceived.
Logic 0 = An interrupt is pending and the ISR contents
may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending. (normal default condi-
tion)
BIT-1
BIT-0
Word length
ISRBIT1-3:(logic0orclearedisthedefaultcondition)
These bits indicate the source for a pending interrupt
at interrupt priority levels 1, 2, and 3 (See Interrupt
Source Table).
0
0
1
1
0
1
0
1
5
6
7
8
ISRBIT4-5:(logic0orclearedisthedefaultcondition)
These bits are enabled when EFR bit-4 is set to a logic
1. ISR bit-4 indicates that matching Xoff character(s)
have been detected. ISR bit-5 indicates that CTS,
RTS have been generated. Note that once set to a
logic 1, the ISR bit-4 will stay a logic 1 until Xon
character(s) are received.
LCR BIT-2: (logic 0 or cleared is the default condition)
The length of stop bit is specified by this bit in
conjunction with the programmed word length.
BIT-2
Word length
Stop bit
length
ISRBIT6-7:(logic0orclearedisthedefaultcondition)
These bits are set to a logic 0 when the FIFO is not
being used. They are set to a logic 1 when the FIFO’s
are enabled
(Bit time(s))
0
1
1
5,6,7,8
5
6,7,8
1
1-1/2
2
Line Control Register (LCR)
The Line Control Register is used to specify the
asynchronous data communication format. The word
length, the number of stop bits, and the parity are
selected by writing the appropriate bits in this register.
LCR BIT-3:
Parity or no parity can be selected via this bit.
Logic 0 = No parity (normal default condition)
Logic 1 = A parity bit is generated during the transmis-
sion, receiver checks the data and parity for transmis-
sionerrors.
Rev.1.20
21
ST16C580
LCRBIT-7:
LCR BIT-4:
The internal baud rate counter latch and Enhance
Feature mode enable.
Logic 0 = Divisor latch disabled. (normal default
condition)
Logic 1 = Divisor latch and enhanced feature register
enabled.
If the parity bit is enabled with LCR bit-3 set to a logic
1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd
number of logic 1’s in the transmitted data. The
receiver must be programmed to check the same
format. (normal default condition)
Modem Control Register (MCR)
Logic 1 = EVEN Parity is generated by forcing an even
the number of logic 1’s in the transmitted. The receiver
must be programmed to check the same format.
This register controls the interface with the modem or
a peripheral device.
LCR BIT-5:
MCR BIT-0:
If the parity bit is enabled, LCR BIT-5 selects the
forced parity format.
LCR BIT-5 = logic 0, parity is not forced (normal
default condition)
Logic 0 = Force -DTR output to a logic 1. (normal
default condition)
Logic 1 = Force -DTR output to a logic 0.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit
is forced to a logical 1 for the transmit and receive
data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit
is forced to a logical 0 for the transmit and receive
data.
MCR BIT-1:
Logic 0 = Force -RTS output to a logic 1. (normal
default condition)
Logic 1 = Force -RTS output to a logic 0.
Automatic RTS may be used for hardware flow control
by enabling EFR bit-6 (See EFR bit-6).
LCR
LCR
LCR
Parity selection
MCR BIT-2:
Bit-5 Bit-4 Bit-3
Logic 0 = Set -OP1 output to a logic 1. (normal default
condition)
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
No parity
Odd parity
Even parity
Force parity “1”
Forced parity “0”
Logic 1 = Set -OP1 output to a logic 0.
MCR BIT-3:
Logic 0 = Set -OP2 output to a logic 1. (normal default
condition)
Logic 1 = Set -OP2 output to a logic 0.
LCR BIT-6:
MCR BIT-4:
When enabled the Break control bit causes a break
condition to be transmitted (the TX output is forced to
a logic 0 state). This condition exists until disabled by
setting LCR bit-6 to a logic 0.
Logic 0 = Disable loop-back mode. (normal default
condition)
Logic 1 = Enable local loop-back mode (diagnostics).
MCR BIT-5:
Not used.
Logic 0 = No TX break condition. (normal default
condition)
Logic 1 = Forces the transmitter output (TX) to a logic
0 for alerting the remote receiver to a line break
condition.
MCR BIT-6:
Logic 0 = Enable Modem receive and transmit input/
output interface. (normal default condition)
Logic 1 = Enable infrared IrDA receive and transmit
Rev.1.20
22
ST16C580
inputs/outputs. While in this mode, the TX/RX output/
Inputsareroutedtotheinfraredencoder/decoder.The
data input and output levels will conform to the IrDA
infrared interface requirement. As such, while in this
modetheinfraredTXoutputwillbealogic0duringidle
data conditions.
LSR BIT-3:
Logic 0 = No framing error (normal default condition).
Logic 1 = Framing error. The receive character did not
have a valid stop bit(s). In the FIFO mode this error is
associated with the character at the top of the FIFO.
LSR BIT-4:
MCR BIT-7:
Logic 0 = No break condition (normal default condi-
tion)
Logic 1 = The receiver received a break signal (RX
was a logic 0 for one character frame time). In the
FIFO mode, only one break character is loaded into
the FIFO.
Logic 0 = Divide by one. The input clock (crystal or
external) is divided by sixteen and then presented to
the Programmable Baud Rate Generator (BGR) with-
out further modification, i.e., divide by one. (normal,
default condition)
Logic 1 = Divide by four. The divide by one clock
described in MCR bit-7 equals a logic 0, is further
divided by four (also see Programmable Baud Rate
Generator section).
LSR BIT-5:
This bit is the Transmit Holding Register Empty indi-
cator. This bit indicates that the UART is ready to
accept a new character for transmission. In addition,
this bit causes the UART to issue an interrupt to CPU
when the THR interrupt enable is set. The THR bit is
settoalogic1whenacharacteristransferredfromthe
transmit holding register into the transmitter shift
register. The bit is reset to logic 0 concurrently with the
loading of the transmitter holding register by the CPU.
In the FIFO mode this bit is set when the transmit FIFO
is empty; it is cleared when at least 1 byte is written to
the transmit FIFO.
Line Status Register (LSR)
This register provides the status of data transfers
between. the 580 and the CPU.
LSR BIT-0:
Logic 0 = No data in receive holding register or FIFO.
(normal default condition)
Logic 1 = Data has been received and is saved in the
receive holding register or FIFO.
LSR BIT-6:
LSR BIT-1:
This bit is the Transmit Empty indicator. This bit is set
to a logic 1 whenever the transmit holding register and
the transmit shift register are both empty. It is reset to
logic 0 whenever either the THR or TSR contains a
data character. In the FIFO mode this bit is set to one
whenever the transmit FIFO and transmit shift register
are both empty.
Logic 0 = No overrun error. (normal default condition)
Logic 1 = Overrun error. A data overrun error occurred
in the receive shift register. This happens when addi-
tional data arrives while the FIFO is full. In this case
the previous data in the shift register is overwritten.
Note that under this condition the data byte in the
receive shift register is not transfer into the FIFO,
therefore the data in the FIFO is not corrupted by the
error.
LSR BIT-7:
Logic 0 = No Error (normal default condition)
Logic 1 = At least one parity error, framing error or
break indication is in the current FIFO data. This bit is
cleared when LSR register is read.
LSR BIT-2:
Logic 0 = No parity error (normal default condition)
Logic 1 = Parity error. The receive character does not
have correct parity information and is suspect. In the
FIFO mode, this error is associated with the character
at the top of the FIFO.
Modem Status Register (MSR)
This register provides the current state of the control
interface signals from the modem, or other peripheral
Rev.1.20
23
ST16C580
device that the 580 is connected to. Four bits of this
register are used to indicate the changed information.
These bits are set to a logic 1 whenever a control input
from the modem changes state. These bits are set to a
logic 0 whenever the CPU reads this register.
MSR BIT-5:
DSR (active high, logical 1). Normally this bit is the
compliment of the -DSR input. In the loop-back mode,
this bit is equivalent to the DTR bit in the MCR register.
MSR BIT-6:
MSR BIT-0:
RI (active high, logical 1). Normally this bit is the
compliment of the -RI input. In the loop-back mode
this bit is equivalent to the OP1 bit in the MCR register.
Logic 0 = No -CTS Change (normal default condition)
Logic 1 = The -CTS input to the 580 has changed state
since the last time it was read. A modem Status
Interrupt will be generated.
MSR BIT-7:
CD (active high, logical 1). Normally this bit is the
compliment of the -CD input. In the loop-back mode
this bit is equivalent to the OP2 bit in the MCR register.
MSR BIT-1:
Logic 0 = No -DSR Change (normal default condition)
Logic1=The-DSRinputtothe580haschangedstate
since the last time it was read. A modem Status
Interrupt will be generated.
Scratchpad Register (SPR)
The ST16C580 provides a temporary data register to
store 8 bits of user information.
MSR BIT-2:
Enhanced Feature Register (EFR)
Logic 0 = No -RI Change (normal default condition)
Logic 1 = The -RI input to the 580 has changed from
a logic 0 to a logic 1. A modem Status Interrupt will be
generated.
Enhanced features are enabled or disabled using this
register.
Bits-0 through 4 provide single or dual character
software flow control selection. When the Xon1 and
Xon2 and/or Xoff1 and Xoff2 modes are selected, the
double 8-bit words are concatenated into two sequen-
tial characters.
MSR BIT-3:
Logic 0 = No -CD Change (normal default condition)
Logic 1 = Indicates that the -CD input to the has
changed state since the last time it was read. A
modem Status Interrupt will be generated.
EFR BIT 0-3: (logic 0 or cleared is the default condi-
tion)
MSR BIT-4:
Combinations of software flow control can be selected
by programming these bits.
-CTS functions as hardware flow control signal input if
it is enabled via EFR bit-7. The transmit holding
register flow control is enabled/disabled by MSR bit-4.
Flow control (when enabled) allows the starting and
stopping the transmissions based on the external
modem -CTS signal. A logic 1 at the -CTS pin will stop
580 transmissions as soon as current character has
finished transmission.
Normally MSR bit-4 bit is the compliment of the -CTS
input. However in the loop-back mode, this bit is
equivalent to the RTS bit in the MCR register.
Rev.1.20
24
ST16C580
Table 7, SOFTWARE FLOW CONTROL FUNCTIONS
Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software flow controls
0
1
0
1
X
X
X
1
0
0
1
1
X
X
X
0
X
X
X
X
0
1
0
1
X
X
X
X
0
0
1
1
No transmit flow control
Transmit Xon1/Xoff1
Transmit Xon2/Xoff2
Transmit Xon1 and Xon2/Xoff1 and Xoff2
No receive flow control
Receiver compares Xon1/Xoff1
Receiver compares Xon2/Xoff2
Transmit Xon1/ Xoff1.
Receiver compares Xon1 and Xon2,
Xoff1 and Xoff2
0
1
0
1
1
0
1
1
1
1
1
1
Transmit Xon2/Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
Transmit Xon1 and Xon2/Xoff1 and Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
No transmit flow control
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
EFR BIT-4:
EFR BIT-5:
Enhanced function control bit. The content of the IER
bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7
can be modified and latched. After modifying any bits
in the enhanced registers, EFR bit-4 can be set to a
logic 0 to latch the new values. This feature prevents
existing software from altering or overwriting the 580
enhanced functions.
Logic 0 = Special Character Detect Disabled (normal
default condition)
Logic 1 = Special Character Detect Enabled. The 580
compares each incoming receive character with Xoff-
2 data. If a match exists, the received data will be
transferred to FIFO and ISR bit-4 will be set to indicate
detection of special character. Bit-0 in the X-registers
correspondswiththeLSBbitforthereceivecharacter.
Whenthisfeatureisenabled, thenormalsoftwareflow
control must be disabled (EFR bits 0-3 must be set to
a logic 0).
Logic 0 = disable/latch enhanced features. IER bits 4-
7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 are
savedtoretaintheusersettings, thenIERbits4-7, ISR
bits 4-5, FCR bits 4-5, and MCR bits 5-7 are initialized
to the default values shown in the Internal Resister
Table. After a reset, the IER bits 4-7, ISR bits 4-5, FCR
bits 4-5, and MCR bits 5-7 are set to a logic 0 to be
compatible with ST16C550 mode. (normal default
condition).
Logic 1 = Enables the enhanced functions. When this
bit is set to a logic 1 all enhanced features of the 580
areenabledandusersettingsstoredduringaresetwill
be restored.
EFR BIT-6:
Automatic RTS may be used for hardware flow control
by enabling EFR bit-6. When AUTO RTS is selected,
an interrupt will be generated when the receive FIFO
is filled to the programmed trigger level and -RTS will
go to a logic 1 at the next trigger level. -RTS will return
toalogic0whendataisunloadedbelowthenextlower
trigger level (Programmed trigger level -1). The state
of this register bit changes with the status of the
Rev.1.20
25
ST16C580
hardware flow control. -RTS functions normally when
hardware flow control is disabled.
SIGNALS
RESETSTATE
TX
Logic 1
Logic 1
Logic 1
Logic 1
Logic 1
Logic 1
Logic 0
Logic 0
0 = Automatic RTS flow control is disabled. (normal
default condition)
1 = Enable Automatic RTS flow control.
-OP1
-OP2
-RTS
-DTR
-RXRDY
-TXRDY
INT
EFR bit-7:
Automatic CTS Flow Control.
Logic 0 = Automatic CTS flow control is disabled.
(normal default condition)
Logic 1 = Enable Automatic CTS flow control. Trans-
mission will stop when -CTS goes to a logical 1.
Transmission will resume when the -CTS pin returns
to a logical 0.
ST16C580 EXTERNAL RESET CONDITIONS
REGISTERS
RESET STATE
IER
ISR
IER BITS 0-7 = logic 0
ISR BIT-0=1, ISR BITS 1-7 = logic
0
LCR, MCR
LSR
BITS 0-7 = logic 0
LSR BITS 0-4 = logic 0,
LSR BITS 5-6 = logic 1 LSR, BIT
7 = logic 0
MSR
MSR BITS 0-3 = logic 0,
MSR BITS 4-7 = logic levels of the
input signals
FCR, EFR
BITS 0-7 = logic 0
Rev.1.20
26
ST16C580
AC ELECTRICAL CHARACTERISTICS
TA=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified.
Symbol
Parameter
Limits
3.3
Limits
5.0
Units Conditions
Min
Max
Min
Max
T1w,T2w Clock pulse duration
17
17
ns
MHz
ns
ns
ns
T3w
Oscillator/Clock frequency
Address strobe width
8
24
T
T
T
4w
5s
5h
35
5
5
25
0
5
Address setup time
Address hold time
T6s
Address setup time
5
0
ns
T
6h
Chip select hold time
0
0
ns
T7d
T7w
T7h
T8d
-IOR delay from chip select
-IOR strobe width
Chip select hold time from -IOR
-IOR delay from address
Read cycle delay
-IOR to -DDIS delay
Delay from -IOR to data
Data disable time
-IOW delay from chip select
-IOW strobe width
Chip select hold time from -IOW
-IOW delay from address
Write cycle delay
10
35
0
10
40
10
25
0
10
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1:
Note 1:
Note 1:
T9d
T11d
T12d
T12h
T13d
T13w
T13h
T14d
T15d
T16s
T16h
T17d
T18d
15
35
25
10
25
15
100 pF load
Note 1:
10
40
0
10
40
20
5
10
25
0
10
30
15
5
Note 1:
Data setup time
Data hold time
Delay from -IOW to output
Delay to set interrupt from MODEM
input
50
40
40
35
100 pF load
100 pF load
T19d
T20d
T21d
T22d
T23d
Delay to reset interrupt from -IOR
Delay from stop to set interrupt
Delay from -IOR to reset interrupt
Delay from stop to interrupt
Delay from initial INT reset to transmit
start
40
1
45
45
24
35
1
40
40
24
ns
Rclk
ns
ns
Rclk
100 pF load
100 pF load
8
8
T24d
T25d
T26d
T27d
T28d
TR
Delay from -IOW to reset interrupt
Delay from stop to set -RxRdy
Delay from -IOR to reset -RxRdy
Delay from -IOW to set -TxRdy
Delay from start to reset -TxRdy
Reset pulse width
45
1
45
45
8
40
1
40
40
8
ns
Rclk
ns
ns
Rclk
ns
40
1
40
1
N
Baud rate devisor
216-1
216-1
Rclk
Note 1: Applicable only when -AS is tied low.
Rev.1.20
27
ST16C580
ABSOLUTE MAXIMUM RATINGS
Supply range
7 Volts
GND - 0.3 V to VCC +0.3 V
-40° C to +85° C
Voltage at any pin
Operating temperature
Storage temperature
Package dissipation
-65° C to 150° C
500 mW
DC ELECTRICAL CHARACTERISTICS
TA=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified.
Symbol
Parameter
Limits
3.3
Limits
5.0
Units Conditions
Min
Max
Min
Max
VILCK
VIHCK
VIL
Clock input low level
Clock input high level
Inputlowlevel
-0.3
2.4
-0.3
2.0
0.6
VCC
0.8
-0.5
3.0
-0.5
2.2
0.6
VCC
0.8
VCC
0.4
V
V
V
V
V
V
V
V
µA
µA
mA
pF
VIH
Inputhighlevel
VOL
VOL
VOH
VOH
IIL
ICL
ICC
CP
Output low level on all outputs
Output low level on all outputs
Output high level
Output high level
Input leakage
Clock leakage
Avg power supply current
Input capacitance
IOL= 5 mA
IOL= 4 mA
IOH= -5 mA
IOH= -1 mA
0.4
2.4
2.0
±10
±10
1.3
5
±10
±10
3
5
Rev.1.20
28
ST16C580
T1w
T2w
EXTERNAL
CLOCK
T3w
-BAUDOUT
1/2 -BAUDOUT
1/3 -BAUDOUT
1/3> -BAUDOUT
X450-CK-1
Clock timing
Rev.1.20
29
ST16C580
T4w
-AS
T5h
T6h
T5s
Valid
Address
A0-A2
T6s
-CS2
CS1-CS0
Valid
T7d
T8d
T7h
T7w
T9d
-IOR
IOR
Active
T11d
T12h
T11d
Active
-DDIS
D0-D7
T12d
Data
X550-RD-1
General read timing
Rev.1.20
30
ST16C580
T4w
-AS
T5h
T6h
T5s
Valid
Address
A0-A2
T6s
-CS2
CS1-CS0
Valid
T13d
T13h
T16h
T13w
T14d
T15d
-IOW
IOW
Active
T16s
Data
D0-D7
X550-WD-1
General write timing
Rev.1.20
31
ST16C580
-IOW
IOW
Active
T17d
Change of state
-RTS
-DTR
Change of state
-CD
-CTS
Change of state
Change of state
-DSR
T18d
T18d
INT
Active
Active
Active
Active
Active
T19d
-IOR
IOR
Active
T18d
Change of state
X450-MD-1
-RI
Modem input/output timing
Rev.1.20
32
ST16C580
START
BIT
STOP
BIT
DATA BITS (5-8)
RX
D0
D1
D2
D3
D4
D5
D6 D7
PARITY
BIT
NEXT
DATA
START
BIT
5 DATA BITS
6 DATA BITS
7 DATA BITS
T20d
Active
INT
T21d
-IOR
IOR
16 BAUD RATE CLOCK
X450-RX-1
Receive timing
Rev.1.20
33
ST16C580
START
BIT
STOP
BIT
DATA BITS (5-8)
RX
D0
D1
D2
D3
D4
D5
D6 D7
PARITY
BIT
NEXT
DATA
START
BIT
T25d
Active
Data
-RXRDY
Ready
T26d
-IOR
IOR
Active
X550-RX-2
Receive ready timing in none FIFO mode
Rev.1.20
34
ST16C580
START
BIT
STOP
BIT
DATA BITS (5-8)
RX
D0
D1
D2
D3
D4
D5
D6 D7
PARITY
First byte
BIT
that reaches
the trigger
level
T25d
Active
Data
-RXRDY
Ready
T26d
-IOR
IOR
Active
X550-RX-3
Receive ready timing in FIFO mode
Rev.1.20
35
ST16C580
START
BIT
STOP
BIT
DATA BITS (5-8)
TX
D0
D1
D2
D3
D4
D5
D6 D7
PARITY
BIT
NEXT
DATA
START
BIT
5 DATA BITS
6 DATA BITS
7 DATA BITS
T22d
Active
Tx Ready
INT
T24d
T23d
-IOW
IOW
Active
Active
16 BAUD RATE CLOCK
X450-TX-1
Transmit timing
Rev.1.20
36
ST16C580
START
BIT
STOP
BIT
DATA BITS (5-8)
TX
D0
D1
D2
D3
D4
D5
D6 D7
PARITY
BIT
NEXT
DATA
START
BIT
-IOW
IOW
Active
T28d
BYTE #1
T27d
Active
Transmitter ready
-TXRDY
Transmitter
not ready
X550-TX-2
Transmit ready timing in none FIFO mode
Rev.1.20
37
ST16C580
START BIT
DATA BITS (5-8)
STOP BIT
TX
D0
D1
D2
D3
D4
D5
D6 D7
5 DATA BITS
PARITY BIT
6 DATA BITS
7 DATA BITS
-IOW
IOW
Active
T28d
D0-D7
BYTE #16
T27d
-TXRDY
FIFO Full
X550-TX-3
Transmit ready timing in FIFO mode
Rev.1.20
38
ST16C580
UART Frame
Data Bits
1
1
1
1
1
0
0
0
0
0
TX
IRTX
1/2 Bit Time
Bit Time
3/16 Bit Time
Infrared transmit timing
IRRX
RX
Bit Time
0-1 16x clock
delay
1
1
1
1
1
0
0
0
0
0
Data Bits
UART Frame
X650-IR-1
Infrared receive timing
Rev.1.20
39
ST16C580
PACKAGEOUTLINEDRAWING
48 LEAD THIN QUAD FLAT PACK
(TQFP)
D
D1
36
25
37
24
D1
D
48
13
1
1
2
B
e
A2
C
A
Seating
Plane
α
A1
L
Note: The control dimension is the millimeter column
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
A1
A2
B
0.039
0.002
0.037
0.007
0.004
0.346
0.272
0.047
0.006
0.041
0.011
0.008
0.362
0.280
1.00
0.05
0.95
0.17
0.09
8.80
6.90
1.20
0.15
1.05
0.27
0.20
9.20
7.10
C
D
D1
e
0.20 BSC
0.50BSC
L
0.018
0.030
7°
0.45
0°
0.75
7°
α
0°
Rev.1.20
40
ST16C580
EXPLANATIONOFDATASHEETREVISIONS:
FROM
1.10
TO
CHANGES
DATE
1.20
Added Patent Number. Added revision history.
Added Device Status to front page.
Sept2003
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improvedesign,performanceorreliability.EXARCorporationassumesnoresponsibilityfortheuseofanycircuits
describedherein,conveysnolicenseunderanypatentorotherright,andmakesnorepresentationthatthecircuits
arefreeofpatentinfringement.Chartsandschedulescontainedhereinareonlyforillustrationpurposesandmay
vary depending upon a user's specific application. While the information in this publication has been carefully
checked; no responsibility, however, is assumed for inaccuracies.
EXARCorporationdoesnotrecommendtheuseofanyofitsproductsinlifesupportapplicationswherethefailure
of the product can reasonably be expected to cause failure of the life support system or to significantly affect its
safetyoreffectiveness.ProductsarenotauthorizedforuseinsuchapplicationsunlessEXARCorporationreceives,
in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user
assumesallsuchrisks;(c)potentialliabilityofEXARCorporationisadequatelyprotectedunderthecircumstances.
Copyright 2003 EXARCorporation
Datasheet September2003
Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com
Reproduction, in part or whole, without prior written consent of EXAR Corporation is prohibited.
Rev.1.20
41
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