ST49C107A [EXAR]
Preprogrammed CPU Mother Board Frequency Generator; 预编程的CPU主机板频率发生器
| 型号： | ST49C107A |
| 厂家： | 
EXAR CORPORATION |
| 描述： | Preprogrammed CPU Mother Board Frequency Generator |
| 文件： | 总8页 (文件大小：69K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
ST49C107A-04
Preprogrammed CPU Mother Board
Frequency Generator
...the analog plus companyTM
June 1997-3
FEATURES
D Provides Reference Clock And Synthesized Clock
D 5 to 32 MHz Input Reference Frequency
D Pin-to-Pin Compatible to Avasem AV9107
D Programmable Analog Phase Locked Loop
D Low Power Single 5V CMOS Technology
D Up to 16 Frequencies Stored Internally
D 8/14 pin DIP or SOIC Package
GENERAL DESCRIPTION
The ST49C107A-04 is a mask programmable monolithic
analog CMOS device designed to generate two
simultaneous clocks. The output frequency can vary from
2 to 130MHz, with up to 16 single selectable
preprogrammed frequencies stored in internal ROM.
in order to reduce board space and number of oscillators.
To provide high speed and low jitter clock, the parts utilize
a high speed analog CMOS phase locked loop using
14.318 MHz system clock as the reference clock (note
that reference clock can be changed to generate optional
frequencies from a standard programmed device). The
programmed clock outputs are selectable via four
address lines.
The ST49C107A-04 is designed to replace existing CPU
mother board clocks generated from individual oscillators
ORDERING INFORMATION
Part No.
Operating
Temperature Range
Package
14 Lead 150 Mil JEDEC SOIC
ST49C107ACF14-04
0°C to 70°C
BLOCK DIAGRAM
XTAL
XTAL
OE1 OE2
1X-CLOCK
2X-CLOCK
Oscillator
Circuit
Output
Buffer
Programmable
Counter
B
Voltage
Controlled
Oscillator
Programmable
Counter
C
Phase
Detector
Charge
Pump
Loop
Filter
Programmable
Counter
A
Voltage
Reference
Circuit
Rom Table
Select
Logic
B=5....128
A=5....128
C = 1, 2, 4
A0-A3
Figure 1. Block Diagram
Rev. P2.00
E1996
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017
1
Preliminary
ST49C107A-04
PIN CONFIGURATION
1
2
3
4
14
A1
A2
A0
1XCLK
13
12
A3
AGND
DGND
PD*
V
CC
2XCLK
OE2
OE1
XTAL2
11
5
6
7
10
9
8
XTAL1
14 Lead SOIC (Jedec, 0.150”)
PIN DESCRIPTION
Symbol
A1
Pin #
Type
Description
1
2
3
4
5
6
7
I
I
Frequency Select Address Input 21.
A2
Frequency Select Address Input 31.
Frequency Select Address Input 41.
Analog Ground.
A3
I
AGND
DGND
PD
O
O
I
Digital Ground.
Power-down (Active Low). Shuts off chip when low1.
XTAL1
I
Crystal Or External Clock Input. A crystal can be connected to this pin and XTAL2 pin to
generate internal phase locked loop reference clock. For external 14.318 MHz clock, XTAL2
is left open or used as buffered clock output.
XTAL2
OE1
8
9
O
I
Crystal Output.
1X-CLOCK Output Enable (Active High). 1X-CLOCK output is three stated when this pin is
low1.
OE2
10
I
2X-CLOCK Output Enable (Active High). 2X-CLOCK output is three stated when this pin is
low1.
2XCLK
VCC
11
12
13
14
O
I
Programmed Output Clock.
Positive Supply Voltage. Single +5 volts.
2X-CLOCK Divide-by-two Output.
Frequency Select Address Input 11.
1XCLK
A0
O
I
Notes
1Have internal pull-up resistors on inputs.
Rev. P2.00
2
Preliminary
ST49C107A-04
DC ELECTRICAL CHARACTERISTICS
Test Conditions: T = 0°C to +70°C, V = 5.0V ꢀ 10% Unless Otherwise Specified
A
CC
Symbol
VIL
Parameter
Min.
2.0
Typ.
Max.
Unit
V
Conditions
Input Low Level
0.8
VIH
Input High Level
Output Low Level
Output High Level
Input Low Current
Input High Current
Operating Current
Standby Current
Input Pull-up Resistance
V
VOL
VOH
IIL
0.4
V
IOL = 8.0mA
2.4
V
IOH = 8.0mA
-10
1
µA
µA
mA
µA
kΩ
Except Crystal Input
VIN=VCC
IIH
ICC
45
25
55
No Load. CLOCK=100MHz
No Load
ISB
RIN
500
900
1300
DC ELECTRICAL CHARACTERISTICS
Test Conditions: T = 0°C to +70°C, V = 5.0V ꢀ 10% Unless Otherwise Specified
A
CC
Symbol
T1
Parameter
Min.
Typ.
1
Max.
2
Unit
ns
Conditions
1X, 2X-CLOCK Rise Time
1X, 2X-CLOCK Fall Time
Duty Cycle
CL=20pF 0.8V - 2.0V
CL=20pF 2.0V - 0.8V
1.4V Switch Point
VCC/2 Switch Point
T2
1
2
ns
T4
40
45
50
60
55
ꢀ2
ꢀ5
32
20
20
%
T5
Duty Cycle
50
%
T3
Jitter 1 Sigma
ꢀ0.5
ꢀ3
%
T3
Jitter Absolute
%
T
Input Frequency
Buffered Clock Rise Time
Buffered Clock Fall Time
2
MHz
ns
T7
T8
ns
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS
Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . -40°C to +150°C
Package Dissipation . . . . . . . . . . . . . . . . . . . . . 500 mW
Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Volts
Voltage at Any Pin . . . . . . . . . GND-0.3V to V +0.3V
CC
Rev. P2.00
3
Preliminary
ST49C107A-04
EXTERNAL CLOCK CONNECTION
CLOCK OUTPUT TABLE FOR ST49C107A-04 (using
14.318 MHz input. All frequencies in MHz).
To minimize the noise pickup, it is recommended to
connect 0.047 (F capacitor to XTAL1, and keep the lead
length of the capacitor to XTAL1 to a minimum to reduce
noise susceptibility.
A3 A2 A1 A0 Factor
2X-
CLOCK
CLOCK
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
95/17
107/23
35/10
95/34
56/8
107/46
38/17
35/20
76/17
2
80.02
66.62
40.01
33.31
50.11
25.06
40.01
20.00
FREQUENCY SELECT CALCULATION
100.23
33.31
50.11
16.66
The ST49C107A-04 contains an analog phase locked
loop circuit with digital closed loop dividers and a final
output multiplexer to achieve the desired dividing ratios
for the clock output.
32.01
16.00
25.06
12.47
64.02
32.01
The accuracy of the frequencies produced by the
ST49C107A-04 depends on the input frequency and
divider ratios. The formula for calculating the exact output
frequency is as follows:
2X-Input
3X-Input
8X-Input
1X-Input
1.5X-Input
4X-Input
3
8
1/2
0.5X-Input 0.25X-Input
CLKOUT = CLKIN * Factor
1/4
0.25X-
Input
0.125X-
Input
For proper output frequency, the ST49C107A-04 can
accept a reference frequency from 5 - 32MHz with max
output frequency of 130MHz (2X – clock).
1
1
1
1
1
1
0
1
109/13
118/13
120.00
129.96
60.00
64.98
1X–CLOCK
2X–CLOCK
CLOCK
T1
T2
T3
T5
T4
BCLK
T8
T7
Figure 2. Timing Diagram
Rev. P2.00
4
Preliminary
ST49C107A-04
14 LEAD SMALL OUTLINE
(150 MIL JEDEC SOIC)
Rev. 1.00
D
14
1
8
7
E
H
C
A
Seating
Plane
α
A
1
e
B
L
INCHES
MIN
MILLIMETERS
SYMBOL
MAX
0.069
0.010
0.020
0.010
0.344
0.157
MIN
1.35
0.10
0.33
0.19
8.55
3.80
MAX
A
0.053
0.004
0.013
0.007
0.337
0.150
1.75
0.25
0.51
0.25
8.75
4.00
A
B
1
C
D
E
e
0.050 BSC
1.27 BSC
H
L
0.228
0.244
0.050
5.80
0.40
6.20
1.27
0.016
α
0°
8°
0°
8°
Note: The control dimension is the millimeter column
Rev. P2.00
5
Preliminary
ST49C107A-04
Notes
Rev. P2.00
6
Preliminary
ST49C107A-04
Notes
Rev. P2.00
7
Preliminary
ST49C107A-04
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.
Copyright 1996 EXAR Corporation
Datasheet June 1997
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. P2.00
8
相关型号：
©2020 ICPDF网 联系我们和版权申明